WO2023051665A1

WO2023051665A1 - Nanopore sequencing circuit unit and gene sequencing apparatus

Info

Publication number: WO2023051665A1
Application number: PCT/CN2022/122448
Authority: WO
Inventors: 张风体; 蒋可; 苏云鹏; 邹耀中
Original assignee: 成都今是科技有限公司
Priority date: 2021-09-30
Filing date: 2022-09-29
Publication date: 2023-04-06
Also published as: CN115876866A

Abstract

A nanopore sequencing circuit unit (200) and a gene sequencing apparatus. The nanopore sequencing circuit unit (200) is implemented using a CMOS circuit, and is used for realizing the detection of a bidirectional micro-current signal of a nanopore (201). The nanopore sequencing circuit unit comprises: a nanopore clamping circuit, which is used for stabilizing the voltage of a detection electrode located on one side of the nanopore (201), generating a fixed voltage difference, across two ends of the nanopore (201), between the detection electrode and a common electrode located on the other side of the nanopore (201), and driving individual nucleotide molecules to pass through the nanopore one by one by means of the voltage difference (201); the nanopore (201) clamping circuit comprises a charging path formed by a first operational amplifier circuit (205) and a first clamping tube (214), and a discharging path formed by a second operational amplifier circuit (204) and a second clamping tube (215); an integral reset circuit, which is used for performing integral amplification on the bidirectional micro-current signal of the nanopore (201) when the charging path and the discharging path of the nanopore (201) clamping circuit are respectively connected, and converting the bidirectional micro-current signal into a voltage signal; and an output circuit, which is used for receiving the voltage signal obtained after the integral reset circuit performs conversion, and outputting the voltage signal. A high-throughput gene sequencing apparatus with a bidirectional detection capability is constructed on the basis of a small-area sequencing circuit unit, such that the detection precision and efficiency can be improved.

Description

Nanopore sequencing circuit unit and gene sequencing device

technical field

The disclosure belongs to the technical field of electronic circuits, and in particular relates to a nanopore sequencing circuit unit and a gene sequencing device, which can be used for the detection of biological microcurrent signals of gene sequencing and pA level microcurrents in other application fields.

Background technique

Nanopore sequencing uses electrophoresis technology to drive individual molecules through nanopores one by one to achieve sequencing. At present, nanopore sequencing technology has gradually been widely used in DNA sequencing, disease detection, drug screening, and environmental monitoring. In the existing nanopore sequencing technology, according to the power supply mode, it can be simply divided into DC power supply and AC power supply, and the corresponding nanopore electrodes can also be divided into DC electrodes and AC electrodes. DC electrodes generally undergo oxidation-reduction reactions with the solution, providing electrons or capturing electrons in the reaction, so they can only provide current in one direction, and the electrodes will be consumed slowly over time, which has a service life problem; AC electrodes will not interact with the solution Oxidation-reduction reactions occur, mainly through the adsorption of ions in the solution or the release of ions to achieve the purpose of power supply. It will not be consumed, but it needs to be charged or discharged to work normally. According to the characteristics of the nanoporous electrode material, the use of alternating current for power supply is beneficial to reduce the area of the electrode and improve the service life.

The currently known Roche gene sequencing solutions only perform sequencing in one direction, and only charge the electrodes in the other direction. There is still much room for improvement in terms of sequencing efficiency and accuracy. In addition, the known gene sequencing device can integrate more sequencing units to work synchronously, and this high-throughput gene sequencing device requires the sequencing unit to have a smaller area.

Contents of the invention

In view of this, the present disclosure provides a nanopore sequencing circuit unit and a gene sequencing device for constructing a high-throughput gene sequencing device with bidirectional detection capability based on a small-area sequencing circuit unit, which can improve detection accuracy and efficiency.

In the first aspect, the present disclosure provides a nanopore sequencing circuit unit, which is implemented by a CMOS circuit and is used to detect bidirectional microcurrent signals of nanopores, which includes:

The nanopore clamping circuit is used to stabilize the detection electrode voltage on one side of the nanopore, and generate a fixed voltage difference between the two ends of the nanopore with the common electrode on the other side of the nanopore, by means of the voltage difference Driving single nucleotide molecules through the nanopore one by one; the nanopore clamping circuit includes a charging path composed of a first operational amplifier circuit and a first clamping tube, and a charging path composed of a second operational amplifier circuit and a second clamping tube. discharge path;

Integral reset circuit for integrally amplifying the bidirectional microcurrent signal of the nanopore and converting it into a voltage signal when the charging path and the discharging path of the nanopore clamping circuit are respectively turned on;

The output circuit is used to receive and output the voltage signal converted by the integral reset circuit.

In an optional implementation manner, the source of the first clamping tube is connected to the source of the second clamping tube and connected to the detection electrode; the drain of the first clamping tube is connected to the second clamping tube The drains of the clamping tubes are connected and connected to the integral reset circuit.

In an optional implementation manner, the negative input terminal of the first operational amplifier circuit is connected to the detection electrode, the positive input terminal is connected to the common level, and the output terminal is connected to the control terminal of the first clamping tube; the The negative input terminal of the second operational amplifier circuit is connected to the detection electrode, the positive input terminal is connected to the common level, and the output terminal is connected to the control terminal of the second clamping tube.

In an optional implementation manner, the first clamping transistor includes a first transistor and a second transistor, and the second clamping transistor includes a third transistor and a fourth transistor; wherein, the drain of the first transistor The pole is connected to the source of the second transistor, the drain of the third transistor is connected to the source of the fourth transistor; the source of the first transistor is connected to the source of the third transistor, and is connected to the source of the third transistor. The detection electrodes are connected; the drain of the second transistor is connected to the drain of the fourth transistor, and connected to the integral reset circuit; the control terminal of the second transistor is connected to the control terminal of the fourth transistor , and connected to the first switching control signal; the first switching control signal controls the nanopore clamping circuit to switch between the charging path and the discharging path.

In an optional implementation manner, the negative input terminal of the first operational amplifier circuit is connected to the detection electrode, the positive input terminal is connected to the common level, and the output terminal is connected to the control terminal of the first transistor; the second The negative input terminal of the operational amplifier circuit is connected to the detection electrode, the positive input terminal is connected to the common level, and the output terminal is connected to the control terminal of the third transistor.

In an optional implementation manner, the first operational amplifier circuit includes a fifth transistor, the second operational amplifier circuit includes a sixth transistor, and the control terminals of the fifth transistor and the sixth transistor are connected to the second switching control signal ; The fifth transistor and the sixth transistor are used to respectively control the power on and off of the first operational amplifier circuit and the second operational amplifier circuit and control the nanometer under the action of the second switching control signal The hole clamp switches between the charge path and the discharge path.

In an optional implementation manner, the first operational amplifier circuit and the second operational amplifier circuit further include a bias voltage input terminal, wherein the bias voltage input terminal of the first operational amplifier circuit inputs a first bias voltage, The bias voltage input terminal of the second operational amplifier circuit inputs a second bias voltage.

In an optional implementation manner, the integration reset circuit includes an integration capacitor and a first reset switch, the first end of the integration capacitor is connected to the first end of the first reset switch, and is connected to the first reset switch at the same time. The drain of the second transistor and the drain of the fourth transistor, the second terminal of the integrating capacitor is connected to the ground potential; the second terminal of the first reset switch is connected to a precharge voltage for periodically charging the integrating capacitor voltage to reset.

In an optional implementation manner, the integration reset circuit includes an integration capacitor and a first reset switch, the first end of the integration capacitor is connected to the first end of the first reset switch, and is connected to the first clamp The drains of the bit tube and the second clamping tube, the second end of the integration capacitor is connected to the ground potential; the second end of the first reset switch is connected to the precharge voltage, which is used to periodically perform the voltage of the integration capacitor reset.

In an optional implementation manner, the output circuit includes a second source follower and a selection switch, the input end of the second source follower is connected to the first end of the integrating capacitor, and the output end is connected to the selection switch. The first end of the switch and the second end of the selection switch output the voltage signal converted by the integral reset circuit to the common signal line.

In an optional embodiment, the nanopore sequencing circuit unit further includes a second reset switch, the first end of the second reset switch is connected to the detection electrode, and the second end is connected to the common level, for The voltage of the detection electrode is fixed at a common level when the nanopore clamp circuit is switched between a charging path and a discharging path.

In the second aspect, the present disclosure also provides a gene sequencing device, which includes a chip integrated with multiple micropore structural units and multiple nanopore sequencing circuit units as described in any one of the foregoing embodiments, and the micropore structural unit includes Nanopores, common electrodes and detection electrodes located on both sides of the nanopores; the plurality of nanopore sequencing circuit units are correspondingly connected to the plurality of micropore structural units for measuring the bidirectional microcurrent signal.

In an optional embodiment, it also includes a common signal line and an analog-to-digital conversion circuit connected to the common signal line, the common signal line is used to receive the voltage signal output by the nanopore sequencing circuit unit, the analog The digital conversion circuit is used to convert the voltage signal into a digital signal.

In an optional implementation manner, a common tail current source is further included, one end of the common tail current source is connected to the common signal line, and the other end of the common tail current source is grounded.

In an optional embodiment, the chip includes a MEMS chip implementing the micropore structure unit.

The nanopore sequencing circuit unit of the present disclosure has a very small circuit area and has bidirectional microcurrent detection capability, and is suitable for the integrated construction of a nanopore gene sequencing device with a flux of millions or even tens of millions of fluxes, which can greatly improve the integration degree, Thus achieving high throughput and high detection efficiency. Furthermore, the nanopore sequencing circuit unit and its gene sequencing device can perform detection in one direction and perform error correction in the other direction, which can further correct errors, reduce error rates, and improve detection accuracy.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description These are some embodiments of the present disclosure. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic diagram of the structure and electrical model of a nanopore test chamber 101 used in an embodiment of the present disclosure;

2 is a schematic circuit diagram of a nanopore sequencing circuit unit 200 according to Embodiment 1 of the present disclosure;

3 is a schematic circuit diagram of a nanopore sequencing circuit unit 300 according to Embodiment 2 of the present disclosure;

4 is a schematic circuit diagram of a nanopore sequencing circuit unit 400 according to Embodiment 3 of the present disclosure;

FIG. 5A is a schematic diagram of the first circuit working state of the nanopore sequencing circuit unit 400 of the embodiment shown in FIG. 4;

5B is a schematic diagram of the second circuit working state of the nanopore sequencing circuit unit 400 of the embodiment shown in FIG. 4;

6 is a schematic circuit diagram of a nanopore sequencing circuit unit 600 according to Embodiment 4 of the present disclosure;

Fig. 7 is a schematic structural diagram of a gene sequencing device according to an embodiment of the present disclosure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Apparently, the described embodiments are some of the embodiments of the present disclosure, not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present disclosure.

In the present disclosure, it should be understood that terms such as "comprising" or "having" are intended to indicate the presence of features, numbers, steps, acts, components, parts or combinations thereof disclosed in the specification, and are not intended to exclude one or a plurality of other features, numbers, steps, acts, parts, parts or combinations thereof exist or are added.

In a nanopore sequencing device, the voltage applied to both ends of the test chamber is usually used to drive nucleotide molecules through the nanopore, and the type of nucleotide molecules passing through the nanopore is detected by detecting the microcurrent characteristic signal output by the nanopore, thereby realizing the genetic sequencing. sequencing.

FIG. 1 is a schematic diagram of the structure and electrical model of a nanopore test chamber 101 used in an embodiment of the present disclosure. As shown in Figure 1, the nanopore test chamber 101 includes a first compartment and a second compartment separated by a phospholipid bimolecular membrane 105, and an electrode 103 connected to the first compartment and an electrode connected to the second compartment 102. The phospholipid bimolecular membrane 105 has a nanopore 104 , and the nucleotide molecule 106 connected with the linker 107 is located in the first compartment and passes through the nanopore 104 under the action of the voltage applied to the electrodes 102 and 103 . In FIG. 1 , the nanopore equivalent capacitance 108 and the nanopore equivalent resistance 109 can be used to simulate the electrical characteristics of the nanopore 104. For convenience of description, the embodiment of the present disclosure simplifies the nanopore test chamber 101 into a nanopore equivalent circuit model. 113.

FIG. 2 is a schematic circuit diagram of a nanopore sequencing circuit unit 200 according to Embodiment 1 of the present disclosure. As shown in FIG. 2 , the nanopore sequencing circuit unit 200 is implemented with a CMOS circuit, including a nanopore clamp circuit, an integral reset circuit and an output circuit.

The nanopore clamping circuit is used to stabilize the detection electrode voltage of the nanopore 201, and generates a fixed voltage difference with the common electrode VCMD 202 located on the other side of the nanopore 201 at both ends of the nanopore 201, and constitutes with the integral reset circuit In the charging and discharging path, single nucleotide molecules are driven through the nanopore one by one by means of the voltage difference between the two ends of the nanopore 201 . Wherein, the nanopore clamping circuit includes a charging path composed of a first operational amplifier circuit (OP1) 205 and a first clamping tube 214, and a discharge path composed of a second operational amplifier circuit (OP2) 204 and a second clamping tube 215. path.

The integral reset circuit is used to integrally amplify the bidirectional microcurrent signal of the nanopore 201 and convert it into a voltage signal when the charging path and the discharging path of the nanopore clamping circuit are respectively turned on. The output circuit is used to receive and output the voltage signal converted by the integral reset circuit.

In some embodiments, the source of the first clamping tube 214 is connected to the source of the second clamping tube 215, and is connected to the detection electrode of the nanopore 201; the drain of the first clamping tube 214 It is connected to the drain of the second clamping tube 215 and connected to the integral reset circuit. Wherein, the negative input terminal of the first operational amplifier circuit (OP1) 205 is connected to the detection electrode of the nanopore 201, and the positive input terminal is connected to the common level VCM 203; the output terminal of the first operational amplifier circuit (OP1) 205 is connected to the first clamp The control end of tube 214 is connected. The negative input end of the second operational amplifier circuit (OP2) 204 is connected to the detection electrode of the nanopore 201, and the positive input end is connected to the common level VCM 203; the output end of the second operational amplifier circuit (OP2) 204 is connected to the second clamping tube 215 control terminal connection.

In some implementations, the first clamping transistor 214 may be a PMOS transistor, and the second clamping transistor 215 may be an NMOS transistor.

In some implementations, the integral reset circuit may include an integral capacitor 208 and a reset switch 207 . The first end of the integrating capacitor 208 (i.e. the charging end) is connected to the first end of the reset switch 207, the other end of the integrating capacitor 208 is grounded, and the second end of the reset switch 207 is connected to the precharge voltage Vpre 206. The charging terminal of the integrating capacitor 208 is connected to the drain of the first clamping tube 214 and the drain of the second clamping tube 215 at the same time, and is used for integrating and amplifying the microcurrent signal of the nanopore to be measured, and converting it into a voltage signal. The reset switch 207 is used to periodically clear and reset the voltage of the integration capacitor 208 under the action of the reset signal Rst.

In some embodiments, when the output terminals of the first operational amplifier circuit (OP1) 205 and the second operational amplifier circuit (OP2) 204 output a low level, the first clamping transistor 214 is turned on, and the second clamping transistor 215 is turned off At this time, the charging path is turned on and the discharging path is turned off. When the output terminals of the first operational amplifier circuit (OP1) 205 and the second operational amplifier circuit (OP2) 204 output a high level, the first clamp tube 214 is turned off, and the second clamp tube 215 is turned on. At this time, the charging path off, the discharge path is turned on. The charging and discharging path transfers the nanopore current to the integrating capacitor 208, and after being integrated and amplified for a fixed time, it is output through the output circuit.

In some implementations, the output circuit includes a source follower 216 and a selection switch 209 . The input terminal of the source follower 216 is connected to the first terminal (ie, the charging terminal) of the integrating capacitor 208 , receives the voltage signal output by the integrating reset circuit, and is connected to the common signal line 211 through the selection switch 209 .

In some implementations, the common signal line 211 is connected in parallel with the tail current source 213 and connected with the analog-to-digital converter 212. The analog-to-digital converter 212 is used to receive the output voltage signal of the source follower 216 and convert it into a digital code value, which has The multiplexing function can be multiplexed among multiple nanopore sequencing circuit units.

The nanopore sequencing circuit unit of the embodiment of the present disclosure is implemented by a CMOS circuit, has a very small circuit area, is convenient for high-throughput integration, and has bidirectional detection capabilities for charging and discharging, which can significantly improve the performance of high-throughput gene sequencing devices. Sequencing accuracy and efficiency.

FIG. 3 is a schematic circuit diagram of a nanopore sequencing circuit unit 300 according to Embodiment 2 of the present disclosure. As shown in FIG. 3 , the nanopore sequencing circuit unit 300 of this embodiment is based on the circuit structure of the first embodiment, and a reset switch Rst_cmd 317 is connected in series between the detection electrode of the nanopore 301 and the common level VCM 303 . The addition of the reset switch 317 can fix the detection electrodes of the nanopore 301 at a common level when the circuit detects and switches the direction of charging and discharging, which is conducive to the rapid establishment of the circuit operating point and improves the response speed of the circuit when switching between two-way detection.

FIG. 4 is a schematic circuit diagram of a nanopore sequencing circuit unit 400 according to Embodiment 3 of the present disclosure. As shown in FIG. 4 , the nanopore sequencing circuit unit 400 of this embodiment further improves the design of the nanopore clamping circuit on the basis of the solutions of the previous embodiments.

Wherein, the first operational amplifier circuit ( OP1 ) 408 and the second operational amplifier circuit ( OP2 ) 409 are realized by five-transistor ( 5T ) operational amplifiers. The first clamping transistor 410 includes a first transistor and a second transistor connected in series, and the second clamping transistor 411 includes a third transistor and a fourth transistor connected in series. The drain of the first transistor is connected to the source of the second transistor, and the drain of the third transistor is connected to the source of the fourth transistor. The source of the first transistor is connected to the source of the third transistor, and is connected to the detection electrode of the nanopore 401 . The drain of the second transistor is connected to the drain of the fourth transistor, and connected to the charging terminal of the integrating capacitor 414 . The control terminal of the second transistor is connected to the control terminal of the fourth transistor and connected to the switching control signal CMD.

The positive input terminal of the first operational amplifier circuit (OP1) 408 is connected to the common level VCM 404, and the negative input terminal is connected to the detection electrode of the nanopore 401. Similarly, the positive input terminal of the second operational amplifier circuit (OP2) 409 is also connected to the common level VCM 404, and the negative input terminal is also connected to the detection electrode of the nanopore 401. The output terminal of the first operational amplifier circuit (OP1) 408 is connected to the control terminal of the first transistor of the first clamping tube 410, and the output terminal of the second operational amplifier circuit (OP2) 409 is connected to the first clamping tube 411 of the second operational amplifier circuit. The control terminal of the three transistors.

The bias voltage input terminal of the first operational amplifier circuit (OP1) 408 inputs a bias voltage VP403, and the bias voltage input terminal of the second operational amplifier circuit (OP2) 409 inputs a bias voltage VN 406.

In some implementations, the nanopore sequencing circuit unit 400 of this embodiment can also connect a reset switch 407 in series between the detection electrode of the nanopore 401 and the common level VCM 404, so that when the circuit performs charging and discharging direction detection switching, Fixing the detection electrodes of the nanopore 401 at a common level is conducive to the rapid establishment of the circuit operating point and improves the response speed of the circuit when switching between two-way detection.

5A and 5B are schematic diagrams of the circuit working state of the nanopore sequencing circuit unit 400 of the embodiment shown in FIG. 4 . As shown in Figure 5A, when the switching control signal CMD is '0', the second transistor controlling the first clamping tube 410 is turned on, and the fourth transistor of the second clamping tube 411 is turned off. state, the charging path formed by the first operational amplifier circuit (OP1) 408 and the first clamp tube 410 is gated and starts to work. At this time, the current flows from the nanopore 401 to the integrating capacitor 414, and is converted into a voltage signal after being integrated and amplified, and then output through the source follower 416 for sampling and analog-to-digital conversion.

When the switching control signal CMD is '1', the second transistor of the first clamping tube 410 is controlled to turn off, and the fourth transistor of the second clamping tube 411 is turned on. At this time, the circuit works in a discharge state, and the second operational amplifier The discharge path formed by the circuit (OP2) 409 and the second clamping tube 411 is gated and started to work. At this time, the current flows from the integrating capacitor 414 to the nanopore 401 , and is converted into a voltage signal after being integrated and amplified, and output through the source follower 416 for sampling to analog-to-digital conversion.

The precharge voltage Vpre is VL in the charging state, and VH in the discharging state, and VL and VH are at the upper and lower sides of the common level VCM. The reference voltage VCMD of the common electrode of the nanopore changes up and down by a fixed voltage difference ΔV around the common level VCM. The reset signal Rst of the reset switch 412 periodically resets the integrating capacitor 414, and the reset voltage value is the precharge voltage Vpre, so the voltage of the integrating capacitor 414 will be bounded by the precharge voltage Vpre, and rises from VL during charging, and rises from VL during discharging. Start descending from VH. It should be noted that although FIG. 5A schematically depicts that the reference voltage VCMD of the common electrode of the nanopore adopts a symmetrical voltage mode, in other implementation manners, the reference voltage VCMD can also be an asymmetrical voltage. In addition, the voltage shown in FIG. 5A Each voltage signal can be flexibly adjusted according to system needs.

As shown in Figure 5B, if the circuit system needs to be fast and stable, the RST_CMD signal of the reset switch 407 can be enabled, and the RST_CMD signal can be turned on at the transition of the switching control signal CMD, the reset switch 407 is turned on, and the detection electrode of the nanopore is directly connected to To the common level VCM, the clamp terminal voltage of the nanopore can be quickly stabilized.

FIG. 6 is a schematic circuit diagram of a nanopore sequencing circuit unit 600 according to Embodiment 4 of the present disclosure. As shown in FIG. 6 , the nanopore sequencing circuit unit 600 of this embodiment further improves the design of the nanopore clamping circuit on the basis of the solutions of the previous embodiments.

In this embodiment, compared with the third embodiment, the first clamping transistor 610 only includes the first transistor, and the second clamping transistor 611 only includes the third transistor. The source of the first transistor is connected to the source of the third transistor, and is connected to the detection electrode of the nanopore 601; the drain of the first transistor is connected to the drain of the third transistor, and connected to To the charging terminal of the integrating capacitor 614. The output terminal of the first operational amplifier circuit (OP1) 608 is connected to the control terminal of the first transistor of the first clamping tube 610, and the output terminal of the second operational amplifier circuit (OP2) 609 is connected to the first clamping tube 611 of the second operational amplifier circuit. The control terminal of the three transistors.

The first operational amplifier circuit (OP1) 608 further increases the fifth transistor 620 on the basis of the five-transistor (5T) operational amplifier, and the second operational amplifier circuit (OP2) 609 further increases the fifth transistor 620 on the basis of the five-transistor (5T) operational amplifier. Six transistors 621. The control terminal of the fifth transistor is connected to the control terminal of the sixth transistor, and is connected to the switching control signal CMDN. The switching control signal CMDN is the inversion signal of the control signal CMD in the foregoing embodiment, and is used to control the fifth transistor and the sixth transistor. The six transistors are turned on and off to switch the working states of the first operational amplifier circuit (OP1) 608 and the second operational amplifier circuit (OP2) 609, and at the same time only one operational amplifier circuit is working in the charge and discharge state. Thereby reducing the power consumption of the entire circuit unit.

When the switching control signal CMDN is "0", the fifth transistor 620 is turned off, the sixth transistor 621 is turned on, the second operational amplifier circuit (OP2) 609 works, the power supply of the first operational amplifier circuit (OP1) 608 is cut off, At the same time, the control terminal of the first clamping tube 610 will be pulled to a high level, the charging path will be closed, and the circuit will work in a discharging state at this time. When the switching control signal CMDN is "1", the fifth transistor 620 is turned on, the sixth transistor 621 is turned off, the first operational amplifier circuit (OP1) 608 works, and the power supply of the second operational amplifier circuit (OP2) 609 is cut off. At the same time, the control terminal of the second clamping tube 611 will be pulled down to a low level, and the discharge path will be closed. At this time, the circuit works in a charging state, thereby realizing the selection of the detection direction of the circuit. Compared with the foregoing embodiments, this embodiment only has one operational amplifier (OP1 or OP2) working, which can reduce the power consumption of the entire unit by about 50%, and can greatly reduce the power consumption during high-throughput integration under the same circuit area. overall power consumption. Compared with the working sequence of the circuit in the third embodiment, the switching control signal CMDN is the inverse signal of CMD, and other control signals are the same.

Fig. 7 is a schematic structural diagram of a gene sequencing device according to an embodiment of the present disclosure. As shown in Figure 7, the gene sequencing device of this embodiment includes a plurality of integrated micropore structural units 702 and a plurality of nanopore sequencing circuit units 706 described in any of the foregoing embodiments, and the micropore structural units 702 and nanopore sequencing The circuit units 706 are in one-to-one correspondence. Each micropore structural unit 702 includes a nanopore 704 , a common electrode 701 and a detection electrode 703 located on both sides of the nanopore 704 . The device can realize the micropore structural unit 702 by MEMS technology, and integrate the micropore structural unit 702 and the corresponding nanopore sequencing circuit unit 706 on the same chip, thereby forming a high-throughput gene sequencing device.

In some embodiments, multiple micropore structural units 702 can share a common electrode 701, and the output voltages of multiple nanopore sequencing circuit units 706 can be output to the shared common signal line 707 through a selection switch, and then passed through an analog-to-digital converter. 709 converts the signal into a digital signal and then outputs it, so as to realize the multiplexing of the analog-to-digital conversion function of the output voltage signal of the nanopore sequencing circuit unit 706 .

In some embodiments, the gene sequencing device further includes a common tail current source 708, one end of the common tail current source 708 is connected to the common signal line 707, and the other end is grounded.

The nanopore sequencing circuit unit of the embodiment of the present disclosure can be realized by using a CMOS circuit, has a very small circuit area, and is suitable for the integrated construction of a nanopore gene sequencing device with a flux of millions or even tens of millions of fluxes, which can greatly improve the integration degree , so as to achieve high throughput and high detection efficiency. In addition, the nanopore sequencing circuit unit of the embodiment of the present disclosure has bidirectional detection capability, which can further reduce the error rate and improve the detection accuracy of sequencing.

It should be noted that the above-mentioned embodiments can be combined freely according to needs, and the devices involved in the circuit are described as CMOS devices, and other devices, such as BJT, JFET, etc., can also implement the technical solution of the present disclosure. The above descriptions are only preferred implementations of the present disclosure. It should be pointed out that those skilled in the art can make several changes and improvements without departing from the principles of the present disclosure. These changes and improvements are also should be regarded as falling within the protection scope of the present disclosure.

Claims

A nanopore sequencing circuit unit, characterized in that the nanopore sequencing circuit unit is implemented using a CMOS circuit, and is used to detect bidirectional microcurrent signals of nanopores, which includes:

The nanopore clamping circuit is used to stabilize the detection electrode voltage on one side of the nanopore, and generate a fixed voltage difference between the two ends of the nanopore with the common electrode on the other side of the nanopore, by means of the voltage difference Driving single nucleotide molecules through the nanopore one by one; the nanopore clamping circuit includes a charging path composed of a first operational amplifier circuit and a first clamping tube, and a charging path composed of a second operational amplifier circuit and a second clamping tube. discharge path;

Integral reset circuit for integrally amplifying the bidirectional microcurrent signal of the nanopore and converting it into a voltage signal when the charging path and the discharging path of the nanopore clamping circuit are respectively turned on;

The output circuit is used to receive and output the voltage signal converted by the integral reset circuit.
The nanopore sequencing circuit unit according to claim 1, wherein the source of the first clamping tube is connected to the source of the second clamping tube and connected to the detection electrode; the first clamping tube is connected to the source of the second clamping tube; The drain of the clamping tube is connected to the drain of the second clamping tube and connected to the integral reset circuit.
The nanopore sequencing circuit unit according to claim 2, wherein the negative input terminal of the first operational amplifier circuit is connected to the detection electrode, the positive input terminal is connected to the common level, and the output terminal is connected to the first clamp The control end of the bit tube is connected; the negative input end of the second operational amplifier circuit is connected to the detection electrode, the positive input end is connected to the common level, and the output end is connected to the control end of the second clamping tube.
The nanopore sequencing circuit unit according to claim 1, wherein the first clamping tube includes a first transistor and a second transistor, and the second clamping tube includes a third transistor and a fourth transistor; wherein , the drain of the first transistor is connected to the source of the second transistor, the drain of the third transistor is connected to the source of the fourth transistor; the source of the first transistor is connected to the source of the third transistor The source is connected to the detection electrode; the drain of the second transistor is connected to the drain of the fourth transistor, and is connected to the integral reset circuit; the control terminal of the second transistor is connected to the The control terminal of the fourth transistor is connected to the first switching control signal; the first switching control signal controls the nanopore clamping circuit to switch between the charging path and the discharging path.
The nanopore sequencing circuit unit according to claim 4, wherein the negative input terminal of the first operational amplifier circuit is connected to the detection electrode, the positive input terminal is connected to a common level, and the output terminal is connected to the first transistor The negative input terminal of the second operational amplifier circuit is connected to the detection electrode, the positive input terminal is connected to the common level, and the output terminal is connected to the control terminal of the third transistor.
The nanopore sequencing circuit unit according to claim 3, wherein the first operational amplifier circuit includes a fifth transistor, the second operational amplifier circuit includes a sixth transistor, and the fifth transistor and the sixth transistor The control end of the control terminal is connected to the second switching control signal; the fifth transistor and the sixth transistor are used to respectively control the power conduction of the first operational amplifier circuit and the second operational amplifier circuit under the action of the second switching control signal switching on and off and controlling the nanopore clamp circuit to switch between the charging path and the discharging path.
The nanopore sequencing circuit unit according to claim 5 or 6, wherein the first operational amplifier circuit and the second operational amplifier circuit also include a bias voltage input terminal, wherein the bias voltage of the first operational amplifier circuit The first bias voltage is input to the input terminal of the set voltage, and the second bias voltage is input to the bias voltage input terminal of the second operational amplifier circuit.
The nanopore sequencing circuit unit according to claim 5, wherein the integration reset circuit includes an integration capacitor and a first reset switch, and the first end of the integration capacitor is connected to the first end of the first reset switch , connected to the drain of the second transistor and the drain of the fourth transistor at the same time, the second end of the integration capacitor is connected to the ground potential; the second end of the first reset switch is connected to the precharge voltage, It is used to periodically reset the voltage of the integrating capacitor.
The nanopore sequencing circuit unit according to claim 6, wherein the integration reset circuit includes an integration capacitor and a first reset switch, and the first end of the integration capacitor is connected to the first end of the first reset switch , connected to the drains of the first clamping tube and the second clamping tube at the same time, the second end of the integration capacitor is connected to the ground potential; the second end of the first reset switch is connected to the precharge voltage for periodic to reset the voltage of the integrating capacitor.
The nanopore sequencing circuit unit according to claim 8 or 9, wherein the output circuit includes a second source follower and a selection switch, and the input end of the second source follower is connected to the integrating capacitor The output end is connected to the first end of the selection switch, and the second end of the selection switch outputs the voltage signal converted by the integral reset circuit to the common signal line.
The nanopore sequencing circuit unit according to claim 10, wherein the nanopore sequencing circuit unit further comprises a second reset switch, the first terminal of the second reset switch is connected to the detection electrode, and the second terminal is connected to the detection electrode. connected to the common level for fixing the voltage of the detection electrode at the common level when the nanopore clamp circuit switches between the charging path and the discharging path.
A gene sequencing device, characterized in that it includes a chip integrated with a plurality of micropore structural units and a plurality of nanopore sequencing circuit units as claimed in any one of claims 1-11, the micropore structural unit comprising nano Holes, common electrodes and detection electrodes located on both sides of the nanopore; the plurality of nanopore sequencing circuit units are correspondingly connected to the plurality of micropore structural units, and are used to measure the bidirectional micropore of the nanopore in the corresponding micropore structural unit current signal.
The gene sequencing device according to claim 12, further comprising a common signal line and an analog-to-digital conversion circuit connected to the common signal line, the common signal line is used to receive the output of the nanopore sequencing circuit unit the voltage signal, and the analog-to-digital conversion circuit is used to convert the voltage signal into a digital signal.
The gene sequencing device according to claim 13, further comprising a common tail current source, one end of the common tail current source is connected to the common signal line, and the other end is grounded.
The gene sequencing device according to claim 12, wherein the chip comprises a MEMS chip realizing the micropore structure unit.