WO2023050288A1 - 检波电路及相关电子装置 - Google Patents

检波电路及相关电子装置 Download PDF

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Publication number
WO2023050288A1
WO2023050288A1 PCT/CN2021/122114 CN2021122114W WO2023050288A1 WO 2023050288 A1 WO2023050288 A1 WO 2023050288A1 CN 2021122114 W CN2021122114 W CN 2021122114W WO 2023050288 A1 WO2023050288 A1 WO 2023050288A1
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Prior art keywords
detection circuit
switch
sampling mode
operational amplifier
specific wave
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PCT/CN2021/122114
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English (en)
French (fr)
Inventor
杜灿鸿
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深圳市汇顶科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 深圳市汇顶科技股份有限公司 filed Critical 深圳市汇顶科技股份有限公司
Priority to CN202180102738.7A priority Critical patent/CN118019991A/zh
Priority to PCT/CN2021/122114 priority patent/WO2023050288A1/zh
Publication of WO2023050288A1 publication Critical patent/WO2023050288A1/zh
Priority to US18/453,862 priority patent/US20230393177A1/en

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/04—Measuring peak values or amplitude or envelope of ac or of pulses
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R23/00—Arrangements for measuring frequencies; Arrangements for analysing frequency spectra
    • G01R23/16—Spectrum analysis; Fourier analysis

Definitions

  • the present application relates to a circuit, in particular to a detection circuit and related electronic devices.
  • sine waves are often used as the carrier of the detection circuit.
  • the purpose of sensing variables is achieved by detecting the amplitude of the sine wave.
  • Detection circuits are required to detect the amplitude of the sine wave.
  • the common detection circuit is a diode detection circuit, but its disadvantage is that it requires a strong input signal amplitude, which is not suitable for weak signal detection.
  • peak detection circuits synchronous detection circuits, phase-sensitive detection circuits, etc. in the industry. These detection circuits have the disadvantages of low detection sensitivity or complex circuit structure. Therefore, how to solve the above problems has become one of the urgent problems in this field.
  • One of the objectives of the present application is to disclose a detection circuit and related electronic devices to solve the above problems.
  • An embodiment of the present application discloses a detection circuit for judging the amplitude of a received signal generated by a receiver after receiving an input signal.
  • the detection circuit includes: an operational amplifier with a positive terminal, a negative terminal and an output terminal; a capacitor unit , coupled between the output terminal and the negative terminal of the operational amplifier; a reset switch, arranged in parallel with the capacitor unit; a first switch, coupled to the reference voltage and the output terminal of the receiver and a second switch, coupled between the output terminal of the receiver and the negative terminal of the operational amplifier; wherein: in the reset phase, the reset switch is turned on and the The second switch is non-conductive, the output terminal of the operational amplifier outputs the reference voltage; and in a general stage, the reset switch is non-conductive, and the received signal includes a plurality of waves with a period T, In the period T of the detection circuit corresponding to the first specific wave among the plurality of waves, the time of T*R is set to sampling mode, and the time of T*(1-R) is set to non-s
  • An embodiment of the present application discloses an electronic device, including the above detection circuit.
  • the detection circuit and the related electronic device of the present application can achieve the effect of high sensitivity with a simple circuit.
  • FIG. 1 is a schematic diagram of a first embodiment of a detection circuit of the present application.
  • FIG. 2 is a timing diagram of the first embodiment of the operation of the detection circuit of FIG. 1 .
  • FIG. 3 is a timing diagram of a second embodiment of the operation of the detection circuit of FIG. 1 .
  • FIG. 4 is a timing diagram of a third embodiment of the operation of the detection circuit of FIG. 1 .
  • FIG. 5 is a timing diagram of a fourth embodiment of the operation of the detection circuit of FIG. 1 .
  • FIG. 6 is a schematic diagram of a second embodiment of the detection circuit of the present application.
  • FIG. 7 is a schematic diagram of a third embodiment of the detection circuit of the present application.
  • FIG. 8 is a schematic diagram of the first embodiment of the control circuit of the detection circuit of the present application.
  • FIG. 9 is a schematic diagram of a second embodiment of the control circuit of the detection circuit of the present application.
  • first and second features are in direct contact with each other; and may also include additional components are formed between the first and second features, such that the first and second features may not be in direct contact.
  • this disclosure may reuse reference symbols and/or labels in various embodiments. Such repetition is for the sake of brevity and clarity, and does not in itself represent a relationship between the different embodiments and/or configurations discussed.
  • FIG. 1 is a schematic diagram of a first embodiment of a detection circuit of the present application.
  • the detection circuit 102 is used to determine the amplitude of the received signal Vs generated by the receiver 104 after receiving the input signal RX.
  • the detection circuit 102 includes an operational amplifier 106 , a capacitor unit 108 , a reset switch 112 , a first switch 114 and a second switch 116 .
  • the operational amplifier 106 has a positive terminal (+), a negative terminal (-) and an output terminal.
  • the capacitor unit 108 is coupled between the output terminal of the operational amplifier 106 and the negative terminal ( ⁇ ).
  • the reset switch 112 is arranged in parallel with the capacitor unit 108 .
  • the first switch 114 is coupled between the reference voltage Vx and the output terminal of the receiver 104 .
  • the second switch 116 is coupled between the output terminal of the receiver 104 and the negative terminal ( ⁇ ) of the operational amplifier 106 .
  • the positive terminal (+) of the operational amplifier 106 is coupled to the reference voltage Vx.
  • the reset switch 112 is controlled by the signal rst
  • the first switch 114 is controlled by the signal ck1
  • the second switch 116 is controlled by the signal ck2.
  • the reset switch 112 , the first switch 114 and the second switch 116 can be implemented by using N-type transistors, but the application is not limited thereto.
  • the capacitance value of the capacitance unit is CI.
  • the receiver 104 equivalently includes a signal generator 120 and a receiver capacitor 118 .
  • the signal generator 120 is used for generating the received signal Vs according to the input signal RX.
  • the receiver capacitor 118 is coupled to the signal generator 120 for receiving the received signal Vs. Wherein the capacitance value of the receiver capacitor 118 is CS.
  • FIG. 2 is a timing diagram of the first embodiment of the operation of the detection circuit in FIG. 1 .
  • the received signal Vs includes a plurality of waves with a period T (eg time point T0 to time point T2 ). As shown in the figure, the received signal Vs is a sine wave.
  • the detection circuit 102 of the present application can be used to sample the amplitude of the received signal Vs. Since the amplitude of the received signal Vs may be very small, in order to increase the sensitivity of the detection circuit 102, the detection circuit 102 will integrate multiple cycles of the received signal Vs Amplitude sampling is performed in the same way, and the sampling results of multiple cycles are accumulated.
  • the detection circuit 102 of the present application is not only applicable to the case where the received signal Vs is a sine wave.
  • the received signal Vs may also be in the form of a triangular wave or a trapezoidal wave. As long as the slope of the rising edge of the received signal Vs from the trough to the peak is less than 90 degrees, and the slope of the falling edge of the received signal Vs from the peak to the trough is greater than -90 degrees.
  • the detection circuit 102 Before the time point T0 and after the time point T7, the detection circuit 102 enters a reset phase.
  • the signal rst is at a high voltage level so that the reset switch 112 is turned on, and the signal ck2 is at a low voltage level so that the second switch 116 is not turned on. Since the operational amplifier 106 forms a negative feedback, the operational amplifier 106 The output terminal and the negative terminal (-) voltage will be limited to be the same as the positive terminal (+) voltage, that is, the reference voltage Vx. And the voltage at both ends of the capacitor unit 108 is the same so that the capacitor value is reset to zero.
  • the signal ck1 may be at a high voltage level to turn on the first switch 114 , so as to reset the equivalent capacitance 118 of the receiver 104 by the way.
  • time point T0, time point T2, time point T4 and time point T6 are aligned with four consecutive valleys of the received signal Vs; time point T1, time point T3 and time point T5 are aligned with the received signal Three consecutive peaks of Vs.
  • the time length from time point T0 to time point T2 , the time length from time point T2 to time point T4 , and the time length from time point T4 to time point T6 are all equal to the period T of the received signal Vs.
  • the first switch 114 and the second switch 116 need to be switched according to the frequency of the received signal Vs.
  • the signal The low voltage level of ck1 makes the first switch 114 non-conductive, and the high voltage level of the signal ck2 makes the second switch 116 conductive, so that the detection circuit 102 enters the sampling mode.
  • the first switch 114 is turned on and the second switch 116 is turned off, causing the detection circuit 102 to enter a non-sampling mode. Therefore, for the three consecutive cycles starting from the time point T0, the detection circuit 102 is in the sampling mode for half of the time (T*0.5) in each cycle, and the detection circuit 102 is in the sampling mode for the other half of the time (T*0.5). The non-sampling mode.
  • the voltage variation of the received signal Vs is reflected in a specific ratio and accumulated at the output terminal of the operational amplifier 106 , and contributes to ⁇ Vout.
  • N is an integer
  • N in FIG. 2 is 3 for illustrative purposes only. The scope of N is not limited in the present application, as long as it is an integer greater than 0. However, in order to realize the advantages of the present application, N can be increased, for example, in the range of 100 to 1000 orders of magnitude.
  • the voltage change of the received signal Vs is not reflected and accumulated at the output terminal of the operational amplifier 106 , so that the voltage Vout at the output terminal of the operational amplifier 106 remains unchanged in the non-sampling mode.
  • the received signal Vs rises from the trough to the peak, but because the first switch 114 is turned on and the second switch 116 is not turned on, the voltage change of the received signal Vs is 2 *VA does not affect the voltage Vout at the output of the operational amplifier 106 . Therefore, the accumulated amount of the voltage Vout from the voltage change of the received signal Vs from the time point T1 to the time point T2 will not be offset.
  • FIG. 3 is a timing diagram of a second embodiment of the detection circuit in FIG. 1 .
  • FIG. 4 is a timing diagram of a third embodiment of the detection circuit in FIG. 1 .
  • the difference between FIG. 4 and FIG. 2 is that the sampling mode in FIG. 4 starts after a period of time after the peak of the received signal Vs, and ends before the trough arrives. Therefore, for three consecutive cycles starting from time point T0, the detection circuit 102 is in the sampling mode for less than half of the time (for example T*0.3) in each cycle, and more than half of the time (for example T*0.7) The detection circuit 102 is in the non-sampling mode.
  • FIG. 5 is a timing diagram of a fourth embodiment of the detection circuit in FIG. 1 .
  • the scenario shown in Fig. 5 is that when it is known in advance that in certain periods of the received signal Vs, the received signal Vs will have interference or signal discontinuity (for example, as shown in Fig. 5, between time point T3 and time point T4 Between the received signal Vs there is interference; between the time point T7 and the time point T8, the received signal Vs is discontinuous), then avoid letting the detection circuit 102 have interference or signal discontinuity in the received signal Vs to enter sampling mode.
  • the advantage of the present application is that the detection and integration of the target period can be selectively performed by flexibly controlling the detection circuit 102 , and multiple target periods can be discontinuous, thereby improving the accuracy of the detection result. In order to achieve the ultimate goal of effectively anti-jamming and improving the signal-to-noise ratio of the detection results.
  • FIG. 6 is a schematic diagram of a second embodiment of the detection circuit of the present application. The difference between the detection circuit 602 in FIG. 6 and the detection circuit 102 in FIG. Two calibration switches 126 . One terminal of the calibration capacitor 122 is coupled to the output terminal of the receiver 104 .
  • the first correction switch 124 is coupled between the other end of the correction capacitor 122 and the first correction voltage V1, wherein the first correction switch 124 is controlled by the signal ck1, so that the conduction state of the first correction switch 124 is synchronized with that of the first switch 114 .
  • the second correction switch 126 is coupled between the other end of the correction capacitor 122 and the second correction voltage V2, wherein the second correction switch 126 is controlled by the signal ck2, so that the conduction state of the second correction switch 126 is synchronized with the second Switch 116.
  • the capacitance value of the calibration capacitor 122 is CB.
  • the first correction switch 124 and the second correction switch 126 are controlled by the signals ck1 and ck2, and will contribute the voltage of CB/CI*(V1-V2) and accumulate it in the operational amplifier 106 output.
  • CB of the correction capacitor 122 By adjusting the capacitance value CB of the correction capacitor 122, the first correction voltage V1 and/or the second correction voltage V2, CB/CI*(V1-V2) can just offset the voltage at the output terminal of the operational amplifier 106 caused by non-ideal factors
  • the value of the static noise carried by Vout prevents the static noise from continuously accumulating in the multi-sampling mode.
  • FIG. 7 is a schematic diagram of a third embodiment of the detection circuit of the present application.
  • the difference between the detection circuit 702 of FIG. 7 and the detection circuit 102 of FIG. 1 is that the positive input terminal (+ ) is coupled to the third correction voltage Vc.
  • the purpose of the above changes is the same as that of the detection circuit 602 in FIG. 6 , which is to offset the static noise of the voltage Vout at the output terminal of the operational amplifier 106 caused by non-ideal factors.
  • the voltage difference between the third calibration voltage Vc and the reference voltage Vx will be reflected in a specific ratio and accumulated at the output terminal of the operational amplifier 106, that is, the contribution of CS/CI*(Vc-Vx) voltage and is accumulated at the output of the operational amplifier 106.
  • the third correction voltage Vc it is possible to make CS/CI*(Vc-Vx) just offset the value of the static noise caused by the non-ideal factors in the voltage Vout of the output terminal of the operational amplifier 106, so that the static noise will not increase Accumulated continuously in subsampling mode.
  • FIG. 8 is a schematic diagram of the first embodiment of the control circuit of the detection circuit of the present application.
  • the control circuit 105 may be included in the detection circuit 102 , the detection circuit 602 and/or the detection circuit 702 .
  • the control circuit 105 generates a first control signal ck1 , a second control signal ck2 and a reset signal rst according to a reference clock (not shown in the figure).
  • control circuit 105 is also used to generate the third control signal ck3 to control the transmitter 107 to generate the output signal TX, wherein the third control signal ck3 is periodic, and the period is T, wherein the output signal TX becomes The input signal RX enters the receiver 104 .
  • the transmitter 107 may be a first transducer and the receiver 104 may be a second transducer.
  • a transducer is a device that converts one form of energy into another. These forms of energy may include electrical energy, mechanical energy, electromagnetic energy, light energy, chemical energy, sound energy, and thermal energy, etc., which are not limited in this application, and the transducer may include any device capable of converting energy.
  • the first transducer and the second transducer can be used in a flow meter to sense the flow velocity and/or flow rate of gas or liquid.
  • the first transducer and the second transducer may be installed in a pipeline, and the emitting direction of the first transducer faces the second transducer.
  • the distance between the first transducer and the second transducer is L, and L is greater than zero.
  • a fluid (such as liquid or gas) with a flow velocity v flows through the first transducer and the second transducer sequentially along the direction in which the pipeline is arranged.
  • the output signal TX of the first transducer passes through the fluid with a flow velocity v and is reflected by the pipe wall of the pipeline to become an input signal RX, which is received by the second transducer and converted to receive Signal Vs.
  • the detection circuit 102 , the detection circuit 602 and/or the detection circuit 702 of the present application may sample the amplitude of the received signal Vs multiple times in multiple sampling modes, and accumulate the sampling results. Its detailed operation is as described above.
  • FIG. 9 is a schematic diagram of a second embodiment of the control circuit of the detection circuit of the present application.
  • the difference between the control circuit 905 and the control circuit 105 in FIG. 8 is that the control circuit 905 generates the first control signal ck1 , the second control signal ck2 and the reset signal rst according to the received signal Vs.
  • the control circuit 905 may be included in the detection circuit 102 , the detection circuit 602 and/or the detection circuit 702 . From the above description, it can be seen that the control circuit 105 is applied to a system that can control both the transmitter and the receiver; the control circuit 905 is applied to a system that only controls the receiver. Since the information of the transmitter cannot be predicted, it needs to be generated according to the received signal Vs.
  • the first control signal ck1, the second control signal ck2 and the reset signal rst are examples of the received signal Vs.
  • the alignment of the peaks and troughs of the first control signal ck1 , the second control signal ck2 , and the received signal Vs can be obtained statistically. For example, for multiple different phases of the first control signal ck1 and the second control signal ck2, the amplitude of the received signal Vs is sampled, and the phase that can make the accumulation result of the voltage Vout at the output terminal of the operational amplifier 106 most significant is found, when Make the best phase.
  • the present application also proposes an electronic device including the detection circuit 102 , the detection circuit 602 and/or the detection circuit 702 .
  • the electronic devices include but are not limited to mobile communication equipment, ultra-mobile personal computer equipment, portable entertainment equipment and other electronic equipment with data interaction functions.
  • the characteristic of mobile communication equipment is that it has mobile communication functions, and its main goal is to provide voice and data communication.
  • Such terminals include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones.
  • Ultra-mobile personal computer devices belong to the category of personal computers, which have computing and processing functions, and generally have mobile Internet access features.
  • Such terminals include: PDA, MID and UMPC equipment, such as iPad.
  • Portable entertainment devices can display and play multimedia content.
  • Such devices include: audio and video players (such as iPod), handheld game consoles, e-books, as well as smart toys and portable car navigation devices.

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Abstract

本申请公开了一种检波电路及相关电子装置。检波电路（102）用来判断接收器（104）接收输入信号后产生的接收信号的幅度，包括：运算放大器（106），具有正端、负端与输出端；电容单元（108），耦接于所述运算放大器（106）的所述输出端与所述负端之间；重置开关（112），与所述电容单元（108）并联设置；第一开关（114），耦接于参考电压及所述接收器（104）的输出端之间；以及第二开关（116），耦接于所述接收器（104）的所述输出端及所述运算放大器（106）的所述负端之间；其中在一般阶段，接收信号包含周期为T的多个波，检波电路（102）在对应多个波中的第一及第二特定波的周期T中，有T*R的时间被设置为采样模式，以及有T*(1-R)的时间被设置为非采样模式。

Description

检波电路及相关电子装置 技术领域
本申请涉及一种电路，尤其涉及一种检波电路及相关电子装置。
背景技术
现代电子传感技术中，经常使用正弦波作为检测电路的载波，通过检测正弦波的幅度达到感测变量的目的，检测正弦波的幅度需要用到检波电路。
常见的检波电路是二极管检波电路，但其缺点是要求输入信号幅度较强，不适合微弱信号检波。另外业内现有还有峰值检波电路、同步检波电路、相敏检波电路等，不一一赘述，这些检波电路存在检波灵敏度低或者电路结构复杂的缺点。因此如何解决上述问题，已成为本领域亟需解决的问题之一。
发明内容
本申请的目的之一在于公开一种检波电路及相关电子装置，来解决上述问题。
本申请的一实施例公开了一种检波电路，用来判断接收器接收输入信号后产生的接收信号的幅度，所述检波电路包括：运算放大器，具有正端、负端与输出端；电容单元，耦接于所述运算放大器的所述输出端与所述负端之间；重置开关，与所述电容单元并联设置；第一开关，耦接于参考电压及所述接收器的输出端之间；以及第二开关，耦接于所述接收器的所述输出端及所述运算放大器的所述负端之间；其中：在重置阶段，所述重置开关导通及所述第二开关不导通，所述运算放大器的所述输出端输出所述参考电压；以及在一般阶段，所述 重置开关不导通，以及所述接收信号包含周期为T的多个波，所述检波电路在对应所述多个波中的第一特定波的周期T中，有T*R的时间被设置为采样模式，以及有T*(1-R)的时间被设置为非采样模式，其中R大于0且小于1；以及所述检波电路在对应所述多个波中的第二特定波的周期T中，有T*R的时间被设置为所述采样模式，以及有T*(1-R)的时间被设置为所述非采样模式，其中：在所述采样模式，所述第一开关不导通且所述第二开端导通，使所述接收信号在所述采样模式期间的幅度改变依特定比例反应且累加在所述运算放大器的所述输出端；以及在所述非采样模式，所述第一开关导通且所述第二开端不导通，使所述接收器产生的所述接收信号在所述非采样模式的幅度改变不反应且不累加在所述运算放大器的所述输出端，使所述运算放大器的所述输出端的电压在所述非采样模式维持不变。
本申请的一实施例公开了一种电子装置，包括上述的检波电路。
相较于现有技术，本申请的检波电路及相关电子装置能够利用简单的电路达到高灵敏度的效果。
附图说明
图1为本申请的检波电路的第一实施例的示意图。
图2为图1的检波电路操作上的第一实施例的时序图。
图3为图1的检波电路操作上的第二实施例的时序图。
图4为图1的检波电路操作上的第三实施例的时序图。
图5为图1的检波电路操作上的第四实施例的时序图。
图6为本申请的检波电路的第二实施例的示意图。
图7为本申请的检波电路的第三实施例的示意图。
图8为本申请的检波电路的控制电路的第一实施例的示意图。
图9为本申请的检波电路的控制电路的第二实施例的示意图。
具体实施方式
以下揭示内容提供了多种实施方式或例示，其能用以实现本揭示内容的不同特征。下文所述之组件与配置的具体例子系用以简化本揭示内容。当可想见，这些叙述仅为例示，其本意并非用于限制本揭示内容。举例来说，在下文的描述中，将一第一特征形成于一第二特征上或之上，可能包括某些实施例其中所述的第一与第二特征彼此直接接触；且也可能包括某些实施例其中还有额外的组件形成于上述第一与第二特征之间，而使得第一与第二特征可能没有直接接触。此外，本揭示内容可能会在多个实施例中重复使用组件符号和/或标号。此种重复使用乃是基于简洁与清楚的目的，且其本身不代表所讨论的不同实施例和/或组态之间的关系。
虽然用以界定本申请较广范围的数值范围与参数皆是约略的数值，此处已尽可能精确地呈现具体实施例中的相关数值。然而，任何数值本质上不可避免地含有因个别测试方法所致的标准偏差。在此处，「约」通常系指实际数值在一特定数值或范围的正负10％、5％、1％或0.5％之内。或者是，「约」一词代表实际数值落在平均值的可接受标准误差之内，视本申请所属技术领域中具有通常知识者的考虑而定。当可理解，除了实验例之外，或除非另有明确的说明，此处所用的所有范围、数量、数值与百分比(例如用以描述材料用量、时间长短、温度、操作条件、数量比例及其他相似者)均经过「约」的修饰。因此，除非另有相反的说明，本说明书与附随申请专利范围所揭示的数值参数皆为约略的数值，且可视需求而更动。至少应将这些数值参数理解为所指出的有效位数与套用一般进位法所得到的数值。在此处，将数值范围表示成由一端点至另一端点或介于二端点之间；除非另有说明，此处所述的数值范围皆包括端点。
图1为本申请的检波电路的第一实施例的示意图。检波电路102用来判断接收器104接收输入信号RX后产生的接收信号Vs的幅度。检波电路102包括运算放大器106、电容单元108、重置开关112、 第一开关114及第二开关116。其中运算放大器106具有正端(+)、负端(-)与输出端。电容单元108耦接于运算放大器106的输出端与负端(-)之间。重置开关112与电容单元108并联设置。第一开关114耦接于参考电压Vx及接收器104的输出端之间。第二开关116耦接于接收器104的所述输出端及运算放大器106的负端(-)之间。运算放大器106的正端(+)耦接于参考电压Vx。其中重置开关112受信号rst控制，第一开关114受信号ck1控制，以及第二开关116受信号ck2控制。在本实施例中，重置开关112、第一开关114以及第二开关116可以使用N型晶体管来实现，但本申请不以此为限。其中电容单元的电容值为CI。
接收器104等效地包含信号产生器120及接收器电容118。信号产生器120用来依据输入信号RX产生接收信号Vs。接收器电容118耦接至信号产生器120，用来接收接收信号Vs。其中接收器电容118的电容值为CS。
请同时参考图2，图2为图1的检波电路操作上的第一实施例的时序图。接收信号Vs包含周期为T(例如时间点T0至时间点T2)的多个波。如图所示，接收信号Vs为正弦波。本申请的检波电路102可用来对接收信号Vs的幅度进行采样，由于接收信号Vs的幅度可能很小，因此为了增加检波电路102的灵敏度，检波电路102会针对多个周期的接收信号Vs以积分的方式进行幅度采样，并将多个周期的采样结果累积起来。本申请的检波电路102不仅适用于接收信号Vs为正弦波的情况。在某些实施例中，接收信号Vs也可以是三角波或梯型波等态样。只要接收信号Vs由波谷升至波峰的上升沿的斜率小于90度，及接收信号Vs由波峰降至波谷的下降沿的斜率大于-90度即可。
在时间点T0之前及时间点T7之后，检波电路102进入重置阶段。在所述重置阶段，信号rst为高电压电平使重置开关112导通，信号ck2为低电压电平使第二开关116不导通，由于运算放大器106形成负反馈，运算放大器106的输出端及负端(-)电压会被限制和 正端(+)电压相同，即参考电压Vx。且电容单元108两端电压相同使其电容值被清零。此外，在所述重置阶段，信号ck1可以为高电压电平使第一开关114导通，以顺便对接收器104的等效电容118进行重置。
在时间点T0及时间点T7之间为一般阶段，重置开关112不导通。在图2所示的操作实施例中，时间点T0、时间点T2、时间点T4及时间点T6对齐接收信号Vs的连续四个波谷；时间点T1、时间点T3及时间点T5对齐接收信号Vs的连续三个波峰。换句话说，时间点T0至时间点T2的时间长度、时间点T2至时间点T4的时间长度以及时间点T4至时间点T6的时间长度都等于接收信号Vs的周期T。
具体来说，在所述一般阶段若要对接收信号Vs进行幅度的采样，第一开关114和第二开关116需要依据接收信号Vs的频率进行开关。在图2所示的操作实施例中，在时间点T1至时间点T2之间的时间、时间点T3至时间点T4之间的时间、以及时间点T5至时间点T6之间的时间，信号ck1为低电压电平使第一开关114不导通，信号ck2为高电压电平使第二开关116导通，使检波电路102进入采样模式。在所述一般阶段的其馀时间，第一开关114导通且第二开关116不导通，使检波电路102进入非采样模式。因此，对时间点T0开始的连续三个周期来说，各周期中有一半的时间(T*0.5)检波电路102在所述采样模式，以及另一半的时间(T*0.5)检波电路102在所述非采样模式。
如图2所示，在每次采样模式中，接收信号Vs的电压改变量会依特定比例反应且累加在运算放大器106的输出端，并贡献ΔVout。以时间点T1至时间点T2之间的时间为例，若接收信号Vs的幅度为VA，接收信号Vs由波峰降至波谷，即接收信号Vs在时间点T1至时间点T2的电压改变量为-2*VA，则ΔVout＝2*VA*CS/CI，使运算放大器106的输出端的电压Vout由参考电压Vx往上累积。由于ΔVout和接收信号Vs的幅度VA正比，因此可以实现检波作用，并且每重 复一次所述采样模式的过程，运算放大器106的输出端的电压Vout都会增加ΔVout，可以重复针对N个周期进行N次所述采样模式，使输出电压Vout＝Vx+N*ΔVout，不断累积上升。经过多次积分，以提高检波电路102的灵敏度。其中N为整数，图2中N为3仅为示意，本申请不限制N的范围，只要为大于0的整数即可。但为体现本申请的优势，N可以被提高，例如在100到1000的数量级范围。
在每次非采样模式中，接收信号Vs的电压改变量不会反应且不会累加在运算放大器106的输出端，使运算放大器106的输出端的电压Vout在所述非采样模式维持不变。以时间点T2至时间点T3之间的时间为例，接收信号Vs由波谷升至波峰，但因第一开关114导通且第二开关116不导通，因此接收信号Vs的电压改变量2*VA不会影响运算放大器106的输出端的电压Vout。因此不会抵销掉时间点T1至时间点T2接收信号Vs的电压改变量对电压Vout累加的量。
请参考图3，图3为图1的检波电路操作上的第二实施例的时序图。图3和图2的差别在于，图3中的采样模式是在接收信号Vs由波谷升至波峰的时间进行，即图3中的采样模式下，接收信号Vs的电压改变量为2*VA，则ΔVout＝-2*VA*CS/CI。也就是使运算放大器106的输出端的电压Vout由参考电压Vx往下以负的方式累积。
请参考图4，图4为图1的检波电路操作上的第三实施例的时序图。图4和图2的差别在于，图4中的采样模式是从接收信号Vs的波峰之后一段时间才开始进行，并在波谷来到之前便结束。因此，对时间点T0开始的连续三个周期来说，各周期中有不到一半的时间(例如T*0.3)检波电路102在所述采样模式，以及超过一半的时间(例如T*0.7)检波电路102在所述非采样模式。这样一来，图4中的采样模式下，接收信号Vs的电压改变量不会再是-2*VA，而是为-2*X*VA，其中X的值小于1且大于0，则ΔVout＝2*X*VA*CS/CI。也就是使运算放大器106的输出端的电压Vout由参考电压Vx往上累积，但累积的量相较于图2小。
请参考图5，图5为图1的检波电路操作上的第四实施例的时序 图。图5所要表达的场景为，当预先得知在接收信号Vs的某些周期中，接收信号Vs会有干扰或信号不连续的情况(例如如图5所示，在时间点T3至时间点T4之间，接收信号Vs有出现干扰的状况；在时间点T7至时间点T8之间，接收信号Vs有不连续的状况)，则避开让检波电路102在接收信号Vs有干扰或信号不连续时进入采样模式。因此，本申请的好处在于可以通过灵活地控制检波电路102，来选择性地对目标周期进行检波积分，且多个目标周期可以是不连续的，藉此来提高检测结果的精度。以达到有效抗干扰，提高检波结果的信噪比的最终目的。
在某些实施例中，由于非理想性因素，例如器件失调、寄生电容等原因，会使运算放大器106的输出端的电压Vout带有静态噪声，造成检波电路102的动态范围被占用。图6为本申请的检波电路的第二实施例的示意图，图6的检波电路602和图1的检波电路102的差异在于，检波电路602中额外包含校正电容122、第一校正开关124以及第二校正开关126。校正电容122的一端耦接于接收器104的输出端。第一校正开关124耦接于校正电容122的另一端以及第一校正电压V1之间，其中第一校正开关124受信号ck1控制，使第一校正开关124的导通状态同步于第一开关114。第二校正开关126耦接于校正电容122的所述另一端以及第二校正电压V2之间，其中第二校正开关126受信号ck2控制，使第二校正开关126的导通状态同步于第二开关116。其中校正电容122的电容值为CB。
图6的检波电路602在每次采样模式中，第一校正开关124以及第二校正开关126受到信号ck1和ck2的控制，会贡献CB/CI*(V1-V2)的电压并累加在运算放大器106的输出端。通过调整校正电容122的电容值CB、第一校正电压V1及/或第二校正电压V2，可以使CB/CI*(V1-V2)刚好抵销非理想性因素导致运算放大器106的输出端的电压Vout带有的静态噪声的值，使静态噪声不会在多次采样模式下不断地积累。
图7为本申请的检波电路的第三实施例的示意图，图7的检波电 路702和图1的检波电路102的差异在于，图7的检波电路702的运算放大器106的的正输入端(+)耦接至第三校正电压Vc。上述变化的目的和图6的检波电路602的目的相同，都是为了抵销非理想性因素导致运算放大器106的输出端的电压Vout带有的静态噪声。
具体来说，在每次采样模式中，第三校正电压Vc和参考电压Vx的电压差会依特定比例反应且累加在运算放大器106的输出端，即贡献CS/CI*(Vc-Vx)的电压并累加在运算放大器106的输出端。通过调整第三校正电压Vc，可以使CS/CI*(Vc-Vx)刚好抵销非理想性因素导致运算放大器106的输出端的电压Vout带有的静态噪声的值，使静态噪声不会在多次采样模式下不断地积累。
图8为本申请的检波电路的控制电路的第一实施例的示意图。控制电路105可被包含在检波电路102、检波电路602及/或检波电路702中。控制电路105依据参考时脉(未绘示于图中)产生第一控制信号ck1、第二控制信号ck2以及重置信号rst。
在本实施例中，控制电路105还用来产生第三控制信号ck3以控制传送器107产生输出信号TX，其中第三控制信号ck3为周期性，周期为T，其中输出信号TX经过通道后成为输入信号RX进入接收器104。
在某些实施例中，传送器107可以是第一换能器，接收器104则可以是第二换能器。换能器是将一种形式的能量转化成另一种形式的器件。这些能量形式可能包括电能、机械能、电磁能、光能、化学能、声能和热能等，本申请并不多做限制，换能器可包括任何能够转化能量的器件。
所述第一换能器以及所述第二换能器可用于流量计中，用来感测气体、液体的流速及/或流量。举例来说，所述第一换能器和所述第二换能器可安装于管路中，且所述第一换能器的发射方向面对所述第二换能器。所述第一换能器和所述第二换能器之间的距离为L，且L大于零。具有流速v的流体(例如液体或是气体)沿所述管路的设置方向依序流过所述第一换能器和所述第二换能器。
所述第一换能器的输出信号TX经过具有流速v的流体，并经所述管路的管壁反射后，成为输入信号RX，并且被所述第二换能器所接收并转换为接收信号Vs。而本申请的检波电路102、检波电路602及/或检波电路702可以在多个采样模式下对接收信号Vs的幅度进行多次采样，并累加采样结果。其详细操作如前所述。
图9为本申请的检波电路的控制电路的第二实施例的示意图。控制电路905和图8的控制电路105的差异在于，控制电路905依据接收信号Vs产生第一控制信号ck1、第二控制信号ck2以及重置信号rst。控制电路905可被包含在检波电路102、检波电路602及/或检波电路702中。通过以上的说明可知，控制电路105应用于可同时控制传送器与接收器的系统；控制电路905则应用于单纯控制接收器的系统，因无法预知传送器的信息，因此需要依据接收信号Vs产生第一控制信号ck1、第二控制信号ck2以及重置信号rst。
在本申请中，无论是图8或图9的控制器配置方式，第一控制信号ck1、第二控制信号ck2和接收信号Vs的波峰和波谷的对齐方式可以采用统计的方式得到。例如针对第一控制信号ck1及第二控制信号ck2的多种不同的相位，对接收信号Vs的幅度进行采样，并找出能使运算放大器106的输出端的电压Vout累积结果最显著的相位，当作最佳的相位。
本申请还提出一种包含检波电路102、检波电路602及/或检波电路702的电子装置。具体的，所述电子装置包括但不限于移动通信设备、超移动个人计算机设备、便携式娱乐设备和其他具有数据交互功能的电子设备。移动通信设备的特点是具备移动通信功能，并且以提供话音、数据通信为主要目标。这类终端包括：智能手机(例如iPhone)、多媒体手机、功能性手机，以及低端手机等。超移动个人计算机设备属于个人计算机的范畴，有计算和处理功能，一般也具备移动上网特性。这类终端包括：PDA、MID和UMPC设备等，例如iPad。便携式娱乐设备可以显示和播放多媒体内容。该类设备包括：音频、视频播放器(例如iPod)，掌上游戏机，电子书，以及智能玩具和便携式车 载导航设备。
上文的叙述简要地提出了本申请某些实施例之特征，而使得本申请所属技术领域具有通常知识者能够更全面地理解本揭示内容的多种态样。本申请所属技术领域具有通常知识者当可明了，其可轻易地利用本揭示内容作为基础，来设计或更动其他工艺与结构，以实现与此处所述之实施方式相同的目的和/或达到相同的优点。本申请所属技术领域具有通常知识者应当明白，这些均等的实施方式仍属于本揭示内容之精神与范围，且其可进行各种变更、替代与更动，而不会悖离本揭示内容之精神与范围。

Claims (15)

  1. 一种检波电路，用来判断接收器接收输入信号后产生的接收信号的幅度，其特征在于，所述检波电路包括：
    运算放大器，具有正端、负端与输出端；
    电容单元，耦接于所述运算放大器的所述输出端与所述负端之间；
    重置开关，与所述电容单元并联设置；
    第一开关，耦接于参考电压及所述接收器的输出端之间；以及
    第二开关，耦接于所述接收器的所述输出端及所述运算放大器的所述负端之间；
    其中：
    在重置阶段，所述重置开关导通及所述第二开关不导通，所述运算放大器的所述输出端输出所述参考电压；以及
    在一般阶段，所述重置开关不导通，以及所述接收信号包含周期为T的多个波，所述检波电路在对应所述多个波中的第一特定波的周期T中，有T*R的时间被设置为采样模式，以及有T*(1-R)的时间被设置为非采样模式，其中R大于0且小于1；以及所述检波电路在对应所述多个波中的第二特定波的周期T中，有T*R的时间被设置为所述采样模式，以及有T*(1-R)的时间被设置为所述非采样模式，其中：
    在所述采样模式，所述第一开关不导通且所述第二开端导通，使所述接收信号在所述采样模式期间的幅度改变依特定比例反应且累加在所述运算放大器的所述输出端；以及
    在所述非采样模式，所述第一开关导通且所述第二开端不导通，使所述接收器产生的所述接收信号在所述非采样模式的幅度改变不反应且不累加在所述运算放大器的所述输出端，使所述运算放大器的所述输出端的电压在所述非采样模式维持不变。
  2. 如权利要求1所述的检波电路，其特征在于，所述接收器等效地包含：
    信号产生器，用来依据所述输入信号产生所述接收信号；以及
    接收器电容，耦接至所述信号产生器，用来接收所述接收信号，其中所述电容单元的电容值为CI，所述接收器电容的电容值为CS。
  3. 如权利要求2所述的检波电路，其特征在于，R为1/2，且：
    所述检波电路在所述第一特定波的波峰降至波谷的T/2的时间中，被设置为所述采样模式；
    所述检波电路在所述第一特定波的波谷升至波峰的T/2的时间中，被设置为所述非采样模式；
    所述检波电路在所述第二特定波的波峰降至波谷的T/2的时间中，被设置为所述采样模式；以及
    所述检波电路在所述第二特定波的波谷升至波峰的T/2的时间中，被设置为所述非采样模式。
  4. 如权利要求3所述的检波电路，其特征在于，所述第一特定波的波峰和波谷的电压差为2*VA，所述第一特定波的波峰降至波谷，使所述运算放大器的所述输出端的电压增加2*VA*CS/CI。
  5. 如权利要求2所述的检波电路，其特征在于，R为1/2，且：
    所述检波电路在所述第一特定波的波谷升至波峰的T/2的时间中，被设置为所述采样模式；
    所述检波电路在所述第一特定波的波峰降至波谷的T/2的时间中，被设置为所述非采样模式；
    所述检波电路在所述第二特定波的波谷升至波峰的T/2的时间中，被设置为所述采样模式；以及
    所述检波电路在所述第二特定波的波峰降至波谷的T/2的时间中，被设置为所述非采样模式。
  6. 如权利要求5所述的检波电路，其特征在于，所述第一特定波的波峰和波谷的电压差为2*VA，所述第一特定波的波谷升至波峰，使所述运算放大器的所述输出端的电压降低2*VA*CS/CI。
  7. 如权利要求1所述的检波电路，其特征在于，在所述一般阶段，所述检波电路在对应所述多个波中的第三特定波的周期T中，整 个周期T的时间被设置为非采样模式，其中所述第三特定波位于所述第一特定波和所述第二特定波之间。
  8. 如权利要求1所述的检波电路，其特征在于，所述运算放大器的所述正端耦接至所述参考电压。
  9. 如权利要求8所述的检波电路，其特征在于，所述检波电路另包含：
    校正电容，一端耦接于所述接收器的所述输出端；
    第一校正开关，耦接于所述校正电容的另一端以及第一校正电压之间，其中所述第一校正开关的导通状态同步于所述第一开关；以及
    第二校正开关，耦接于所述校正电容的所述另一端以及第二校正电压之间，其中所述第二校正开关的导通状态同步于所述第二开关。
  10. 如权利要求1所述的检波电路，其特征在于，所述运算放大器的所述正端耦接至第三校正电压。
  11. 如权利要求1所述的检波电路，其特征在于，所述接收信号包含周期为T的多个正弦波或三角波。
  12. 如权利要求1所述的检波电路，其特征在于，另包括：
    控制电路，依据参考时脉产生：
    第一控制信号以控制所述第一开关；
    第二控制信号以控制所述第二开关；
    重置信号以控制所述重置开关；以及
    第三控制信号以控制传送器产生输出信号，其中所述第三控制信号为周期性，周期为T，其中所述输出信号经过通道后成为所述输入信号进入所述接收器。
  13. 如权利要求12所述的检波电路，其特征在于，所述传送器包含第一换能器，所述接收器包含第二换能器。
  14. 如权利要求1所述的检波电路，其特征在于，另包括：
    控制电路，依据所述接收信号产生：
    第一控制信号以控制所述第一开关；
    第二控制信号以控制所述第二开关；以及
    重置信号以控制所述重置开关。
  15. 一种电子装置，其特征在于，包括：
    如权利要求1至14中任一项所述的检波电路。
PCT/CN2021/122114 2021-09-30 2021-09-30 检波电路及相关电子装置 WO2023050288A1 (zh)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030150977A1 (en) * 2002-02-13 2003-08-14 Canon Kabushiki Kaisha Photoelectric conversion apparatus
CN1947020A (zh) * 2004-04-27 2007-04-11 爱特梅尔格勒诺布尔公司 采用同步检测和相关采样的测定方法和装置
CN205486168U (zh) * 2015-11-05 2016-08-17 比亚迪股份有限公司 指纹检测装置及电子装置
CN109787563A (zh) * 2019-01-16 2019-05-21 电子科技大学 一种基于运放失调补偿的相关双采样电路
CN111095916A (zh) * 2019-10-10 2020-05-01 深圳市汇顶科技股份有限公司 Cmos结构、图像传感器及手持装置

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030150977A1 (en) * 2002-02-13 2003-08-14 Canon Kabushiki Kaisha Photoelectric conversion apparatus
CN1947020A (zh) * 2004-04-27 2007-04-11 爱特梅尔格勒诺布尔公司 采用同步检测和相关采样的测定方法和装置
CN205486168U (zh) * 2015-11-05 2016-08-17 比亚迪股份有限公司 指纹检测装置及电子装置
CN109787563A (zh) * 2019-01-16 2019-05-21 电子科技大学 一种基于运放失调补偿的相关双采样电路
CN111095916A (zh) * 2019-10-10 2020-05-01 深圳市汇顶科技股份有限公司 Cmos结构、图像传感器及手持装置

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