WO2023040595A1 - Puce et procédé de génération de code d'authentification de message - Google Patents

Puce et procédé de génération de code d'authentification de message Download PDF

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Publication number
WO2023040595A1
WO2023040595A1 PCT/CN2022/114040 CN2022114040W WO2023040595A1 WO 2023040595 A1 WO2023040595 A1 WO 2023040595A1 CN 2022114040 W CN2022114040 W CN 2022114040W WO 2023040595 A1 WO2023040595 A1 WO 2023040595A1
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WIPO (PCT)
Prior art keywords
mul
series circuit
key
subkey
clock cycle
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PCT/CN2022/114040
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English (en)
Chinese (zh)
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闫磊
焦海
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Oppo广东移动通信有限公司
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Publication of WO2023040595A1 publication Critical patent/WO2023040595A1/fr

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/08—Key distribution or management, e.g. generation, sharing or updating, of cryptographic keys or passwords
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W12/00—Security arrangements; Authentication; Protecting privacy or anonymity
    • H04W12/06—Authentication

Definitions

  • the embodiment of the present application relates to the field of chip technology, and in particular to a chip and a method for generating a message authentication code.
  • the 3rd Generation Partnership Project (3GPP) specifies three sets of security algorithms to protect the confidentiality and integrity of communication data.
  • the SNOW3G algorithm is one of the stream cipher algorithms
  • NIA1 is an integrity protection algorithm with the SNOW3G algorithm as the core.
  • the process of the NIA1 algorithm is as follows: firstly, each parameter required by the SNOW3G algorithm is input, a key stream is generated through the SNOW3G algorithm, and then a MUL operation is performed on the key stream together with other parameters, and a message authentication code is generated after the operation is completed. Send and transmit the data operation Message Authentication Code (MAC) at the user equipment side and the wireless network controller side respectively, and confirm the integrity of the data by comparing whether they are consistent.
  • MAC Message Authentication Code
  • the MUL operation is implemented in a hardware circuit, it is composed of 64 circuits connected in series. The input of the current circuit is the output of the upper circuit, and the output of the current circuit is the input of the next circuit.
  • the embodiment of the present application provides a method for generating a chip and a message authentication code, which can improve the operating speed of the circuit by reducing the number of series of MUL series circuits, and at the same time reduce the area consumption of the hardware circuit and thereby reduce the manufacturing cost of the chip. Described technical scheme is as follows:
  • an embodiment of the present application provides a chip, and the chip includes:
  • the SNOW3G module is configured to generate a key stream and transmit the key stream to the MUL module, the length of the first key in the key stream is m, and m is a positive integer greater than 1;
  • the MUL module includes a control circuit, a data selector, and an n-level MUL series circuit;
  • control circuit is configured to split the first key into i subkeys, i is an integer greater than or equal to 2, and the length of each subkey is less than or equal to n, and n is less than m ;
  • the data selector is configured to input the j-th subkey to the n-level MUL series circuit in the j-th clock cycle, and j is an integer less than or equal to i;
  • the n-stage MUL series circuit is configured to perform a MUL operation on the j-th subkey and the target message in the j-th clock cycle.
  • an embodiment of the present application provides a method for generating a message authentication code, the method including:
  • the length of the first key in the key stream is m, where m is a positive integer greater than 1;
  • splitting the first key into i subkeys where i is an integer greater than or equal to 2;
  • the MUL operation is performed on the j-th subkey and the target message through an n-level MUL series circuit, n is less than m, and the length of each subkey is less than or equal to n, and j is less than Integer equal to i.
  • FIG. 1 shows a schematic structural diagram of a MUL computing hardware circuit provided by an exemplary embodiment of the present application
  • FIG. 2 shows a schematic structural diagram of a chip provided by an exemplary embodiment of the present application
  • FIG. 3 shows a schematic structural diagram of a MUL module provided by an exemplary embodiment of the present application
  • Fig. 4 shows a schematic structural diagram of an alternative data selector provided by an exemplary embodiment of the present application
  • FIG. 5 shows a schematic structural diagram of a data selector for selecting one from four provided in an exemplary embodiment of the present application
  • FIG. 6 shows a flowchart of a method for generating a message authentication code provided in an exemplary embodiment of the present application
  • Fig. 7 shows a flowchart of a method for generating a message authentication code provided by another exemplary embodiment of the present application.
  • the confidentiality and integrity of communication data has become one of the core issues in the field of mobile communication based on the open architecture of network protocols and the characteristics of wireless transmission.
  • 3GPP specifies three sets of security algorithms to protect the confidentiality and integrity of communication data, and the SNOW3G algorithm is one of them, a stream cipher algorithm.
  • the NIA1 algorithm is an integrity protection algorithm with the SNOW3G algorithm as the core. The integrity protection algorithm is used to ensure that the communication data will not be tampered with by a third party other than the communication parties during the transmission process.
  • the process of the NIA1 algorithm is as follows: first, input the parameters required by the SMOW3G algorithm, and generate five 32-bit (bit) key streams Z1, Z2, Z3, Z4, and Z5 through the SNOW3G algorithm, among which Z1 and Z2 form variables P, Z3, and Z4 Composition variable Q, Z5 composition variable OTP.
  • the lengths of the variables P, Q, and OTP are 64 bits, 64 bits, and 32 bits, respectively.
  • the above-mentioned key stream, the target message, and the length of the target message are processed through the MUL operation to obtain the message authentication code. Its operation process is as follows:
  • M D-2 MESSAGE[64(D-2)]
  • EVAL Mul(EVAL,Q,0x000000000000001b);
  • LENGTH represents the length of the target message.
  • M i represents the i-th group of target messages
  • M D-2 represents the last group of target messages.
  • M D-1 represents the length of each group of target messages.
  • the MUL operation realizes the conversion of the data length from 192 bits to 64 bits, which is realized by the MULxPOW function through 64 cycles. Its implementation is as follows:
  • the MUL function is used to realize the conversion of the data length from 192 bits to 64 bits
  • the MULxPOW function is used to realize the conversion of the data length from 128 bits to 64 bits.
  • the MUL operation when the MUL operation is implemented in a hardware circuit, it consists of 64 stages of MUL series circuits.
  • the 64-stage MUL series circuit includes 64-stage MULxPOW operation units 10 , 64 data selectors 11 and exclusive OR logic gates 12 .
  • Each stage of MULxPOW operation unit 10 corresponds to a data selector 11 .
  • the input of the MULxPOW operation unit 10 at each stage is the operation result of the MULxPOW operation unit 10 at the previous stage.
  • the target message M i and the variable P are subjected to MUL operation.
  • the variable P has a total of 64 bits, and each bit of the variable P is used as the input of the control signal terminals of 64 data selectors 11 in turn, and the MULxPOW operation unit 10 of each stage and the constant h are used as the input of the data input terminals of the data selector 11.
  • MULxPOW_0 is the first-level MULxPOW operation unit 10
  • its corresponding data selector is the first data selector 11 .
  • the first bit P[0] of the variable P is the input of the control signal terminal of the first data selector 11
  • the operation result and constant of MULxPOW_0 are the input of the data 11 input terminal of the first data selector, if P[0] is 0, then Output the constant h, if P[0] is 1, then output the operation result of MULxPOW_0.
  • the operation result of MULxPOW_0 is the input of MULxPOW_1.
  • Exclusive OR operation is performed on the results output by all the data selectors 11 . The above operations are all realized within one clock cycle.
  • the embodiment of the present application optimizes the MUL module.
  • the variable P is input into the n-level MUL series circuit in multiple clock cycles through the control circuit and the data selector, which reduces the number of circuit stages, improves the circuit speed and reduces the hardware circuit.
  • the area consumption is described below using a schematic embodiment.
  • FIG. 2 shows a schematic structural diagram of a chip provided by an exemplary embodiment of the present application.
  • the chip is a chip with a message integrity protection function, such as a baseband chip in a terminal device or a network device, which is not limited in the embodiment of the present application.
  • the chip includes a SNOW3G module 20 and a MUL module 21 .
  • the SNOW3G module 20 transmits the generated key stream to the MUL module 21 .
  • the MUL module 21 After the key stream is transmitted to the MUL module 21 , the MUL module 21 generates a stop signal and feeds back the stop signal to the SNOW3G module 20 , and the SNOW3G module 20 stops transmitting the key stream to the MUL module 21 .
  • SMOW3G module 20 is based on counting (COUNT), bearer (BEARER), direction (DIRECTION), key (KEY), length (LENGTH) data input port input data, generates key stream by SNOW3G stream cipher algorithm, in the key stream Contains multiple keys.
  • the SNOW3G stream cipher algorithm is one of the security algorithms specified by 3GPP to protect the confidentiality and integrity of communication data.
  • the lengths of the multiple keys are the same.
  • the SNOW3G module 20 generates a key stream, which includes 5 keys, which are respectively defined as Z1, Z2, Z3, Z4, and Z5.
  • the Z1 and Z2 keys form the variable P
  • the Z3 and Z4 keys form the variable Q
  • the Z5 keys form the variable OTP.
  • the variable P is the first key, and its length is m.
  • the size of m is related to the length of a single key, and m is a positive integer greater than 1.
  • the variable Q and the variable OTP can be used as the second key.
  • the length of each key is 32 bits.
  • the first key variable P has a length of 64 bits
  • the variable Q has a length of 64 bits
  • the variable OTP has a length of 32 bits.
  • the MUL module 21 includes a control circuit 210 , a data selector 211 , and an n-stage MUL series circuit 212 .
  • the message (MESSAGE), the data input by the message length (LENGTH) data input port and the key stream generated by the SNOW3G module 20 are used as the input data of the MUL module 21, and finally generate the message authentication code 23 corresponding to the target message.
  • the message authentication code 23 is used to verify whether the communication data of both communication parties is tampered with by a third party during transmission.
  • the control circuit 210 splits the first key into multiple subkeys according to their lengths. Based on the control signal of the control circuit 210 , the data selector 211 sequentially selects a segment of subkeys to be input into the n-stage MUL series circuit 212 in each clock cycle until all subkeys are input into the n-level MUL series circuit 212 . The n-stage MUL series circuit 212 performs MUL operation on the subkey and the target message input in each clock cycle.
  • the control circuit 210 splits the first key into i subkeys according to the length through the control signal, where i is an integer greater than or equal to 2.
  • i may be 2, 3, 4, etc., which is not limited in this embodiment of the present application.
  • the number of segments of the subkey and the length of each segment of the subkey are related to the circuit number n of the n-stage MUL series circuit 212, where n is less than m.
  • the length of each segment subkey is less than or equal to n, the purpose is to ensure that each segment subkey can be completed in one operation after being input into the MUL circuit.
  • the lengths of the segment subkeys may be the same or different, which is not limited in this embodiment of the present application.
  • the number of circuit stages n of the n-stage MUL series circuit 212 is 32, and the length of the first key variable P is 64 bits, then the first key variable P is split into two subkeys, The length of each subkey is 32 bits.
  • the number of circuit stages n of the n-level MUL series circuit 212 is 22, and the length of the first key variable P is 64 bits, then the first key variable P is split into three subkeys, The length of the first subkey and the second subkey is 22, and the length of the third subkey is 20.
  • the data selector 211 selects a segment of sub-keys in each clock cycle according to the control signal of the control circuit 210, and sequentially inputs them into the n-level MUL series circuit 212 until the last segment of the sub-key is input into the n-level MUL series circuit in the last clock cycle. circuit 212.
  • the number of clock cycles is the same as the number of subkey segments.
  • the data selector 211 inputs the j-th subkey to the n-stage MUL series circuit in the j-th clock cycle, where j is an integer less than or equal to i.
  • the control circuit 210 splits the first key into 4 subkeys according to length, and it takes 4 clock cycles to input the 4 subkeys into the n-stage MUL series circuit 212 .
  • the data selector 211 inputs the first segment subkey to the n-level MUL series circuit 212 in the first clock cycle, until the fourth clock cycle inputs the fourth segment subkey to the n-level MUL series circuit 212, and the data selector 211 stops selecting data input.
  • the type of the data selector 211 is related to the number of segments of the subkey.
  • the type of the data selector 211 is an alternative data selector.
  • the type of the data selector 211 is a four-choice one data selector.
  • the number of data selectors 211 may be one or more, which is not limited in this embodiment of the present application.
  • the n-stage MUL series circuit 212 performs the MUL operation on the subkey of each clock cycle and the target message input from the input port of the MUL module 21 to obtain the MUL operation result of each cycle.
  • the number n of circuit stages of the n-stage MUL series circuit 212 may be 32, 22, etc., which is not limited in this embodiment of the present application.
  • the embodiment of the present application is only described with the number n of the circuit stages of the n-stage MUL series circuit 212 described above.
  • the value of the number of circuit stages n is comprehensively determined by the degree of complexity, which is not limited in this embodiment of the present application.
  • the n-stage MUL series circuit 212 performs MUL operation on the j-th subkey and the target message in the j-th clock cycle to obtain a MUL operation result.
  • the number of segments of the subkey is 4, and the n-level MUL series circuit 212 performs the MUL operation on the first segment of the subkey and the target message in the first clock cycle to obtain the corresponding MUL operation result until In the 4th clock cycle, perform the MUL operation on the 4th subkey and the target message to obtain the corresponding MUL operation result.
  • the target message and the sub-key are subjected to MUL operation, the target message is divided into multiple segments, and the sub-key operates on a certain segment in the target message. After the operation of the current target message segment and the sub-key is completed, the sub-key The key needs to be operated on with the next target message segment. In one cycle, the subkey is operated with all target message segments.
  • the i-segment sub-keys are segmented into n-level MUL series circuits in multiple clock cycles through the control circuit and data selector for operation .
  • the number of circuit stages is reduced, and the total amount of data operation is unchanged, and the time period of the unit clock cycle is improved. The speed at which the circuit operates. Further, since the number of circuit stages is reduced, the area consumption of the hardware circuit is also reduced, thereby reducing the chip manufacturing cost.
  • the MUL module further includes logic gates.
  • the logic gate is configured to perform logical operations on the MUL operation results corresponding to each clock cycle to obtain an intermediate operation result, and the intermediate operation result is used for the message authentication code corresponding to the second key generation target message in the key stream.
  • the logic gate is an XOR gate
  • the corresponding logic operation is an XOR operation
  • the MUL module 21 further includes an exclusive OR logic gate 213 .
  • the XOR logic gate 213 performs an XOR operation on the MUL operation result obtained by the n-stage MUL series circuit 212 in each clock cycle to obtain an intermediate operation result.
  • the intermediate operation result is logically operated with the second key variable Q and the variable OTP generated by the SNOW3G module 20 and the length of the target message to generate a message authentication code 23 corresponding to the target message.
  • the logical operation may be an exclusive OR operation.
  • the MUL module includes a plurality of first registers, and each first register is respectively used to store a MUL operation result corresponding to a corresponding clock cycle.
  • the n-level MUL series circuit is formed by connecting n-level MULxPOW computing units in series, and the MUL module also includes a second register;
  • the n-stage MUL series circuit is configured to write the operation result of the n-stage MULxPOW operation unit into the second register, and the data in the second register is the input of the n-stage MUL series circuit in the next clock cycle.
  • the data selector includes i input terminals
  • the control circuit is configured to input the subkey described in paragraph i to the data selector through the i input terminal, and input the jth control signal to the data selector at the jth clock cycle, wherein different clock cycles correspond to different control signals;
  • the data selector is configured to select, based on the jth control signal, the jth segment of subkeys input from the jth input terminal, and input the jth segment of subkeys to the n-stage MUL series circuit.
  • n is an integer multiple of n, and the length of the subkey in each segment is n.
  • FIG. 3 shows a schematic structural diagram of a MUL module provided by an exemplary embodiment of the present application.
  • the n-stage MUL series circuit 212 in the MUL module 21 is formed by connecting n-stage MULXPOW operation units in series.
  • the n-level MULxPOW operation unit has been described above, and will not be repeated in this embodiment of the present application.
  • the MUL module 21 also includes a first register 214 and a second register 215 .
  • the first register 214 is used to store the results of each MUL operation.
  • every clock cycle, the subkey and the target message are subjected to the MUL operation through the n-stage MUL circuit 212 to obtain a MUL operation result.
  • the first register 214 is used to store all MUL operation results from the first clock cycle to the penultimate clock cycle. Since the MUL operation result of the last clock cycle needs to be logically operated with all previous MUL operation results, the MUL operation result of the last clock cycle will not be stored in the first register.
  • the MUL module includes a plurality of first registers 214 .
  • the MUL operation result of the MUL operation between the last segment of the subkey and the target message does not need to be written into the first register 214, so the number of multiple first registers 214 is the number of sub-key split segments- 1.
  • each register is used to store a MUL operation result corresponding to one clock cycle.
  • the data storage size of each register is the same, which is the length of the target message.
  • the length of the first key variable P is 64 bits, and the control circuit 210 splits it into 4 subkeys, each of which has a length of 16 bits.
  • the data selector 211 Based on the control signal of the control circuit 210, the data selector 211 sequentially outputs it to the n-stage MUL series circuit 212 within 4 clock cycles, and the subkey and the target message are subjected to MUL operation in each clock cycle to obtain the first MUL operation result respectively , the second MUL operation result, the third MUL operation result, and the fourth MUL operation result.
  • three first registers 214 are used, and the first MUL operation result to the third MUL operation result are written into three first registers 214 respectively, and the data storage capacity of each first register 214 is all the same, all of which are the target message. length.
  • the MUL module includes a first register 214, and the data storage capacity of the first register 214 is i-1 times the length of the target message.
  • the length of the target message is 64 bits
  • the data storage capacity of the first register is 64 ⁇ (2-1) , which is 64 bits. If the first key variable P is input into the data selector in 4 clock cycles, the data storage capacity of the first register is 64 ⁇ (4-1), that is, 192 bits.
  • the second register 215 is used to store the operation result of the last stage MULxPOW operation unit, which is used as the input of the first MULxPOW operation unit in the next clock cycle.
  • the data selector 211 includes a plurality of input ports, the number of which is the same as the number of segments of the subkey. Multi-segment subkeys are used as the input of the data selector, and the control circuit 210 inputs a corresponding control signal to the data selector in each clock cycle, and the control data selector 211 selects the corresponding subkey to input to the n-stage MUL series circuit 212.
  • Different types of data selectors select subkeys differently based on control signals.
  • the following describes how two different types of data selectors select subkeys based on control signals.
  • the data selector 211 is an alternative data selector, which has two data input ports 22, a control signal input port 42 and a data output port 41, the control signal input port 42
  • the input control signal 43 is 1 bit.
  • the length of the first key variable P is 64 bits, and it is divided into two sections, which are the first subkey P[31:0] and the second subkey P[63:32], and each subkey The length is 32 bits.
  • Two sub-keys are used as the data input of the data selector 211, the first clock cycle starts, the control circuit 210 inputs the first control signal 0 to the data selector 211, based on the first control signal being the same as the data selector signal 0, the data selection The selector 211 selects the first segment subkey P[31:0] (upper 32 bits) as the output of the data selector 211, and inputs it to the n-stage MUL series circuit 212.
  • the second clock cycle starts, and the control circuit 210 inputs the second control signal 1 to the data selector 211. Based on the fact that the second control signal is the same as the data selector signal 1, the data selector 211 selects the second subkey P[63:32] (Lower 32 bits) is input to the n-stage MUL series circuit 212 as the output of the data selector 211 .
  • the data selector 211 is a four-to-one data selector, which has four data input ports 22 , one control signal input port 42 and one data output port 41 .
  • the control signal 43 input to the control signal input port 42 is 2 bits.
  • the length of the first key variable P is 64 bits, and it is divided into 4 sections, which are the first section subkey P[15:0], the second section subkey P[31:16], and the third section subkey P[47:32] and the fourth segment of subkeys P[63:32], the length of each segment of subkeys is 16 bits, and 4 segments of subkeys are used as the input of the data selector 211 .
  • the control signal 43 of the one-of-four data selector is 2 bits, and the data selector 211 is further controlled to select the corresponding subkey through different combinations of the control signals.
  • the first control signal is 00, and the control circuit 210 controls the data selector 211 to output the first subkey P[15:0]; in the second clock cycle, the second control signal is 01, and the control circuit 210 controls The data selector 211 outputs the second segment subkey P[31:16]; the third clock cycle, the third control signal is 10, and the control circuit 210 controls the data selector 211 to output the third segment subkey P[47:32]; In the fourth clock cycle, the fourth control signal is 11, and the control circuit 210 controls the data selector 211 to output the fourth subkey P[63:32]. Every clock cycle, the data selector 211 inputs the subkeys it selects and outputs to the n-stage MUL series circuit 212 .
  • the first key is split into multiple subkeys by the control circuit, and based on the control signal of the control circuit, the data selector selects a subkey within multiple clock cycles as the n-level MUL series circuit
  • the input combined with the first register and the second register, realizes the operation of the MUL operation result in multiple clock cycles, and improves the operating speed of the circuit in a unit clock cycle.
  • the target message, the length of the target message and other parameters are input into the chip through corresponding data input ports.
  • the SNOW3G module 20 generates five key streams, which are respectively defined as Z1, Z2, Z3, Z4, and Z5. Each keystream is 32 bits long.
  • the Z1 and Z2 key streams form variable P
  • the Z3 and Z3 key streams form variable Q
  • the Z5 key stream forms variable OTP.
  • Variable P is the first key.
  • the variable Q and the variable OTP may be the second key.
  • the length of the variable P is 64 bits
  • the lengths of the variable Q and the variable OTP are 64 bits and 32 bits respectively.
  • the SNOW3G module 20 inputs the generated first key and the second key into the MUL module 21 .
  • the MUL module 21 receives the first key and the second key, it sends a stop signal to the SNOW3G module 20 , and the SNOW3G module stops sending the first key and the second key to the MUL module 21 .
  • the n-stage MUL series circuit 212 in the MUL module 21 is a 32-stage MUL series circuit.
  • the 32-stage MUL series circuit is formed by series-connecting 32-stage MULxPOW arithmetic units.
  • the control circuit 210 divides the first key variable P into two subkeys, which are respectively the first subkey P[31:0] (high 32 bits) and the second subkey P[63:32] (lower 32 bits), the length of each subkey is 32 bits. Since the first key variable P is divided into two segments of sub-keys, the type of the data selector 211 is a one-of-two data selector.
  • the two sub-keys are used as the input of the data selector 211, the first clock cycle starts, the control circuit 210 inputs the first control signal 0 to the data selector 211, based on the fact that the first control signal is the same as the data selector signal 0, the data selector 211 selects the first subkey P[31:0] (upper 32 bits) as an output, and inputs it to the 32-level MUL series circuit 212.
  • the 32-level MUL series circuit 212 pairs the first subkey P[31: 0] (upper 32 bits) and the target message to perform MUL operation to obtain the first MUL operation result.
  • the data storage size of the first register 214 is 64 bits.
  • the data storage size of the second register 215 is 64 bits.
  • the second clock cycle starts, and the control circuit 210 inputs the second control signal 1 to the data selector 211. Based on the fact that the second control signal is the same as the data selector signal 1, the data selector 211 selects the second subkey P[63:32] (lower 32 bits) as an output, which is input to the 32-stage MUL series circuit 212 .
  • the result of the 32nd stage MULxPOW operation unit in the second register 215 is used as the input of the first stage MULxPOW operation unit in the second cycle.
  • the 32-stage MUL series circuit 212 performs MUL operation on the second subkey P[63:32] (lower 32 bits) and the target message to obtain the second MUL operation result.
  • the second MUL operation result is not written into the first register 214 , but directly performs XOR operation with the first MUL operation result in the first register 214 through the XOR logic gate 213 to obtain an intermediate operation result.
  • the variable Q and the variable OTP input to the MUL module 21 by the SNOW3G module 20 and the length of the target message the message authentication code is obtained.
  • the operation process of this part has been described above, and will not be repeated in this embodiment of the present application.
  • the embodiment of the present application adopts a 32-stage MUL series circuit. Based on the 7nm manufacturing process conditions, since the number of stages of the MUL series circuit in the embodiment of the application is reduced by 1/2, compared with the related technology, the corresponding circuit operation speed is increased by 2 times, and the area consumption of the hardware circuit is reduced. 1/2.
  • the number n of circuit stages of the n-stage MUL series circuit 212 may also be 22.
  • the 22-stage MUL series circuit 212 is formed by connecting 22 stages of MULxPOW computing units in series.
  • the control circuit 210 divides the first key variable P into three subkeys, which are respectively the first subkey P[21:0], the second subkey P[43:22] and the third subkey For the key P[63:44], the length of the first subkey and the second subkey is 22 bits, and the length of the third subkey is 20 bits. Therefore, the type of the data selector 211 is a three-choice one data selector.
  • the control signal input by the control input port of the data selector 211 is 2 bits, based on different combinations of the control signals of the control circuit 210, the data selector 211 is further controlled to select a corresponding subkey.
  • first MUL operation result and the second MUL operation result obtained by the 22-stage MUL series circuit 212 in the first clock cycle and the second clock cycle into the first register 214, based on the first register 214 storing two clocks Periodic MUL operation results, so the data storage capacity of the first register 214 is 128 bits.
  • two first registers 214 may also be used, the data storage capacity of which is 64 bits, and respectively store the first MUL operation result and the second MUL operation result.
  • the third subkey P[63:44] and the target message are based on a 22-stage MUL series circuit In 212, the first 20 stages of MULxPOW computing units perform MUL computing, and then generate a third MUL computing result.
  • the third MUL operation result is not written into the first register 214, and is directly XORed with the first MUL operation result and the second MUL operation result in the first register 214 to obtain an intermediate operation result.
  • the method provided by the embodiment of the present application is used to generate the message authentication code corresponding to the target message. Therefore, in the jth clock cycle, after performing the MUL operation on the jth subkey and the target message through the n-level MUL series circuit, further, each A logic operation is performed on the MUL operation result corresponding to the clock cycle to obtain an intermediate operation result, and further, the intermediate operation result is combined with the second key in the key stream to generate a message authentication code corresponding to the target message.
  • FIG. 6 shows a flowchart of a method for generating a message authentication code provided by an exemplary embodiment of the present application.
  • Step 610 generate a key stream, the length of the first key in the key stream is m, where m is a positive integer greater than 1.
  • the key stream is generated by the SNOW3G module, and the key stream contains multiple keys, which can be arbitrarily combined into the first key.
  • the length m of the first key is related to the length of a single key.
  • SNOW3G generates a key stream, which includes 5 keys, which are respectively defined as Z1, Z2, Z3, Z4, and Z5.
  • the Z1 and Z2 keys form a first key, defined as a variable P, of length m.
  • the length of each key is 32 bits, and the length m of the variable P is 64 bits.
  • Step 620 split the first key into i subkeys, where i is an integer greater than or equal to 2.
  • the control circuit splits the first key into i subkeys according to the length through the control signal, where i is an integer greater than or equal to 2.
  • i may be 2, 3, 4, etc., which is not limited in this embodiment of the present application.
  • Step 630 In the jth clock cycle, perform the MUL operation on the jth subkey and the target message through the n-level MUL series circuit to obtain the MUL operation result, n is less than m, and the length of each subkey is less than or equal to n, j is an integer less than or equal to i, and the result of the MUL operation is used to generate a message authentication code.
  • the data selector selects a section of subkeys in each clock cycle according to the control signal of the control circuit, and sequentially inputs them into the n-level MUL series circuit until the last section of subkeys is input into the n-level MUL series circuit in the last clock cycle.
  • the n-level MUL series circuit performs MUL operation on the subkey and the target message in each clock cycle to obtain the MUL operation result in each cycle.
  • the number of clock cycles is the same as the number of subkey segments.
  • the length of the subkey is less than or equal to n.
  • Step 640 performing logical operations on the MUL operation results corresponding to each clock cycle to obtain an intermediate operation result.
  • the logic gate performs a logic operation on the MUL operation result obtained through the operation of the n-stage MUL series circuit in each clock cycle, and obtains an intermediate operation result.
  • the logic gate is an XOR gate
  • the corresponding logic operation is an XOR operation
  • the XOR gate performs an XOR operation on the MUL operation result obtained through the operation of the n-stage MUL series circuit in each clock cycle, to obtain an intermediate operation result.
  • Step 650 Generate a message authentication code corresponding to the target message based on the intermediate operation result and the second key in the key stream.
  • the intermediate operation result is logically operated with other keys generated by the SNOW3G module and the length of the target message to generate a message authentication code corresponding to the target message.
  • the logical operation may be an exclusive OR operation.
  • the i-segment sub-keys are segmented into n-level MUL series circuits in multiple clock cycles through the control circuit and data selector for operation .
  • Logical operations are performed on the MUL operation results corresponding to each clock cycle to obtain an intermediate operation result, and further, a message authentication code corresponding to the target message is generated by using the intermediate operation result and the second key in the key stream.
  • the number of circuit stages is reduced, and the operation speed of the circuit within a unit clock cycle is improved under the condition that the total amount of data operation remains unchanged. Further, since the number of circuit stages is reduced, the area consumption of the hardware circuit is also reduced, thereby reducing the chip manufacturing cost.
  • the method further includes:
  • the XOR operation is performed on each MUL operation result to obtain an intermediate operation result.
  • read the stored MUL operation results from the first register, including:
  • Each MUL operation result is read from a plurality of first registers, and different first registers are used to store MUL operation results corresponding to different clock cycles.
  • the n-level MUL series circuit is formed by connecting n-level MULxPOW computing units in series;
  • the method further includes:
  • the method before performing the MUL operation on the j-th subkey and the target message through the n-level MUL series circuit, the method further includes:
  • n is an integer multiple of n, and the length of each segment subkey is n.
  • FIG. 7 shows a flowchart of a method for generating a message authentication code provided by another exemplary embodiment of the present application.
  • Step 701 generate a key stream, the length of the first key in the key stream is m, where m is a positive integer greater than 1.
  • Step 701 is the same as step 610, which will not be repeated in this embodiment of the present application.
  • Step 702 split the first key into i subkeys, where i is an integer greater than or equal to 2.
  • Step 702 is the same as step 620, which will not be repeated in this embodiment of the present application.
  • Step 703 based on the jth control signal, select the jth segment of subkeys from the i segment of subkeys.
  • the control circuit inputs a corresponding control signal to the data selector at each clock cycle, and controls the data selector to select a corresponding subkey as an output.
  • the length of the first key variable P is 64 bits, and the control circuit divides it into two sections, which are the first subkey P[31:0] and the second subkey P[63:32] , the length of each subkey is 32 bits, and the two subkeys are output as data from the data selector.
  • the first clock cycle starts, and the control circuit 210 inputs the first control signal 0 to the data selector 211. Based on the first control signal being the same as the data selector signal 0, the data selector 211 selects the first subkey P[31:0 ] (upper 32 bits) as the output of the data selector 211.
  • the second clock cycle starts, and the control circuit 210 inputs the second control signal 1 to the data selector 211. Based on the fact that the second control signal is the same as the data selector signal 1, the data selector 211 selects the second subkey P[63:32] (lower 32 bits) as the output of the data selector 211.
  • Step 704 input the j-th subkey into the n-stage MUL series circuit.
  • the corresponding subkeys output by the data selector in each clock cycle are input into the n-stage MUL series circuit.
  • the n-stage MUL series circuit is used to perform MUL operation on the subkey and the target message output by the middle data selector in each clock cycle, and obtain the MUL operation result in each clock cycle.
  • Step 705 in the jth clock cycle, perform MUL operation on the jth subkey and the target message through the n-level MUL series circuit to obtain the MUL operation result, n is less than m, and the length of each subkey is less than or equal to n, j is an integer less than or equal to i, and the result of the MUL operation is used to generate a message authentication code.
  • Step 705 is the same as step 630, which will not be repeated in this embodiment of the present application.
  • Step 706 write the results of each MUL operation output by the n-stage MUL series circuits into the first register.
  • the first key is split into multiple sub-keys and input to the n-stage MUL operation series circuit for operation within multiple clock cycles, it is necessary to use registers to store the intermediate data generated during the operation.
  • the n-stage MUL series circuit is formed by connecting n-stage MULxPOW operation units in series.
  • write the operation result of the n-level MULxPOW operation unit in the n-level MUL series circuit into the second register the data in the second register is the input of the n-stage MUL series circuit in the j+1th clock period.
  • the MUL operation is performed on the subkey of the first segment and the target message through the n-stage MUL series circuit to obtain the first MUL operation result.
  • the second clock cycle starts, and the operation result of the last-stage MULxPOW operation unit in the second register will be used as the input of the first-stage MULxPOW operation unit in the second clock cycle.
  • each MUL operation result is read from a plurality of first registers, and different first registers are used to store MUL operation results corresponding to different clock cycles.
  • first registers there are multiple first registers, different first registers store MUL operation results corresponding to different clock cycles, and MUL operation results corresponding to different clock cycles are respectively read from multiple first registers. Operation result.
  • the number of the first register is one, and the MUL operation results corresponding to different clock cycles are read from a single first register.
  • step 708 an XOR operation is performed on each MUL operation result to obtain an intermediate operation result.
  • the last subkey is input into the n-level MUL series circuit, and the last subkey and the target message are subjected to MUL operation to obtain the MUL operation result.
  • the MUL operation result calculated in the last clock cycle and each MUL operation result in the first register are subjected to an exclusive OR operation through an exclusive OR logic gate to obtain an intermediate operation result.
  • Step 709 Generate a message authentication code corresponding to the target message based on the intermediate operation result and the second key in the key stream.
  • Step 709 is the same as step 650, which will not be repeated in this embodiment of the present application.
  • a method for generating a message authentication code is illustrated below with reference to FIG. 2 and FIG. 3 .
  • the target message, the length of the target message and other parameters are input into the chip through the corresponding data input port 22 .
  • the SNOW3G module 20 generates five key streams, which are respectively defined as Z1, Z2, Z3, Z4, and Z5. Each keystream is 32 bits long.
  • the Z1 and Z2 key streams form variable P
  • the Z3 and Z3 key streams form variable Q
  • the Z5 key stream forms variable OTP.
  • the variable P is the first key
  • the variable Q and the variable OTP may be the second key.
  • the length of the variable P is 64 bits
  • the lengths of the variable Q and the variable OTP are 64 bits and 32 bits respectively.
  • the SNOW3G module 20 inputs the generated first key and the second key into the MUL module 21. After receiving the first key and the second key, the MUL module 21 sends a stop signal to the SNOW3G module 20 , and then the SNOW3G module stops sending the first key and the second key to the MUL module 21 .
  • the n-stage MUL series circuit 212 in the MUL module 21 is a 32-stage MUL series circuit.
  • the 32-stage MUL series circuit is formed by series-connecting 32-stage MULxPOW arithmetic units.
  • the control circuit 210 divides the first key variable P into two subkeys, which are respectively the first subkey P[31:0] (high 32 bits) and the second subkey P[63:32] (lower 32 bits), the length of each subkey is 32 bits. Since the first key variable P is divided into two segments of sub-keys, the type of the data selector 211 is an alternative data selector.
  • the two sub-keys are used as the input of the data selector 211, the first clock cycle starts, the control circuit 210 inputs the first control signal 0 to the data selector 211, based on the fact that the first control signal is the same as the data selector signal 0, the data selector 211 selects the first subkey P[31:0] (upper 32 bits) as an output, and inputs it to the 32-level MUL series circuit 212.
  • the 32-level MUL series circuit 212 pairs the first subkey P[31: 0] (upper 32 bits) and the target message to perform MUL operation to obtain the first MUL operation result.
  • the first MUL operation result is written into the first register 214, and the data storage capacity of the first register 214 is 64 bits.
  • the result of the 32nd stage MULxPOW operation unit is written into the second register 215, and the data storage capacity of the second register 215 is 64 bits.
  • the second clock cycle starts, and the control circuit 210 inputs the second control signal 1 to the data selector 211. Based on the fact that the second control signal is the same as the data selector signal 1, the data selector 211 selects the second subkey P[63:32] (lower 32 bits) as an output, which is then input to the 32-stage MUL series circuit 212 .
  • the result of the 32nd stage MULxPOW operation unit in the second register 215 is used as the input of the first stage MULxPOW operation unit in the second clock cycle.
  • the 32-level MUL series circuit 212 performs MUL operation on the second subkey P[63:32] (lower 32 bits) and the target message to obtain the second MUL operation result.
  • the second MUL operation result is not written into the first register 214 , but directly performs XOR operation with the first MUL operation result in the first register 214 through the XOR logic gate 213 to obtain an intermediate operation result.
  • the message authentication code is obtained.
  • the operation process of this part has been described above, and will not be repeated in this embodiment of the present application.
  • the first key is split into multiple subkeys by the control circuit, and based on the control signal of the control circuit, the data selector selects a subkey within multiple clock cycles as the n-level MUL series circuit
  • the input combined with the first register and the second register, realizes the calculation of the operation result of the n-stage MUL series circuit in multiple clock cycles, and improves the operating speed of the circuit in a unit clock cycle.

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Mobile Radio Communication Systems (AREA)

Abstract

L'invention concerne une puce et un procédé de génération d'un code d'authentification de message, qui appartiennent au domaine technique des puces. La puce comprend : un module 3G SNOW (20), qui est configuré pour générer un flux de clé et transmettre le flux de clé à un module MUL, la longueur d'une première clé dans le flux de clé étant M ; le module MUL (21), comprenant un circuit de commande (210), un sélecteur de données (211) et un circuit série MUL à n niveau (212), n étant inférieur à m ; le circuit de commande (210) est configuré pour diviser la première clé en i segments de sous-clé, et la longueur de chaque segment de sous-clé est inférieure ou égale à n ; le sélecteur de données (211) est configuré pour entrer un j-ième segment de sous-clé dans le circuit série MUL à n niveau dans un j-ième cycle d'horloge ; et le circuit série MUL à n niveau (212) est configuré pour effectuer une opération MUL sur le j-ième segment de sous-clé et un message cible dans le j-ième cycle d'horloge, de manière à obtenir un résultat d'opération MUL. Au moyen de la présente solution, la vitesse de fonctionnement d'un circuit peut être augmentée, et la consommation de zone d'un circuit matériel est également réduite.
PCT/CN2022/114040 2021-09-18 2022-08-22 Puce et procédé de génération de code d'authentification de message WO2023040595A1 (fr)

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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102143490A (zh) * 2010-01-28 2011-08-03 联芯科技有限公司 一种lte系统中生成消息验证码的方法及装置
CN103260156A (zh) * 2012-02-15 2013-08-21 中国移动通信集团公司 密钥流生成装置及方法、机密性保护装置及方法
US9419792B2 (en) * 2012-12-28 2016-08-16 Intel Corporation Instruction for accelerating SNOW 3G wireless security algorithm
US20190296894A1 (en) * 2018-03-22 2019-09-26 Arm Limited Low area optimization of snow 3g feedback
CN112513856A (zh) * 2018-05-30 2021-03-16 北欧半导体公司 存储器高效的硬件加密引擎

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102143490A (zh) * 2010-01-28 2011-08-03 联芯科技有限公司 一种lte系统中生成消息验证码的方法及装置
CN103260156A (zh) * 2012-02-15 2013-08-21 中国移动通信集团公司 密钥流生成装置及方法、机密性保护装置及方法
US9419792B2 (en) * 2012-12-28 2016-08-16 Intel Corporation Instruction for accelerating SNOW 3G wireless security algorithm
US20190296894A1 (en) * 2018-03-22 2019-09-26 Arm Limited Low area optimization of snow 3g feedback
CN112513856A (zh) * 2018-05-30 2021-03-16 北欧半导体公司 存储器高效的硬件加密引擎

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