WO2023035433A1

WO2023035433A1 - Method for forming semiconductor structure and semiconductor structure

Info

Publication number: WO2023035433A1
Application number: PCT/CN2021/135656
Authority: WO
Inventors: 刘志拯
Original assignee: 长鑫存储技术有限公司
Priority date: 2021-09-13
Filing date: 2021-12-06
Publication date: 2023-03-16
Also published as: CN115810618A

Abstract

Disclosed are a method for forming a semiconductor structure and a semiconductor structure. The method for forming a semiconductor structure comprises: providing a plurality of first chiplets, through silicon via structures being provided in first chiplets; vertically stacking the plurality of first chiplets to form a chiplet stacking structure, part of the through silicon via structures forming a first shielding structure, the first shielding structure being disposed in the edge region of the chiplet stacking structure; and forming a second shielding structure, the second shielding structure surrounding the chiplet stacking structure along the circumferential direction of the chiplet stacking structure, and the second shielding structure covering the sidewall of each first chiplet in the chiplet stacking structure.

Description

Method for forming semiconductor structure and semiconductor structure

This disclosure is based on a Chinese patent application with the application number 202111070235.4, the filing date is September 13, 2021, and the application name is "Method for forming a semiconductor structure and a semiconductor structure", and claims the priority of the Chinese patent application. The Chinese patent The entire content of the application is hereby incorporated by reference into this disclosure.

technical field

The present disclosure relates to but is not limited to a method for forming a semiconductor structure and the semiconductor structure.

Background technique

With the development of dynamic random access memory (Dynamic Random Access Memory, referred to as DRAM) to the miniaturization, in order to further improve the integration of integrated circuit (integrated circuit, IC), by forming vertically interconnected Through silicon via structure (Through Silicon Via, TSV), and through the subsequent redistribution layer (Redistribution Layer, referred to as RDL) to achieve electrical interconnection between different core particles, so as to stack multiple core particles.

Stacked dies are often used in high-speed broadband communications, and wide communication bands may interfere with the signal transmission of stacked dies.

Contents of the invention

The following is an overview of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.

The disclosure provides a method for forming a semiconductor structure and the semiconductor structure.

A first aspect of the present disclosure provides a method for forming a semiconductor structure, and the method for forming a semiconductor structure includes the following steps:

providing a plurality of first core particles, the first core particles are provided with through-silicon via structures;

vertically stacking a plurality of the first core particles to form a core particle stack structure, and part of the through-silicon via structures form a first shielding structure, and the first shielding structure is disposed at an edge region of the core particle stack structure;

forming a second shielding structure, the second shielding structure surrounds the core particle stacking structure along the circumferential direction of the core particle stacking structure, the second shielding structure covers each of the core particle stacking structures A sidewall of a core particle.

According to some embodiments of the present disclosure, the providing the first core particle includes:

Provide initial core particles;

forming a first through-silicon via structure, the first through-silicon via structure is disposed in the central region of the initial core particle;

forming a second through-silicon via structure, the second through-silicon via structure is disposed around the central region of the initial core particle at the edge region of the initial core particle, and the second through-silicon via structure surrounds the first silicon via structure The via structure has one or more turns, and the second TSV structure includes the first shielding layer.

According to some embodiments of the present disclosure, the forming the core particle stack structure includes:

forming a first pad, the first pad is disposed on the first surface of the first core particle, the first pad covers the first silicon exposed on the first surface of the first core particle through-hole structure;

forming a second pad, the second pad is disposed on the second surface of the first core particle opposite to the first surface, the second pad covers the second surface of the first core particle the exposed first TSV structure;

Stacking a plurality of first core particles vertically in the order that the first surface and the second surface are oppositely arranged to form the core particle stack structure, the first pads of the adjacent first core particles and the The second pad is bonded and connected, a first cavity is formed between adjacent first dies, and the second TSV structure forms the first shielding structure.

According to some embodiments of the present disclosure, the forming the core particle stack structure further includes:

forming a third pad, the third pad covers the second TSV structure exposed on the first surface of the first chip, and the outside of the third pad is covered with a second shielding layer;

forming a fourth pad, the fourth pad covers the second TSV structure exposed on the second surface of the first chip, and the outside of the fourth pad is covered with a third shielding layer;

In the die stack structure, the third pad and the fourth pad of the adjacent first die are bonded and connected, and the vertically connected second TSV structure, the The third pad and the fourth pad jointly form the first shielding structure.

A first dielectric layer is formed, the first dielectric layer filling the first cavity.

According to some embodiments of the present disclosure, along the circumferential direction of the die stack structure, the second shielding structure also covers sidewalls of each of the first dielectric layers in the die stack structure.

According to some embodiments of the present disclosure, the forming the second shielding structure includes:

depositing a shielding material covering the sidewalls of the die stack structure and the top surface of the die stack structure;

The shielding material covering the top surface of the die stack structure is removed, and the remaining shielding material forms the second shielding structure.

According to some embodiments of the present disclosure, the method for forming the semiconductor structure further includes:

forming an isolation layer, the isolation layer covering the top surface of the core particle stack structure;

The shielding material covers the isolation layer.

According to some embodiments of the present disclosure, the removing the shielding material covering the top surface of the die stack structure includes:

removing the isolation layer and the shielding material covering the isolation layer.

A second aspect of the present disclosure provides a semiconductor structure comprising:

A core particle stacking structure, the core particle stacking structure at least includes a plurality of stacked first core particles, the first core particle is provided with a through-silicon via structure, and the first core particle passes through the through-silicon via structure stack vertically;

A first shielding structure, the first shielding structure is arranged in the die stack structure, the first shielding structure at least includes part of the TSV structure, the first shielding structure is arranged in the die stack the edge region of the structure;

A second shielding structure, the second shielding structure is arranged around the core particle stacking structure on the peripheral edge of the core particle stacking structure, and the second shielding structure covers each of the core particle stacking structures. A sidewall of a core particle.

According to some embodiments of the present disclosure, the TSV structure includes a plurality of first TSV structures and a plurality of second TSV structures;

A plurality of the first TSV structures are arranged in the central area of the first core particle, and a plurality of the second TSV structures are arranged in the first core particle around the first TSV structures. In the edge area, the plurality of second TSV structures surround the first TSV structure one or more times, and the first shielding layer is disposed in the second TSVs.

According to some embodiments of the present disclosure, the core particle stack structure further includes:

The first pad, the first pad is arranged on the first surface of the first chip, the first pad covers the first silicon via exposed on the first surface of the first chip hole structure;

The second pad, the second pad is arranged on the second surface opposite to the first surface of the first core particle, and the second pad covers the exposed part of the second surface of the first core particle the first TSV structure;

In the core chip stacking structure, a plurality of the first core particles are vertically stacked in the order that the first surface and the second surface are oppositely arranged, and the first pads and the first bonding pads of the adjacent first core particles are Two pads are bonded and connected, a first cavity is provided between adjacent first core particles, and the second TSV structure is provided as the first shielding structure.

a third pad, the third pad covers the second TSV structure exposed on the first surface of the first chip, and the outside of the third pad is covered with a second shielding layer;

a fourth pad, the fourth pad covers the second TSV structure exposed on the second surface of the first chip, and the outside of the fourth pad is covered with a third shielding layer;

In the die stack structure, the third pad and the fourth pad of the adjacent first die are bonded and connected, and the vertically connected second TSV structure, the The third pad and the fourth pad are jointly configured to form the first shielding structure.

a first dielectric layer filling the first cavity.

Other aspects will be apparent to others upon reading and understanding the drawings and detailed description.

Description of drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and, together with the description, serve to explain principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to denote like elements. The drawings in the following description are some, but not all, embodiments of the present disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without any creative work.

Fig. 1 is a flowchart showing a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 2 is a flow chart of providing initial core particles in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 3 is a flow chart of forming a die stack structure in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 4 is a flow chart of forming a second shielding structure in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 5 is a flowchart showing a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 6 is a schematic diagram of initial core particles provided in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 7 is a schematic diagram of forming a first opening and a second opening in a method for forming a semiconductor structure according to an exemplary embodiment.

FIG. 8 is a top view of the structure shown in FIG. 7 .

Fig. 9 is a schematic diagram of forming a first barrier layer and a second barrier layer in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 10 is a schematic diagram of forming a shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 11 is a schematic diagram of forming a first shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 12 is a schematic diagram of forming a first TSV structure and a second TSV structure in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 13 is a schematic diagram of etching back an initial core particle to form a first core particle in a method for forming a semiconductor structure according to an exemplary embodiment.

FIG. 14 is a top view of the first core particle formed in FIG. 13 .

Fig. 15 is a schematic diagram of a first core particle formed in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 16 is a schematic diagram of forming a first bonding pad and a third bonding pad in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 17 is a schematic diagram of forming a second bonding pad and a fourth bonding pad in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 18 is a schematic diagram of forming a die stack structure in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 19 is a schematic diagram of forming a die stack structure in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 20 is a schematic diagram of forming an isolation layer in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 21 is a schematic diagram of depositing a shielding layer material in a method for forming a semiconductor structure according to an exemplary embodiment.

Fig. 22 is a schematic diagram of forming a second shielding layer in a method for forming a semiconductor structure according to an exemplary embodiment.

Reference signs:

10, the initial core particle; 11, the central area of the initial core particle; 12, the edge area of the initial core particle;

20. The first opening;

30. The second opening;

40. The first mask layer; 41. The first pattern;

50. Covering layer;

60. Isolation layer;

100. Core particle stacking structure; 110. First core particle; 1101. The first surface of the first core particle; 1102. The second surface of the first core particle; 111. The central area of the first core particle; 112. The first The edge area of the core particle; 115, the first space; 120, the first dielectric layer; 130, the first pad; 140, the second pad; 150, the third pad; 151, the second shielding layer; 160, The fourth pad; 161, the third shielding layer; 170, the substrate;

200. Through-silicon via structure; 210. First through-silicon via structure; 211. First barrier layer; 212. First conductive layer; 220. Second through-silicon via structure; 221. Second barrier layer; 222. First shielding layer; 223, the second conductive layer;

400. The first shielding structure;

500. A second shielding structure.

Detailed ways

In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments It is a part of the embodiments of the present disclosure, but not all of them. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative efforts belong to the protection scope of the present disclosure. It should be noted that, in the case of no conflict, the embodiments in the present disclosure and the features in the embodiments can be combined arbitrarily with each other.

An exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, as shown in FIG. 1 , which shows a flowchart of a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure. FIG. 6-FIG. 22 are schematic diagrams of various stages of a method for forming a semiconductor structure. The method for forming a semiconductor structure will be described below in conjunction with FIG. 6-FIG. 22 .

This embodiment does not limit the semiconductor structure. The following will introduce DRAM as an example of the semiconductor structure, but this embodiment is not limited thereto. The semiconductor structure in this embodiment may also be other structures.

As shown in FIG. 1 , a method for forming a semiconductor structure provided by an exemplary embodiment of the present disclosure includes the following steps:

Step S100 : providing a plurality of first core particles, and the first core particles are provided with TSV structures.

As shown in FIG. 13 , FIG. 14 , and FIG. 15 , the first core particle 110 includes a central area 111 and an edge area 112 , and the edge area 112 is arranged in a peripheral area of the central area 111 .

Each first core particle 110 is provided with several TSV structures 200 , part of the TSV structures 200 are provided in the central region 111 of the first core particle 110 , and the other part of the TSV structures 200 are provided in the first core particle 110 . edge area 112 . The arrangement position and the arrangement manner of the TSV structures 200 in each first die 110 are the same.

Step S200: vertically stacking a plurality of first core dies to form a core die stack structure, and part of the through-silicon via structure forms a first shielding structure, and the first shielding structure is disposed at an edge region of the core die stack structure.

As shown in FIG. 18, referring to FIG. 14, a plurality of first core particles 110 are vertically stacked, and the plurality of first core particles 110 are connected through the same arrangement of TSV structures 200 to form a core particle stack structure 100. The plurality of first core particles The TSV structures 200 of the particles 110 are vertically connected, and part of the TSV structures 200 vertically connected form the first shielding structure 400 . In this embodiment, the TSV structures 200 disposed on the edge region 112 of the first core 110 are vertically connected to form the first shielding structure 400, the first shielding structure 400 is disposed on the edge region of the die stack structure 100, and the second A shielding structure 400 surrounds the central area of the die stack structure 100 .

In this embodiment, in the chip stacking structure 100, the arrangement position and the arrangement method of the TSV structures 200 in each first chip 110 are the same. That is, taking the top surface of the core particle stack structure 100 as the projection plane, among the plurality of first core particles 110 belonging to the core particle stack structure 100 , the correspondingly arranged TSV structures 200 are on the top surface of the core particle stack structure 100 The projections on the overlap.

Step S300 : forming a second shielding structure, the second shielding structure surrounds the die stacking structure along the circumference of the die stacking structure, and the second shielding structure covers the sidewall of each first die in the die stacking structure.

As shown in FIG. 22 , the second shielding structure 500 is disposed around the peripheral edge of the die stack structure 100 , and the second shielding structure 500 at least covers the sidewall of each first die 110 in the die stack structure 100 .

In the semiconductor structure formed in this embodiment, the first shielding structure is formed in the core grain stacking structure, and the second shielding structure is arranged around the core grain stacking structure along the circumferential direction of the core grain stacking structure, and the first shielding structure is along the core grain stacking structure. The outer edge of the structure is arranged in the edge region of the core particle stack structure, the second shielding structure is arranged outside the core particle stack structure along the outer edge of the core particle stacking structure, the first shielding structure and the second shielding structure are in the circumferential direction of the semiconductor structure The edge forms a multi-turn shielding structure around the central area of the core particle stacking structure. When there is an interfering electromagnetic wave in the working environment of the semiconductor structure, the first shielding structure and the second shielding structure shield the interfering electromagnetic wave on the circumferential edge of the conductor structure. To prevent the central area of the stacked structure of core particles from being disturbed, the semiconductor structure formed in this embodiment has a good anti-electromagnetic interference effect.

According to an exemplary embodiment of the present disclosure, this embodiment is a further description of step S100 in the above embodiment.

As shown in Figure 2, the first core particles are provided, including:

S110: providing initial core particles.

As shown in FIG. 6 , the initial core particle 10 may be a semiconductor core particle, and the initial core particle 10 may include one or more semiconductor materials among silicon, germanium, silicon-germanium compound, and silicon-carbon compound.

S120: Forming a first through-silicon via structure, the first through-silicon via structure is disposed in a central region of the initial core particle.

As shown in FIG. 7 and FIG. 8 , a plurality of first openings 20 are formed, and the plurality of first openings 20 are respectively arranged in the central region 11 of the initial core particle 10 . As shown in FIG. 9 , a barrier material is deposited to form a first barrier layer 211 , and the first barrier layer 211 covers the first opening 20 . As shown in FIG. 12 , referring to FIG. 9 , a conductive metal is deposited to fill the first opening 20 to form a first conductive layer 212 , and the first barrier layer 211 and the first conductive layer 212 form a first TSV structure 210 . In this embodiment, the barrier material may be tantalum (Tantalum, Ta) or tantalum compound, and the conductive metal may be copper or copper compound.

S130: forming a second through-silicon via structure, the second through-silicon via structure is arranged around the central region of the initial core particle at the edge region of the initial core particle, and the second through-silicon via structure surrounds the first through-silicon via structure one or more times , the second TSV structure includes a first shielding layer.

As shown in FIG. 7, a plurality of second openings 30 are formed. Referring to FIG. 30 are uniformly arranged around the central region 11 of the primary core particle 10 and at the edge region 12 of the primary core particle 10 . As shown in FIG. 9 , a barrier material is deposited to cover the second opening 30 to form a second barrier layer 221 . As shown in FIG. 11 , referring to FIG. 9 , a shielding material is deposited, and the shielding material covers the second barrier layer 221 to form the first shielding layer 222 . As shown in FIG. 12 , referring to FIG. 11 , conductive metal is deposited to fill the second opening 30 to form a second conductive layer 223 and form a second TSV structure 220 . As shown in FIG. 12 , along the radial direction of the second TSV structure 220 , the second TSV structure 220 sequentially includes a second barrier layer 221 , a first shielding layer 222 and a second conductive layer 223 from outside to inside. In this embodiment, the barrier material may be tantalum (Ta) or tantalum compound. The shielding material can be metal aluminum (Aluminium, Al), metal tungsten (Tungsten, W), aluminide or tungsten compound, or a mixed metal material of two or more, and the conductive metal can be copper or copper compounds.

In this embodiment, step S120 and step S130 can be carried out simultaneously, as shown in FIG. 6, referring to FIG. 8, a first mask layer 40 is formed on the initial core particle 10, and the first mask layer 40 covers the initial core particle 10 The first mask layer 40 includes a first pattern 41 , the first pattern 41 exposes part of the top surface of the central area 11 of the initial core particle 10 and part of the top surface of the edge area 12 of the initial core particle 10 . According to the first mask layer 40, the exposed part of the initial core particle 10 is removed to form several TSV openings, wherein, as shown in FIG. 7, referring to FIG. The TSV openings are used as the first openings 20 , and the TSV openings disposed on the edge region 12 of the initial core particle 10 are used as the second openings 30 .

As shown in FIG. 9 , referring to FIG. 7 , a barrier material is deposited, the barrier material covers the first opening 20 to form a first barrier layer 211 , and the barrier material covers the second opening 30 to form a second barrier layer 221 . As shown in FIG. 10 , referring to FIG. 9 , a shielding layer 50 is formed, covering the top surface of the initial core particle 10 and filling the first opening 20 . As shown in FIG. 11 , referring to FIG. 10 , a shielding material is deposited to form a first shielding layer 222 in the second opening 30 , and the first shielding layer 222 covers the second barrier layer 221 .

As shown in FIG. 12 , referring to FIG. 11 , the shielding layer 50 is removed, and a conductive material is deposited to fill the first opening 20 and the second opening 30 to form a first TSV structure 210 and a second TSV structure 220 . As shown in FIG. 13 , referring to FIG. 12 , the backside of the initial core particle 10 is etched back to expose the first TSV structure 210 and the second TSV structure 220 , and the etching is stopped to form the first core particle 110 . As shown in FIG. 14 , the second TSV structure 220 is disposed on the edge region 112 of the first chip 110 , and the first shielding layer 222 is disposed in the second TSV structure 220 .

In other embodiments of the present disclosure, when forming the second TSV structure 220, a shielding material may be deposited to fill the second opening 30. As shown in FIG. 15, the formed second TSV structure 220 does not include the second conductive layer. 223.

In this embodiment, the first shielding layer is arranged in the second TSV structure, and a plurality of second TSV structures are arranged in the edge region of the first core particle to form a central region surrounding the first core particle. The edge area of the chip forms the first shielding structure, which can shield the interference of the semiconductor structure working environment on the chip stacking structure, and the shielding material in the first shielding layer of the second TSV structure is selected from low resistance such as aluminum or tungsten. When the semiconductor structure is in a high-frequency interference electromagnetic field, the eddy current generated by the shielding material in the first shielding layer can offset the interference electromagnetic wave, so as to achieve the effect of shielding the interference electromagnetic wave, so as to prevent the first core particle in the central area of the first core particle. A TSV structure is subject to electromagnetic interference.

According to an exemplary embodiment of the present disclosure, this embodiment is a further description of step S200 in the above embodiment.

As shown in Figure 3, a stacked structure of core particles is formed, including:

S210: Form a first pad, the first pad is disposed on the first surface of the first chip, and the first pad covers the first TSV structure exposed on the first surface of the first chip.

As shown in FIG. 16 , referring to FIG. 13 , the first pad 130 can be connected to the first TSV structure 210 through a soldering process (Soldering), and the first pad 120 forms a first surface opposite to the first chip 110. 1101 of the bump.

S220: Forming a second pad, the second pad is disposed on the second surface of the first core particle opposite to the first surface, and the second pad covers the first through-silicon via exposed on the second surface of the first core particle structure.

As shown in FIG. 17 , referring to FIG. 16 , the second pad 140 can be connected to the first TSV structure 210 through a soldering process (Soldering), and the second pad 140 forms a second surface opposite to the first chip 110. 1102 raised.

S230: Vertically stack a plurality of first core particles in the order that the first surface and the second surface are opposite to each other to form a chip stack structure, and the first pads and the second pads of adjacent first core particles are bonded and connected , a first cavity is formed between adjacent first core particles, and the second TSV structure forms a first shielding structure.

As shown in FIG. 18 , referring to FIG. 17 , a substrate 170 is provided, and a plurality of first core particles 110 are sequentially stacked on the substrate 170 in the same arrangement direction. Relatively arranged sequences are vertically stacked to form a core particle stacking structure 100 . The first bonding pads 130 and the second bonding pads 140 of adjacent first dies 110 are connected by bonding.

As shown in FIG. 18 , the first TSV structure 210 , the first pad 130 and the second pad 140 in the chip stack structure 100 form a metal interconnection. Along the stacking direction of the first chip 110 , a plurality of first The second TSV structure 210 of the die 110 forms the first shielding structure 400 disposed in the die stack structure 100 along the outer edge of the die stack structure 100 .

S240: Form a first dielectric layer, and the first dielectric layer fills the first cavity.

As shown in Figure 19, with reference to Figure 18, by atomic layer deposition (Atomic layer deposition, ALD) or chemical vapor deposition (Chemical VaporDeposition, CVD) deposition dielectric material fills the first space between adjacent first core particles 110 115 , forming a first dielectric layer 120 between adjacent first core particles 110 . The dielectric material may be silicon dioxide.

In the chip stack structure formed in this embodiment, the second TSV structures in the plurality of first core particles form a first shielding structure surrounding the central area of the chip stack structure, the first TSV structures, the first pads and the second pad form a metal interconnection in the central area of the chip stack structure. When transmitting communication signals in the metal interconnection in the central area of the chip stack structure, the first shielding structure can provide a good anti-interference effect for the metal interconnection and avoid semiconductor interference. The information transmitted in the structure is disturbed.

In the step of forming the core particle stacking structure, in addition to steps S210 to S240 in the above embodiment, it also includes:

S250: forming a third pad, the third pad covers the second TSV structure exposed on the first surface of the first chip, and the outside of the third pad is covered with a second shielding layer.

As shown in FIG. 16 , referring to FIG. 13 , the third pad 150 can be connected to the second TSV structure 220 through a soldering process (Soldering), and the third pad 150 forms a first surface opposite to the first chip 110. 1101 of the bump. In this embodiment, the shielding material in the second shielding layer 151 is the same as that in the first shielding layer 222 . In this embodiment, step S250 and step S210 may be performed simultaneously.

S260: forming a fourth pad, the fourth pad covers the second TSV structure exposed on the second surface of the first chip, and the outside of the fourth pad is covered with a third shielding layer.

As shown in FIG. 17 , referring to FIG. 16 , the fourth pad 160 can be connected to the second TSV structure 220 through a soldering process (Soldering), and the fourth pad 160 forms a second surface opposite to the first chip 110. 1102 raised. The shielding material in the third shielding layer 161 is the same as that in the first shielding layer 222 . In this embodiment, step S260 may be performed simultaneously with step S220.

As shown in FIG. 18, in the chip stack structure 100 formed by stacking a plurality of first chips 110, the third pads 150 and the fourth pads 160 of adjacent first chips 110 are bonded and connected, and the vertically connected The second TSV structure 220 , the third pad 150 and the fourth pad 160 together form the first shielding structure 400 .

In this embodiment, in the chip stack structure, the vertically connected second TSV structure, the third pad and the fourth pad also form a metal interconnection, and the first shielding structure is formed around the edge area of the chip stack structure. The shielding effect formed by the direction is better.

According to an exemplary embodiment of the present disclosure, this embodiment is a further description of step S300 in the foregoing embodiment.

As shown in Figure 4, a second shielding structure is formed, including:

S310: Deposit a shielding material, the shielding material covers the sidewall of the core particle stack structure and the top surface of the core particle stack structure.

As shown in FIG. 21 , referring to FIG. 19 , the shielding material is deposited by atomic layer deposition (Atomic layer deposition, ALD), and the shielding material covers the sidewall and top surface of the stacked core structure 100 . The deposited shielding material may be any one of metal aluminum (Aluminum, Al), metal tungsten (Tungsten, W), aluminide or tungsten compound or a mixed metal-like material of two or more. The covering die stack structure 100 is configured such that the shielding material forming the second shielding structure 500 is the same as or different from the shielding material in the first shielding layer 222 of the second TSV structure 220 . In this embodiment, different shielding metals are selected for the shielding material forming the second shielding structure 500 and the shielding material in the first shielding layer 222 .

S320: Remove the shielding material covering the top surface of the die stack structure, and the retained shielding material forms a second shielding structure.

As shown in FIG. 22 , referring to FIG. 21 , the shielding material covering the top surface of the core particle stack structure 100 is etched and removed by dry etching or wet etching process, and the shielding material covering the side surfaces of the core particle stack structure 100 is retained. A second shielding structure 500 is formed. Along the circumferential direction of the die stacking structure 100 , the second shielding structure 500 covers the sidewalls of each first die 110 and each first dielectric layer 120 in the die stacking structure 100 .

The semiconductor structure formed in this embodiment forms a second shielding structure surrounding the core grain stacking structure in the circumferential direction of the core grain stacking structure, the first shielding structure and the second shielding structure form a shielding area at the edge of the semiconductor structure, and the semiconductor structure is at a low frequency When the environment of the electromagnetic wave is disturbed, the first shielding structure and the second shielding structure can confine the disturbing electromagnetic wave in the shielding area, and prevent the disturbing electromagnetic wave from diffusing into the central area of the stacked structure of core particles. The semiconductor structure formed in this embodiment has a good shielding effect on both low-frequency electromagnetic waves and high-frequency electromagnetic waves.

An exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure. As shown in FIG. 5 , the method for forming a semiconductor structure provided in this embodiment includes the following steps:

Step S10: providing a plurality of first core particles, wherein the first core particles are provided with TSV structures.

Step S20: vertically stacking a plurality of first core particles to form a core chip stack structure, and part of the TSV structure forms a first shielding structure, and the first shielding structure is arranged at an edge region of the core chip stack structure.

Step S30: forming an isolation layer, the isolation layer covers the top surface of the stacked structure of core particles.

As shown in FIG. 20 , referring to FIG. 19 , the isolation layer 60 may include a photolithographic resist.

Step S40 : forming a second shielding structure, the second shielding structure surrounds the die stacking structure along the circumference of the die stacking structure, and the second shielding structure covers the sidewall of each first die in the die stacking structure.

The method for forming steps S10 and S20 in this embodiment is the same as the implementation of steps S100 and S200 in the above embodiment, and will not be repeated here.

In this embodiment, before forming the second shielding structure 500, as shown in FIG. 19 , an isolation layer 60 is formed on the top surface of the die stack structure 100 with reference to FIG. When shielding the material, it is sufficient to directly remove the isolation layer 60 and the shielding material covering the isolation layer 60 , and the operation of removing the shielding material covering the die stack structure 100 is simpler.

According to an exemplary embodiment of the present disclosure, this embodiment provides a semiconductor structure. As shown in FIG. 22 , referring to FIG. 13 and FIG. 14 , the semiconductor structure in this embodiment includes: The first shielding structure 400 in the die stacking structure 100 and the second shielding structure 500 disposed around the die stacking structure 100 at the peripheral edge of the die stacking structure 100 .

The die stack structure 100 at least includes a plurality of stacked first dies 110 , the first dies 110 are provided with a TSV structure 200 , and the first dies 110 are vertically stacked through the TSV structure 200 . The first shielding structure 400 is disposed at the edge region of the die stack structure 100 , and the first shielding structure 400 at least includes a part of the TSV structure 200 . The second shielding structure 500 is disposed around the die stacking structure 100 on the peripheral edge of the die stacking structure 100 , and the second shielding structure 500 covers the sidewall of each first die 110 in the die stacking structure 100 .

In the semiconductor structure of the present embodiment, a first shielding structure 400 and a second shielding structure 500 arranged around the core stacking structure 100 are provided in the chip stacking structure 100, and two inner and outer shielding structures are formed on the edge of the semiconductor structure, which is The semiconductor structure provides a better shielding effect to prevent the central area of the die stack structure 100 from being disturbed.

According to an exemplary embodiment, most of the content of the semiconductor structure of this embodiment is the same as that of the above embodiment. The difference between this embodiment and the above embodiment is that, as shown in FIG. 22 , referring to FIG. The hole structure 200 includes a plurality of first through-silicon via structures 210 and a plurality of second through-silicon via structures 220, the plurality of first through-silicon via structures 210 are arranged in the central region 111 of the first chip 110, and the plurality of second silicon via structures 220 The TSV structure 220 is arranged around the first TSV structure 210 at the edge region 112 of the first chip 110 , a plurality of second TSV structures 220 surround the first TSV structure 110 one or more times, and the second TSV structure 220 surrounds the first TSV structure 110 . A first shielding layer 222 is disposed in the through hole 220 .

In this embodiment, a plurality of second TSV structures 220 may be evenly disposed on the edge region 112 of the first die 110 to form one or more ring structures surrounding the first TSV structures 110 . In other embodiments of the present disclosure, the plurality of second TSV structures 220 may also be discretely disposed on the edge region 112 of the first die 110 . When the top view image of the first chip 110 has a square or rectangular structure, multiple second TSV structures 220 can also be arranged at the four corners of the first chip 110 to increase the area of the central region 111 of the first chip 110 .

In this embodiment, as shown in FIG. 22 , referring to FIG. 17 , the chip stack structure 100 further includes: a first bonding pad 130 and a third bonding pad 150 disposed on the first surface 1101 of the first chip 110 , and The second bonding pad 140 and the fourth bonding pad 160 are disposed on the second surface 1102 of the first die 110 . The first pad 130 covers the first TSV structure 210 exposed by the first surface 1101 of the first chip 110; the third pad 150 covers the second TSV structure exposed by the first surface 1101 of the first chip 110. For the hole structure 220 , referring to FIG. 17 , the outside of the third pad 150 is covered with the second shielding layer 151 . The second pad 140 covers the first TSV structure 210 exposed on the second surface of the first chip 110 , and the fourth pad 160 covers the second TSV structure exposed on the second surface of the first chip 110 220 , referring to FIG. 17 , the outside of the fourth pad 160 is covered with a third shielding layer 161 .

In the chip stack structure 100, a plurality of first core particles 110 are vertically stacked in the order that the first surface 1101 and the second surface 1102 are oppositely arranged, and the first bonding pads 130 and the second bonding pads 140 of adjacent first chip particles 110 Bonding connection, the third bonding pad 150 and the fourth bonding pad 160 bonding connection, referring to FIG. The two TSV structures 220 form the first shielding structure 400 surrounding the central area of the die stack structure 100 .

In this embodiment, as shown in FIG. 22 , according to FIG. 18 , the core chip stack structure 100 further includes: a first dielectric layer 120 , and the first dielectric layer 120 fills the first cavity 115 .

In this embodiment, as shown in FIG. 22 , the vertically connected second TSV structure 220 , the third pad 150 and the fourth pad 160 are jointly configured as a first shielding structure 400 .

According to an exemplary embodiment, most of the content of the semiconductor structure of this embodiment is the same as that of the above embodiment, and the difference between this embodiment and the above embodiment is that, as shown in FIG. In the circumferential direction, the second shielding structure 500 also covers the sidewall of each first dielectric layer 120 in the die stack structure 100 .

The semiconductor structure provided by the present disclosure includes a first shielding structure disposed in the die stack structure along the outer edge of the die stack structure and a second shielding structure disposed around the circumferential outer edge of the die stack structure, the first shielding structure and The second shielding structure forms a multi-turn shielding structure surrounding the central area of the core particle stacking structure on the peripheral edge of the semiconductor structure, which has a good anti-interference effect.

Each embodiment or implementation manner in this specification is described in a progressive manner, each embodiment focuses on the differences from other embodiments, and the same and similar parts of each embodiment can be referred to each other.

In the description of this specification, descriptions with reference to the terms "embodiments", "exemplary embodiments", "some implementations", "exemplary implementations", "examples" and the like mean that the descriptions are described in conjunction with the implementations or examples. A specific feature, structure, material, or characteristic is included in at least one embodiment or example of the present disclosure.

In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the described specific features, structures, materials or characteristics may be combined in any suitable manner in any one or more embodiments or examples.

In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" etc. The indicated orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the referred device or element must have a specific orientation, or in a specific orientation. construction and operation are therefore not to be construed as limitations on the present disclosure.

It can be understood that the terms "first", "second" and the like used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

In one or more drawings, like elements are indicated with like reference numerals. For the sake of clarity, various parts in the drawings are not drawn to scale. Also, some well-known parts may not be shown. For simplicity, the structure obtained after several steps can be described in one figure. In the following, many specific details of the present disclosure, such as structures, materials, dimensions, processing techniques and techniques of devices, are described for a clearer understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present disclosure, not to limit them; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still Modifications are made to the technical solutions described in the foregoing embodiments, or equivalent replacements are made to some or all of the technical features; these modifications or replacements do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present disclosure.

Industrial Applicability

In the method for forming a semiconductor structure of the present disclosure, the first shielding structure is formed in the stacked core structure, and the second shielding structure is formed at the peripheral edge of the stacked core structure, which provides a good shielding effect for the semiconductor structure.

Claims

A method for forming a semiconductor structure, the method for forming a semiconductor structure comprises the following steps:

providing a plurality of first core particles, the first core particles are provided with through-silicon via structures;

vertically stacking a plurality of the first core particles to form a core particle stack structure, and part of the through-silicon via structures form a first shielding structure, and the first shielding structure is disposed at an edge region of the core particle stack structure;

forming a second shielding structure, the second shielding structure surrounds the core particle stacking structure along the circumferential direction of the core particle stacking structure, the second shielding structure covers each of the core particle stacking structures A sidewall of a core particle.
The method for forming a semiconductor structure according to claim 1, wherein said providing the first core particle comprises:

Provide initial core particles;

forming a first through-silicon via structure, the first through-silicon via structure is disposed in the central region of the initial core particle;

forming a second through-silicon via structure, the second through-silicon via structure is disposed around the central region of the initial core particle at the edge region of the initial core particle, and the second through-silicon via structure surrounds the first silicon via structure The via structure has one or more turns, and the second TSV structure includes the first shielding layer.
The method for forming a semiconductor structure according to claim 2, wherein said forming a stacked structure of core particles comprises:

forming a first pad, the first pad is disposed on the first surface of the first core particle, the first pad covers the first silicon exposed on the first surface of the first core particle through-hole structure;

forming a second pad, the second pad is disposed on the second surface of the first core particle opposite to the first surface, the second pad covers the second surface of the first core particle the exposed first TSV structure;

Stacking a plurality of first core particles vertically in the order that the first surface and the second surface are oppositely arranged to form the core particle stack structure, the first pads of the adjacent first core particles and the The second pad is bonded and connected, a first cavity is formed between adjacent first dies, and the second TSV structure forms the first shielding structure.
The method for forming a semiconductor structure according to claim 3, said forming a stacked structure of core grains, further comprising:

forming a third pad, the third pad covers the second TSV structure exposed on the first surface of the first chip, and the outside of the third pad is covered with a second shielding layer;

forming a fourth pad, the fourth pad covers the second TSV structure exposed on the second surface of the first chip, and the outside of the fourth pad is covered with a third shielding layer;

In the die stack structure, the third pad and the fourth pad of the adjacent first die are bonded and connected, and the vertically connected second TSV structure, the The third pad and the fourth pad jointly form the first shielding structure.
The method for forming a semiconductor structure according to claim 3, said forming a stacked structure of core particles, further comprising:

A first dielectric layer is formed, the first dielectric layer filling the first cavity.
According to the method for forming a semiconductor structure according to claim 5, along the circumferential direction of the stacked core structure, the second shielding structure also covers the sides of each of the first dielectric layers in the stacked core structure. wall.
The method for forming a semiconductor structure according to claim 1, wherein said forming the second shielding structure comprises:

depositing a shielding material covering the sidewalls of the die stack structure and the top surface of the die stack structure;

The shielding material covering the top surface of the die stack structure is removed, and the remaining shielding material forms the second shielding structure.
The method for forming a semiconductor structure according to claim 7, further comprising:

forming an isolation layer, the isolation layer covering the top surface of the core particle stack structure;

The shielding material covers the isolation layer.
The method for forming a semiconductor structure according to claim 8, wherein said removing the shielding material covering the top surface of the die stack structure comprises:

removing the isolation layer and the shielding material covering the isolation layer.
A semiconductor structure comprising:

A core particle stacking structure, the core particle stacking structure at least includes a plurality of stacked first core particles, the first core particle is provided with a through-silicon via structure, and the first core particle passes through the through-silicon via structure stack vertically;

A first shielding structure, the first shielding structure is arranged in the die stack structure, the first shielding structure at least includes part of the TSV structure, the first shielding structure is arranged in the die stack the edge region of the structure;

A second shielding structure, the second shielding structure is arranged around the core particle stacking structure on the peripheral edge of the core particle stacking structure, and the second shielding structure covers each of the core particle stacking structures. A sidewall of a core particle.
The semiconductor structure according to claim 10, wherein the TSV structure comprises a plurality of first TSV structures and a plurality of second TSV structures;

A plurality of the first TSV structures are arranged in the central area of the first core particle, and a plurality of the second TSV structures are arranged in the first core particle around the first TSV structures. In the edge area, the plurality of second TSV structures surround the first TSV structure one or more times, and the first shielding layer is disposed in the second TSVs.
The semiconductor structure according to claim 11, the die stack structure further comprising:

The first pad, the first pad is arranged on the first surface of the first chip, the first pad covers the first silicon via exposed on the first surface of the first chip hole structure;

The second pad, the second pad is arranged on the second surface opposite to the first surface of the first core particle, and the second pad covers the exposed part of the second surface of the first core particle the first TSV structure;

In the core chip stacking structure, a plurality of the first core particles are vertically stacked in the order that the first surface and the second surface are oppositely arranged, and the first pads and the first bonding pads of the adjacent first core particles are Two pads are bonded and connected, a first cavity is provided between adjacent first core particles, and the second TSV structure is provided as the first shielding structure.
The semiconductor structure according to claim 12, the die stack structure further comprising:

a third pad, the third pad covers the second TSV structure exposed on the first surface of the first chip, and the outside of the third pad is covered with a second shielding layer;

a fourth pad, the fourth pad covers the second TSV structure exposed on the second surface of the first chip, and the outside of the fourth pad is covered with a third shielding layer;

In the die stack structure, the third pad and the fourth pad of the adjacent first die are bonded and connected, and the vertically connected second TSV structure, the The third pad and the fourth pad are jointly configured to form the first shielding structure.
The semiconductor structure according to claim 13, the die stack structure further comprising:

a first dielectric layer filling the first cavity.
According to the semiconductor structure of claim 14, along the circumferential direction of the die stack structure, the second shielding structure also covers the sidewall of each of the first dielectric layers in the die stack structure.