CN115810618A - Semiconductor structure forming method and semiconductor structure - Google Patents

Semiconductor structure forming method and semiconductor structure Download PDF

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Publication number
CN115810618A
CN115810618A CN202111070235.4A CN202111070235A CN115810618A CN 115810618 A CN115810618 A CN 115810618A CN 202111070235 A CN202111070235 A CN 202111070235A CN 115810618 A CN115810618 A CN 115810618A
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core
shielding
grain
bonding pad
silicon via
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刘志拯
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202111070235.4A priority Critical patent/CN115810618A/en
Priority to PCT/CN2021/135656 priority patent/WO2023035433A1/en
Publication of CN115810618A publication Critical patent/CN115810618A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass

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Abstract

The present disclosure provides a method for forming a semiconductor structure and a semiconductor structure, the method for forming the semiconductor structure includes: providing a plurality of first core particles, wherein the first core particles are provided with silicon through hole structures, the first core particles are vertically stacked to form a core particle stacking structure, part of the silicon through hole structures form a first shielding structure, and the first shielding structure is arranged at the edge region of the core particle stacking structure; and forming a second shielding structure, wherein the second shielding structure surrounds the core grain stacking structure along the circumferential direction of the core grain stacking structure, and the second shielding structure covers the side wall of each first core grain in the core grain stacking structure. In the method for forming the semiconductor structure, the first shielding structure is formed in the core grain stacking structure, and the second shielding structure is formed at the circumferential edge of the core grain stacking structure, so that a good shielding effect is provided for the semiconductor structure.

Description

Semiconductor structure forming method and semiconductor structure
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a method for forming a semiconductor structure and a semiconductor structure.
Background
With the development of Dynamic Random Access Memory (DRAM) with smaller size, in order to further improve the integration of Integrated Circuit (IC), a Through Silicon Via (TSV) structure is formed on each of a plurality of core dies, and then a Redistribution Layer (RDL) is used to electrically interconnect the different core dies, so as to stack the plurality of core dies.
Stacked core particles are commonly used for high-speed broadband communications, and the broadband communications band may interfere with signal transmission of the stacked core particles.
Disclosure of Invention
The following is a summary of the subject matter described in detail in this disclosure. This summary is not intended to limit the scope of the claims.
The disclosure provides a semiconductor structure and a forming method thereof.
A first aspect of the present disclosure provides a method of forming a semiconductor structure, including:
providing a plurality of first core particles, wherein the first core particles are provided with through silicon via structures;
vertically stacking a plurality of the first cores to form a core grain stacking structure, wherein part of the through silicon via structures form a first shielding structure, and the first shielding structure is arranged at the edge region of the core grain stacking structure;
forming a second shielding structure surrounding the core grain stacking structure along a circumferential direction of the core grain stacking structure, the second shielding structure covering sidewalls of each of the first core grains in the core grain stacking structure.
According to some embodiments of the disclosure, the providing a first core particle comprises:
providing an initial core particle;
forming a first through-silicon-via structure disposed in a central region of the initial core grain;
and forming a second through silicon via structure, wherein the second through silicon via structure is arranged at the edge region of the initial core grain around the central region of the initial core grain, the second through silicon via structure surrounds the first through silicon via structure for one or more circles, and the second through silicon via structure comprises a first shielding layer.
According to some embodiments of the disclosure, the forming a core particle stack structure comprises:
forming a first bonding pad arranged on the first surface of the first core grain, wherein the first bonding pad covers the first through silicon via structure exposed from the first surface of the first core grain;
forming a second bonding pad, wherein the second bonding pad is arranged on a second surface of the first core grain, which is opposite to the first surface, and the second bonding pad covers the first through silicon via structure exposed from the second surface of the first core grain;
the first core grains are vertically stacked according to the order that the first side and the second side are oppositely arranged to form the core grain stacking structure, the first bonding pads and the second bonding pads of the adjacent first core grains are in bonding connection, a first cavity is formed between the adjacent first core grains, and the second through silicon via structure forms the first shielding structure.
According to some embodiments of the present disclosure, the forming a core particle stack structure further comprises:
forming a third bonding pad, wherein the third bonding pad covers the second silicon through hole structure exposed from the first surface of the first core grain, and a second shielding layer covers the outer side of the third bonding pad;
forming a fourth bonding pad, wherein the fourth bonding pad covers the second silicon through hole structure exposed from the second surface of the first core grain, and the outer side of the fourth bonding pad is covered with a third shielding layer;
in the core grain stacking structure, the third bonding pad and the fourth bonding pad of the adjacent first core grain are connected in a bonding mode, and the second through silicon via structure, the third bonding pad and the fourth bonding pad which are connected vertically form the first shielding structure together.
According to some embodiments of the present disclosure, the forming a core particle stack structure further comprises:
forming a first dielectric layer that fills the first cavity.
According to some embodiments of the present disclosure, the second shielding structure further covers sidewalls of each of the first dielectric layers in the core grain stack structure along a circumferential direction of the core grain stack structure.
According to some embodiments of the disclosure, the forming the second shielding structure comprises:
depositing a shielding material covering sidewalls of the core grain stack structure and a top surface of the core grain stack structure;
removing the shielding material covering the top surface of the core grain stacking structure, and forming the second shielding structure by the remaining shielding material.
According to some embodiments of the present disclosure, the method of forming a semiconductor structure further comprises:
forming an isolation layer covering a top surface of the core grain stack structure;
the shielding material covers the isolation layer.
According to some embodiments of the present disclosure, the removing the shielding material covering the top surface of the core particle stack structure comprises:
and removing the isolation layer and the shielding material covering the isolation layer.
A second aspect of the present disclosure provides a semiconductor structure comprising:
a core grain stack structure including at least a plurality of first core grains stacked, the first core grains having through-silicon via structures disposed therein, the first core grains being vertically stacked through the through-silicon via structures;
a first shielding structure disposed in the core die stack structure, the first shielding structure including at least a portion of the through silicon via structure, the first shielding structure disposed at an edge region of the core die stack structure;
a second shielding structure disposed around the core die stack at a circumferential edge of the core die stack, the second shielding structure covering a sidewall of each of the first core dies in the core die stack.
According to some embodiments of the present disclosure, the through-silicon via structure comprises a plurality of first through-silicon via structures and a plurality of second through-silicon via structures;
the plurality of first through silicon via structures are arranged in the central region of the first core grain, the plurality of second through silicon via structures are arranged in the edge region of the first core grain around the first through silicon via structures, the plurality of second through silicon via structures surround the first through silicon via structures for one or more circles, and a first shielding layer is arranged in each second through silicon via.
According to some embodiments of the present disclosure, the core particle stack structure further comprises:
a first bonding pad disposed on a first side of the first core grain, the first bonding pad covering the first through-silicon-via structure exposed from the first side of the first core grain;
a second pad disposed on a second side opposite the first side of the first core grain, the second pad covering the first through-silicon-via structure exposed by the second side of the first core grain;
the first core grains are vertically stacked in the core grain stacking structure according to the order that the first face and the second face are oppositely arranged, the first bonding pads and the second bonding pads of the adjacent first core grains are in bonding connection, a first cavity is arranged between the adjacent first core grains, and the second through silicon via structure is arranged as the first shielding structure.
According to some embodiments of the present disclosure, the core particle stack structure further comprises:
the third bonding pad covers the second silicon through hole structure exposed from the first surface of the first core grain, and a second shielding layer covers the outer side of the third bonding pad;
the fourth bonding pad covers the second silicon through hole structure exposed from the second surface of the first core grain, and a third shielding layer covers the outer side of the fourth bonding pad;
in the core grain stacking structure, the third bonding pad and the fourth bonding pad of the adjacent first core grain are connected in a bonding mode, and the vertically connected second through silicon via structure, the third bonding pad and the fourth bonding pad are jointly arranged into the first shielding structure.
According to some embodiments of the present disclosure, the core particle stack structure further comprises:
a first dielectric layer filling the first cavity.
According to some embodiments of the present disclosure, the second shielding structure further covers sidewalls of each of the first dielectric layers in the core grain stack structure along a circumferential direction of the core grain stack structure.
In the semiconductor structure and the method for forming the same provided by the embodiment of the disclosure, the first shielding structure is formed in the core particle stacking structure, and the second shielding structure is formed at the circumferential edge of the core particle stacking structure, so that a good shielding effect is provided for the semiconductor structure.
Other aspects will be apparent upon reading and understanding the attached drawings and detailed description.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure. In the drawings, like reference numerals are used to indicate like elements. The drawings in the following description are directed to some, but not all embodiments of the disclosure. For a person skilled in the art, other figures can be derived from these figures without inventive effort.
FIG. 1 is a flow chart illustrating a method of forming a semiconductor structure according to an exemplary embodiment.
Fig. 2 is a flow chart illustrating providing initial core grains in a method of forming a semiconductor structure according to an exemplary embodiment.
Fig. 3 is a flow chart illustrating a method of forming a core grain stack structure in a method of forming a semiconductor structure according to an exemplary embodiment.
Fig. 4 is a flowchart illustrating the formation of a second shielding structure in a method of forming a semiconductor structure according to an exemplary embodiment.
FIG. 5 is a flow chart illustrating a method of forming a semiconductor structure according to an exemplary embodiment.
FIG. 6 is a schematic diagram illustrating an initial core grain provided in a method of forming a semiconductor structure, according to an exemplary embodiment.
Fig. 7 is a schematic diagram illustrating the formation of a first opening and a second opening in a method of forming a semiconductor structure according to an example embodiment.
Fig. 8 is a top view of the structure shown in fig. 7.
Fig. 9 is a schematic diagram illustrating the formation of a first barrier layer and a second barrier layer in a method of forming a semiconductor structure according to an example embodiment.
Fig. 10 is a schematic view illustrating formation of a blocking layer in a method of forming a semiconductor structure according to an exemplary embodiment.
Fig. 11 is a schematic diagram illustrating formation of a first shield layer in a method of forming a semiconductor structure according to an example embodiment.
Fig. 12 is a schematic diagram illustrating formation of a first through-silicon-via structure and a second through-silicon-via structure in a method of forming a semiconductor structure according to an example embodiment.
Fig. 13 is a schematic diagram illustrating a method of forming a semiconductor structure in which an initial core grain is etched back to form a first core grain, according to an example embodiment.
Fig. 14 is a top view of the first core particle formed in fig. 13.
Fig. 15 is a schematic view of a first core particle formed in a method of forming a semiconductor structure, according to an example embodiment.
Fig. 16 is a schematic diagram illustrating the formation of a first pad and a third pad in a method of forming a semiconductor structure according to an example embodiment.
Fig. 17 is a schematic diagram illustrating the formation of a second pad and a fourth pad in a method of forming a semiconductor structure according to an example embodiment.
Fig. 18 is a schematic diagram illustrating formation of a core grain stack structure in a method of forming a semiconductor structure according to an example embodiment.
Fig. 19 is a schematic diagram illustrating formation of a core grain stack structure in a method of forming a semiconductor structure according to an example embodiment.
Fig. 20 is a schematic diagram illustrating formation of an isolation layer in a method of forming a semiconductor structure according to an example embodiment.
FIG. 21 is a schematic illustration of a method of forming a semiconductor structure showing the deposition of a shield layer material according to an example embodiment.
Fig. 22 is a schematic diagram illustrating the formation of a second shield layer in a method of forming a semiconductor structure according to an example embodiment.
Reference numerals:
10. an initial core particle; 11. a central region of the initial core particle; 12. an edge region of the initial core particle;
20. a first opening;
30. a second opening;
40. a first mask layer; 41. a first pattern;
50. a shielding layer;
60. an isolation layer;
100. a core particle stack structure; 110. a first core particle; 1101. a first face of the first core particle; 1102. a second face of the first core particle; 111. a central region of the first core particle; 112. an edge region of the first core particle; 115. a first space; 120. a first dielectric layer; 130. a first pad; 140. a second pad; 150. a third pad; 151. a second shielding layer; 160. a fourth pad; 161. a third shielding layer; 170. a substrate;
200. a through silicon via structure; 210. a first through-silicon-via structure; 211. a first barrier layer; 212. a first conductive layer; 220. a second through-silicon-via structure; 221. a second barrier layer; 222. a first shielding layer; 223. a second conductive layer;
400. a first shielding structure;
500. a second shielding structure.
Detailed Description
To make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be described clearly and completely with reference to the drawings in the embodiments of the present disclosure, and it is obvious that the described embodiments are some embodiments of the present disclosure, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments disclosed herein without making any creative effort, shall fall within the protection scope of the present disclosure. It should be noted that, in the present disclosure, the embodiments and features of the embodiments may be arbitrarily combined with each other without conflict.
In an exemplary embodiment of the present disclosure, a method for forming a semiconductor structure is provided, as shown in fig. 1, fig. 1 is a flowchart illustrating a method for forming a semiconductor structure according to an exemplary embodiment of the present disclosure, and fig. 6 to 22 are schematic diagrams illustrating various stages of the method for forming a semiconductor structure, which will be described below with reference to fig. 6 to 22.
In this embodiment, the semiconductor structure is not limited, and a dynamic random access memory is taken as an example of the semiconductor structure, but the embodiment is not limited thereto, and the semiconductor structure in this embodiment may be other structures.
As shown in fig. 1, an exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, including the following steps:
step S100: a plurality of first core particles are provided, and through silicon via structures are arranged in the first core particles.
As shown in fig. 13, 14, and 15, the first core particle 110 includes a central region 111 and an edge region 112, and the edge region 112 is disposed in a region peripheral to the central region 111.
A plurality of through-silicon via structures 200 are disposed in each first core grain 110, a portion of the through-silicon via structures 200 are disposed in the central region 111 of the first core grain 110, and another portion of the through-silicon via structures 200 are disposed in the edge region 112 of the first core grain 110. The through-silicon via structures 200 in each of the first core particles 110 are disposed at the same position and arranged in the same manner.
Step S200: a plurality of first core particles are vertically stacked to form a core particle stacking structure, and part of the silicon through hole structure forms a first shielding structure which is arranged at the edge area of the core particle stacking structure.
As shown in fig. 18, referring to fig. 14, a plurality of first core particles 110 are vertically stacked, the plurality of first core particles 110 are connected by the same arrangement of through-silicon via structures 200 to form a core particle stacked structure 100, the through-silicon via structures 200 of the plurality of first core particles 110 are vertically connected, and a portion of the vertically connected through-silicon via structures 200 forms a first shielding structure 400. In the present embodiment, the tsv structures 200 disposed at the edge region 112 of the first core grain 110 are vertically connected to form a first shielding structure 400, the first shielding structure 400 is disposed at the edge region of the core grain stack structure 100, and the first shielding structure 400 surrounds the central region of the core grain stack structure 100.
In the present embodiment, in the core particle stacked structure 100, the arrangement position and arrangement of the through-silicon via structures 200 in each of the first core particles 110 are the same. That is, with the top surface of the core grain stacked structure 100 as a projection surface, among the plurality of first core grains 110 belonging to the core grain stacked structure 100, the projections of the through-silicon via structures 200 correspondingly disposed on the top surface of the core grain stacked structure 100 overlap.
Step S300: and forming a second shielding structure, wherein the second shielding structure surrounds the core grain stacking structure along the circumferential direction of the core grain stacking structure, and the second shielding structure covers the side wall of each first core grain in the core grain stacking structure.
As shown in fig. 22, the second shielding structure 500 is disposed around the circumferential outer edge of the core pellet stack 100, and the second shielding structure 500 covers at least the sidewall of each first core pellet 110 in the core pellet stack 100.
The semiconductor structure formed by the present embodiment forms a first shielding structure in the core particle stacked structure, a second shielding structure is disposed around the core particle stacked structure along a circumferential direction of the core particle stacked structure, the first shielding structure is disposed in an edge region of the core particle stacked structure along an outer edge of the core particle stacked structure, the second shielding structure is disposed outside the core particle stacked structure along the outer edge of the core particle stacked structure, the first shielding structure and the second shielding structure form a multi-turn shielding structure disposed around a central region of the core particle stacked structure at the circumferential edge of the semiconductor structure, when there is an interfering electromagnetic wave in an operating environment of the semiconductor structure, the first shielding structure and the second shielding structure shield the interfering electromagnetic wave at the circumferential edge of the conductor structure, so as to prevent the central region of the core particle stacked structure from being interfered, and the semiconductor structure formed by the present embodiment has a good electromagnetic interference resistance effect.
According to an exemplary embodiment of the present disclosure, the present embodiment is a further description of step S100 in the above embodiment.
As shown in fig. 2, providing a first core particle comprising:
s110: providing an initial core particle.
As shown in fig. 6, the initial core particle 10 may be a semiconductor core particle, and the initial core particle 10 may include one or more semiconductor materials of silicon, germanium, a silicon germanium compound, and a silicon carbon compound.
S120: and forming a first through silicon via structure, wherein the first through silicon via structure is arranged in the central region of the initial core grain.
As shown in fig. 7 and 8, a plurality of first openings 20 are formed, and the plurality of first openings 20 are respectively disposed in the central region 11 of the initial core particle 10. As shown in fig. 9, a barrier material is deposited to form a first barrier layer 211, and the first barrier layer 211 covers the first opening 20. Referring to fig. 9, as shown in fig. 12, a conductive metal is deposited to fill the first opening 20 to form a first conductive layer 212, and the first barrier layer 211 and the first conductive layer 212 form a first through-silicon-via structure 210. In the present embodiment, the barrier material may be Tantalum (Ta) or a Tantalum compound, and the conductive metal may be copper or a copper compound.
S130: and forming a second silicon through hole structure, wherein the second silicon through hole structure is arranged at the edge region of the initial core grain around the central region of the initial core grain, the second silicon through hole structure surrounds the first silicon through hole structure for one or more circles, and the second silicon through hole structure comprises a first shielding layer.
As shown in fig. 7, a plurality of second openings 30 are formed, and referring to fig. 8, the plurality of second openings 30 are respectively disposed at the edge regions 12 of the initial core particle 10, and in the present embodiment, the plurality of second openings 30 are uniformly disposed at the edge regions 12 of the initial core particle 10 around the central region 11 of the initial core particle 10. As shown in fig. 9, a second barrier layer 221 is formed by depositing a barrier material to cover the second opening 30. Referring to fig. 9, as shown in fig. 11, a shielding material is deposited, covering the second barrier layer 221, to form a first shielding layer 222. Referring to fig. 11, as shown in fig. 12, a conductive metal is deposited to fill the second opening 30, forming a second conductive layer 223, forming a second through-silicon-via structure 220. As shown in fig. 12, the second through silicon via structure 220 sequentially includes a second barrier layer 221, a first shielding layer 222, and a second conductive layer 223 from outside to inside along a radial direction of the second through silicon via structure 220, and in this embodiment, the barrier material may be tantalum (Ta) or tantalum compound. The shielding material may be one or a mixed metal material of two or more of aluminum (Al), tungsten (W), aluminide or Tungsten, and the conductive metal may be copper or copper.
In this embodiment, the steps S120 and S130 may be performed simultaneously, as shown in fig. 6, referring to fig. 8, a first mask layer 40 is formed on the initial core grain 10, the first mask layer 40 covers the top surface of the initial core grain 10, the first mask layer 40 includes a first pattern 41, and the first pattern 41 exposes a portion of the top surface of the central region 11 of the initial core grain 10 and a portion of the top surface of the edge region 12 of the initial core grain 10. Removing the exposed portion of the initial core grain 10 according to the first mask layer 40 forms several through-silicon-via openings, wherein, as shown in fig. 7, referring to fig. 8, the through-silicon-via opening disposed on the central region 11 of the initial core grain 10 is taken as the first opening 20, and the through-silicon-via opening disposed on the edge region 12 of the initial core grain 10 is taken as the second opening 30.
Referring to fig. 7, as shown in fig. 9, a barrier material is deposited, the barrier material covering the first opening 20 forming a first barrier layer 211, and the barrier material covering the second opening 30 forming a second barrier layer 221. Referring to fig. 9, as shown in fig. 10, a barrier layer 50 is formed, the barrier layer 50 covering the top surface of the initial core particle 10 and filling the first open hole 20. Referring to fig. 10, as shown in fig. 11, a shielding material is deposited to form a first shielding layer 222 in the second opening 30, and the first shielding layer 222 covers the second barrier layer 221.
Referring to fig. 11, as shown in fig. 12, the shielding layer 50 is removed, and a conductive material is deposited to fill the first opening 20 and the second opening 30, thereby forming a first through-silicon-via structure 210 and a second through-silicon-via structure 220, respectively. Referring to fig. 12, as shown in fig. 13, the back side of the initial core grain 10 is etched back to expose the first through silicon via structure 210 and the second through silicon via structure 220, and the etching is stopped to form the first core grain 110. As shown in fig. 14, the second through-silicon via structure 220 is disposed at the edge region 112 of the first core particle 110, and the first shielding layer 222 is disposed in the second through-silicon via structure 220.
In other embodiments of the present application, a shielding material may be deposited to fill the second opening 30 when forming the second through silicon via structure 220, as shown in fig. 15, and the second through silicon via structure 220 is formed without the second conductive layer 223.
In this embodiment, the first shielding layer is disposed in the second tsv structure, the plurality of second tsv structures are disposed in the edge region of the first core grain to form a first shielding structure surrounding the center region of the first core grain, so as to shield the interference of the working environment of the semiconductor structure on the stacked structure of the core grains, and the shielding material in the first shielding layer of the second tsv structure is made of a metal material with low resistivity, such as aluminum or tungsten, so that when the semiconductor structure is in an interfering electromagnetic field with a higher frequency, the eddy current generated by the shielding material in the first shielding layer can counteract the interfering electromagnetic wave, thereby achieving the effect of shielding the interfering electromagnetic wave, and preventing the first tsv structure in the center region of the first core grain from being subjected to electromagnetic interference.
According to an exemplary embodiment of the present disclosure, the present embodiment is a further description of step S200 in the above embodiment.
As shown in fig. 3, a core particle stack structure is formed, including:
s210: and forming a first bonding pad, wherein the first bonding pad is arranged on the first surface of the first core grain, and the first bonding pad covers the first silicon through hole structure exposed from the first surface of the first core grain.
Referring to fig. 13, as shown in fig. 16, the first pad 130 may be connected to the first through-silicon-via structure 210 through a Soldering process (Soldering), and the first pad 120 forms a protrusion with respect to the first face 1101 of the first core particle 110.
S220: and forming a second bonding pad, wherein the second bonding pad is arranged on a second surface of the first core grain, which is opposite to the first surface, and the second bonding pad covers the first silicon through hole structure exposed from the second surface of the first core grain.
Referring to fig. 16, as shown in fig. 17, the second pad 140 may be connected to the first through-silicon-via structure 210 through a Soldering process (Soldering), and the second pad 140 forms a protrusion with respect to the second surface 1102 of the first core particle 110.
S230: the method comprises the steps of vertically stacking a plurality of first core particles according to the sequence that a first face and a second face are oppositely arranged to form a core particle stacking structure, connecting a first bonding pad and a second bonding pad of adjacent first core particles in a bonding mode, forming a first cavity between the adjacent first core particles, and forming a first shielding structure through a second silicon through hole structure.
As shown in fig. 18, referring to fig. 17, a substrate 170 is provided, a plurality of first core particles 110 are sequentially stacked on the substrate 170 in the same arrangement direction, and the plurality of first core particles 110 are vertically stacked in an order in which a first face 1101 and a second face 1102 are oppositely disposed, to form a core particle stacked structure 100. The first and second pads 130 and 140 of the adjacent first core particles 110 are bonded.
As shown in fig. 18, the first through silicon via structure 210, the first pad 130, and the second pad 140 in the core die stack structure 100 form metal interconnections, and the second through silicon via structures 210 of the plurality of first core dies 110 form a first shielding structure 400 disposed in the core die stack structure 100 along an outer edge of the core die stack structure 100 in a stacking direction of the first core dies 110.
S240: a first dielectric layer is formed, and the first dielectric layer fills the first cavity.
As shown in fig. 19, referring to fig. 18, a first dielectric layer 120 is formed between the adjacent first core particles 110 by filling the first spaces 115 between the adjacent first core particles 110 by depositing a dielectric material through Atomic Layer Deposition (ALD) or Chemical Vapor Deposition (CVD). The dielectric material may be silicon dioxide.
In the chip stacking structure formed in this embodiment, the second tsv structures in the plurality of first core particles form a first shielding structure surrounding a central region of the chip stacking structure, the first tsv structures, the first pads and the second pads form metal interconnections in the central region of the chip stacking structure, and when a communication signal is transmitted in the metal interconnections in the central region of the chip stacking structure, the first shielding structure can provide a good anti-interference effect for the metal interconnections, so that information transmitted in the semiconductor structure is prevented from being interfered.
According to an exemplary embodiment of the present disclosure, the present embodiment is a further description of step S200 in the above embodiment.
The step of forming the core particle stacked structure includes, in addition to steps S210 to S240 in the above embodiment:
s250: and forming a third bonding pad, wherein the third bonding pad covers the second silicon through hole structure exposed from the first surface of the first core grain, and the outer side of the third bonding pad is covered with a second shielding layer.
Referring to fig. 13, as shown in fig. 16, the third pad 150 may be connected to the second through-silicon-via structure 220 through a Soldering process (Soldering), and the third pad 150 forms a protrusion with respect to the first face 1101 of the first core particle 110. In the present embodiment, the shielding material in the second shielding layer 151 is the same as the material in the first shielding layer 222. In this embodiment, step S250 may be performed simultaneously with step S210.
S260: and forming a fourth bonding pad, wherein the fourth bonding pad covers the second silicon through hole structure exposed from the second surface of the first core grain, and the outer side of the fourth bonding pad is covered with a third shielding layer.
Referring to fig. 16, as shown in fig. 17, the fourth pad 160 may be connected to the second through-silicon-via structure 220 through a Soldering process (Soldering), and the fourth pad 160 forms a protrusion with respect to the second face 1102 of the first core particle 110. The material of the shield layer in the third shield layer 161 is the same as the material of the first shield layer 222. In this embodiment, step S260 may be performed simultaneously with step S220.
As shown in fig. 18, in the core grain stacked structure 100 formed by stacking a plurality of first core grains 110, the third pads 150 and the fourth pads 160 of adjacent first core grains 110 are bonded and connected, and the vertically connected second through silicon via structures 220, the third pads 150 and the fourth pads 160 collectively form a first shielding structure 400.
In this embodiment, in the core particle stacked structure, the second through silicon via structure, the third pad and the fourth pad which are vertically connected also form metal interconnections, and the shielding effect of the first shielding structure formed in the circumferential direction of the edge region of the core particle stacked structure is better.
According to an exemplary embodiment of the present disclosure, the present embodiment is further described for step S300 in the above embodiment.
As shown in fig. 4, a second shielding structure is formed, including:
s310: and depositing a shielding material, wherein the shielding material covers the side wall of the core grain stacking structure and the top surface of the core grain stacking structure.
As shown in fig. 21, referring to fig. 19, a shielding material is deposited by Atomic Layer Deposition (ALD), and the shielding material covers the sidewalls and the top surface of the core particle stack structure 100. The deposited shielding material may be one or a mixed metal material of two or more of metal aluminum (Al), metal Tungsten (Tungsten, W), aluminide or Tungsten. Wherein the shielding material covering the core particle stack structure 100 for forming the second shielding structure 500 is the same as or different from the shielding material in the first shielding layer 222 of the second through-silicon-via structure 220. In the present embodiment, different shielding metals are used for the shielding material used to form the second shielding structure 500 and the shielding material in the first shielding layer 222.
S320: and removing the shielding material covering the top surface of the core grain stacking structure, and forming a second shielding structure by the retained shielding material.
As shown in fig. 22, referring to fig. 21, the shielding material covering the top surface of the core grain stack structure 100 is removed by etching through a dry etching process or a wet etching process, and the shielding material covering the side surfaces of the core grain stack structure 100 is remained to form a second shielding structure 500, where the second shielding structure 500 covers each first core grain 110 and the sidewall of each first dielectric layer 120 in the core grain stack structure 100 along the circumferential direction of the core grain stack structure 100.
The semiconductor structure formed by the embodiment forms the second shielding structure surrounding the core particle stacked structure in the circumferential direction of the core particle stacked structure, the first shielding structure and the second shielding structure form the shielding region at the edge of the semiconductor structure, and when the semiconductor structure is in an environment of low-frequency interference electromagnetic waves, the first shielding structure and the second shielding structure can limit the interference electromagnetic waves in the shielding region and avoid the interference electromagnetic waves from diffusing into the central region of the core particle stacked structure. The semiconductor structure formed in this embodiment has a good shielding effect for both low-frequency electromagnetic waves and high-frequency electromagnetic waves.
The exemplary embodiment of the present disclosure provides a method for forming a semiconductor structure, and as shown in fig. 5, the method for forming a semiconductor structure provided by the present embodiment includes the following steps:
step S10: a plurality of first core particles are provided, and through silicon via structures are arranged in the first core particles.
Step S20: a plurality of first core particles are vertically stacked to form a core particle stacking structure, and part of the silicon through hole structure forms a first shielding structure which is arranged at the edge area of the core particle stacking structure.
Step S30: and forming an isolation layer, wherein the isolation layer covers the top surface of the core grain stacking structure.
As shown in fig. 20, referring to fig. 19, the isolation layer 60 may include a photoresist.
Step S40: and forming a second shielding structure, wherein the second shielding structure surrounds the core grain stacking structure along the circumferential direction of the core grain stacking structure, and the second shielding structure covers the side wall of each first core grain in the core grain stacking structure.
The forming method of steps S10 and S20 in this embodiment is the same as the implementation manner of steps S100 and S200 in the above embodiment, and therefore, the description thereof is omitted.
In this embodiment, before forming the second shielding structure 500, as shown in fig. 19, referring to fig. 18, an isolation layer 60 is formed on the top surface of the core grain stacked structure 100, and when the shielding material covering the top surface of the core grain stacked structure 100 is removed in step S40, the isolation layer 60 and the shielding material covering the isolation layer 60 are directly removed, so that the operation of removing the shielding material covering the core grain stacked structure 100 is simpler.
According to an exemplary embodiment of the present disclosure, the present embodiment provides a semiconductor structure, as shown in fig. 22, and referring to fig. 13 and 14, the semiconductor structure in the present embodiment includes: the core grain stack structure 100, the first shielding structure 400 disposed in the core grain stack structure 100, and the second shielding structure 500 disposed at a circumferential edge of the core grain stack structure 100 around the core grain stack structure 100.
The core grain stack structure 100 at least includes a plurality of first core grains 110 stacked, a through silicon via structure 200 is disposed in the first core grains 110, and the first core grains 110 are vertically stacked through the through silicon via structure 200. The first shielding structure 400 is disposed at an edge region of the core grain stacked structure 100, and the first shielding structure 400 includes at least a portion of the through silicon via structure 200. The second shielding structure 500 is disposed at a circumferential edge of the core grain stack 100 around the core grain stack 100, and the second shielding structure 500 covers a sidewall of each of the first core grains 110 in the core grain stack 100.
In the semiconductor structure of the present embodiment, the first shielding structure 400 and the second shielding structure 500 disposed around the core grain stacking structure 100 are disposed in the core grain stacking structure 100, and an inner and outer shielding structure is formed at the edge of the semiconductor structure, so as to provide a better shielding effect for the semiconductor structure, so as to prevent the central area of the core grain stacking structure 100 from being interfered.
According to an exemplary embodiment, most of the contents of the semiconductor structure of the present embodiment are the same as those of the above-described embodiment, and the present embodiment is different from the above-described embodiment in that, as shown in fig. 22, referring to fig. 14, a through silicon via structure 200 includes a plurality of first through silicon via structures 210 and a plurality of second through silicon via structures 220, the plurality of first through silicon via structures 210 are disposed in a central region 111 of a first core grain 110, the plurality of second through silicon via structures 220 are disposed in an edge region 112 of the first core grain 110 around the first through silicon via structures 210, the plurality of second through silicon via structures 220 surround the first through silicon via structures 110 for one or more turns, and a first shielding layer 222 is disposed in the second through silicon via structures 220.
In the present embodiment, the plurality of second through silicon via structures 220 may be uniformly disposed on the edge region 112 of the first core particle 110, forming one or more circles of ring structures surrounding the first through silicon via structure 110. In other embodiments of the present disclosure, the plurality of second through silicon via structures 220 may also be discretely disposed at the edge region 112 of the first core particle 110. When the top view of the first chip 110 is a square or rectangular structure, a plurality of second tsv structures 220 may be further disposed at four corners of the first chip 110 to increase the area of the central region 111 of the first chip 110.
In the present embodiment, as shown in fig. 22, referring to fig. 17, the core particle stack structure 100 further includes: the first and third pads 130 and 150 disposed on the first side 1101 of the first core particle 110, and the second and fourth pads 140 and 160 disposed on the second side 1102 of the first core particle 110. The first pad 130 covers the first through-silicon-via structure 210 exposed from the first side 1101 of the first core particle 110; the third pad 150 covers the second through silicon via structure 220 exposed from the first face 1101 of the first core particle 110, and referring to fig. 17, the outside of the third pad 150 is covered with the second shielding layer 151. The second pad 140 covers the first through-silicon via structure 210 exposed from the second surface of the first core particle 110, the fourth pad 160 covers the second through-silicon via structure 220 exposed from the second surface of the first core particle 110, and referring to fig. 17, the outer side of the fourth pad 160 is covered with the third shielding layer 161.
In the core die stack structure 100 in which a plurality of first core dies 110 are vertically stacked in an order in which a first face 1101 and a second face 1102 are oppositely disposed, first pads 130 and second pads 140 of adjacent first core dies 110 are bonded and connected, and third pads 150 and fourth pads 160 are bonded and connected, referring to fig. 18, first cavities 115 are disposed between adjacent first core dies 110, and second through silicon via structures 220 of the plurality of first core dies 110 form a first shielding structure 400 surrounding a central region of the core die stack structure 100.
In the present embodiment, as shown in fig. 22, according to fig. 18, the core particle stacked structure 100 further includes: a first dielectric layer 120, the first dielectric layer 120 filling the first cavity 115.
In the present embodiment, as shown in fig. 22, the vertically connected second through silicon via structure 220, third pad 150, and fourth pad 160 are collectively provided as a first shielding structure 400.
According to an exemplary embodiment, the semiconductor structure of the present embodiment is mostly the same as the above-described embodiment, and the present embodiment is different from the above-described embodiment in that, as shown in fig. 22, the second shielding structure 500 also covers the sidewall of each first dielectric layer 120 in the core grain stacked structure 100 along the circumferential direction of the core grain stacked structure 100.
The semiconductor structure provided by the disclosure comprises a first shielding structure arranged in the core particle stacking structure along the outer edge of the core particle stacking structure and a second shielding structure arranged around the circumferential outer edge of the core particle stacking structure, wherein the first shielding structure and the second shielding structure form a multi-turn shielding structure arranged around the central area of the core particle stacking structure at the circumferential edge of the semiconductor structure, and the semiconductor structure has a good anti-interference effect.
The embodiments or implementation modes in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments may be referred to each other.
In the description herein, references to the description of the terms "embodiment," "exemplary embodiment," "some embodiments," "exemplary embodiment," "example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the disclosure.
In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
In the description of the present disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing and simplifying the present disclosure, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and thus, should not be construed as limiting the present disclosure.
It will be understood that the terms "first," "second," and the like as used in this disclosure may be used in the present disclosure to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.
Like elements in one or more of the drawings are referred to by like reference numerals. For purposes of clarity, the various features in the drawings are not drawn to scale. In addition, certain well known components may not be shown. For the sake of simplicity, the structure obtained after several steps can be described in one figure. Numerous specific details of the present disclosure, such as structures, materials, dimensions, processing techniques and techniques of the devices, are set forth in the following description in order to provide a more thorough understanding of the present disclosure. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details.
Finally, it should be noted that: the above embodiments are only used for illustrating the technical solutions of the present disclosure, and not for limiting the same; although the present disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art will appreciate that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present disclosure.

Claims (15)

1. A method for forming a semiconductor structure, the method comprising:
providing a plurality of first core particles, wherein the first core particles are provided with through silicon via structures;
vertically stacking a plurality of the first core particles to form a core particle stacking structure, wherein a part of the through silicon via structures form a first shielding structure, and the first shielding structure is arranged at the edge region of the core particle stacking structure;
and forming a second shielding structure, wherein the second shielding structure surrounds the core grain stacking structure along the circumferential direction of the core grain stacking structure, and the second shielding structure covers the side wall of each first core grain in the core grain stacking structure.
2. The method of claim 1, wherein the providing the first core grain comprises:
providing an initial core particle;
forming a first through-silicon-via structure disposed in a central region of the initial core grain;
forming a second through silicon via structure, the second through silicon via structure being disposed at an edge region of the initial core grain around a central region of the initial core grain, the second through silicon via structure surrounding the first through silicon via structure for one or more turns, the second through silicon via structure comprising a first shielding layer.
3. The method of claim 2, wherein forming the core-grain stack structure comprises:
forming a first bonding pad arranged on the first surface of the first core grain, wherein the first bonding pad covers the first through silicon via structure exposed from the first surface of the first core grain;
forming a second bonding pad, wherein the second bonding pad is arranged on a second surface of the first core grain, which is opposite to the first surface, and the second bonding pad covers the first through silicon via structure exposed from the second surface of the first core grain;
the first core grains are vertically stacked according to the order that the first side and the second side are oppositely arranged to form the core grain stacking structure, the first bonding pads and the second bonding pads of the adjacent first core grains are in bonding connection, a first cavity is formed between the adjacent first core grains, and the second through silicon via structure forms the first shielding structure.
4. The method of claim 3, wherein the forming a core-grain stack structure further comprises:
forming a third bonding pad, wherein the third bonding pad covers the second silicon through hole structure exposed from the first surface of the first core grain, and a second shielding layer covers the outer side of the third bonding pad;
forming a fourth bonding pad, wherein the fourth bonding pad covers the second silicon through hole structure exposed from the second surface of the first core grain, and the outer side of the fourth bonding pad is covered with a third shielding layer;
in the core grain stacking structure, the third bonding pad and the fourth bonding pad of the adjacent first core grain are connected in a bonding mode, and the second through silicon via structure, the third bonding pad and the fourth bonding pad which are connected vertically form the first shielding structure together.
5. The method of claim 3, wherein the forming a core-grain stack structure further comprises:
forming a first dielectric layer that fills the first cavity.
6. The method as claimed in claim 5, wherein the second shielding structure further covers sidewalls of each of the first dielectric layers in the core die stack structure along a circumferential direction of the core die stack structure.
7. The method as claimed in claim 1, wherein the forming of the second shielding structure comprises:
depositing a shielding material covering sidewalls of the core grain stack structure and a top surface of the core grain stack structure;
removing the shielding material covering the top surface of the core grain stacking structure, and forming the second shielding structure by the remaining shielding material.
8. The method of claim 7, further comprising:
forming an isolation layer covering a top surface of the core grain stack structure;
the shielding material covers the isolation layer.
9. The method of claim 8, wherein said removing the shielding material covering the top surface of the core die stack structure comprises:
and removing the isolation layer and the shielding material covering the isolation layer.
10. A semiconductor structure, comprising:
a core grain stack structure including at least a plurality of first core grains stacked, the first core grains having through-silicon via structures disposed therein, the first core grains being vertically stacked through the through-silicon via structures;
a first shielding structure disposed in the core die stack structure, the first shielding structure including at least a portion of the through silicon via structure, the first shielding structure disposed at an edge region of the core die stack structure;
a second shielding structure disposed around the core die stack at a circumferential edge of the core die stack, the second shielding structure covering a sidewall of each of the first core dies in the core die stack.
11. The semiconductor structure of claim 10, wherein the through silicon via structure comprises a plurality of first through silicon via structures and a plurality of second through silicon via structures;
the first through silicon via structures are arranged in the central region of the first core grain, the second through silicon via structures are arranged in the edge region of the first core grain around the first through silicon via structures, the second through silicon via structures surround the first through silicon via structures for one or more circles, and a first shielding layer is arranged in each second through silicon via.
12. The semiconductor structure of claim 11, wherein the core die stack further comprises:
a first bonding pad disposed on a first side of the first core die, the first bonding pad covering the first through-silicon-via structure exposed from the first side of the first core die;
a second pad disposed on a second side opposite the first side of the first core grain, the second pad covering the first through-silicon-via structure exposed by the second side of the first core grain;
the first core grains are vertically stacked in the core grain stacking structure according to the order that the first face and the second face are oppositely arranged, the first bonding pads and the second bonding pads of the adjacent first core grains are in bonding connection, a first cavity is arranged between the adjacent first core grains, and the second through silicon via structure is arranged as the first shielding structure.
13. The semiconductor structure of claim 12, wherein the core die stack further comprises:
the third bonding pad covers the second silicon through hole structure exposed from the first surface of the first core grain, and a second shielding layer covers the outer side of the third bonding pad;
the fourth bonding pad covers the second silicon through hole structure exposed from the second surface of the first core grain, and a third shielding layer covers the outer side of the fourth bonding pad;
in the core grain stacking structure, the third bonding pad and the fourth bonding pad of the adjacent first core grain are connected in a bonding mode, and the vertically connected second silicon through hole structure, the third bonding pad and the fourth bonding pad are jointly arranged into the first shielding structure.
14. The semiconductor structure of claim 13, wherein the core die stack further comprises:
a first dielectric layer filling the first cavity.
15. The semiconductor structure of claim 14, wherein the second shielding structure further covers sidewalls of each of the first dielectric layers in the core die stack structure along a circumferential direction of the core die stack structure.
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