WO2023034608A1 - Dispositifs à base de nitrure iii développés sur ou au-dessus d'un modèle conforme aux contraintes - Google Patents

Dispositifs à base de nitrure iii développés sur ou au-dessus d'un modèle conforme aux contraintes Download PDF

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WO2023034608A1
WO2023034608A1 PCT/US2022/042526 US2022042526W WO2023034608A1 WO 2023034608 A1 WO2023034608 A1 WO 2023034608A1 US 2022042526 W US2022042526 W US 2022042526W WO 2023034608 A1 WO2023034608 A1 WO 2023034608A1
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Norleakvisoth LIM
Philip Chan
Steven P. Denbaars
Michael J. Gordon
Shuji Nakamura
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The Regents Of The University Of California
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Definitions

  • DenBaars and Shuji Nakamura entitled “III- NITRIDE BASED DEVICES GROWN ON A THIN TEMPLATE ON THERMALLY-DECOMPOSED MATERIAL,” attorneys’ docket number G&C 30794.0802USP1 (UC 2021-888-1); and U.S. Provisional Application Serial No. 63/230,205, filed on August 6, 2021, by Philip Chan, Steven P. DenBaars and Shuji Nakamura, entitled “III-NITRIDE BASED DEVICES GROWN ON A THIN TEMPLATE ON THERMALLY-DECOMPOSED MATERIAL,” attorneys’ docket number G&C 30794.0802USP2 (UC 2021-888-2); and
  • This invention relates to Ill-nitride-based devices grown with a strain compliant template (SCT) to create a relaxed active region for the Ill-nitride-based devices and to improve the surface morphology of the Ill-nitride-based devices.
  • SCT strain compliant template
  • LEDs Inorganic micron-sized light-emitting diodes
  • LCDs liquid crystal displays
  • OLEDs organic light emitting diodes
  • UV ultra-violet
  • GaN gallium nitride
  • RGB red-green-blue
  • AlInGaP aluminum indium gallium phosphide
  • the main challenge encountered in fabricating higher efficiency, red light emitting InGaN-based pLEDs is growing InGaN layers with a high Indium content, while maintaining high structural and crystal qualities, which ultimately influence the optical and electrical properties of the devices.
  • the heteroepitaxial growth of GaN and InGaN thin films causes InGaN layers to be coherently strained to the GaN substrate, leading to decreased Indium incorporation [9], defect formation [10], and reduction in electron-hole recombination probabilities [5], Further, formation of InGaN alloys with a high Indium content is a thermodynamically unfavorable process, due to its wide immiscibility gap and high critical temperature [11], Moreover, growing InGaN films often results in phase-separated alloys.
  • the key to improving the efficiency of LEDs emitting red light and longer wavelengths is to develop a method to relieve strain in the quantum wells and quantum barriers in order to improve Indium incorporation, increase crystal quality, decrease defects, and grow at higher temperatures.
  • Previous studies have attempted different methods of strain relaxation through the addition of a relaxed layer between a GaN substrate and an active region containing multi-quantum wells (MQWs).
  • MQWs multi-quantum wells
  • a red light emitting InGaN-based LED was fabricated with the active region grown at a temperature of 870 °C, which is the highest growth temperature reported for red light emitting LEDs.
  • this method is limited by the InGaN buffer layer, which subjects the active region to compressive strain.
  • Atomic Force Micrograph (AFM) images show a high surface roughness greater than 5 nm and a no step-grow surface morphology.
  • the InGaN buffer showed a root mean square (RMS) roughness in a 5 x 5 pm 2 atomic force micrograph of 6 nm ⁇ 20 nm.
  • the present invention provides a method for fabricating a Ill-nitride based device, and the resulting Ill-nitride based device, using a mechanically -flexible strain compliant template (SCT) that allows subsequent layers to relax so that they are not coherently strained to a substrate or a template layer on the substrate, wherein: the strain compliant template comprises a decomposition layer (DL) and a decomposition stop layer (DSL); the decomposition stop layer is grown coherently strained to the decomposition layer; the decomposition layer is thermally-decomposed, which causes the decomposition stop layer to relax further; the Ill-nitride based device is grown on or above the decomposition stop layer after the decomposition layer is thermally-decomposed; the Ill-nitride based device comprises an n-type layer, an active region, and a p-type layer; and the n-type layer is relaxed because it is grown on or above the decomposition stop layer,
  • SCT mechanically
  • Fig. 1 is a cross-sectional schematic of an epitaxial structure grown with a buffer in tensile strain.
  • Fig. 2(a) is a cross-sectional schematic of a micro-LED
  • Fig. 2(b) is a top down view of the micro-LED
  • Fig. 3(a) is an X-ray diffraction (XRD) reciprocal space map (RSM)
  • Fig. 3(b) is a graph of intensity (counts/s) vs. wavelength (nm) for different current densities
  • Fig. 3(c) is a graph of EQE (%) vs. current density J (A/cm 2 ) for different pLED sizes
  • Fig. 3(d) is a graph of peak EQE (%) vs. device size (pm), for the microLED structure shown in Fig. 2(a).
  • Fig. 4 is a graph of peak EQE (%) for a 0.1mm 2 LED vs. relaxation (%)of the buffer layer of the LED.
  • Fig. 5 is a cross-sectional schematic of an epitaxial structure according to an embodiment of the invention.
  • Fig. 6 is a cross-sectional schematic of an epitaxial structure similar to that of Fig. 5, with the addition of an optional unintentionally doped (uid) DSL, without an electron blocking layer (EBL), and with the inclusion of a tunnel junction (TJ) contact.
  • Uid unintentionally doped
  • EBL electron blocking layer
  • TJ tunnel junction
  • Fig. 7 is a cross-sectional schematic of a device with an epitaxial structure similar to that of Fig. 5.
  • Fig. 8 is a cross-sectional schematic of a flip-chip device with an epitaxial structure similar to that of Fig. 5.
  • Fig. 9 is a cross-sectional schematic of an edge-emitting laser diode (EELD) with an epitaxial structure similar to that of Fig. 5.
  • EELD edge-emitting laser diode
  • Fig. 10 is a cross-sectional schematic of an epitaxial structure with a thermally-decomposed InGaN/GaN SL.
  • Fig. 11 is a cross-sectional schematic of a vertical cavity surface emitting laser (VCSEL) using thermally-decomposed InGaN/GaN SLs as distributed Bragg reflectors (DBRs).
  • VCSEL vertical cavity surface emitting laser
  • DBRs distributed Bragg reflectors
  • Fig. 12 is a cross-sectional schematic of an epitaxial structure according to an embodiment of the present invention, with a smooth InGaN buffer layer grown on a multi-layer GaN DSL at a low and high temperatures with N2 and H2 carrier gases.
  • Fig. 13 is a cross-sectional schematic of an epitaxial structure according to an embodiment of the present invention, with an InGaN buffer is comprised of an InGaN / GaN SL, wherein one period of the SL is shown.
  • Fig. 14 is a cross-sectional schematic of an epitaxial structure according to an embodiment of the present invention, illustrating an LED grown on an InGaN buffer comprised of an InGaN / GaN SL grown on an SCT.
  • Figs. 15(a), 15(b), 15(c) and 15(d) are RSMs and AFM images, wherein:
  • Fig. 15(a) is an RSM for a 90% relaxed Ino.025Gao.975N buffer layer comprised of InGaN / GaN SL grown on 200 nm GaN DSL grown at a temperature of 1150 °C, wherein the RSM is taken aligned to an off-axis (-1-124) peak, and the points plotted indicate a 90% relaxed Ino.o25Gao.975N layer;
  • Fig. 15(b) is an AFM image showing the surface morphology of the InGaN / GaN SL with a root mean square (RMS) surface roughness of 1.1 nm by 5 pm x 5 pm AFM, wherein step-grow surface morphology is observed;
  • RMS root mean square
  • Fig. 15(c) is an RSM for a 69% relaxed Ino.046Gao.954N buffer layer comprised of InGaN / GaN SL grown on a 300 nm GaN DSL at a temperature of 1150 °C; and
  • Fig. 15(d) is an AFM image showing the surface morphology of the InGaN / GaN SL with an RMS surface roughness of 2.0 nm by 5pm x 5pm AFM, wherein step-grow surface morphology is observed.
  • Figs. 16(a), 16(b) and 16(c) are AFM images showing the morphological improvement gained from increasing the growth temperature of a 70 nm GaN DSL using hydrogen as a carrier gas after capping the DL, wherein:
  • Fig. 16(a) shows the 70 nm GaN DSL grown at 930 °C in a nitrogen carrier gas, wherein the RMS roughness is 4.9 nm;
  • Fig. 16(b) shows the 70 nm GaN DSL grown at 975 °C in a nitrogen carrier gas, wherein the RMS roughness is 1.8 nm;
  • Fig. 16(c) shows the 70 nm GaN DSL grown at 930 °C in hydrogen carrier gas, wherein the RMS roughness is 2.8 nm; and no step-grow surface morphology is observed for all of the 70 nm DSL due to the low temperature growth less than 1000°C.
  • Figs. 17(a) and 17(b) illustrate an LED structure, wherein the n-type DSL is an n-type InGaN / GaN SL consisting of 10 periods of 5 nm InGaN and 5 nm GaN grown at a temperature of 930 °C, and then a red light emitting LED structure was grown including an n-type InGaN buffer consisting of 10 periods of 5 nm InGaN and 5 nm GaN grown at 900 °C as a part of a cladding layer, an active layer, and p-type layers, wherein:
  • Fig. 17(a) is a AFM image of the LED surface showing a 5.5 nm RMS roughness, pitting and lack of a step morphology by 5pm x 5pm AFM;
  • Fig. 17(b) is a graph of intensity (a.u.) vs, wavelength (nm) showing the emission spectrum with a peak wavelength around 640 nm at a current density of 20 A cm' 2 .
  • Figs. 18(a) and 18(b) illustrate an LED structure, wherein a high temperature n-type GaN DSL was grown at a temperature of 1100 °C, with the first 20 nm of GaN grown with nitrogen carrier gas while the remaining 980 nm of GaN was grown with hydrogen carrier gas, and then a red light emitting LED structure was grown including twenty -four periods of an InGaN / GaN SL consisting of 5 nm InGaN and 5 nm GaN grown at a temperature of 930 °C to form the n-type InGaN buffer layer, active layer, and p-type layers, wherein:
  • Fig. 18(a) is an AFM image of the LED surface showing a 3.5 nm RMS roughness, wherein V-pits are visible, but the surface shows a step morphology by 5 pm x 5 pm AFM;
  • Fig. 18(b) is a graph of intensity (a.u.) vs, wavelength (nm) showing the emission spectrum with a peak wavelength around 500 nm ⁇ 520 nm at a current density of 20 A cm' 2 .
  • Figs. 19(a), 19(b), and 19(c) illustrate an LED structure, wherein a 200 nm n- type GaN DSL was grown at a high temperature of 1150 °C, with the first 40 nm in nitrogen gas and the last 160 nm grown in hydrogen gas, an n-type InGaN buffer layer consisting of 50 periods of 16 nm n-type InGaN was grown at 950 °C in nitrogen gas, 2 nm n-type GaN was grown at 950 °C in nitrogen gas, and 2 nm n-type GaN was grown at 1000 °C in 5% hydrogen and 95% nitrogen gas, and then an active layer and p-type layers were grown to form the red light emitting LED structure, wherein:
  • Fig. 19(a) is a AFM image that shows the surface morphology of the LED, wherein step-flow growth is shown with an RMS surface roughness of 0.9 nm by 5 pm x 5 pm AFM;
  • Fig. 19(b) is a graph of intensity (a.u.) vs, wavelength (nm) showing the emission spectrum with a peak wavelength around 460 nm at a current density of 20 A cm' 2 ;
  • Fig. 19(c) is an X-ray RSM showing a 113% relaxation of the InGaN buffer layer of Ino.028Gao.972N, which is an average composition of InGaN / GaN SL.
  • Fig. 20 is a flowchart that illustrates the steps for a process of fabricating a III- nitride-based device according to the present invention.
  • This invention discloses a method of fabricating Ill-nitride-based devices, such as LEDs and LDs, using a mechanically-flexible SCT that allows subsequent layers to relax so that they are not coherently strained to a substrate or a template layer on the substrate.
  • the Ill-nitride-based devices are grown with a relaxed active region.
  • the SCT comprises a DL, which is an InGaN underlayer, and a DSL, which is one or more GaN and/or InGaN layers.
  • a thin n- type layer which is an InGaN buffer layer, is grown on the SCT, followed by a thick InGaN active region, and a thin p-type layer.
  • the DSL is grown coherently strained to the DL. Once the DL is thermally- decomposed and relaxed, this causes the DSL to either relax further or be in tensile strain. The subsequent thin n-type layer is in tensile strain because it is coherently strained to the DSL. This allows the active region to relax further, leading to higher crystal film quality, lower defects, and higher peak EQEs.
  • Fig. 1 illustrates an LED structure grown on a tensile strained InGaN buffer layer and SCT.
  • the LED structure 100 includes a c-GaN or PSS substrate 101, GaN template 102, InGaN DL 103, InGaN/GaN DSL 104, InGaN/GaN buffer 105, InGaN/GaN active region 106, p-GaN 107, p-InGaN/p-GaN 108, and p++GaN 109.
  • InGaN layers are defined as In x Ga(i- X )N layers, where 0 ⁇ x ⁇ l.
  • a sample was prepared comprising a GaN template 102 with a thickness > 2.15 pm that was grown on a c-GaN or PSS substrate 101.
  • the DL 103 which is comprised of an InGaN layer of approximately 2.6 nm thickness, was grown at a trimethylindium (TMI) to triethylgallium (TEG) molar ratio of 3 and a growth temperature of 720°C.
  • TMI trimethylindium
  • TMG triethylgallium
  • the DSL 104 which is comprised of 10 periods of 7 nm InGaN and 3 nm GaN, was grown at a temperature of 950°C.
  • the InGaN buffer layer 105 which is a thin n-type layer, comprised of 5 periods of 20 nm InGaN and 2 nm GaN, was grown at a temperature of 920 °C.
  • the DL 103 is expected to thermally decompose during the growth of the DSL 104 and InGaN buffer layer 105.
  • an active region 106 comprised of 8 periods of 2.5 nm InGaN quantum wells and 7 nm GaN quantum barriers, was grown at a temperature of 820°C.
  • the InGaN/GaN buffer layer 105 has an average Indium composition of 4.9% with a tensile strain of 0. 16%.
  • the peak wavelength was determined to be 627 nm ⁇ 1 nm through a quick test (QT) method at three points on the sample, from a center to an edge of a 2-inch wafer.
  • the whole 2- inch wafer shows uniform red emission.
  • the uniformity becomes very poor with varying peak wavelengths, ranging from a red emission at the center to a blue emission at the edge of the 2-inch wafer.
  • the peak EQEs of 100x100 pm 2 and 5x5 pm 2 pLEDs fabricated from the same LED structure are -0.15% and -0.40%, respectively.
  • Fig. 2(a) shows a cross-sectional side-view of the micro-LED 200, which has an epitaxial structure similar to the epitaxial structure 100 of Fig.
  • SiC reactive ion etching was used to etch a mesa 210 and electrically isolate each device 200.
  • the mesa 210 sidewalls were passivated by depositing 20 nm of SiO2 211 using atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • 300 nm of SiO2 was deposited as an omni-directional broadband reflector 212 using an ion beam deposition technique.
  • the metal contacts 208, 209 comprised of 300 nm Al, 100 nm Ni, and 700 nm Au, were deposited via an electron beam deposition method.
  • Fig. 3(a) shows the result of x-ray diffraction measurements of the LED 200 described in Figs. 2(a) and 2(b).
  • the RSM shows three distinct peaks for GaN, Ino.024Gao.976N and Ino.049Gao.951N, wherein the average Indium compositions of the DSL 203 and the buffer layer 204 are 2.4% and 4.9%, respectively.
  • their respective tensile strains are 0.28% and 0.16%.
  • This shows that a buffer layer 204 can be grown in tensile strain on the DSL 203. It is observed that the emission peak wavelength is quite uniform across half of a 2-inch wafer containing such LEDs 200, varying from 620 nm to 630 nm due to the uniform strain over the 2-inch wafer.
  • Fig. 3(b) shows the electroluminescence (EL) intensity and spectra of a 0.1 mm 2 LED fabricated with the same structure as shown in Figs. 2(a) and 2(b) at different current densities.
  • the LED displays a peak wavelength shift from 633 nm to 606 nm from 10 A cm 2 to 200 A cm 2 .
  • Fig. 3(c) shows the current density and the corresponding EQE of 100x100 pm 2 , 40x40 pm 2 , 20x20 pm 2 , 10x10 pm 2 , and 5x5 pm 2 LEDs fabricated as described in Figs. 2(a) and 2(b).
  • the current density corresponding to peak EQE remains about the same across the different device sizes, ranging from 6 A cm 2 to 10 A cm 2 . This indicates that there is little to no contribution from sidewall recombination, which would reduce the EQE as the device size decreases.
  • Fig. 3(d) shows the peak EQE trend with respect to device size.
  • the peak EQE increases with respect to the decreasing device size.
  • the peak EQE of 5x5 pm 2 LEDs can increase up to two times of that the 100x100 pm 2 LEDs.
  • the smaller mesa could have relaxed during the SiCh RIE etch or during the SiCh passivation, which was carried out at 300°C for approximately an hour, due to thermal annealing.
  • the mesa relaxation could have been facilitated by the SCT. This would ultimately reduce the strain in the quantum wells, reduce the quantum confinement stark effect (QCSE), and increase the radiative recombination efficiency of the quantum wells.
  • QCSE quantum confinement stark effect
  • Fig. 4 shows the peak EQE of 0.1mm 2 LEDs fabricated with varying degrees of buffer layer relaxation.
  • the buffer layer relaxation exceeds 100%, it implies that the buffer layer is under tensile strain.
  • the peak EQE of the LED increases with respect to increasing buffer layer relaxation. This further supports that growing the buffer layer in tensile strain on an SCT can lead to further relaxation in the active region; thus enhancing the EQE of LEDs.
  • Fig. 5 depicts an epitaxial structure 500 in an embodiment of the present invention.
  • the structure 500 includes a substrate 501, GaN template 502, SCT 503 (comprised of a DSL and decomposed DL), n-type layers or InGaN buffer 504, active region 505, p-AlGaN EBL 506, and p-type layers 507.
  • the substrate 501 can be sapphire (patterned or polished), Si, SiC, bulk GaN, or a GaN template, of any crystal plane such as semipolar, nonpolar, Ga-plane (c-plane) and N-plane (-c-plane).
  • a GaN template means a GaN layer with a thickness of 3 to 10 pm grown on a substrate comprised of sapphire (patterned or polished), Si, SiC, or bulk GaN of any crystal plane.
  • GaN templates grown on sapphire or Si substrates are commercially available.
  • an n-type or uid GaN template 502 with a typical thickness between 3 and 10 pm. This layer 502 is dependent on the substrate 501 and is used as a method of reducing defect density and seeding morphologically good crystal growth for subsequent layers.
  • the SCT 503 is then grown as either a single high Indium composition In x Gai- X N layer or as a series of In x Gai- x N layers with GaN, lower composition InGaN, or AlGaN interlayers between the In x Gai-xN layers.
  • An n-type or uid DL may be included in the SCT 503, wherein the DL layer is GaN, InGaN or AlGaN grown at a low temperature of 720 °C.
  • An n-type or uid DSL may be included in the SCT 503, wherein the DSL layer is GaN, InGaN or AlGaN grown at a high temperature over 900 °C, which thermally decomposes the DL, which serves to form voids in the DL, to allow the expansion of the in-plane lattice constant to reduce strain in the active region 505.
  • a full P-I-N diode is then grown.
  • the n-type layers or InGaN buffer 504 are grown first. These may be n-type In y Gai- y N with y being less than x, or GaN. These layers 504 are under tensile strain and must be grown thin enough to prevent cracking.
  • the active region 505 is comprised of undoped active layers, including a bottom spacer, single or multiple periods of quantum wells and barriers, and a top spacer.
  • the spacer and barriers may be GaN, InGaN or AlGaN, and have thicknesses less than 50 nm.
  • the quantum wells are InGaN layers less than 10 nm thick emitting in blue, green, red or near infrared wavelengths.
  • An AlGaN cap layer with the thickness less than 4 nm could be inserted between the InGaN QWs and GaN barriers to minimize the strain between the InGaN QWs and GaN barriers.
  • the GaN barrier growth temperature could be increased about 100°C higher than the InGaN QW growth temperature.
  • the Mg-doped p-type AlGaN EBL 506 with an Al mol fraction ranging from 0.1 to 0.4 and 10-30 nm in thickness may be included.
  • One or more p-type layers 507 including InGaN and/or GaN layers, also under tensile strain, are grown.
  • An optional tunnel junction (not shown) may be formed with the growth or regrowth of n-type GaN and/or InGaN layers on top of the p-type layers 507.
  • Fig. 6 depicts an epitaxial structure 600 in another embodiment of the present invention.
  • the structure 600 includes a substrate 601, GaN template 602, SCT 603, n-type layers 604, active region 605, p-type layers 606, and n-type layers (tunnel junction) 607.
  • This structure 600 includes the addition of the optional n-type DSL in the SCT 603, without an EBL, and with the inclusion of a tunnel junction 607.
  • the n-type and p-type layers 604, 606 should be under tensile strain with the active region 605 being relaxed or under slight compressive stress.
  • Fig. 7 illustrates a device using epitaxial layers similar to those in Fig. 1, in another embodiment of the present invention.
  • the LED 700 includes a substrate 701, GaN template 702, SCT 703, n-type layers 704 and 705, active region 706, EBL 707, p-type layers 708, p-contact 709, n-contact 710, SiCh passivation layers 711, and p-pad 712.
  • TCO transparent conducting oxide
  • ITO indium tin oxide
  • ZnO zinc oxide
  • a mesa 713 is patterned through photolithography. This pattern is used to etch the TCO layer 709 using, for example, a methane/hydrogen/argon RIE etch and the mesa 713 is formed to the n-type layers 704 by dry etching, for example, a SiCL RIE etch.
  • the mesa 713 may be any size, typically between 1x1 mm 2 and over 1x1 pm 2 .
  • An isolation oxide such as the SiO2 layer 711, is then deposited over the sidewalls of the mesa 713 using a photolithographic lift-off technique to allow for an off-mesa p-pad 712.
  • a more complex dielectric stack may be used to form an omnidirectional reflector.
  • the sidewall passivation oxide 711 is deposited by ALD, and comprises either SiCh or AI2O3.
  • photolithography is again used to pattern the device 700 for the n- contact 710 and pad metal (not shown). If an ALD oxide was used to passivate the sidewall, then an oxide etch is performed before metal is deposited, for example, 700 nm Al, 100 nm Ni and 700 nm Au.
  • Fig. 8 illustrates another embodiment of the present invention, wherein the device architecture is a flip-chip LED 800, which involves the removal of the substrate (not shown).
  • the LED 800 includes n-type layers 801, 802, active region 803, EBL 804, p-type layers 805, SiO2 passivation layers 806, p-contact
  • n-contact 807 n-contact 807
  • p-pad 808 submount 809.
  • This flip-chip LED 800 can be achieved by the inclusion of a sacrificial layer (not shown) during the epitaxial growth, wherein the sacrificial layer comprises a single quantum well (SQW) or multi-quantum wells (MQWs) in the n-type layers 801.
  • a photoelectrochemical (PEC) etch can be used to selectively etch the sacrificial layer when exposed to remove the substrate.
  • PEC photoelectrochemical
  • an etch or thermal or chemical process may be used to delaminate the epitaxial layers from the substrate at the DL without the need to include a sacrificial layer comprising a SQW or MQW.
  • a TCO layer is deposited to form the p-contact
  • a mesa 810 is patterned through photolithography, and the TCO layer 807 and epilayers 802, 803, 804, 805 are etched through a dry etching process.
  • the mesa 810 is etched through the active region 803 but stopping short of the sacrificial layer, be it a SQW, MQW or the DL.
  • the sidewall is passivated by SiO2 806 deposited by ALD.
  • a second, larger mesa is patterned by photolithography and etched through the sacrificial layer.
  • Metal is then deposited as the p-pad 808 and patterned through a liftoff technique.
  • a typical metal stack for p-pad 808 is 700 nm Al, 100 nm Ni and 700 nm Au.
  • the device 800 is then flipped and bonded onto the submount 809. Several options for the submount 809 and its bonding methods are possible and are application dependent.
  • the substrate is then removed as described before, leaving the device 800 bonded to the submount 809. Finally, metal is deposited and patterned to form the n-contact 808.
  • Fig. 9 illustrates another embodiment of the present invention, wherein thin, tensile-strained, n-type and p-type layers may be used to create an edge-emitting laser diode (EELD) 900.
  • the EELD 900 includes a substrate 901, GaN template 902, SCT 903, n-type layers 904, 905, active region 906, p-type layers 907, 908, SiCh passivation layer 909, p-contact 910, n-contacts 911, and p-pad 912.
  • n- and p-side e.g., n-type layers 905 and p-type layers 907
  • SCH separate confinement heterostructure
  • a ridge structure 913 is patterned by photolithography.
  • the epitaxial layers 908 are etched by reactive ion etch, for example, SiCh or Ch.
  • An isolation oxide, for example, SiCh 909, is then deposited and patterned through lift-off in a selfaligned process.
  • This ridge 913 serves as a lateral waveguide.
  • a TCO is deposited as p-contact 910 and patterned by photolithograph and dry etch. Top-side n-contacts
  • a typical metal stack for the p-pad 912 is 10 nm Ti and 1000 nm Au.
  • Fig. 10 illustrates a device structure 1000 in another embodiment of the present invention, which includes the realization of a series of InGaN and GaN layers for the thermally-decomposed DL.
  • the device structure 1000 includes a substrate 1001, GaN template 1002, decomposed InGaN/GaN SL 1003 as the DL, n- type layers 1004, active region 1005, and p-type layers 1006.
  • the alternating layers of the thermally-decomposed InGaN and GaN SL 1003 will lead to better control of the relaxation, better crystal quality, and improved surface morphology.
  • the n-type layers 1004 are grown on top of the thermally - decomposed InGaN/GaN SL 1003.
  • a P-I-N diode structure 1004, 1005, 1006 is grown on the thermally-decomposed InGaN/GaN SL 1003.
  • the p-type and the n-type layers 1004, 1006 are grown in tensile strain, whereas the active region 1005 should be partially relaxed or fully relaxed.
  • the thermally-decomposed InGaN/GaN SL 1003 includes voids, and thus the average refractive index of the decomposed InGaN layers within 1003 will be different from that of a normal InGaN layer.
  • the thermally-decomposed InGaN/GaN SL 1003 can be considered as a distributed Bragg reflector (DBR).
  • DBR distributed Bragg reflector
  • the wavelength-dependent reflectivity of the thermally-decomposed InGaN/GaN SL 1003 can be tuned by varying the thicknesses of InGaN and GaN layers therein, and the degree of void formation in the InGaN layers therein. By tuning the reflectivity of the thermally-decomposed InGaN and GaN layers in the SL 1003, the light extraction of the device structure 1000 can be enhanced; thus, significantly improving the EQE of the device structure 1000.
  • Fig. 11 illustrates another embodiment of the present invention that makes use of the thermally-decomposed InGaN and/or GaN layers as a DBR.
  • the device structure 1100 includes a substrate 1101, GaN template 1102, decomposed InGaN/GaN SL 1103, n-type layers 1104, active region 1105, oxide aperture 1106, p- type layers 1107, and decomposed InGaN/GaN SL 1108.
  • both the thermally-decomposed InGaN/GaN SLs 1103, 1108 are DBRs.
  • This DBR design can be further applied to a vertical cavity surface emitting laser (VCSEL).
  • VCSEL vertical cavity surface emitting laser
  • a series of thermally- decomposed InGaN and GaN layers 1103 are grown as an SL on a GaN template 1102.
  • This InGaN and GaN SL 1103 can be uid or doped.
  • the InGaN and GaN SL 1103 has at least one layer that serves as the DL and simultaneously as a backside DBR.
  • the InGaN and GaN SL 1103 also includes one or more layers that serve as an DSL grown on the DL.
  • An active region 1105 and a layer 1106 of dielectric oxide are grown on the n-type layers 1104, with the layer 1106 serving as the aperture.
  • one or more p-type layers 1107 are grown on the oxide layer 1106.
  • the p-type layers 1107 can be p- doped InGaN, p-doped GaN, or a series of p-GaN and p-InGaN layers.
  • SL 1108 is grown, which is a frontside DBR.
  • the thicknesses and degrees of void formation of the InGaN and GaN layers in both the frontside and backside DBRs 1108, 1103, are determined based on the target emission wavelength of the device 1100.
  • This invention disclose a method of fabricating Ill-nitride-based devices, such as LEDs or LDs, wherein the devices are comprised of a mechanically-flexible SCT that allows subsequent layers to relax so that they are not coherently strained to the substrate.
  • the devices are comprised of a mechanically-flexible SCT that allows subsequent layers to relax so that they are not coherently strained to the substrate.
  • the SCT uses a thin thermally-decomposed InGaN underlayer as the DL with the thickness less than 20 nm, and a thin GaN or InGaN DSL.
  • a thin n-type layer comprising an InGaN buffer, with a thickness less than 400 nm, is grown on the SCT, followed by a relatively thick InGaN active region with more than 4 QWs, and a subsequently grown thin p-type layer with the thickness less than 300 nm.
  • the GaN/InGaN DSL is grown coherently strained to the InGaN DL.
  • the InGaN DL is thermally-decomposed and relaxed, this will cause the GaN/InGaN DSL to either relax further or be in tensile strain.
  • the subsequent InGaN buffer layer or n-type layer will be in tensile strain because it is coherently strained to the DSL. This will allow the active region to relax further, leading to higher crystal film quality, lower defects, and higher EQE.
  • GaN and an InGaN / GaN SL was used as the DSL.
  • the growth temperature of the DSL was lower than 1000°C. Due to the low temperature growth of the DSL, the surface of InGaN buffer comprised of an InGaN / GaN SL grown on the DSL, and the top surface of the LED device itself, have no step-grow surface morphology, and showed an RMS roughness in a 5 * 5 pm 2 AFM of 6 nm ⁇ 20 nm.
  • the GaN DSL was grown at a high temperature of more than 1000 °C, and more preferably, at a growth temperature of 1100 °C ⁇ 1150 °C, with a hydrogen carrier gas.
  • the first 10 nm ⁇ 200 nm of the GaN DSL was grown with a nitrogen carrier gas to prevent the dissociation of the underlayer InGaN DL.
  • a step growth of the InGaN buffer on the DSL was observed, and a top surface of the LED was smooth, i.e., the top surface of the LED had an RMS roughness less than 4 nm in a 5x5 pm 2 AFM.
  • the InGaN/GaN buffer comprised of 50 periods of a 16 nm InGaN / 4 nm GaN SL, was grown on 200 nm or 300 nm of the GaN DSL at 950°C to improve the surface morphology further.
  • Each InGaN layer of the InGaN/GaN buffer was grown with a nitrogen carrier gas at 950 °C
  • each 2 nm GaN of the InGaN/GaN buffer was grown with a nitrogen carrier gas at 950 °C
  • another 2 nm GaN was grown with 5% hydrogen and 95% nitrogen.
  • an InGaN buffer is grown only with a nitrogen carrier gas, which results in a surface morphology of the InGaN buffer and the LED that is very poor.
  • the output power or EQE of those devices can be increased.
  • Fig. 12 depicts an epitaxial structure with a smooth buffer layer on an SCT, according to one embodiment of the present invention.
  • the device structure 1200 includes a substrate 1201, GaN template 1202, InGaN DL 1203, low temperature GaN layer 1204, high temperature GaN layer 1205 grown using an N2 carrier gas, high temperature GaN layer 1206 grown using an H2 carrier gas, and n- type buffer 1207.
  • the substrate 1201 can be sapphire (patterned or polished), Si or bulk GaN of any crystal plane.
  • an- type or uid GaN template 1202 with typical thickness between 5 and 10 pm. This layer 1202 is dependent on the substrate 1201 and is used as a method of reducing defect density and seeding morphologically -good crystal growth for subsequent layers.
  • the InGaN DL 1203 is then grown, comprising a single high Indium composition In x Gai- x N layer, or as a series of In x Gai- x N layers with GaN layers, lower composition InGaN, or AlGaN interlayers between the In x Gai- x N layers.
  • the InGaN DL 1203 is thermally-decomposed, which allows for the expansion of the in-plane lattice constant to reduce strain in an active region (not shown).
  • n-type or uid GaN DSL is included, wherein the GaN DSL is grown in several steps.
  • a thin capping layer 1204 is grown above the DL 1203. This layer 1204 serves to preserve the DL 1203 and is grown at or near the growth temperature of the DL 1203.
  • a GaN layer 1205 is grown at a high temperature over 1000 °C, which serves to recover morphologically smooth growth and form voids in the DL 1203 to allow for relaxation.
  • the first part of the high temperature GaN 1205 growth is done with a nitrogen carrier gas to prevent gas-etching of the Indium-containing DL 1203.
  • the final part of the high temperature GaN 1206 growth is done with a hydrogen or mixture of hydrogen and nitrogen carrier gases to improve morphology.
  • the layers 1204, 1205, 1206 are less than 2 pm thick to prevent cracking from tensile stress.
  • the buffer layer 1207 is an InGaN/GaN SL, one period 1300 of which is depicted in Fig. 13.
  • the InGaN layer 1301 serves to increase the in-plane lattice constant and allow for subsequent growth of a partially-relaxed active region.
  • This InGaN layer 1301 may have an Indium composition from 0% to 30% and is grown at a temperature Ti between 850 °C to 1000 °C with nitrogen as the carrier gas.
  • a thin GaN layer 1302 is then grown, also with a nitrogen carrier gas at Ti. This GaN layer 1302 serves to protect the InGaN layer 1301 underneath it. Then, the temperature is increased and another GaN layer 1303 is grown at T2 with hydrogen or a mixture of hydrogen and nitrogen as a earner gas. This sequence is repeated to create a buffer layer 1207 with a thickness greater than 500 nm.
  • Fig. 14 depicts an LED structure on a smooth buffer layer on an SCT, according to one embodiment of the present invention.
  • the LED structure 1400 includes a substrate 1401, GaN template 1402, SCT 1403, n-type layers 1404, active region 1405, p-type AlGaN EBL 1406 and p-type layers 1407.
  • the n-type layers 1404 include a buffer layer. Additional uid or n-type GaN or InGaN layers may be included in the n-type layers 1404 above the buffer.
  • the active region 1405 is comprised of undoped active layers, including a bottom spacer, single or multiple periods of quantum wells and quantum barriers, and a top spacer.
  • the spacer and barriers may be GaN, InGaN or AlGaN and be of thicknesses less than 50 nm.
  • the quantum wells are InGaN layers with a thickness under 10 nm emitting in blue, green, red or near infrared wavelengths.
  • the Mg-doped p-type AlGaN EBL 1406 has an Al mol fraction ranging from 0.1 to 0.4 with a thickness of 10-30 nm.
  • the p-type layers 1407 may comprise InGaN or GaN layers 1407.
  • An optional tunnel junction (not shown) may be formed with the growth or regrowth of n-type GaN or InGaN layers on top of the p-type layers 1407.
  • Figs. 15(a), 15(b), 15(c) and 15(d) are high resolution x-ray diffraction RSMs and AFMs of acceptable smooth InGaN buffer layers on SCTs.
  • the structures with data shown in Figs. 15 were all grown by metalorganic chemical vapor deposition (MOCVD) on 7 pm GaN templates on patterned sapphire substrates (PSS).
  • MOCVD metalorganic chemical vapor deposition
  • the GaN templates show very low roughness under 1 nm root RMS and step-flow morphology.
  • Precursors in all subsequent layers include triethylgallium (TEG) and trimethylgallium (TMG), trimethylindium (TMI), trimethylaluminum (TMA), disilane, biscyclopentadienylmagnesium (Cp2Mg), and ammonia (NHs).
  • TAG triethylgallium
  • TMG trimethylgallium
  • TMI trimethylindium
  • TMA trimethylaluminum
  • disilane trimethylaluminum
  • Cp2Mg biscyclopentadienylmagnesium
  • NHs ammonia
  • Figs. 15(a) and 15(b) show an RSM and AFM of a structure with a 90% relaxed Ino.025Gao.975N buffer layer with a RMS surface roughness of 1.1 nm.
  • An additional 2 nm of GaN was grown at 750 °C with 2.5 pmol/min of TEG, 2 nm of GaN grown at 850 °C with 2.5 pmol/min of TEG, 6 nm of GaN grown at 950 °C with 3.8 pmol/min of TEG, and 190 nm of GaN grown at 1150 °C with 13.2 pmol/min of TMG to make up the DSL.
  • the first 40 nm of the GaN grown at 1150 °C are grown with a nitrogen carrier gas, while the last 150 nm is grown with hydrogen carrier gas.
  • the buffer consists of 50 periods of 16 nm Ino.o25Gao.o975N grown at 950 °C with nitrogen carrier gas, 2 nm of GaN grown at 950 °C with nitrogen carrier gas, and 2 nm of GaN grown at 1000 °C with 5% hydrogen and 95% nitrogen carrier gas.
  • the buffer is grown in low ammonia flow of 1 slm, 15.2 pmol/min of TEG and 15.4 pmol/min of TMI in the InGaN layers.
  • Figs. 15(c) and 15(d) show an RSM and AFM of another structure. They depict a 69% relaxed Ino.o46Gao.954N buffer layer with a root mean square (RMS) surface roughness of 2.0 nm. As seen in the Fig. 15(d), v-pit structures are visible because of the increased indium content and fewer buffer periods in the structure when compared to the structure used for Figs. 15(a) and 15(b).
  • RMS root mean square
  • the first 133 nm of the GaN grown at 1150 °C are grown with a nitrogen carrier gas while the last 177 nm is grown with hydrogen carrier gas.
  • the buffer consists of 50 periods of 16 nm Ino.046Gao.954N grown at 950 °C with nitrogen carrier gas, 2 nm of GaN grown at 920 °C with nitrogen carrier gas, and 2 nm of GaN grown at 1000 °C with 5% hydrogen and 95% nitrogen carrier gas. Both of InGaN buffer shows a step-grow surface morphology.
  • Figs. 16(a), 16(b) and 16(c) show the morphological improvement gained from increasing the temperature of 70 nm GaN DSL growth and using hydrogen as a carrier gas after capping the DL.
  • Fig. 16(a) shows an AFM of an SCT comprised of a 2.5 nm InGaN DL grown at 720 °C, 2 nm of GaN grown at 720 °C, 2 nm of GaN grown at 835 °C, and 70 nm of GaN grown at 930 °C in nitrogen carrier gas.
  • the RMS roughness is 4.9 nm.
  • Fig. 17(a) shows an AFM
  • Fig. 17(b) shows the spectra from an LED grown without these improvements.
  • a 2.5 nm InGaN DL was grown at 720 °C followed by 2 nm of GaN at 720 °C and 2 nm of GaN at 835 °C. No GaN DSL was included.
  • n-type first SL was then grown consisting of 10 periods of 5 nm InGaN and 5 nm GaN at 930 °C.
  • a second n-type SL was then grown consisting of 10 periods of 5 nm InGaN and 5 nm GaN at 900 °C. These layers form an n-type InGaN buffer for the device.
  • Fig. 18(a) shows an AFM and Fig. 18(b) shows the spectra from an LED with this improvement.
  • the device structure starts with a 2.5 nm InGaN DL grown at 750 °C on top of a 7 pm GaN template on PSS.
  • a high temperature GaN DSL was grown at a temperature of 1100 °C.
  • the first 20 nm of GaN was grown with nitrogen carrier gas while the remaining 980 nm of GaN was grown with hydrogen carrier gas.
  • Twenty-four periods of 5 nm InGaN and 5 nm GaN were grown at a temperature of 930 °C to form the n-type InGaN buffer layer.
  • 30 nm of p-type GaN was grown with a 15 nm p + -GaN contact layer both grown at 920 °C.
  • the LED surface shows 3.5 nm RMS roughness. V-pits are visible from the InGaN layer but the surface shows a step morphology. Finally, the emission spectrum at a current density of 20 A cm' 2 at the center of the two-inch wafer (dark blue), half-radius (light blue) and edge (purple) is shown.
  • Fig. 19(a) shows an AFM and Fig. 19(b) shows the spectra from an LED with a GaN DSL grown at high temperature, partly in hydrogen, and the buffer condition outlined in Fig. 13.
  • the DL is grown at 750 °C.
  • 2 nm of GaN is grown at 750 °C
  • 2 nm of GaN is grown at 850 °C
  • 3 nm of GaN is grown at 950 °C.
  • the DSL is grown at 1150 °C, with the first 40 nm in nitrogen gas and the last 160 nm in hydrogen gas.
  • the buffer layer consists of 50 periods of 16 nm n-type InGaN grown at 950 °C in nitrogen gas, 2 nm n-type GaN grown at 950 °C in nitrogen gas, and 2 nm n-type GaN grown at 1000 °C grown in 5% hydrogen and 95% nitrogen gas.
  • 30 nm of p-type GaN was grown with a 15 nm p + -GaN contact layer both grown at 920 °C.
  • Fig. 19(a) shows the morphology of the LED. Step-flow growth is shown with an RMS surface roughness of 0.9 nm.
  • the emission spectrum in Fig. 19(b) was taken at a current density of 20 A cm' 2 at the center of the two-inch wafer (dark blue) and half-radius (light blue).
  • An RSM is shown in Fig. 19(c) showing the buffer layer is relaxed Ino.028Gao.972N.
  • FIG. 20 is a flowchart that illustrates the steps for a process of fabricating a Ill-nitride-based device, according to the present invention. Specifically, the flowchart illustrates the steps for a method comprising fabricating a Ill-nitride-based device using a mechanically -flexible strain compliant template that allows subsequent layers to relax so that the subsequent layers are not coherently strained to a substrate or a template layer on the substrate.
  • Block 2000 represents the step of loading a substrate into a chamber of an MOCVD reactor.
  • the substrate may comprise sapphire, bulk GaN, SiC, Si, or other materials.
  • Block 2001 represents the optional step of growing a Ill-nitride-based template on or above the substrate.
  • the Ill-nitride-based template may comprise GaN when fabricating InGaN-based devices.
  • Blocks 2002-2003 represent the steps of creating the strain compliant template, which is comprised of a decomposition layer and a decomposition stop layer.
  • Block 2002 represents the step of creating a Ill-nitride-based decomposition layer on or above the Ill-nitride-based template.
  • the III-nitride- based decomposition layer comprises one or more InGaN and/or GaN layers, for example, an InGaN/GaN superlattice, which may comprise a distributed Bragg reflector (DBR).
  • DBR distributed Bragg reflector
  • Block 2003 represents the step of creating a Ill-nitride-based decomposition stop layer (DSL) on or above the Ill-nitride based decomposition layer, wherein the decomposition stop layer is grown coherently strained to the decomposition layer.
  • the Ill-nitride-based decomposition stop layer comprises one or more InGaN and/or GaN layers.
  • Block 2004 represents the step of decomposing and relaxing the III -nitridebased decomposition layer by increasing the temperature, but not decomposing the Ill-mtnde-based decomposition stop layer, which causes the decomposition stop layer to relax further.
  • This step may be performed as part of Block 2003 when epitaxially growing the Ill-nitride-based decomposition stop layer.
  • the Ill-nitride-based template or substrate may be annealed at a high temperature to decompose or melt the Ill-nitride-based decomposition layer, which has a lower sublimation temperature or melting point than the Ill-nitride-based decomposition stop layer.
  • the decomposition stop layer is grown at a high temperature of at least 950 °C, preferably more than 1000 °C, and more preferably 1100 °C ⁇ 1150 °C.
  • a first portion of the decomposition stop layer may be grown with a nitrogen carrier gas to prevent the dissociation of the decomposition layer, and a remaining portion of the decomposition stop layer may be grown with a hydrogen carrier gas.
  • Block 2005 represents the optional step of epitaxially growing a III-nitride- based buffer layer on or above the Ill-nitride-based decomposition stop layer after the Ill-nitride-based decomposition layer is decomposed.
  • the buffer layer may comprise an n-type layer, such as a GaN layer, an InGaN layer, or an InGaN and GaN superlattice, and the buffer layer may exhibit a step growth on the decomposition stop layer.
  • each InGaN layer of the InGaN/GaN superlattice is grown with a nitrogen carrier gas
  • each GaN layer of the InGaN/GaN superlattice is grown with a nitrogen carrier gas for a first portion
  • each GaN layer of the InGaN/GaN superlattice is grown with a partially hydrogen carrier gas for a remaining portion at a higher growth temperature than the InGaN layer.
  • Block 2006 represents the step of epitaxially growing a Ill-nitride-based device structure on or above the Ill-nitride-based decomposition stop layer and the optional Ill-nitride-based buffer layer, wherein the Ill-nitride based device structure is grown on or above the decomposition stop layer after the decomposition layer is thermally-decomposed.
  • the Ill-nitride-based device structure includes at least an n-type layer, active region, and p-type layer.
  • the n-type layer is relaxed because it is grown on or above the decomposition stop layer, which allows the active region to relax further.
  • the tensile strain in the n-type layer is controlled by changing growth conditions of the decomposition stop layer and the n-type layer.
  • Block 2007 represents the step of processing the Ill-nitride-based device structure into a Ill-nitride based device, such as an LED or LD, and then packaging the device. This may include, but is not limited to, depositing TCO layers, submounting, etching mesas or ridge waveguides, passivating sidewalls, depositing electrodes, etc.
  • Block 2008 represents the end result of the method, namely, a III -nitride-based device according to the present invention, wherein the Ill-nitride-based decomposition stop layer is created on or above the Ill-nitride-based decomposition layer; the III- nitride-based decomposition layer is decomposed, but the Ill-nitride based decomposition stop layer is not decomposed; and the Ill-nitride-based device structure is grown on or above the Ill-nitride-based decomposition stop layer.
  • the III-nitride- based device may comprise, for example, an LED, LD, or other device.
  • these terms as used herein are intended to be broadly construed to include respective nitrides of the single species, B, Al, Ga, In, Sc and Yn, as well as binary, ternary, quaternary, etc., compositions of such Group III metal species. Accordingly, these terms include, but are not limited to, the compounds of AIN, GaN, InN, AlGaN, AllnN, InGaN, AlGalnN, etc.
  • compositions including stoichiometric proportions as well as off-stoichiometric proportions (with respect to the relative mole fractions present of each of the (B, Al, Ga, In, Sc, Y)N component species that are present in the composition), can be employed within the broad scope of this invention.
  • compositions and materials within the scope of the invention may further include quantities of dopants and/or other impurity materials and/or other inclusional materials.
  • This invention also covers the selection of particular crystal orientations, directions, terminations and polarities of Ill-nitride materials.
  • braces, ⁇ ⁇ denotes a set of symmetry-equivalent planes, which are represented by the use of parentheses, ( ).
  • brackets, [ ] denotes a direction
  • brackets, ⁇ > denotes a set of symmetry-equivalent directions.
  • III -nitride devices are grown along a polar orientation, namely a c-plane ⁇ 0001 ⁇ of the crystal, although this results in an undesirable quantum-confined Stark effect (QCSE), due to the existence of strong piezoelectric and spontaneous polarizations.
  • QCSE quantum-confined Stark effect
  • One approach to decreasing polarization effects in Ill-nitnde devices is to grow the devices along nonpolar or semipolar orientations of the crystal.
  • nonpolar includes the ⁇ 11-20 ⁇ planes, known collectively as a- planes, and the ⁇ 10-10 ⁇ planes, known collectively as m-planes. Such planes contain equal numbers of Group-Ill and Nitrogen atoms per plane and are charge-neutral. Subsequent nonpolar layers are equivalent to one another, so the bulk crystal will not be polarized along the growth direction.
  • semipolar can be used to refer to any plane that cannot be classified as c-plane, a-plane, or m-plane.
  • a semipolar plane would be any plane that has at least two nonzero h, i, or k Miller indices and a nonzero 1 Miller index. Subsequent semipolar layers are equivalent to one another, so the crystal will have reduced polarization along the growth direction.

Abstract

L'invention concerne un procédé de fabrication d'un dispositif à base de nitrure III à l'aide d'un modèle conforme aux contraintes (SCT) qui permet aux couches suivantes de se relâcher de sorte qu'elles ne sont pas contraintes de manière cohérente sur un substrat ou une couche de modèle, le SCT comprenant une couche de décomposition (DL) et une couche d'arrêt de décomposition (DSL) ; la DSL est développée de manière cohérente sur la DL ; la DL est décomposée thermiquement et détendue, ce qui amène la DSL à se détendre davantage ; le dispositif est développé sur ou au-dessus de la DSL après la décomposition thermique de la DL ; et une couche de type n du dispositif est relâchée en contrainte car elle est développée sur ou au-dessus de la DSL, ce qui permet à une région active de se détendre davantage. Le dispositif présente également une amélioration de la morphologie de surface.
PCT/US2022/042526 2021-09-03 2022-09-02 Dispositifs à base de nitrure iii développés sur ou au-dessus d'un modèle conforme aux contraintes WO2023034608A1 (fr)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023150550A3 (fr) * 2022-02-01 2023-10-05 The Regents Of The University Of California Dispositifs à haut rendement et haute puissance à base de nitrure iii développés sur ou au-dessus d'un modèle de relaxation de contrainte

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US20100289122A1 (en) * 2000-03-13 2010-11-18 Cree, Inc. Iii-v nitride substrate boule and method of making and using the same
US20170200707A1 (en) * 2009-05-12 2017-07-13 The Board Of Trustees Of The University Of Illinois Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays
US20190081211A1 (en) * 2016-07-19 2019-03-14 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip
WO2021148813A1 (fr) * 2020-01-22 2021-07-29 Poro Technologies Ltd Structure de semiconducteur et procédé de fabrication

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Publication number Priority date Publication date Assignee Title
US20100289122A1 (en) * 2000-03-13 2010-11-18 Cree, Inc. Iii-v nitride substrate boule and method of making and using the same
US20170200707A1 (en) * 2009-05-12 2017-07-13 The Board Of Trustees Of The University Of Illinois Printed Assemblies of Ultrathin, Microscale Inorganic Light Emitting Diodes for Deformable and Semitransparent Displays
US20190081211A1 (en) * 2016-07-19 2019-03-14 Osram Opto Semiconductors Gmbh Optoelectronic Semiconductor Chip
WO2021148813A1 (fr) * 2020-01-22 2021-07-29 Poro Technologies Ltd Structure de semiconducteur et procédé de fabrication

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2023150550A3 (fr) * 2022-02-01 2023-10-05 The Regents Of The University Of California Dispositifs à haut rendement et haute puissance à base de nitrure iii développés sur ou au-dessus d'un modèle de relaxation de contrainte

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