WO2023030784A1 - Method for producing an electronics arrangement, electronics arrangement and module - Google Patents

Method for producing an electronics arrangement, electronics arrangement and module Download PDF

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Publication number
WO2023030784A1
WO2023030784A1 PCT/EP2022/071339 EP2022071339W WO2023030784A1 WO 2023030784 A1 WO2023030784 A1 WO 2023030784A1 EP 2022071339 W EP2022071339 W EP 2022071339W WO 2023030784 A1 WO2023030784 A1 WO 2023030784A1
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WO
WIPO (PCT)
Prior art keywords
assembly
layer
spacer layer
spacer
assemblies
Prior art date
Application number
PCT/EP2022/071339
Other languages
German (de)
French (fr)
Inventor
Thomas Kiedrowski
Hartmut Wayand
Johannes MECKBACH
Lukas Loeber
Arne Stephen FISCHER
Original Assignee
Robert Bosch Gmbh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch Gmbh filed Critical Robert Bosch Gmbh
Publication of WO2023030784A1 publication Critical patent/WO2023030784A1/en

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F10/00—Additive manufacturing of workpieces or articles from metallic powder
    • B22F10/20—Direct sintering or melting
    • B22F10/28—Powder bed fusion, e.g. selective laser melting [SLM] or electron beam melting [EBM]
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B22—CASTING; POWDER METALLURGY
    • B22F—WORKING METALLIC POWDER; MANUFACTURE OF ARTICLES FROM METALLIC POWDER; MAKING METALLIC POWDER; APPARATUS OR DEVICES SPECIALLY ADAPTED FOR METALLIC POWDER
    • B22F7/00—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression
    • B22F7/06—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression of composite workpieces or articles from parts, e.g. to form tipped tools
    • B22F7/062—Manufacture of composite layers, workpieces, or articles, comprising metallic powder, by sintering the powder, with or without compacting wherein at least one part is obtained by sintering or compression of composite workpieces or articles from parts, e.g. to form tipped tools involving the connection or repairing of preformed parts
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y10/00—Processes of additive manufacturing
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y40/00—Auxiliary operations or equipment, e.g. for material handling
    • B33Y40/20—Post-treatment, e.g. curing, coating or polishing
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    • B33—ADDITIVE MANUFACTURING TECHNOLOGY
    • B33Y—ADDITIVE MANUFACTURING, i.e. MANUFACTURING OF THREE-DIMENSIONAL [3-D] OBJECTS BY ADDITIVE DEPOSITION, ADDITIVE AGGLOMERATION OR ADDITIVE LAYERING, e.g. BY 3-D PRINTING, STEREOLITHOGRAPHY OR SELECTIVE LASER SINTERING
    • B33Y80/00—Products made by additive manufacturing
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    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
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    • H05K3/36—Assembling printed circuits with other printed circuits
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    • H05K2201/09736—Varying thickness of a single conductor; Conductors in the same plane having different thicknesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1333—Deposition techniques, e.g. coating
    • H05K2203/1344—Spraying small metal particles or droplets of molten metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps

Definitions

  • the invention relates to a method for producing an electronic arrangement, in particular an electronic arrangement, in which a first assembly, for example a power assembly, is electrically contacted with a second assembly, for example a logic assembly, the connection between the two assemblies being made using at least one, in geometry produced by an additive manufacturing process in the form of a spacer layer. Furthermore, the invention relates to an electronic arrangement, which was preferably produced using a method according to the invention, and an assembly.
  • the applicant's DE 102006 033 175 A1 discloses a method for producing an electronic arrangement having the features of the preamble of claim 1 .
  • the known electronic arrangement is characterized by a first assembly in the form of a logic substrate, which is connected to a second assembly in the form of a power substrate by means of soldered connections.
  • the power substrate or the second module is electrically contacted with the upper side of the first module via bond connections.
  • the electronics arrangement described so far is covered by a casting compound that also fills the gaps between the two assemblies. It is also important that the two assemblies are arranged parallel to one another.
  • spacers Due to the arrangement of semiconductor components on the power substrate on the side facing the logic substrate, it is also necessary to add spacers, so-called spacers, for the parallel arrangement of the two assemblies use.
  • spacers typically designed as stamped parts made of electrically conductive material, can be used to advantage if there is a uniform, relatively large distance between the two assemblies or if soldered connections are provided for coupling that require a certain tolerance compensation due to stamping burrs on the spacers, for example or similar enable.
  • spacers typically also have to be provided with a surface finish, depending on the connection technique (soldering, sintering).
  • the spacers have a certain minimum area, which in turn has a negative effect on the required area and thus the costs of the semiconductor components.
  • the method according to the invention for producing an electronic assembly with the features of claim 1 has the advantage that it enables the electronic assembly to be designed in a manner that is particularly advantageous and cost-effective in terms of production technology, in which the two assemblies are arranged parallel to one another, with the distance between the two assemblies being highly precise and thus can also be set relatively low. Furthermore, the method according to the invention makes it possible to achieve particularly good electromechanical properties of the electronics arrangement by minimizing the coupling of mechanical stress into the assemblies by selecting a thermal expansion coefficient for the material of the spacer layers that is adapted to the overall system.
  • an additive manufacturing method is typically understood to mean a manufacturing method in which powdered metallic material is applied in the target area, whereupon the material is then selectively melted by the action of a laser beam in particular and then solidifies.
  • the powdery metallic material preferably consists of or contains copper and/or aluminum and/or a copper alloy and/or an aluminum alloy.
  • the metallic powder contains a composite comprising carbon.
  • the additive structure allows the materials mentioned to be mixed into a powder mixture in order to produce different alloys through the melting process.
  • the at least one spacer layer is applied exclusively to the second assembly (logic substrate). This is against the background that the second assembly (logic substrate) is typically flat on the side facing the first assembly.
  • Such a planar design of the second assembly on the side facing the first assembly has the advantage that the layers of powdered material can be applied particularly easily to the surface of the second assembly, for example using a doctor blade method. In particular, no components protruding beyond the surface of the electronics substrate can be damaged by the flat surface, since they are not present there.
  • a further preferred embodiment of the invention provides that the at least one spacer layer is treated by a surface treatment to form the soldered or sintered connection that takes place subsequently surface treated, in particular provided with a further layer.
  • a further layer or surface treatment can in particular involve the application of a silver layer or similar layers in the electroplating process that are advantageous for forming a soldered or sintered connection.
  • the additive manufacturing process of the at least one spacer layer makes it possible to set the thickness of the spacer layer with high precision. This also makes it possible, in particular, to allow the assemblies to be arranged in parallel despite a relatively small distance between the two assemblies.
  • a further variant of the method according to the invention provides that several areas with different heights of the spacer layers are formed, the different heights of which allow a parallel arrangement of the two assemblies (substrates) in the manufactured state of the electronic arrangement.
  • a soldering or sintering paste to be applied, in particular printed, in the area of the assembly that does not have any spacer layers in order to form the soldered or sintered connection.
  • the at least one spacer layer is preferably formed by applying a metallic powder and then melting the powder using an electron beam, in particular using a laser beam.
  • thermal stress on the electronics substrate (logic substrate) should be minimized as far as possible in order to avoid damage or pre-damage to structures or components of the electronics substrate.
  • a further variant of the method according to the invention therefore provides that the welding depth of an electron beam for melting the (construction) material of the at least one spacer layer is increased with a greater distance from the assembly or increasing layer thickness.
  • the reduction of the welding depth or its adjustment depending on the number or thickness of the spacer layers it is conceivable on the one hand to bring about such an adjustment by adjusting the process parameters (for example laser power, laser travel speed, etc.).
  • a further possibility is to influence the process by using so-called ultra-short pulse lasers for melting the powder material or the starting material for the at least one spacer layer. Due to the pulsed laser radiation, high absorbed intensities are possible with a comparatively low average power absorbed at the same time.
  • a very precise welding depth can be set using many weak laser pulses.
  • a further optimization can be achieved by working with finer powders or a narrower powder size distribution.
  • the layer thicknesses that can be achieved are typically in the range between 0.1 ⁇ m and 5 ⁇ m. As soon as a certain structural height or a certain number of spacer layers has been reached, which for example have a total height of 10 pm to 100 pm, the process can switch to the classic method, in which the typically deeper welding depths are achieved.
  • LTM process laser transfer metallization process
  • LIFT process laser induced forward transfer process
  • a further preferred method for the optimized, protected arrangement of the electronics arrangement provides for the electronics arrangement to be covered with a casting compound.
  • the potting compound typically consists of an (epoxy) resin, but gels or other media known per se for encapsulation can also be used.
  • the casting compound also penetrates into the space between the two assemblies, and it can also be provided that the casting compound also covers the side of the second assembly that is opposite the first assembly.
  • the invention also includes an assembly, in particular a logic substrate, and an electronic assembly, which is preferably produced using a method according to the invention that has been described so far, the electronic assembly having a first assembly in the form of a power substrate and a second assembly in the form of a logic substrate, wherein between the both assemblies for electrical contact between the two assemblies soldered or sintered connections are formed.
  • the electronic arrangement according to the invention is characterized in that the soldered or sintered connections are arranged in the area of at least one spacer layer formed in the additive manufacturing process.
  • the metallization layer on the assembly on which the at least one spacer layer is built up can also be advantageous for the metallization layer on the assembly on which the at least one spacer layer is built up to be more than 5 pm, preferably more than 10 pm, particularly preferably about 50 pm.
  • Fig. 1 bis 4 show, in simplified representations in each case, a method for producing an electronic arrangement during various process steps that follow one another in time.
  • the method described in more detail below is used to produce an electronics arrangement 100 shown in FIG.
  • the two assemblies 11 , 21 are connected to one another in three areas 12 to 14 , for example, on sides facing one another.
  • connection between the two assemblies 11, 21 is made, for example, by means of three soldered connections in the areas 12 to 14.
  • connections in the areas 12 to 14 can also be in the form of sintered connections.
  • bonding connections (not shown) can also be provided, which connect or contact the upper sides of the two substrates with one another.
  • Both the power substrate 10 and the logic substrate 20 are each formed in multiple layers in a manner known per se and are therefore not illustrated in any more detail. Furthermore, semiconductor components 15 are arranged on the side of the power substrate 10 facing the logic substrate 20, as should be illustrated in FIGS. 3 and 4 using a single semiconductor component 15. FIG.
  • connection between the side of the power substrate 10 facing the semiconductor component 15 and the semiconductor component 15 is made, for example, by means of a solder layer 16 during the manufacture of the first assembly 11. Furthermore, on the side of the semiconductor component 15 facing the logic assembly 20 and to the side there are solder layers 17 to 19 , preferably applied by printing, arranged. As can be seen particularly clearly from FIG. 3, the first assembly 11 or the power substrate 10 has a greater height in the area of the semiconductor component 15 and is therefore at a smaller distance from the logic assembly 20 than in the areas in which no semiconductor component 15 is provided .
  • spacer layers 22 to 24 produced in the additive manufacturing process are formed in the area of the second assembly 21 or the logic substrate 20 in the areas 12 to 14.
  • the spacer layer 24 assigned to the solder layer 19 has a greater height than the two spacer layers 22, 23 in the region of the semiconductor component 15, both of which have the same height or thickness.
  • the spacer layers 22 to 24 are typically produced, corresponding to the different height, by a different number of layers (each having the same layer thickness) from a metallic starting material in the form of a metal powder, which is deposited in the areas 12 to 14 on a metallization layer 25 of the logic substrate 20 is applied and then liquefied by selective melting by means of a high-energy beam in the form of a laser beam 26 shown only in FIG. 1 on the spacer layer 23 .
  • the (starting) material of the spacer layers 22 to 24 is preferably of the same type as the material of the metallization layer 25 in order to enable a material connection with the metallization layer 25 . After the (metallic) powder has liquefied, the powder then solidifies to form a layer of the spacer layer 22 to 24.
  • the penetration depth of the laser beam 26 or the welding depth is the smaller, the smaller the distance between the respective layer of the spacer layer 22 to 24 and the surface or the metallization layer 25 of the logic substrate 20 is.
  • the spacer layers 22 to 24 on the logic substrate 20 After the formation of the spacer layers 22 to 24 on the logic substrate 20, this is optionally covered with a further layer at least in the area of the spacer layers 22 to 24 on the top side and the side surfaces and partially overlapping the side of the logic substrate 20 facing it 27 for surface finishing of the spacer layers 22 to 24 provided.
  • the further layer 27 is applied (galvanically) in a manner known per se, in particular in the form of a silver coating, and is used to improve the connection of the spacer layers 22 to 24 to the solder layers 17 to 19 of the power substrate 10.
  • the logic substrate 20 with the spacer layers 22 to 24 and the further layer 27 is thus formed by way of example.
  • the two assemblies 11 , 21 are joined, with the solder layers 17 to 19 being arranged so that they overlap or are aligned with the spacer layers 22 to 24 .
  • the solder layers 17 to 19 are brought into contact with the spacer layers 22 to 24, with the solder of the solder layers 17 to 19 being liquefied by a corresponding heat treatment and becoming electrically conductive with the spacer layers 22 to 24 or the further layer 27 connects.

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  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
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Abstract

The invention relates to a method for producing an electronics arrangement (100) according to which a first module (11), in particular in the form of a power substrate (10), is electrically connected to a second module (21), in particular in the form of a logical substrate (20), by means of a soldered connection (17 to 19) or a sintered connection.

Description

Beschreibung Description
Verfahren zur Herstellung einer Elektronikanordnung, Elektronikanordnung und Baugruppe Method for producing an electronic arrangement, electronic arrangement and assembly
Technisches Gebiet technical field
Die Erfindung betrifft ein Verfahren zur Herstellung einer Elektronikanordnung, insbesondere einer Elektronikanordnung, bei der eine erste Baugruppe, beispielsweise eine Leistungsbaugruppe, mit einer zweiten Baugruppe, beispielsweise einer Logikbaugruppe, elektrisch kontaktiert werden, wobei die Verbindung zwischen den beiden Baugruppen unter Verwendung wenigstens einer, in einem additiven Fertigungsverfahren hergestellten Geometrie in Form einer Abstandsschicht erfolgt. Ferner betrifft die Erfindung eine Elektronikanordnung, die vorzugsweise nach einem erfindungsgemäßen Verfahren hergestellt wurde, und eine Baugruppe. The invention relates to a method for producing an electronic arrangement, in particular an electronic arrangement, in which a first assembly, for example a power assembly, is electrically contacted with a second assembly, for example a logic assembly, the connection between the two assemblies being made using at least one, in geometry produced by an additive manufacturing process in the form of a spacer layer. Furthermore, the invention relates to an electronic arrangement, which was preferably produced using a method according to the invention, and an assembly.
Stand der Technik State of the art
Aus der DE 102006 033 175 A1 der Anmelderin ist ein Verfahren zur Herstellung einer Elektronikanordnung mit den Merkmalen des Oberbegriffs des Anspruchs 1 bekannt. Die bekannte Elektronikanordnung zeichnet sich durch eine erste Baugruppe in Form eines als Logiksubstrats auf, die mit einer zweiten Baugruppe in Form eines Leistungssubstarts mittels Lötverbindungen verbunden wird. Darüber hinaus erfolgt eine elektrische Kontaktierung des Leistungssubstarts bzw. der zweiten Baugruppe mit der Oberseite der ersten Baugruppe über Bondverbindungen. Die soweit beschriebene Elektronikanordnung ist von einer Vergussmasse überdeckt, die auch die Zwischenräume zwischen den beiden Baugruppen ausfüllt. Wesentlich ist auch, dass die beiden Baugruppen parallel zueinander angeordnet sind. Aufgrund der Anordnung von Halbleiterbauelementen auf dem Leistungssubstrat auf der dem Logiksubstrat zugewandten Seite ist es darüber hinaus erforderlich, zur parallelen Anordnung der beiden Baugruppen Abstandshalteelemente, sogenannte Spacer, zu verwenden. Diese, typischerweise als Stanzteile aus elektrisch leitendem Material ausgebildeten Abstandshalter sind dann vorteilhaft einsetzbar, wenn ein gleichmäßiger, möglichst relativ großer Abstand zwischen den beiden Baugruppen vorhanden ist bzw. wenn Lötverbindungen zur Ankopplung vorgesehen sind, die einen gewissen Toleranzausgleich aufgrund beispielsweise von Stanzgrate an den Spacern o.ä. ermöglichen. Darüber hinaus müssen derartige Spacer zur Gewährleistung einer optimalen Verbindung je nach Verbindungstechnik (Löten, Sintern) typischerweise zusätzlich auch mit einer Oberflächenveredelung versehen werden. Weiterhin weisen die Spacer aus herstellungstechnischen Gründen und aufgrund geometrischer Aspektverhältnisse eine bestimmte Mindestfläche auf, die wiederum die benötigte Fläche und dadurch die Kosten der Halbleiterbauelemente negativ beeinflussen. The applicant's DE 102006 033 175 A1 discloses a method for producing an electronic arrangement having the features of the preamble of claim 1 . The known electronic arrangement is characterized by a first assembly in the form of a logic substrate, which is connected to a second assembly in the form of a power substrate by means of soldered connections. In addition, the power substrate or the second module is electrically contacted with the upper side of the first module via bond connections. The electronics arrangement described so far is covered by a casting compound that also fills the gaps between the two assemblies. It is also important that the two assemblies are arranged parallel to one another. Due to the arrangement of semiconductor components on the power substrate on the side facing the logic substrate, it is also necessary to add spacers, so-called spacers, for the parallel arrangement of the two assemblies use. These spacers, typically designed as stamped parts made of electrically conductive material, can be used to advantage if there is a uniform, relatively large distance between the two assemblies or if soldered connections are provided for coupling that require a certain tolerance compensation due to stamping burrs on the spacers, for example or similar enable. In addition, to ensure an optimal connection, such spacers typically also have to be provided with a surface finish, depending on the connection technique (soldering, sintering). Furthermore, for manufacturing reasons and because of geometric aspect ratios, the spacers have a certain minimum area, which in turn has a negative effect on the required area and thus the costs of the semiconductor components.
Offenbarung der Erfindung Disclosure of Invention
Das erfindungsgemäße Verfahren zur Herstellung einer Elektronikanordnung mit den Merkmalen des Anspruchs 1 hat den Vorteil, dass es eine herstellungstechnisch besonders vorteilhafte und kostengünstige Ausbildung der Elektronikanordnung ermöglicht, bei dem die beiden Baugruppen parallel zueinander angeordnet sind, wobei der Abstand zwischen den beiden Baugruppen hochgenau und somit auch relativ gering eingestellt werden kann. Weiterhin ermöglicht es das erfindungsgemäße Verfahren, besonders gute elektromechanische Eigenschaften der Elektronikanordnung zu erzielen, indem durch die Wahl eines an das Gesamtsystem angepassten thermischen Ausdehnungskoeffizienten für das Material der Abstandsschichten die Einkopplung von mechanischem Stress in die Baugruppen minimiert wird. The method according to the invention for producing an electronic assembly with the features of claim 1 has the advantage that it enables the electronic assembly to be designed in a manner that is particularly advantageous and cost-effective in terms of production technology, in which the two assemblies are arranged parallel to one another, with the distance between the two assemblies being highly precise and thus can also be set relatively low. Furthermore, the method according to the invention makes it possible to achieve particularly good electromechanical properties of the electronics arrangement by minimizing the coupling of mechanical stress into the assemblies by selecting a thermal expansion coefficient for the material of the spacer layers that is adapted to the overall system.
Die oben genannten Vorteile werden bei einem erfindungsgemäßen Verfahren zur Herstellung einer Elektronikanordnung mit den Merkmalen des Anspruchs 1 dadurch erzielt, dass im Bereich der Löt- oder Sinterverbindung zwischen den beiden Baugruppen auf der ersten oder der zweiten Baugruppe in einem additiven Fertigungsverfahren zur Einstellung des Abstands zwischen den beiden Baugruppen wenigstens eine Abstandsschicht aufgebracht wird. Mit anderen Worten gesagt bedeutet dies, dass anstelle vorgefertigter bzw. starrer metallischer Abstandshalterelemente (Spacer) der Abstand zwischen den beiden Baugruppen im Bereich der Löt- oder Sinterverbindung(en) dadurch hochgenau erzeugt werden kann, dass im additiven Fertigungsverfahren wenigstens eine Abstandsschicht mit einer definierten Schichtdicke erzeugt wird. Unter einem additiven Fertigungsverfahren wird im Rahmen der Erfindung typischerweise ein Fertigungsverfahren verstanden, bei dem pulverförmiges, metallisches Material im Zielgebiet aufgebracht wird, worauf das Material anschließend durch Einwirkung insbesondere eines Laserstrahls selektiv aufgeschmolzen wird und anschließend erstarrt. Grundsätzlich sind jedoch auch andere, aus dem Stand der Technik bekannte additive Fertigungsverfahren möglich. Vorzugsweise besteht das pulverförmige metallische Material (metallisches Pulver) aus oder enthält Kupfer und/oder Aluminium und/oder eine Kupferlegierung und/oder eine Aluminiumlegierung. Alternativ oder zusätzlich enthält das metallische Pulver ein Komposit umfassend Kohlenstoff. In besonders vorteilhafter Weise ermöglicht der additive Aufbau ein Mischen der genannten Materialen zu einem Pulvergemisch, um so unterschiedliche Legierungen durch den Schmelzvorgang zu erzeugen. The advantages mentioned above are achieved in a method according to the invention for producing an electronic assembly with the features of claim 1 in that in the area of the soldered or sintered connection between the two assemblies on the first or the second assembly in an additive manufacturing process to adjust the distance between at least one spacer layer is applied to the two assemblies. In other words, this means that instead of prefabricated or rigid metallic spacer elements (spacers), the distance between the two assemblies in the area of the soldered or sintered connection(s) can be produced with high precision by using at least one spacer layer with a defined Layer thickness is generated. In the context of the invention, an additive manufacturing method is typically understood to mean a manufacturing method in which powdered metallic material is applied in the target area, whereupon the material is then selectively melted by the action of a laser beam in particular and then solidifies. In principle, however, other additive manufacturing processes known from the prior art are also possible. The powdery metallic material (metallic powder) preferably consists of or contains copper and/or aluminum and/or a copper alloy and/or an aluminum alloy. Alternatively or additionally, the metallic powder contains a composite comprising carbon. In a particularly advantageous manner, the additive structure allows the materials mentioned to be mixed into a powder mixture in order to produce different alloys through the melting process.
Vorteilhafte Weiterbildungen des erfindungsgemäßen Verfahrens zur Herstellung einer Elektronikanordnung sind in den Unteransprüchen aufgeführt. Advantageous developments of the method according to the invention for producing an electronic arrangement are listed in the dependent claims.
Bevorzugt ist es, wenn die wenigstens eine Abstandsschicht ausschließlich auf der zweiten Baugruppe (Logiksubstrat) aufgebracht wird. Dies vor dem Hintergrund, dass die zweite Baugruppe (Logiksubstrat) auf der der ersten Baugruppe zugewandten Seite typischerweise eben ausgebildet ist. Eine derartige, ebene Ausbildung der zweiten Baugruppe auf der der ersten Baugruppe zugewandten Seite hat den Vorteil, dass das Aufträgen der Schichten von pulverförmigem Material auf die Oberfläche der zweiten Baugruppe besonders einfach erfolgen kann, beispielsweise in einem Rakelverfahren. Insbesondere können dabei durch die ebene Oberfläche keine die Oberfläche des Elektroniksubstrats überragende Bauteile beschädigt werden, da diese dort nicht vorhanden sind. It is preferred if the at least one spacer layer is applied exclusively to the second assembly (logic substrate). This is against the background that the second assembly (logic substrate) is typically flat on the side facing the first assembly. Such a planar design of the second assembly on the side facing the first assembly has the advantage that the layers of powdered material can be applied particularly easily to the surface of the second assembly, for example using a doctor blade method. In particular, no components protruding beyond the surface of the electronics substrate can be damaged by the flat surface, since they are not present there.
Eine weitere, bevorzugte Ausgestaltung der Erfindung sieht vor, dass die wenigstens eine Abstandsschicht durch eine Oberflächenbehandlung zur Ausbildung der anschließend stattfindenden Löt- oder Sinterverbindung oberflächenbehandelt, insbesondere mit einer weiteren Schicht versehen wird. Bei einer derartigen weiteren Schicht bzw. Oberflächenbehandlung kann es sich insbesondere um das Aufbringen einer Silberschicht oder ähnlichen, zur Ausbildung einer Löt- oder Sinterverbindung vorteilhaften Schichten im Galvanikverfahren handeln. A further preferred embodiment of the invention provides that the at least one spacer layer is treated by a surface treatment to form the soldered or sintered connection that takes place subsequently surface treated, in particular provided with a further layer. Such a further layer or surface treatment can in particular involve the application of a silver layer or similar layers in the electroplating process that are advantageous for forming a soldered or sintered connection.
Wie bereits oben erläutert, ermöglicht es das additive Fertigungsverfahren der wenigstens einen Abstandsschicht, die Dicke der Abstandsschicht hochgenau einstellen zu können. Dies ermöglicht es insbesondere auch, trotz einem relativ geringen Abstand zwischen den beiden Baugruppen eine parallele Anordnung der Baugruppen zu ermöglichen. Vor diesem Hintergrund sieht es eine weitere Variante des erfindungsgemäßen Verfahrens vor, dass mehrere Bereiche mit einer unterschiedlichen Höhe der Abstandsschichten ausgebildet werden, deren unterschiedliche Höhen im gefertigten Zustand der Elektronikanordnung eine parallele Anordnung der beiden Baugruppen (Substrate) ermöglicht. As already explained above, the additive manufacturing process of the at least one spacer layer makes it possible to set the thickness of the spacer layer with high precision. This also makes it possible, in particular, to allow the assemblies to be arranged in parallel despite a relatively small distance between the two assemblies. Against this background, a further variant of the method according to the invention provides that several areas with different heights of the spacer layers are formed, the different heights of which allow a parallel arrangement of the two assemblies (substrates) in the manufactured state of the electronic arrangement.
Bei einem weiteren bevorzugten Verfahren zur Herstellung der Elektronikanordnung ist es vorgesehen, dass im Bereich der Baugruppe, die keine Abstandsschichten aufweist, zur Ausbildung der Löt- oder Sinterverbindung eine Löt- oder Sinterpaste aufgebracht, insbesondere aufgedruckt wird. In a further preferred method for producing the electronic arrangement, provision is made for a soldering or sintering paste to be applied, in particular printed, in the area of the assembly that does not have any spacer layers in order to form the soldered or sintered connection.
Wie bereits oben erläutert, erfolgt das Ausbilden der wenigstens einen Abstandsschicht vorzugsweise durch Aufbringen eines metallischen Pulvers und anschließendes Aufschmelzen des Pulvers durch einen Elektronenstrahl, insbesondere durch einen Laserstrahl. Mit Blick auf die Anordnung der wenigstens einen Abstandsschicht im Bereich des Elektroniksubstrats ist dabei eine thermische Belastung des Elektroniksubstrats (Logiksubstrat) möglichst zu minimieren, um eine Beschädigung oder Vorschädigung von Strukturen bzw. Bauelementen des Elektroniksubstrats zu vermeiden. Eine weitere Variante des erfindungsgemäßen Verfahrens sieht es daher vor, dass die Einschweißtiefe eines Elektronenstrahls zum Aufschmelzen des (Aufbau-) Materials der wenigstens einen Abstandsschicht mit größerem Abstand zur Baugruppe bzw. zunehmender Schichtdicke vergrößert wird. Mit anderen Worten gesagt bedeutet dies, dass insbesondere bei den ersten Abstandsschichten die Einschweißtiefe bzw. Eindringtiefe des Elektronenstrahls derart reduziert wird, dass eine thermische Überlastung der Oberfläche bzw. des Elektroniksubstrats verhindert wird. Bezüglich der Reduzierung der Einschweißtiefe bzw. deren Anpassung in Abhängigkeit von der Anzahl bzw. Dicke der Abstandsschichten ist es zum einen denkbar, durch Anpassung der Prozessparameter (beispielsweise Laserleistung, Laserverfahrgeschwindigkeit usw.) eine derartige Anpassung zu bewirken. Eine weitere Möglichkeit besteht darin, den Prozess durch Verwendung sogenannter Ultrakurzpuls-Laser für das Aufschmelzen des Pulverwerkstoffs bzw. des Ausgangswerkstoffs für die wenigstens eine Abstandsschicht zu beeinflussen. Durch die gepulste Laserstrahlung sind hohe absorbierte Intensitäten bei gleichzeitig vergleichsweise geringer absorbierter mittlerer Leistung möglich. Insbesondere lässt sich durch viele schwache Laserpulse eine sehr präzise Einschweißtiefe einstellen. Eine weitere Optimierung kann dabei dadurch erfolgen, dass mit feineren Pulvern bzw. einer engeren Pulvergrößenverteilung gearbeitet wird. Die dabei erreichbaren Schichtdicken liegen typischerweise im Bereich zwischen 0,1 pm und 5pm. Sobald eine gewisse Aufbauhöhe bzw. eine gewisse Anzahl von Abstandsschichten erreicht ist, die beispielsweise eine Gesamthöhe von 10pm bis 100pm aufweisen, kann der Prozess auf das klassische Verfahren wechseln, bei dem die typischerweise tieferen Einschweißtiefen erzielt werden. As already explained above, the at least one spacer layer is preferably formed by applying a metallic powder and then melting the powder using an electron beam, in particular using a laser beam. With regard to the arrangement of the at least one spacer layer in the area of the electronics substrate, thermal stress on the electronics substrate (logic substrate) should be minimized as far as possible in order to avoid damage or pre-damage to structures or components of the electronics substrate. A further variant of the method according to the invention therefore provides that the welding depth of an electron beam for melting the (construction) material of the at least one spacer layer is increased with a greater distance from the assembly or increasing layer thickness. In other words, this means that, particularly in the case of the first spacer layers, the welding depth or penetration depth of the electron beam is reduced in such a way that thermal overloading of the surface or the electronic substrate is prevented. Regarding the reduction of the welding depth or its adjustment depending on the number or thickness of the spacer layers, it is conceivable on the one hand to bring about such an adjustment by adjusting the process parameters (for example laser power, laser travel speed, etc.). A further possibility is to influence the process by using so-called ultra-short pulse lasers for melting the powder material or the starting material for the at least one spacer layer. Due to the pulsed laser radiation, high absorbed intensities are possible with a comparatively low average power absorbed at the same time. In particular, a very precise welding depth can be set using many weak laser pulses. A further optimization can be achieved by working with finer powders or a narrower powder size distribution. The layer thicknesses that can be achieved are typically in the range between 0.1 μm and 5 μm. As soon as a certain structural height or a certain number of spacer layers has been reached, which for example have a total height of 10 pm to 100 pm, the process can switch to the classic method, in which the typically deeper welding depths are achieved.
Eine weitere denkbare Anpassung des Aufbauprozesses wäre die Verwendung des sogenannten LTM-Verfahrens (Laser-Transfer-Metallisierung-Verfahren), welches eine Weiterentwicklung des LIFT-Verfahrens (Laser-Induced-Forward- Transfer- Verfahrens) ist. Das LTM-Verfahren, welches eigentlich für die Herstellung von Leiterplatten benutzt wird, erfüllt ebenfalls die wesentlichen Anforderungen an den Prozess für die ersten Abstandsschichten. Another conceivable adaptation of the build-up process would be to use the so-called LTM process (laser transfer metallization process), which is a further development of the LIFT process (laser induced forward transfer process). The LTM process, which is actually used for the production of printed circuit boards, also fulfills the essential requirements of the process for the first spacer layers.
Auch ist es denkbar, zur Verbesserung der Robustheit bzw. Verbesserung der Wärmeabfuhr die Metallisierungsschicht an dem Substrat, auf der die wenigstens eine Abstandsschicht aufgebaut wird, in ihrer Schichtdicke zu vergrößern, die beim Stand der Technik typischerweise weniger als 10pm beträgt. It is also conceivable to increase the thickness of the metallization layer on the substrate, on which the at least one spacer layer is built up, which is typically less than 10 μm in the prior art, in order to improve the robustness or improve the heat dissipation.
Ein weiteres bevorzugtes Verfahren zur optimierten geschützten Anordnung der Elektronikanordnung sieht vor, dass die Elektronikanordnung mit einer Vergussmasse überdeckt wird. Die Vergussmasse besteht typischerweise aus einem (Epoxid-) Harz, es können jedoch auch Gele oder sonstige, zur Einkapselung an sich bekannte Medien verwendet werden. Wie bereits erläutert dringt die Vergussmasse auch in den Zwischenraum zwischen den beiden Baugruppen ein, wobei es darüber hinaus vorgesehen sein kann, dass die Vergussmasse auch die der ersten Baugruppe gegenüberliegende Seite der zweiten Baugruppe überdeckt. A further preferred method for the optimized, protected arrangement of the electronics arrangement provides for the electronics arrangement to be covered with a casting compound. The potting compound typically consists of an (epoxy) resin, but gels or other media known per se for encapsulation can also be used. As already explained If necessary, the casting compound also penetrates into the space between the two assemblies, and it can also be provided that the casting compound also covers the side of the second assembly that is opposite the first assembly.
Weiterhin umfasst die Erfindung auch eine Baugruppe, insbesondere ein Logiksubstrat, und eine Elektronikanordnung, die vorzugsweise nach einem soweit beschriebenen erfindungsgemäßen Verfahren hergestellt ist, wobei die Elektronikanordnung eine erste Baugruppe in Form eines Leistungssubstrats und eine zweite Baugruppe in Form eines Logiksubstrats aufweist, wobei zwischen den beiden Baugruppen zur elektrischen Kontaktierung zwischen den beiden Baugruppen Löt- oder Sinterverbindungen ausgebildet sind. Die erfindungsgemäße Elektronikanordnung zeichnet sich dadurch aus, dass die Lötoder Sinterverbindungen im Bereich wenigstens einer, im additiven Fertigungsverfahren ausgebildeten Abstandsschicht angeordnet sind. Furthermore, the invention also includes an assembly, in particular a logic substrate, and an electronic assembly, which is preferably produced using a method according to the invention that has been described so far, the electronic assembly having a first assembly in the form of a power substrate and a second assembly in the form of a logic substrate, wherein between the both assemblies for electrical contact between the two assemblies soldered or sintered connections are formed. The electronic arrangement according to the invention is characterized in that the soldered or sintered connections are arranged in the area of at least one spacer layer formed in the additive manufacturing process.
Eine Weiterbildung der soweit beschriebenen Elektronikanordnung sieht vor, dass mehrere Bereiche mit unterschiedlichen Höhen der aufgebrachten Abstandsschichten vorhanden sind. A development of the electronic arrangement described so far provides that there are several areas with different heights of the spacer layers applied.
Zur Optimierung des Aufbauprozesses bzw. zur Verringerung der thermischen Belastung beim Aufbau der unteren bzw. ersten Abstandsschichten kann es darüber hinaus von Vorteil sein, dass die Metallisierungsschicht an der Baugruppe, an der die wenigstens eine Abstandsschicht aufgebaut wird, mehr als 5pm, vorzugsweise mehr als 10pm, besonders bevorzugt etwa 50pm beträgt. In order to optimize the build-up process or to reduce the thermal load when building up the lower or first spacer layers, it can also be advantageous for the metallization layer on the assembly on which the at least one spacer layer is built up to be more than 5 pm, preferably more than 10 pm, particularly preferably about 50 pm.
Weitere Vorteile, Merkmale und Einzelheiten der Erfindung ergeben sich aus der nachfolgenden Beschreibung bevorzugter Ausführungsformen der Erfindung sowie anhand der Zeichnungen. Further advantages, features and details of the invention result from the following description of preferred embodiments of the invention and from the drawings.
Kurze Beschreibung der Zeichnungen Brief description of the drawings
Fig. 1 bis Fig. 4 zeigen in jeweils vereinfachten Darstellungen ein Verfahren zur Herstellung einer Elektronikanordnung während verschiedener, zeitlich aufeinanderfolgender Prozessschritte. Fig. 1 bis 4 show, in simplified representations in each case, a method for producing an electronic arrangement during various process steps that follow one another in time.
Ausführungsformen der Erfindung Embodiments of the invention
Gleiche Elemente bzw. Elemente mit gleicher Funktion sind in den Figuren mit den gleichen Bezugsziffern versehen. Identical elements or elements with the same function are provided with the same reference numbers in the figures.
Das nachfolgend noch näher beschriebene Verfahren dient zur Herstellung einer in der Fig. 4 dargestellten Elektronikanordnung 100, die aus einer ersten Baugruppe 11 in Form eines Leistungssubstrats 10 und einer mit der ersten Baugruppe 11 verbundenen zweiten Baugruppe 21 in Form eines Logiksubstrats 20 besteht. Die beiden Baugruppen 11 , 21 sind beispielhaft auf einander zugewandten Seiten an drei Bereichen 12 bis 14 miteinander verbunden. The method described in more detail below is used to produce an electronics arrangement 100 shown in FIG. The two assemblies 11 , 21 are connected to one another in three areas 12 to 14 , for example, on sides facing one another.
Die Verbindung zwischen den beiden Baugruppen 11 , 21 erfolgt beispielhaft mittels dreier Lötverbindungen in den Bereichen 12 bis 14. The connection between the two assemblies 11, 21 is made, for example, by means of three soldered connections in the areas 12 to 14.
Ergänzend wird erwähnt, dass die Verbindungen in den Bereichen 12 bis 14 auch in Form von Sinterverbindungen ausgebildet sein können. Darüber hinaus können auch (nicht dargestellte) Bondverbindungen vorgesehen sein, die die Oberseiten der beiden Substrate miteinander verbinden bzw. kontaktieren. In addition, it is mentioned that the connections in the areas 12 to 14 can also be in the form of sintered connections. In addition, bonding connections (not shown) can also be provided, which connect or contact the upper sides of the two substrates with one another.
Sowohl das Leistungssubstrat 10 als auch das Logiksubstrat 20 sind jeweils, in an sich bekannter Art und Weise und daher nicht näher dargestellt, mehrlagig ausgebildet. Weiterhin sind auf der dem Logiksubstrat 20 zugewandten Seite des Leistungssubstrats 10 Halbleiterbauelemente 15 angeordnet, wie es in den Fig. 3 und 4 anhand eines einzigen Halbleiterbauelements 15 verdeutlicht sein soll. Both the power substrate 10 and the logic substrate 20 are each formed in multiple layers in a manner known per se and are therefore not illustrated in any more detail. Furthermore, semiconductor components 15 are arranged on the side of the power substrate 10 facing the logic substrate 20, as should be illustrated in FIGS. 3 and 4 using a single semiconductor component 15. FIG.
Die Verbindung zwischen der dem Halbleiterbauelement 15 zugewandten Seite des Leistungssubstrats 10 und dem Halbleiterbauelement 15 erfolgt beispielhaft mittels einer Lotschicht 16 bei der Fertigung der ersten Baugruppe 11. Weiterhin sind auf der der Logikbaugruppe 20 zugewandten Seite des Halbleiterbauelements 15 sowie seitlich daneben Lotschichten 17, bis 19, vorzugsweise im Druckverfahren aufgebracht, angeordnet. Wie besonders deutlich anhand der Fig. 3 erkennbar ist, weist die erste Baugruppe 11 bzw. das Leistungssubstrat 10 im Bereich des Halbleiterbauelements 15 eine größere Höhe und somit einen geringeren Abstand zur Logikbaugruppe 20 auf als in den Bereichen, in denen kein Halbleiterbauelement 15 vorgesehen ist. The connection between the side of the power substrate 10 facing the semiconductor component 15 and the semiconductor component 15 is made, for example, by means of a solder layer 16 during the manufacture of the first assembly 11. Furthermore, on the side of the semiconductor component 15 facing the logic assembly 20 and to the side there are solder layers 17 to 19 , preferably applied by printing, arranged. As can be seen particularly clearly from FIG. 3, the first assembly 11 or the power substrate 10 has a greater height in the area of the semiconductor component 15 and is therefore at a smaller distance from the logic assembly 20 than in the areas in which no semiconductor component 15 is provided .
Um eine parallele Anordnung zwischen den beiden Baugruppen 11 , 21 zu ermöglichen, sind im Bereich der zweiten Baugruppe 21 bzw. des Logiksubstrats 20 in den Bereichen 12 bis 14 im additiven Fertigungsverfahren erzeugte Abstandsschichten 22 bis 24 ausgebildet. Dabei weist die der Lotschicht 19 zugeordnete Abstandsschicht 24 eine größere Höhe auf als die beiden Abstandsschichten 22, 23 im Bereich des Halbleiterbauelements 15, die beide die gleiche Höhe bzw. Dicke aufweisen. In order to enable a parallel arrangement between the two assemblies 11, 21, spacer layers 22 to 24 produced in the additive manufacturing process are formed in the area of the second assembly 21 or the logic substrate 20 in the areas 12 to 14. In this case, the spacer layer 24 assigned to the solder layer 19 has a greater height than the two spacer layers 22, 23 in the region of the semiconductor component 15, both of which have the same height or thickness.
Die Abstandsschichten 22 bis 24 werden typischerweise, entsprechend der unterschiedlichen Höhe, durch eine unterschiedliche Anzahl von (jeweils eine gleiche Schichtdicke aufweisenden) Lagen aus einem metallischen Ausgangsmaterial mit Form eines Metallpulvers erzeugt, das in den Bereichen 12 bis 14 auf einer Metallisierungsschicht 25 des Logiksubstrats 20 aufgebracht und anschließend durch selektives Aufschmelzen mittels eines lediglich in der Fig. 1 an der Abstandsschicht 23 dargestellten energiereichen Strahls in Form eines Laserstrahls 26 verflüssigt wird. Das (Ausgangs-) Material der Abstandsschichten 22 bis 24 ist vorzugsweise artgleich mit dem Material der Metallisierungsschicht 25, um eine stoffschlüssige Verbindung mit der Metallisierungsschicht 25 zu ermöglichen. Nach dem Verflüssigen des (metallischen) Pulvers erstarrt das Pulver anschließend unter Ausbildung einer Lage der Abstandsschicht 22 bis 24. The spacer layers 22 to 24 are typically produced, corresponding to the different height, by a different number of layers (each having the same layer thickness) from a metallic starting material in the form of a metal powder, which is deposited in the areas 12 to 14 on a metallization layer 25 of the logic substrate 20 is applied and then liquefied by selective melting by means of a high-energy beam in the form of a laser beam 26 shown only in FIG. 1 on the spacer layer 23 . The (starting) material of the spacer layers 22 to 24 is preferably of the same type as the material of the metallization layer 25 in order to enable a material connection with the metallization layer 25 . After the (metallic) powder has liquefied, the powder then solidifies to form a layer of the spacer layer 22 to 24.
Bevorzugt ist es vorgesehen, dass zur Verringerung der thermischen Belastung des Logiksubstarts 20 die Eindringtiefe des Laserstrahls 26 bzw. die Einschweißtiefe umso geringer ist, je geringer der Abstand der jeweiligen Lage der Abstandsschicht 22 bis 24 von der Oberfläche bzw. der Metallisierungsschicht 25 des Logiksubstrats 20 ist. In order to reduce the thermal load on the logic substrate 20, it is preferably provided that the penetration depth of the laser beam 26 or the welding depth is the smaller, the smaller the distance between the respective layer of the spacer layer 22 to 24 and the surface or the metallization layer 25 of the logic substrate 20 is.
Nach dem Ausbilden der Abstandsschichten 22 bis 24 auf dem Logiksubstrat 20 wird dieses zumindest noch im Bereich der Abstandsschichten 22 bis 24 an deren Oberseite sowie den Seitenflächen und teilweise in Überdeckung mit der ihr zugewandten Seite des Logiksubstrats 20 optional mit einer weiteren Schicht 27 zur Oberflächenveredelung der Abstandsschichten 22 bis 24 versehen. Die weitere Schicht 27 wird insbesondere in Form einer Silberbeschichtung auf an sich bekannte Art und Weise (galvanisch) aufgebracht und dient der besseren Anbindung der Abstandsschichten 22 bis 24 an die Lotschichten 17 bis 19 des Leistungssubstrats 10. After the formation of the spacer layers 22 to 24 on the logic substrate 20, this is optionally covered with a further layer at least in the area of the spacer layers 22 to 24 on the top side and the side surfaces and partially overlapping the side of the logic substrate 20 facing it 27 for surface finishing of the spacer layers 22 to 24 provided. The further layer 27 is applied (galvanically) in a manner known per se, in particular in the form of a silver coating, and is used to improve the connection of the spacer layers 22 to 24 to the solder layers 17 to 19 of the power substrate 10.
Entsprechend der obigen Erläuterungen und der Fig. 1 und 2 wird somit beispielhaft das Logiksubstrat 20 mit den Abstandsschichten 22 bis 24 und der weiteren Schicht 27 ausgebildet. Anschließend erfolgt entsprechend der Fig. 3 ein Fügen zwischen den beiden Baugruppen 11 , 21 , wobei die Lotschichten 17 bis 19 in Überdeckung bzw. Ausrichtung mit den Abstandsschichten 22 bis 24 angeordnet werden. Anschließend erfolgt entsprechend der Fig. 4 ein Inkontaktbringen der Lotschichten 17 bis 19 mit den Abstandsschichten 22 bis 24, wobei durch eine entsprechende Wärmebehandlung das Lot der Lotschichten 17 bis 19 verflüssigt wird und sich elektrisch leitend mit den Abstandsschichten 22 bis 24 bzw. der weiteren Schicht 27 verbindet. In accordance with the above explanations and FIGS. 1 and 2, the logic substrate 20 with the spacer layers 22 to 24 and the further layer 27 is thus formed by way of example. Subsequently, as shown in FIG. 3 , the two assemblies 11 , 21 are joined, with the solder layers 17 to 19 being arranged so that they overlap or are aligned with the spacer layers 22 to 24 . Subsequently, according to FIG. 4, the solder layers 17 to 19 are brought into contact with the spacer layers 22 to 24, with the solder of the solder layers 17 to 19 being liquefied by a corresponding heat treatment and becoming electrically conductive with the spacer layers 22 to 24 or the further layer 27 connects.
Anschließend kann es vorgesehen sein, dass die so ausgebildete Elektronikanordnung 100 mittels einer Moldmasse 30 überdeckt wird, zumindest im Bereich des Logiksubstrats 20, wobei die Moldmasse 30 auch die Zwischenräume zwischen den beiden Substraten ausfüllt. Dies ist bereichsweise in der Fig. 4 dargestellt. Provision can then be made for the electronic arrangement 100 formed in this way to be covered by a molding compound 30, at least in the area of the logic substrate 20, with the molding compound 30 also filling the gaps between the two substrates. This is partially shown in FIG.
Das soweit beschriebene Verfahren kann in vielfältiger Art und Weise abgewandelt bzw. modifiziert werden, ohne vom Erfindungsgedanken abzuweichen. The method described so far can be altered or modified in many ways without deviating from the spirit of the invention.

Claims

Ansprüche Expectations
1. Verfahren zur Herstellung einer Elektronikanordnung (100), bei dem eine erste Baugruppe (11), insbesondere in Form eines Leistungssubstrats (10), mit einer zweiten Baugruppe (21), insbesondere in Form eines Logiksubstrats (20), mittels wenigstens einer Lötverbindung (17 bis 19) oder einer Sinterverbindung elektrisch verbunden wird, dadurch gekennzeichnet, dass im Bereich der Lötverbindung (17 bis 19) oder der Sinterverbindung auf der ersten und/oder der zweiten Baugruppe (11 , 21) in einem additiven Fertigungsverfahren wenigstens eine Abstandsschicht (22 bis 24) aufgebracht wird. 1. A method for producing an electronic arrangement (100), in which a first assembly (11), in particular in the form of a power substrate (10), with a second assembly (21), in particular in the form of a logic substrate (20), by means of at least one soldered connection (17 to 19) or a sintered connection is electrically connected, characterized in that in the area of the soldered connection (17 to 19) or the sintered connection on the first and/or the second assembly (11, 21) in an additive manufacturing process at least one spacer layer ( 22 to 24) is applied.
2. Verfahren nach Anspruch 1 , dadurch gekennzeichnet, dass die wenigstens eine Abstandsschicht (22 bis 24) ausschließlich auf der als Logiksubstrat (21) ausgebildeten zweiten Baugruppe (20) aufgebracht wird. 2. The method according to claim 1, characterized in that the at least one spacer layer (22 to 24) is applied exclusively to the second assembly (20) designed as a logic substrate (21).
3. Verfahren nach Anspruch 1 oder 2, dadurch gekennzeichnet, dass die wenigstens eine Abstandsschicht (22 bis 24) durch eine Oberflächenbehandlung insbesondere mit einer weiteren Schicht (27) versehen wird. 3. The method according to claim 1 or 2, characterized in that the at least one spacer layer (22 to 24) is provided by a surface treatment, in particular with a further layer (27).
4. Verfahren nach einem der Ansprüche 1 bis 3, dadurch gekennzeichnet, dass mehrere Bereiche (12 bis 14) mit einer unterschiedlichen Höhe der Abstandsschichten (22 bis 24) ausgebildet werden, deren unterschiedliche Höhen im gefertigten Zustand der Elektronikanordnung (100) eine parallele Anordnung der beiden Baugruppen (11, 21) ermöglichen. 4. The method according to any one of claims 1 to 3, characterized in that several areas (12 to 14) with a different height of the spacer layers (22 to 24) are formed, the different heights in the finished state of the electronic assembly (100) a parallel arrangement allow the two assemblies (11, 21).
5. Verfahren nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass im Bereich der Baugruppe (11), die keine Abstandsschichten (22 bis 24) aufweist, zur Ausbildung der Löt- oder Sinterverbindung mit der wenigstens einen Abstandsschicht (22 bis 24) eine Lot- oder Sinterpaste zur Ausbildung einer Lotschicht (17 bis 19) oder einer Sinterverbindung aufgebracht, insbesondere aufgedruckt wird. Verfahren nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass die Einschweißtiefe eines Laserstrahls (26) zum Aufschmelzen des Ausgangsmaterials der wenigstens einen Abstandsschicht (22 bis 24) mit größerem Abstand zur Oberfläche der Baugruppe (11) bzw. zunehmender Schichtdicke vergrößert wird. Verfahren nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass die Elektronikanordnung (100) zumindest im Bereich der zweiten Baugruppe (21), die Zwischenräume zwischen den beiden Baugruppen (11, 21) ausfüllend, mit einer Vergussmasse (30) überdeckt wird. Elektronikanordnung (100), vorzugsweise hergestellt nach einem Verfahren nach einem der Ansprüche 1 bis 7, mit einer ersten Baugruppe (11) in Form eines Leistungssubstrats (10) und einer zweiten Baugruppe (21) in Form eines Logiksubstrats (20), wobei zwischen den beiden Baugruppen (11 , 21) zur elektrischen Kontaktierung zwischen den beiden Baugruppen (11, 21) Löt- oder Sinterverbindungen ausgebildet sind, dadurch gekennzeichnet, dass die Löt- oder Sinterverbindungen im Bereich wenigstens einer, im additiven Fertigungsverfahren ausgebildeten Abstandsschicht (22 bis 24) angeordnet sind. Elektronikanordnung nach Anspruch 8, dadurch gekennzeichnet, dass mehrere Bereiche (12 bis 14) mit unterschiedlichen Höhen aufweisenden Abstandschichten (22 bis 24) vorhanden sind. Elektronikanordnung nach Anspruch 8 oder 9, dadurch gekennzeichnet, dass die Dicke einer Metallisierungsschicht (25) an der Baugruppe (21), auf der die wenigstens eine Abstandschicht (22 bis 24 ) aufgebaut ist, mehr als 5pm, vorzugsweise mehr als 10pm, besonders bevorzugt etwa 50pm beträgt. Baugruppe (21), insbesondere ein Logiksubstrat (20), dadurch gekennzeichnet, dass die Baugruppe (21) wenigstens eine, im additiven Fertigungsverfahren ausgebildete Abstandsschicht (22 bis 24) aufweist. Baugruppe (21) nach Anspruch 11, dadurch gekennzeichnet, dass die Baugruppe (21) mehrere Bereiche (12 bis 14) mit unterschiedlichen Höhen aufweisenden Abstandschichten (22 bis 24) aufweist. Baugruppe (21) nach Anspruch 11 oder 12, dadurch gekennzeichnet, dass die wenigstens eine Abstandsschicht (22 bis 24) auf einer Metallisierungsschicht (25) aufgebracht ist und/oder dass die wenigstens eine Abstandsschicht (22 bis 24) mit einer weiteren Schicht (27), insbesondere einer Silberbeschichtung, versehen ist. 5. The method according to any one of claims 1 to 4, characterized in that in the area of the assembly (11), which has no spacer layers (22 to 24), to form the soldered or sintered connection with the at least one spacer layer (22 to 24), a solder or sinter paste is used to form a solder layer (17 to 19) or a sintered compound applied, in particular printed. Method according to one of Claims 1 to 5, characterized in that the welding depth of a laser beam (26) for melting the starting material of the at least one spacer layer (22 to 24) is increased with a greater distance from the surface of the assembly (11) or increasing layer thickness. Method according to one of Claims 1 to 6, characterized in that the electronics arrangement (100) is covered with a casting compound (30) at least in the region of the second assembly (21), filling the gaps between the two assemblies (11, 21). Electronic arrangement (100), preferably produced by a method according to any one of claims 1 to 7, with a first assembly (11) in the form of a power substrate (10) and a second assembly (21) in the form of a logic substrate (20), wherein between the Both assemblies (11, 21) for electrical contacting between the two assemblies (11, 21) soldered or sintered connections are formed, characterized in that the soldered or sintered connections in the area of at least one spacer layer (22 to 24) formed in the additive manufacturing process are arranged. Electronics arrangement according to Claim 8, characterized in that there are a plurality of regions (12 to 14) with spacer layers (22 to 24) having different heights. Electronics arrangement according to claim 8 or 9, characterized in that the thickness of a metallization layer (25) on the assembly (21) on which the at least one spacer layer (22 to 24) is built is more than 5 pm, preferably more than 10 pm, particularly preferably about 50 pm. Assembly (21), in particular a logic substrate (20), characterized in that the assembly (21) has at least one spacer layer (22 to 24) formed in the additive manufacturing process. Assembly (21) according to Claim 11, characterized in that the assembly (21) has a plurality of regions (12 to 14) with spacer layers (22 to 24) having different heights. Assembly (21) according to Claim 11 or 12, characterized in that the at least one spacer layer (22 to 24) is applied to a metallization layer (25) and/or that the at least one spacer layer (22 to 24) is covered with a further layer (27 ), in particular a silver coating.
PCT/EP2022/071339 2021-08-30 2022-07-29 Method for producing an electronics arrangement, electronics arrangement and module WO2023030784A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006033175A1 (en) 2006-07-18 2008-01-24 Robert Bosch Gmbh electronics assembly
US20170215286A1 (en) * 2016-01-27 2017-07-27 Northrop Grumman Systems Corporation Resilient micro lattice electrical interconnection assembly
EP3751605A1 (en) * 2019-06-11 2020-12-16 Siemens Aktiengesellschaft Electronic switching circuit and method for producing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102006033175A1 (en) 2006-07-18 2008-01-24 Robert Bosch Gmbh electronics assembly
US20170215286A1 (en) * 2016-01-27 2017-07-27 Northrop Grumman Systems Corporation Resilient micro lattice electrical interconnection assembly
EP3751605A1 (en) * 2019-06-11 2020-12-16 Siemens Aktiengesellschaft Electronic switching circuit and method for producing same

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