WO2023030053A1 - 一种llc芯片、缓存系统以及llc芯片的读写方法 - Google Patents

一种llc芯片、缓存系统以及llc芯片的读写方法 Download PDF

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Publication number
WO2023030053A1
WO2023030053A1 PCT/CN2022/113704 CN2022113704W WO2023030053A1 WO 2023030053 A1 WO2023030053 A1 WO 2023030053A1 CN 2022113704 W CN2022113704 W CN 2022113704W WO 2023030053 A1 WO2023030053 A1 WO 2023030053A1
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storage
logic unit
interface logic
llc
chip
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PCT/CN2022/113704
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English (en)
French (fr)
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江喜平
周小锋
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西安紫光国芯半导体有限公司
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Publication of WO2023030053A1 publication Critical patent/WO2023030053A1/zh
Priority to US18/526,281 priority Critical patent/US20240099034A1/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B80/00—Assemblies of multiple devices comprising at least one memory device covered by this subclass
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/406—Management or control of the refreshing or charge-regeneration cycles
    • G11C11/40607—Refresh operations in memory devices with an internal cache or data buffer
    • G—PHYSICS
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/084—Multiuser, multiprocessor or multiprocessing cache systems with a shared cache
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate

Definitions

  • the present application relates to the field of data cache, in particular to an LLC chip, a cache system and a method for reading and writing the LLC chip.
  • LLC last-level cache, ultimate cache
  • CPU Central Processing Unit, central processing unit
  • MLC mid-level cache, secondary cache
  • LLC uses MRAM memory modules for data caching, where MRAM memory is a medium memory with a small capacity.
  • the present application at least provides an LLC chip, a cache system, and a method for reading and writing the LLC chip, so as to realize a large-capacity, high-bandwidth LLC.
  • the first aspect of the present application provides an LLC chip.
  • the LLC chip includes a storage wafer, an interface logic unit, and a packaging substrate.
  • the interface logic unit and the storage wafer are sequentially arranged on the packaging substrate.
  • a plurality of processing components are connected to an interface logic unit to perform read and write operations on the storage wafer through the interface logic unit;
  • the interface logic unit includes: an on-chip network, a controller, and a register; wherein, one end of the on-chip network is used to connect an interface, and the interface is used to connect the interface logic unit to the processing component, The other end of the on-chip network is connected to one end of the controller, the other end of the controller is connected to one end of the register, and the other end of the register is connected to the storage wafer.
  • the interface logic unit includes: a plurality of controllers and a plurality of registers; the on-chip network is connected to the plurality of controllers, each of the controllers is correspondingly connected to a register, and the registers are connected to all storage wafers.
  • the network-on-chip includes a plurality of interconnected routers to form a plurality of nodes, each of the nodes is connected to a controller, and the processing component accesses the corresponding router connection by accessing the address of the router.
  • the controller is used to access the storage array of the storage wafer connected to the controller through the controller, so as to perform data read and write operations.
  • the interface logic unit includes multiple independent interfaces, controllers, and registers
  • the storage wafer includes multiple independent DRAM arrays
  • multiple independent interfaces, controllers, and registers form independent access to multiple DRAM arrays
  • the plurality of processing components are respectively connected to paths through corresponding interfaces, so as to perform non-shared independent storage access to independently corresponding DRAM arrays.
  • the interface logic unit includes: an on-chip network, and the on-chip network is connected to a plurality of the controllers.
  • the interface logic unit includes: a DDR controller, the DDR controller is connected to the on-chip network, and the DDR controller is also used to connect to the DDR memory to implement read and write operations on the DDR memory.
  • At least one processing component among the plurality of processing components performs read and write operations on the corresponding DRAM array through the channel.
  • the storage wafer includes at least one DRAM wafer, and multiple DRAM arrays are distributed in different regions of the same DRAM wafer; or, multiple DRAM arrays are distributed on multiple storage wafers, corresponding to multiple storage wafer layers or Projected overlapping regions of multiple memory wafers.
  • the storage wafer further includes a plurality of first bonding columns
  • the interface logic unit further includes a plurality of second bonding columns and a plurality of bumps
  • the package substrate includes a plurality of lead ports
  • each first bonding column Connect with the corresponding second bonding column, so that the storage wafer is connected to the interface logic unit, the interface logic unit is connected to the packaging substrate through a plurality of bumps, and the packaging substrate is connected to a plurality of processing components through a plurality of lead ports.
  • the controller includes a cache coherence protocol controller, and the cache coherence protocol controller accesses the DDR controller through the on-chip network to implement read and write operations on the DDR memory;
  • the cache coherence protocol controllers of multiple controllers communicate with each other through the on-chip network.
  • the LLC chip includes a plurality of storage wafers, and the plurality of storage wafers are sequentially stacked on the interface logic unit, and two adjacent storage wafers among the plurality of storage wafers are connected by bonding.
  • the LLC chip further includes an interface, the interface is connected to the interface logic unit, and the interface is used to connect to the processing component.
  • the second aspect of the present application provides a cache system, the cache system includes an LLC chip; processing components; each of the processing components includes at least two central processing units, at least two L1 level caches and one L2 level cache, a plurality of The processing component is connected to the LLC chip to perform read and write operations; the LLC chip includes a storage wafer, an interface logic unit and a packaging substrate, and the interface logic unit and the storage wafer are sequentially arranged on the packaging substrate On the above, the storage wafer and the interface logic unit are three-dimensionally integrated and arranged on the packaging substrate to form the LLC chip; multiple processing components are connected to the interface logic unit to pass the interface logic The unit performs read and write operations on the storage wafer; the storage wafer includes at least one storage space, and multiple processing components perform read and write operations on a specific storage space or any storage space, so as to realize non- Shared independent storage access or shared storage access; wherein, the storage space of the storage wafer is divided according to the access volume or access speed of a plurality of the processing components.
  • the second aspect of the present application provides a method for reading and writing an LLC chip, including: receiving input information from a central processing unit; driving a corresponding controller according to the input information; and accessing a DRAM array for reading and writing operations.
  • the present application improves the signal transmission bandwidth of the LLC chip through the three-dimensional integration of the storage wafer and the interface logic unit through multiple distributed interfaces; at the same time, the present application adopts the non-shared mode or shared mode for data caching, so that the processing components can perform read and write operations on the storage wafer, and improve the efficiency of the processing components in accessing data.
  • Fig. 1 is the first structural representation of an embodiment of the LLC chip of the present application
  • Fig. 2 is the second structural schematic diagram of an embodiment of the LLC chip of the present application.
  • Fig. 3 is a schematic structural diagram of an embodiment of an interface logic unit in Fig. 1;
  • Fig. 4 is a schematic structural diagram of another embodiment of the interface logic unit in Fig. 1;
  • FIG. 5 is a schematic structural diagram of another embodiment of the LLC chip of the present application.
  • FIG. 6 is a schematic structural diagram of another embodiment of the LLC chip of the present application.
  • FIG. 7 is a schematic structural diagram of the arrangement of the DRAM array of the present application.
  • FIG. 8 is a schematic structural diagram of another embodiment of the LLC chip of the present application.
  • Fig. 9 is a schematic flow chart of the application's LLC chip for reading and writing operations
  • FIG. 10 is a schematic structural diagram of the caching system of the present application.
  • the way of CPU cache data includes FLC (first-level cache, primary cache), MLC (mid-level cache, secondary cache) and LLC (last-level cache, ultimate cache), corresponding to L1 level cache respectively , L2 cache and L3 cache.
  • L3-level cache Compared with L1-level cache and L2-level cache, L3-level cache has the advantages of higher frequency and lower latency for data access.
  • a NoC is added between the MLC and the LLC of the CPU to increase the bandwidth for the CPU to access the LLC.
  • the LLC uses the MRAM memory module for data caching, and the MRAM memory is a medium memory with a small capacity.
  • the present application provides an LLC chip for implementing a large-capacity, high-bandwidth LLC.
  • FIG. 1 is a first schematic structural diagram of an embodiment of the LLC chip of the present application
  • FIG. 2 is a second structural schematic diagram of an embodiment of the LLC chip of the present application.
  • the LLC chip 1 includes a packaging substrate 10 , an interface logic unit 20 and a storage wafer 30 .
  • the interface logic unit 20 and the storage wafer 30 are sequentially arranged on the packaging substrate 10
  • the storage wafer 30 and the interface logic unit 20 are three-dimensionally integrated and arranged on the packaging substrate 10 to form the LLC chip 1 .
  • packaging substrate 10 is connected to the interface logic unit 20 , and the interface logic unit 20 is further connected to the storage wafer 30 .
  • the CPU is interconnected with the LLC chip through the packaging substrate 10 of the LLC chip.
  • the CPU and the LLC chip are interconnected through an additional packaging substrate and/or a circuit board; or the CPU is assembled on the packaging substrate of the LLC chip and interconnected with the LLC chip.
  • CPU and LLC chips are interconnected through an additional package substrate and/or a circuit board as an example.
  • the memory wafer 30 includes a plurality of first bonding pillars 31
  • the interface logic unit 20 includes a plurality of second bonding pillars 22 and a plurality of bumps 21
  • the packaging substrate 10 includes a plurality of lead ports 11 .
  • a plurality of first bonding pillars 31 are arranged corresponding to a plurality of second bonding pillars 22, and each first bonding pillar 31 is connected to a corresponding second bonding pillar 22, so that the storage wafer 30 is connected to the interface logic Unit 20.
  • the interface logic unit 20 is connected to the package substrate 10 through a plurality of bumps 21 , and the package substrate 10 is connected to the CPU through a plurality of lead ports 11 .
  • the storage wafer 30 is connected to the CPU through the interface logic unit 20 and the packaging substrate 10 in sequence, so that the CPU performs read and write operations on the storage wafer 30 .
  • the LLC chip 1 three-dimensionally integrates the storage wafer 30 and the interface logic unit 20, and connects the storage wafer 30 and the interface logic unit 20 by setting a plurality of first bonding pillars 31 and a plurality of second bonding pillars 22 correspondingly. , and then improve the signal transmission bandwidth through multiple distributed interfaces.
  • the bonding between the first bonding pillar 31 and the second bonding pillar 22 is set as one of the ways to realize the connection between the storage wafer 30 and the interface logic unit 20, in other embodiments
  • the storage wafer 30 and the interface logic unit 20 can also be connected through TSV (Through Silicon Via), RDL (Re Distribution Layer) or Bump.
  • FIG. 3 is a schematic structural diagram of an embodiment of the interface logic unit in FIG. 1 .
  • the interface logic unit 20 includes an on-chip network 23 , a controller 24 and a register 25 .
  • the central processing unit (CPU) 2 is connected to the interface logic unit 20 through the interface 40 .
  • the central processing unit 2 is integrated with an L1 cache 201 and an L2 cache 202 to form a processing component 200 , and the processing component 200 is further connected to the LLC chip 1 through the interface 40 , that is, connected to the L3 cache.
  • the integrated L2 cache 202 in the CPU 2 can be omitted.
  • the interface 40 may be an existing LLC logical interface.
  • the interface 40 may be composed of a plurality of bumps 21 interfacing with the logic unit 20 , the packaging substrate 10 , and a plurality of lead ports 11 of the packaging substrate 10 .
  • One end of the on-chip network 23 is connected to the interface 40 , the other end of the on-chip network 23 is connected to one end of the controller 24 , the other end of the controller 24 is connected to one end of the register 25 , and the other end of the register 25 is connected to the storage wafer 30 .
  • the interface 40 is used to connect the central processing unit 2 and the network on chip 23, so that the interface logic unit 20 searches for the node corresponding to the network on chip 23 according to the input information of the central processing unit 2, and then drives the controller 24 corresponding to the node; 24 is used for accessing the storage wafer 30; the register 25 is used for data buffering.
  • the register 25 is connected to the storage wafer 30 through multiple ports for data buffering.
  • the central processing unit 2 of the processing assembly 200 When the central processing unit 2 of the processing assembly 200 outputs read and write instructions to the LLC chip 1, the central processing unit 2 sequentially passes through the L1 level cache 201, the L2 level cache 202, the interface 40, the network on chip 23, the controller 24 and the register 25 to store Wafer 30 performs read and write operations.
  • the read and write operations conform to a cache coherence protocol, such as the MESI protocol.
  • the storage wafer 30 is a DRAM (Dynamic Random Access Memory, Dynamic Random Access Memory) wafer, and the DRAM wafer includes at least one DRAM array 32, and the interface logic unit 20 is connected to at least one DRAM array 32, To make the central processing unit 2 perform read and write operations.
  • DRAM Dynamic Random Access Memory
  • DRAM is a volatile memory, which is different from non-volatile memory in that DRAM can perform data access faster and has lower data access delay.
  • the LLC chip 1 uses a volatile memory DRAM wafer as the storage wafer 30 to increase the data access speed and further increase the speed of the central processing unit 2 to read and write the LLC chip 1 .
  • the LLC chip 1 of this embodiment is provided with a register 25 connected to the storage wafer 30 and the controller 24 to reduce performance loss caused by frequent data switching.
  • FIG. 4 is a schematic structural diagram of another embodiment of the interface logic unit in FIG. 1 .
  • the interface logic unit 20 of this embodiment includes multiple controllers 24 and multiple registers 25 .
  • the on-chip network 23 is connected to multiple controllers 24 , and each controller 24 is connected to the storage wafer 30 through a register 25 .
  • the network on chip 23 includes a plurality of interconnected routers to form a plurality of nodes, each node is connected to a single controller 24, and the central processing unit 2 can access the controller 24 corresponding to the router by accessing the address of the router. to read and write data.
  • the central processing unit 2 inputs an address through the interface logic unit 20 , and the interface logic unit 20 drives the controller 24 connected to the node corresponding to the address according to the address, so that the central processing unit 2 performs read and write operations on the storage wafer 30 .
  • central processing units 2 there may be two central processing units 2 , each of which is integrated with an L1 level cache 201 , and the two central processing units 2 share an L2 level cache 202 .
  • two CPUs 2 , two L1 caches 201 and a shared L2 cache 202 form a processing component 200 , and the processing component 200 is connected to the LLC chip 1 through an interface 40 .
  • processing component 200 can perform read and write operations on the LLC chip 1 through non-shared independent memory access or shared memory access.
  • the storage wafer 30 includes at least one storage space, and the two central processing units 2 in the processing component 200 respectively correspond to different storage spaces. device 2 for memory access.
  • the DRAM array 32 performs read and write operations, that is, performs read and write operations on a specific storage space.
  • the two central processing units 2 can simultaneously or independently perform read and write operations on the storage wafer 30 , that is, realize the non-shared mode cache data of the LLC chip 1 .
  • the LLC chip 1 may also perform data caching in a shared mode.
  • any central processing unit 2 in the processing assembly 200 can read and write any DRAM array 32 in the storage wafer 30 through the network on chip 23, that is, read and write any storage space of the storage wafer 30. operate.
  • the central processing unit 2 reads and writes to the DRAM array 32
  • the next central processing unit 2 to be executed further performs the reading and writing operation on the DRAM array 32 that the current central processing unit 2 performs the reading and writing operation, or another
  • the DRAM array 32 performs read and write operations, it needs to wait for the current CPU 2 to complete the corresponding read and write operations before accessing the target DRAM array 32 to execute the read and write operations.
  • the LLC chip 1 is connected to multiple controllers 24 through the on-chip network 23 , and the address is corresponding to the controller 24 to quickly find the target controller 24 , thereby realizing large-scale high-speed calculation.
  • the LLC chip 1 of this embodiment performs data caching through the non-shared mode or the shared mode, so that the central processing unit 2 performs read and write operations on the target DRAM array 32, and improves the efficiency of the central processing unit 2 in accessing data.
  • FIG. 5 is a schematic structural diagram of another embodiment of the LLC chip of the present application.
  • this embodiment may include a plurality of processing components 200, each processing component 200 includes at least two central processing units 2, and at least two central processing units 2 in each processing component 200
  • the L2 level cache 202 is commonly used to form a processing component 200 , and multiple processing components 200 are connected to the LLC chip 1 through the interface 40 .
  • each processing component 200 is different, and the required storage space is different, that is, the required number of DRAM arrays 32 is different. Therefore, a plurality of processing components 200 can be connected with different numbers of DRAM arrays 32 according to requirements, as their corresponding storage spaces.
  • the DRAM array 32 has a certain number of rows and columns, and the division of the DRAM array 32 can be as an individual DRAM array 32 with a preset number of rows and columns, and different processing components 200 correspond to different numbers of individual DRAM arrays 32 .
  • the number of rows of the DRAM array 32 is divided according to the ratio of the storage space requirements of different processing components 200 , and each processing component 200 includes a DRAM array 32 with a corresponding number of rows.
  • the number of columns of the DRAM array 32 is divided according to the ratio of storage space requirements of different processing components 200 , and each processing component 200 includes a DRAM array 32 with a corresponding number of columns.
  • the processing component 200 only includes one CPU 2 , one L1 cache 201 and one L2 cache 202 .
  • FIG. 6 is a schematic structural diagram of another embodiment of the LLC chip of the present application.
  • at least two central processing units 2 share the L2 level cache 202 to form a processing component 200, and at least two processing components 200 are respectively connected to the LLC chip 1 through an independent corresponding interface 40.
  • the controller 24 and the register 25 communicate with each other to perform non-shared independent storage access to the independently corresponding DRAM array 32 .
  • the LLC chip 1 includes a plurality of interfaces 40, and each interface 40 corresponds to a DDR storage array access channel, respectively through an independent controller 24, an independent register 25, corresponding and independent access, non-shared, storage array 32 .
  • controller 24 includes a storage access controller (not shown) of the DRAM array 32 for establishing storage access to the corresponding DRAM array 32; , access the DDR controller 26, and then realize the read and write operations to the DDR memory 50 (main memory).
  • a storage access controller (not shown) of the DRAM array 32 for establishing storage access to the corresponding DRAM array 32; , access the DDR controller 26, and then realize the read and write operations to the DDR memory 50 (main memory).
  • the cache coherence protocol controllers in the plurality of controllers 24 also communicate with each other by means of the on-chip network 23, and are used to realize at least part of the data exchange between the processing components 200, so as to overcome the problem of multiple central processing units in the non-shared storage structure.
  • the data synchronization between the device 2 improves the function of the cache coherence protocol.
  • each processing component 200 can independently realize reading and writing to the large-capacity and high-bandwidth LLC storage space, and an independent cache line (cache line) can be designed for each processing component 200 to increase cache exchange efficiency; It is also possible to increase the bit width of cache lines of part or all of the processing components 200 to fully utilize the advantage of the ultra-large bandwidth of the three-dimensionally integrated memory-bonded memory wafer 30 .
  • multiple sets of DDR controllers 26 may be designed to be interconnected with the on-chip network 23 to form multiple DDR channels and control multiple sets of DDR memories 50 respectively.
  • the arrangement of multiple DRAM arrays 32 may be as shown in FIG. 7 , which is a schematic structural diagram of the arrangement of DRAM arrays in the present application.
  • multiple DRAM arrays 32 may be distributed in different regions of the same storage wafer 30 .
  • multiple DRAM arrays 32 can also be distributed on multiple storage wafers 30, each storage wafer 30 is a storage wafer layer, and multiple DRAM arrays 32 are respectively distributed on multiple storage wafers. storage wafer layer.
  • multiple DRAM arrays 32 can also be distributed on multiple storage wafers 30.
  • This schematic diagram takes two storage wafers 30 as an example, and the two storage wafers 30 are parallel to the storage wafers.
  • the projections on the plane of 30 have a partial overlapping area, and the DRAM arrays 32 are distributed in the partial overlapping area.
  • different storage wafers 30 have different partial overlapping areas in the projections on a plane parallel to the storage wafers 30, and then a plurality of DRAM arrays 32 correspond to different storage wafers respectively. 30 projected partial overlap area.
  • the storage wafer 30 includes a DRAM array 32, and the formed storage capacity (hundreds of megabytes to tens of megabytes) is 2 to 4 orders of magnitude higher than that of the prior art (more than ten megabytes), which is enough to provide each group of processing components 200 with independent
  • the non-shared LLC storage space the storage capacity is still much larger than the existing technology, which greatly increases the LLC hit rate and reduces the frequency of storage access to the main memory.
  • the storage wafer 30 contains a DRAM array 32, which is connected to the LLC chip 1 through three-dimensional integrated bonding.
  • the interconnection density is extremely high (1 micron pitch, millions of connection points per square millimeter), and the storage wafer 30 and the LLC chip 1 can be connected.
  • a very large bus bit width (thousands to hundreds of thousands) is established between the chips 1, which is 2 to 4 orders of magnitude higher than that of the prior art (64 bits).
  • the large bus bit width provides independent non-shared LLC storage access channels for at least part or all of the processing components 200, and the memory access bandwidth is still far greater than that of the prior art.
  • each processing component 200 can independently realize the reading and writing of the large-capacity and high-bandwidth LLC storage space, getting rid of the constraints of the bus of the controller 24 in the shared storage LLC structure, and there is no need to establish mutual waiting for time-sharing access
  • the mechanism not only simplifies the design difficulty of the controller 24, but also realizes the concurrent reading and writing of the large-capacity and high-bandwidth LLC storage space by the processing component 200, and fully releases the ultra-large bandwidth advantage of the three-dimensional integrated bonded storage wafer 30.
  • FIG. 8 is a schematic structural diagram of another embodiment of the LLC chip of the present application.
  • the LLC chip 1 includes a plurality of storage wafers 30 .
  • the number of memory wafers 30 may be 2, 3, 4 and so on.
  • a plurality of storage wafers 30 are sequentially stacked on the interface logic unit 20 , and two adjacent storage wafers 30 among the plurality of storage wafers 30 are connected by bonding.
  • the plurality of storage wafers 30 of the LLC chip 1 in this embodiment all include a DRAM array 32.
  • the central processing unit 2 adopts a non-shared mode to cache data
  • the plurality of central processing units 2 can be based on The specific operation required for the division of the storage space may be to use the DRAM array 32 of a single storage wafer 30 as an individual DRAM array 32, and different central processing units 2 correspond to different numbers of individual DRAM arrays 32, that is, different central processing units 2 correspond to different The number of memory wafers is 30.
  • multiple central processors 2 can divide the specific operation of the storage space according to the demand, which can be multiple stacked storage wafers In the storage wafer array formed by 30, the partial areas where the projections of different storage wafers 30 overlap are used as individual DRAM arrays 32, and different central processing units 2 correspond to individual DRAM arrays 32 of different capacities, that is, different central processing units 2 correspond to storage In the wafer array, the projections of different areas partially overlap.
  • central processing unit 2 when the central processing unit 2 caches data in a shared mode, multiple central processing units 2 do not need to divide the storage space, and can directly access the corresponding DRAM array 32 according to the address.
  • the LLC chip 1 of this embodiment increases the data capacity of the LLC chip 1 by sequentially stacking a plurality of storage wafers 30, and improves the speed of data access through the bonding connection mode between the plurality of storage wafers 30, thereby realizing large capacity, High bandwidth data cache.
  • the storage wafer 30 and the interface logic unit 20 are connected by three-dimensionally integrating the storage wafer 30 and the interface logic unit 20, and the storage wafer 30 and the interface logic unit 20 are connected by a plurality of first bonding pillars 31 and a plurality of second bonding pillars 22 corresponding to each other.
  • Multiple distributed interfaces increase signal transmission bandwidth.
  • the application uses the DRAM wafer of volatile memory as storage wafer 30, improves the bandwidth and the speed of data access, further improves the speed that central processing unit 2 carries out read and write operation to LLC chip 1.
  • the present application implements data caching in a non-shared mode, so that the central processing unit 2 can perform read and write operations on the target DRAM array 32 to improve the efficiency of the central processing unit 2 in accessing data.
  • the present application increases the data capacity of the LLC chip 1 by stacking multiple storage wafers 30 in sequence, and improves the data access rate through the bonding connection mode between multiple storage wafers 30 to achieve large capacity and high bandwidth. data cache.
  • FIG. 9 is a schematic flow chart of the read and write operations of the LLC chip of the present application.
  • the method for the LLC chip of this embodiment to perform read and write operations may include the following steps:
  • Step S11 Receive input information from the central processing unit.
  • the LLC chip 1 receives information input by the central processing unit 2 through a plurality of lead ports 11 .
  • the input information includes read and write instructions and address information.
  • the read/write instruction is specifically a write instruction
  • the input signal also includes data information to be stored.
  • Step S12 Drive the corresponding controller according to the input information.
  • the input information is sequentially transmitted to the interface logic unit 20 through the plurality of lead ports 11 of the package substrate 10, the package substrate 10 and the plurality of bumps 21, and the interface logic unit 20 searches for the address information in the on-chip network 23 according to the address information contained in the input information.
  • the node corresponding to the address information further drives the controller 24 connected to the node; and, the data information in the input information is temporarily stored in the register 25 by the controller 24 .
  • Step S13 accessing the DRAM array for read and write operations.
  • the central processing unit 2 when the storage space of the register 25 is full, the central processing unit 2 further accesses the storage wafer 30, and transmits the temporarily stored data through the register 25 to the DRAM array 32 contained in the storage wafer 30 through the port for reading and writing. operate.
  • the central processing unit 2 reads the data information stored in the DRAM array 32 corresponding to the central processing unit 2 through the controller 24 and the register 25 , and the data information is pre-stored in the register 25 .
  • the register 25 further transmits the data information to the CPU 2 through the controller 24 and the on-chip network 23 .
  • the present application also provides a caching system, please refer to FIG. 10 , which is a schematic structural diagram of the caching system of the present application.
  • the cache system 50 includes an LLC chip 51 and a plurality of processing components 52 .
  • the LLC chip 51 is the LLC chip 1 disclosed in the above-mentioned embodiment
  • the processing component 52 is the processing component 200 disclosed in the above-mentioned embodiment, which will not be repeated here.
  • a plurality of processing components 52 are respectively connected to the LLC chip 51 to perform read and write operations on the LLC chip 51 .
  • multiple processing components 52 can independently perform read and write operations on the LLC chip 51, or multiple processing components 52 simultaneously perform read and write operations on the LLC chip 51, or at least two of the multiple processing components 52 simultaneously perform read and write operations on the LLC chip 51. 51 for read and write operations.
  • the cache system 50 divides the storage space of the storage wafer 30 according to the access volume or access speed of multiple processing components 52, so that each processing component 52 performs read and write operations on the corresponding storage space.
  • the specific division method is as above, and will not be repeated here.
  • multiple processing components 52 are packaged in the same device.

Abstract

一种LLC芯片（1）及缓存系统（50），该LLC芯片（1）包括存储晶圆（30）、接口逻辑单元（20）和封装基板（10），接口逻辑单元（20）与存储晶圆（30）依次设置于封装基板（10）上，存储晶圆（30）与接口逻辑单元（20）通过三维集成，并且设置于所述封装基板（10）上，以形成LLC芯片（1），多个处理组件（200）连接接口逻辑单元（20），以通过接口逻辑单元（20）对存储晶圆（30）进行读写操作；存储晶圆（30）包括至少一个存储空间，多个处理组件（200）对特定存储空间或任一存储空间进行读写操作，以实现非共享独立存储访问或共享存储访问；其中，存储晶圆（30）的存储空间根据多个处理组件（200）的访问量或访问速度划分。通过三维集成存储晶圆（30）与接口逻辑单元（20），进而通过多个分布式的接口提高信号传输带宽，并通过非共享模式或共享模式进行数据缓存，提高处理组件（200）访问数据的效率。

Description

一种LLC芯片、缓存系统以及LLC芯片的读写方法
相关申请的交叉引用
本申请基于2021年9月2日提交的中国专利申请202111027040.1主张其优先权，此处通过参照引入其全部的记载内容。
【技术领域】
本申请涉及数据缓存领域，特别是涉及一种LLC芯片、缓存系统以及LLC芯片的读写方法。
【背景技术】
现有技术中CPU(Central Processing Unit，中央处理器)为了实现LLC(last-level cache，终极缓存)，在CPU的MLC(mid-level cache，次级缓存)和LLC之间增加一个NoC(network-on-chip，片上网络)，以增加CPU对LLC访问的带宽，LLC通过使用MRAM存储器模块进行数据缓存，其中MRAM存储器为介质存储器，容量较小。
【发明内容】
本申请至少提供一种LLC芯片、缓存系统以及LLC芯片的读写方法，用于实现大容量、高带宽的LLC。
本申请第一方面提供了一种LLC芯片，该LLC芯片包括存储晶圆、接口逻辑单元和封装基板，接口逻辑单元与存储晶圆依次设置于封装基板上，存储晶圆与接口逻辑单元通过三维集成，并且设置于所述封装基板上，以形成LLC芯片，多个处理组件连接接口逻辑单元，以通过接口逻辑单元对存储晶圆进行读写操作；
可选地，所述接口逻辑单元包括：片上网络、控制器和寄存器；其中，所述片上网络的一端用于连接接口，所述接口用于将所述接口逻辑单元与所述处理组件连接，所述片上网络的另一端连接所述控制器的一端，所述控制器的另一端连接所述寄存器的一端，所述寄存器的另一端连接所述存储晶圆。
可选地，所述接口逻辑单元包括：多个控制器和多个寄存器；所述片上网络连接所述多个控制器，每一所述控制器对应连接一个寄存器，且通过所述寄 存器连接所述存储晶圆。
可选地，所述片上网络包括多个相互连接的路由器，以形成多个节点，每个所述节点连接一个控制器，所述处理组件通过访问所述路由器的地址，进而访问对应的路由器连接的控制器，以通过所述控制器访问与其连接的存储晶圆的存储阵列，从而进行数据读写操作。
可选地，接口逻辑单元包括多个独立的接口、控制器以及寄存器，存储晶圆包括多个独立的DRAM阵列，多个独立的接口、控制器与寄存器形成独立访问多个DRAM阵列的通路，多个处理组件分别通过对应的接口连接通路，以对独立对应的DRAM阵列进行非共享独立存储访问。
可选地，所述接口逻辑单元包括：片上网络，所述片上网络连接多个所述控制器。
可选地，所述接口逻辑单元包括：DDR控制器，所述DDR控制器连接所述片上网络，所述DDR控制器还用于连接DDR存储器，实现对DDR存储器的读写操作。
可选地，多个处理组件中的至少一个处理组件通过通路对与其对应设置的DRAM阵列进行读写操作。
可选地，存储晶圆包括至少一个DRAM晶圆，多个DRAM阵列分布于同一DRAM晶圆的不同区域；或，多个DRAM阵列分布于多个存储晶圆，对应多个存储晶圆层或多个存储晶圆的投影重叠区域。
可选地，存储晶圆还包括多个第一键合柱，接口逻辑单元还包括多个第二键合柱和多个凸点，封装基板包括多个引线端口，每个第一键合柱与对应的第二键合柱连接，以使存储晶圆连接接口逻辑单元，接口逻辑单元通过多个凸点连接封装基板，封装基板通过多个引线端口连接多个处理组件。
可选地，控制器包括缓存一致性协议控制器，缓存一致性协议控制器通过片上网络访问DDR控制器，以实现对DDR存储器的读写操作；
可选地，多个控制器的缓存一致性协议控制器通过片上网络相互通讯。
可选地，LLC芯片包括多个存储晶圆，多个存储晶圆依次堆叠设置于接口逻辑单元上，多个存储晶圆中相邻的两个存储晶圆通过键合的方式进行连接。
可选地，所述LLC芯片还包括接口，所述接口连接所述接口逻辑单元，且所述接口用于连接所述处理组件。
本申请第二方面提供了一种缓存系统，该缓存系统包括LLC芯片；处理组 件；每个所述处理组件包括至少两个中央处理器、至少两个L1级缓存与一个L2级缓存，多个所述处理组件连接所述LLC芯片，以进行读写操作；所述LLC芯片包括存储晶圆、接口逻辑单元和封装基板，所述接口逻辑单元与所述存储晶圆依次设置于所述封装基板上，所述存储晶圆与所述接口逻辑单元通过三维集成，并且设置于所述封装基板上，以形成所述LLC芯片；多个处理组件连接所述接口逻辑单元，以通过所述接口逻辑单元对所述存储晶圆进行读写操作；所述存储晶圆包括至少一个存储空间，多个所述处理组件对特定所述存储空间或任一所述存储空间进行读写操作，以实现非共享独立存储访问或共享存储访问；其中，所述存储晶圆的存储空间根据多个所述处理组件的访问量或访问速度划分。
可选地，根据权利要求15所述的LLC芯片，其特征在于，所述LLC芯片还包括接口，所述接口连接所述接口逻辑单元，且所述接口连接所述处理组件。
可选地，根据权利要求15所述的LLC芯片，其特征在于，所述缓存系统包括多个处理组件，每一所述处理组件包括至少两个中央处理器。
本申请第二方面提供了一种LLC芯片的读写方法，包括：接收中央处理器输入信息；根据输入信息，驱动对应的控制器；访问DRAM阵列，以进行读写操作。
本申请的有益效果是：区别于现有技术，本申请通过三维集成存储晶圆与接口逻辑单元，进而通过多个分布式的接口提高LLC芯片的信号传输带宽；同时，本申请通过非共享模式或共享模式进行数据缓存，以使处理组件对存储晶圆进行读写操作，提高处理组件访问数据的效率。
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，而非限制本申请。
【附图说明】
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其它的附图。
图1是本申请LLC芯片一实施例的第一结构示意图；
图2是本申请LLC芯片一实施例的第二结构示意图；
图3是图1中接口逻辑单元一实施例的结构示意图；
图4是图1中接口逻辑单元另一实施例的结构示意图；
图5是本申请LLC芯片另一实施例的结构示意图；
图6是本申请LLC芯片又一实施例的结构示意图；
图7是本申请DRAM阵列排布方式的结构示意图；
图8是本申请LLC芯片再一实施例的结构示意图；
图9是本申请LLC芯片进行读写操作的流程示意图；
图10是是本申请缓存系统的结构示意图。
【具体实施方式】
为使本领域的技术人员更好地理解本申请的技术方案，下面结合附图和具体实施方式对本申请所提供的LLC芯片及缓存系统做进一步详细描述。可以理解的是，所描述的实施例仅仅是本申请一部分实施例，而不是全部实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性的劳动前提下所获得的所有其它实施例，都属于本申请保护的范围。
本申请中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排它的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
现有技术中，CPU缓存数据的方式包括FLC(first-level cache，初级缓存)、MLC(mid-level cache，次级缓存)和LLC(last-level cache，终极缓存)，分别对应L1级缓存、L2级缓存和L3级缓存。相较与L1级缓存以及L2级缓存，L3级缓存具有更高的频率以及更低的时延进行数据访问的优点。
为了实现LLC，现有技术通过在CPU的MLC和LLC之间增加一个NoC以增加CPU对LLC访问的带宽。同时LLC通过使用MRAM存储器模块进行数据缓存，而MRAM存储器为介质存储器，容量较小。
因此，本申请提供一种LLC芯片，用于实现大容量、高带宽的LLC。
请参阅图1与图2，图1是本申请LLC芯片一实施例的第一结构示意图，图2是本申请LLC芯片一实施例的第二结构示意图。如图1所示，LLC芯片1包括封装基板10、接口逻辑单元20和存储晶圆30。其中，接口逻辑单元20与 存储晶圆30依次设置于封装基板10上，存储晶圆30与接口逻辑单元20通过三维集成，并且设置于封装基板10，以形成LLC芯片1。
其中，封装基板10连接接口逻辑单元20，接口逻辑单元20进一步连接存储晶圆30。
CPU通过LLC芯片的封装基板10与LLC芯片互连。具体地，CPU和LLC芯片，通过额外的封装基板，和/或，电路板互连；或者CPU被装配到LLC芯片的封装基板上，与LLC芯片互连。以下以CPU和LLC芯片，通过额外的封装基板，和/或，电路板互连为例。
如图2所示，存储晶圆30包括多个第一键合柱31，接口逻辑单元20包括多个第二键合柱22和多个凸点21，封装基板10包括多个引线端口11。
其中，多个第一键合柱31与多个第二键合柱22对应设置，每个第一键合柱31与对应的第二键合柱22连接，以使存储晶圆30连接接口逻辑单元20。接口逻辑单元20通过多个凸点(bump)21连接封装基板10，封装基板10通过多个引线端口11连接中央处理器。
当中央处理器对LLC芯片1输出读写指令时，存储晶圆30依次通过接口逻辑单元20和封装基板10连接中央处理器，使得中央处理器对存储晶圆30进行读写操作。
本实施例LLC芯片1三维集成存储晶圆30与接口逻辑单元20，通过多个第一键合柱31与多个第二键合柱22对应设置的方式连接存储晶圆30与接口逻辑单元20，进而通过多个分布式的接口提高信号传输带宽。
可选地，本实施例中通过第一键合柱31与第二键合柱22之间的键合设置为实现存储晶圆30与接口逻辑单元20连接的方式之一，在其它实施例中，存储晶圆30与接口逻辑单元20还可通过TSV(Through Silicon Via)、RDL(Re Distribution Layer)或Bump的方式进行连接。
结合图1-2，进一步参阅图3，图3是图1中接口逻辑单元一实施例的结构示意图。如图3所示，接口逻辑单元20包括片上网络23、控制器24和寄存器25。
中央处理器(CPU)2通过接口40连接接口逻辑单元20。其中，中央处理器2集成有L1级缓存201以及L2级缓存202，以构成处理组件200，处理组件200通过接口40进一步连接LLC芯片1，即连接L3级缓存。在另一实施例中，中央处理器2中集成的L2级缓存202可以被省略。
可选地，接口40可为现有的LLC逻辑接口。具体地，在本实施例中，接口40可由接口逻辑单元20的多个凸点21、封装基板10以及封装基板10的多个引线端口11组成。
片上网络23的一端连接接口40，片上网络23的另一端连接控制器24的一端，控制器24的另一端连接寄存器25的一端，寄存器25的另一端连接存储晶圆30。
其中，接口40用于连接中央处理器2与片上网络23，以使接口逻辑单元20根据中央处理器2的输入信息寻找片上网络23对应的节点，进而驱动该节点对应的控制器24；控制器24用于访问存储晶圆30；寄存器25用于进行数据缓冲。
具体地，寄存器25通过多个端口与存储晶圆30连接，用于数据缓冲。
当处理组件200的中央处理器2对LLC芯片1输出读写指令时，中央处理器2依次通过L1级缓存201、L2级缓存202、接口40、片上网络23、控制器24以及寄存器25对存储晶圆30进行读写操作。在一实施例中，所述读写操作行为符合缓存一致性协议，如MESI协议等。
其中，在本实施例中，存储晶圆30为DRAM(动态随机存取存储器，Dynamic Random Access Memory)晶圆，DRAM晶圆包括至少一个DRAM阵列32，接口逻辑单元20连接至少一个DRAM阵列32，以使中央处理器2进行读写操作。
其中，DRAM为易失性存储器，区别于非易失性存储器，DRAM能够更快速的进行数据访问，且数据访问延迟更低。
本实施例LLC芯片1使用易失性存储器的DRAM晶圆作为存储晶圆30，提高数据访问速度，进一步提高中央处理器2对LLC芯片1进行读写操作的速度。同时，本实施例LLC芯片1设置与存储晶圆30和控制器24连接的寄存器25，降低数据频繁切换所造成的性能损失。
结合图1-3，进一步参阅图4，图4是图1中接口逻辑单元另一实施例的结构示意图。如图4所示，区别于上述实施例，本实施例接口逻辑单元20包括多个控制器24以及多个寄存器25。
片上网络23连接多个控制器24，每一个控制器24通过一个寄存器25连接存储晶圆30。
可选地，片上网络23包括多个相互连接的路由器，以形成多个节点，每个节点连接单个控制器24，中央处理器2通过访问路由器的地址即可访问对应该 路由器的控制器24，以进行数据的读写操作。
即中央处理器2通过接口逻辑单元20输入地址，接口逻辑单元20根据地址，驱动与地址对应的节点连接的控制器24，以使中央处理器2对存储晶圆30进行读写操作。
其中，在本实施例中，中央处理器2可为两个，两个中央处理器2各自集成有L1级缓存201，两个中央处理器2共同使用L2级缓存202。其中，两个中央处理器2、两个L1级缓存201与共同使用的L2级缓存202构成处理组件200，处理组件200通过接口40连接LLC芯片1。
其中，处理组件200可通过非共享独立存储访问或共享存储访问对LLC芯片1进行读写操作。
具体地，存储晶圆30包括至少一个存储空间，处理组件200中的两个中央处理器2分别对应不同的存储空间，处理组件200通过对特定存储空间进行读写操作，以使特定的中央处理器2进行存储访问。
当LLC芯片1接收两个中央处理器2中的至少一个中央处理器2发出的读写指令时，多个中央处理器2中的至少一个中央处理器2通过接口逻辑单元20对与其对应设置的DRAM阵列32进行读写操作，即对特定存储空间进行读写操作。
可选地，两个中央处理器2可同时或单独对存储晶圆30进行读写操作，即实现LLC芯片1的非共享模式缓存数据。
可选地，在其它实施例中，LLC芯片1还可以通过共享模式进行数据缓存。具体地，处理组件200中的任一中央处理器2可通过片上网络23对存储晶圆30中的任一DRAM阵列32进行读写操作，即对存储晶圆30的任一存储空间进行读写操作。当中央处理器2对DRAM阵列32进行读写操作时，下一待运行的中央处理2无论是要对当前中央处理器2执行读写操作的DRAM阵列32进一步进行读写操作，或对另一DRAM阵列32进行读写操作，都需等当前的中央处理器2完成对应读写操作，方可访问待执行的目标DRAM阵列32，以执行读写操作。
本实施例LLC芯片1通过片上网络23连接多个控制器24，通过地址对应控制器24的方式，实现快速寻找目标控制器24，进而实现大规模高速计算。同时，本实施例LLC芯片1通过非共享模式或共享模式进行数据缓存，以使中央处理器2对目标对象DRAM阵列32进行读写操作，提高中央处理器2访问数 据的效率。
结合图1-4，进一步参阅图5，图5是本申请LLC芯片另一实施例的结构示意图。如图5所示，区别于上述实施例，本实施例可包括多个处理组件200，每一处理组件200包括至少两个中央处理器2，每一处理组件200中至少两个中央处理器2共同使用L2级缓存202，构成处理组件200，多个处理组件200通过接口40连接LLC芯片1。
具体地，每个处理组件200的访问量或访问速度不同，其所需的存储空间不同，即所需的DRAM阵列32数量不同。因此，多个处理组件200可根据需求对应连接不同数量的DRAM阵列32，作为自身对应的存储空间。
可选地，DRAM阵列32具有一定数量的行和列，对DRAM阵列32的划分可为将具有预设数量的行和列作为个体DRAM阵列32，不同处理组件200对应不同数量的个体DRAM阵列32。
或，按不同处理组件200的存储空间需求的比例，对DRAM阵列32的行数进行划分，每一处理组件200包含对应行数的DRAM阵列32。
或，按不同处理组件200的存储空间需求的比例，对DRAM阵列32的列数进行划分，每一处理组件200包含对应列数的DRAM阵列32。
可选地，在另一实施例中，处理组件200中只包含一个中央处理器2、一个L1级缓存201和一个L2级缓存202。
结合图1-5，进一步参阅图6，图6是本申请LLC芯片又一实施例的结构示意图。如图6所示，区别于上述实施例，至少两个中央处理器2共同使用L2级缓存202，构成处理组件200，至少两个处理组件200分别通过独立对应的接口40连接LLC芯片1中的控制器24、寄存器25通路，对独立对应的DRAM阵列32进行非共享独立存储访问。
具体地，LLC芯片1上包含多个接口40，每个接口40对应一个DDR存储阵列访问通道，分别通过独立的控制器24、独立的寄存器25，对应并独立访问，非共享的，存储阵列32。
控制器24中包含，DRAM阵列32的存储访问控制器(图未示)，用于建立对对应DRAM阵列32的存储访问；缓存一致性协议控制器(图未示)，用于通过片上网络23，访问DDR控制器26，进而实现对DDR存储器50(主内存)的读写操作。
多个控制器24中的缓存一致性协议控制器，还借助片上网络23实现相互 通讯，用于实现至少部分构成处理组件200之间的数据交换，以克服非共享存储结构中，多个中央处理器2之间的数据同步，完善缓存一致性协议的功能。
非共享存储结构中，每个处理组件200都能独立实现对大容量高带宽的LLC存储空间读写，可以为每个处理组件200设计独立的缓存行(cache line)，以增加缓存交换效率；还可以增加部分或全部处理组件200的缓存行位宽，以充分利用三维集成存键合的存储晶圆30的超大带宽优势。
可选地，可以设计多组DDR控制器26与片上网络23互连，用于形成多个DDR通道，分别控制多组DDR存储器50。
可选地，多个DRAM阵列32排布方式可如图7所示，图7是本申请DRAM阵列排布方式的结构示意图。
具体地，如图7(a)所示，多个DRAM阵列32可以分布在同一个存储晶圆30的不同区域。
如图7(b)所示，多个DRAM阵列32也可以分布在多个存储晶圆30上，每个存储晶圆30为一层存储晶圆层，多个DRAM阵列32分别对应分布于多个存储晶圆层。
如图7(c)所示，多个DRAM阵列32也可以分布在多个存储晶圆30上，本示意图以两个存储晶圆30为例，两个存储晶圆30在平行于存储晶圆30的平面上的投影存在部分重叠区域，则DRAM阵列32分布于该部分重叠区域。当存在多个存储晶圆30时，不同的存储晶圆30之间在平行于存储晶圆30的平面上的投影存在不同的部分重叠区域，则多个DRAM阵列32分别对应不同的存储晶圆30投影的部分重叠区域。
存储晶圆30上包含DRAM阵列32，所形成的存储容量(几百M到几十G)，较现有技术(十几M)提高2～4个数量级，足以为每组处理组件200提供独立的非共享LLC存储空间，存储容量仍远大于现有技术，大大增加LLC命中率，降低对主内存的存储访问频率。
存储晶圆30上包含DRAM阵列32，通过三维集成键合，连接LLC芯片1，互连密度极大(1微米间距，每平方毫米百万量级连接点)，可以在存储晶圆30和LLC芯片1之间建立极大的总线位宽(几千到几十万)，较现有技术(64位)提高提高2～4个数量级，拆分存储晶圆30和LLC芯片1之间建立极大的总线位宽，为至少部分或全部处理组件200提供独立的非共享LLC存储访问通道，访存带宽仍远大于现有技术。
非共享存储结构中，每个处理组件200都能独立实现对大容量高带宽的LLC存储空间读写，摆脱了共享存储LLC结构中，控制器24的总线的束缚，不用建立相互等待分时访问机制，不仅简化了控制器24的设计难度，更实现了处理组件200对大容量高带宽的LLC存储空间的并发读写，充分释放了三维集成键合的存储晶圆30的超大带宽优势。
结合图1-7，进一步参阅图8，图8是本申请LLC芯片再一实施例的结构示意图。如图8所示，区别于上述实施例，LLC芯片1包括多个存储晶圆30。可选地，存储晶圆30的数量可为2、3、4等等。
其中，多个存储晶圆30依次堆叠设置于接口逻辑单元20上，多个存储晶圆30中相邻的两个存储晶圆30通过键合的方式进行连接。
可选地，本实施例LLC芯片1的多个存储晶圆30均包含DRAM阵列32，在本实施例中，当中央处理器2采用非共享模式缓存数据时，多个中央处理器2可根据需求对存储空间的划分的具体操作，可为将单个存储晶圆30的DRAM阵列32作为个体DRAM阵列32，不同中央处理器2对应不同数量的个体DRAM阵列32，即不同中央处理器2对应不同数量的存储晶圆30。
可选地，在其它实施例中，当中央处理器2采用非共享模式缓存数据时，多个中央处理器2可根据需求对存储空间的划分的具体操作，可为将多个层叠存储晶圆30构成的存储晶圆阵列中，不同存储晶圆30的投影部分重叠的部分区域，作为个体DRAM阵列32，不同中央处理器2对应不同容量的个体DRAM阵列32，即不同中央处理器2对应存储晶圆阵列中，不同面积的投影部分重叠的部分区域。
可选地，在其它实施例中，当中央处理器2采用共享模式缓存数据时，多个中央处理器2无需对存储空间进行划分，可直接根据地址访问对应的DRAM阵列32。
本实施例LLC芯片1通过多个存储晶圆30依次堆叠，提高LLC芯片1的数据容量，并通过多个存储晶圆30之间键合的连接方式，提高数据访问的速率，实现大容量、高宽带的数据缓存。
本申请通过三维集成存储晶圆30与接口逻辑单元20，通过多个第一键合柱31与多个第二键合柱22对应设置的方式连接存储晶圆30与接口逻辑单元20，进而通过多个分布式的接口提高信号传输带宽。
其次，本申请使用易失性存储器的DRAM晶圆作为存储晶圆30，提高数据 访问的带宽和速度，进一步提高中央处理器2对LLC芯片1进行读写操作的速度。同时，本申请通过非共享模式进行数据缓存，以使中央处理器2对目标对象DRAM阵列32进行读写操作，提高中央处理器2访问数据的效率。
再次，本申请通过多个存储晶圆30依次堆叠，提高LLC芯片1的数据容量，并通过多个存储晶圆30之间键合的连接方式，提高数据访问的速率，实现大容量、高宽带的数据缓存。
本申请还提供一种LLC芯片进行读写操作的方法，其流程示意图如图9所示。请结合图1-8，参阅图9，图9是本申请LLC芯片进行读写操作的流程示意图。具体而言，本实施例的LLC芯片进行读写操作的方法可以包括以下步骤：
步骤S11：接收中央处理器输入信息。
其中，LLC芯片1接收中央处理器2通过多个引线端口11输入的信息。具体地，输入信息包括读写指令以及地址信息。当读写指令具体为写指令时，输入信号还包括待存储的数据信息。
步骤S12：根据输入信息，驱动对应的控制器。
其中，输入信息依次通过封装基板10的多个引线端口11、封装基板10以及多个凸点21传输至接口逻辑单元20，接口逻辑单元20根据输入信息所包含的地址信息找寻片上网络23中与地址信息对应的节点，进而驱动与该节点连接的控制器24；并且，输入信息中的数据信息通过控制器24暂存于寄存器25内。
步骤S13：访问DRAM阵列，以进行读写操作。
其中，当寄存器25的存储空间存储满时，中央处理器2进一步访问存储晶圆30，通过寄存器25将临时保存的数据通过端口传输至存储晶圆30所包含的DRAM阵列32，以进行读写操作。
当输入信息包含读指令时，中央处理器2通过控制器24和寄存器25读取存储于与中央处理器2对应的DRAM阵列32中的数据信息，该数据信息预存于寄存器25。当寄存器25的存储空间存储满时，寄存器25进一步将数据信息通过控制器24以及片上网络23传输至中央处理器2。
本申请还提供一种缓存系统，请参阅图10，图10是是本申请缓存系统的结构示意图。如图10所示，缓存系统50包括LLC芯片51以及多个处理组件52。其中，该LLC芯片51为上述实施例所揭示的LLC芯片1，处理组件52为上述实施例所揭示的处理组件200，在此不再赘述。
多个处理组件52分别连接LLC芯片51，以对LLC芯片51进行读写操作。 具体地，多个处理组件52可单独对LLC芯片51进行读写操作，或多个处理组件52同时对LLC芯片51进行读写操作，或多个处理组件52中的至少两个同时对LLC芯片51进行读写操作。
可选地，缓存系统50根据多个处理组件52的访问量或访问速度划分存储晶圆30的存储空间，以使每个处理组件52对对应的存储空间进行读写操作。其中，具体的划分方法如上，在此不再赘述。
可选地，在另一实施例中，多个处理组件52，被封装在同一个器件内。
以上仅为本申请的实施例，并非因此限制本申请的专利范围，凡是利用本申请说明书及附图内容所作的等效结构或等效流程变换，或直接或间接运用在其它相关的技术领域，均同理包括在本申请的专利保护范围内。

Claims (18)

  1. 一种LLC芯片，其特征在于，所述LLC芯片包括存储晶圆、接口逻辑单元和封装基板，所述接口逻辑单元与所述存储晶圆依次设置于所述封装基板上，所述存储晶圆与所述接口逻辑单元通过三维集成，并且设置于所述封装基板上，以形成所述LLC芯片；
    多个处理组件连接所述接口逻辑单元，以通过所述接口逻辑单元对所述存储晶圆进行读写操作；
    所述存储晶圆包括至少一个存储空间，多个所述处理组件对特定所述存储空间或任一所述存储空间进行读写操作，以实现非共享独立存储访问或共享存储访问；其中，所述存储晶圆的存储空间根据多个所述处理组件的访问量或访问速度划分。
  2. 根据权利要求1所述的LLC芯片，其特征在于，所述接口逻辑单元包括：
    片上网络、控制器和寄存器；
    其中，所述片上网络的一端用于连接接口，所述接口用于将所述接口逻辑单元与所述处理组件连接，所述片上网络的另一端连接所述控制器的一端，所述控制器的另一端连接所述寄存器的一端，所述寄存器的另一端连接所述存储晶圆。
  3. 根据权利要求2所述的LLC芯片，其特征在于，所述接口逻辑单元包括：多个控制器和多个寄存器；
    所述片上网络连接所述多个控制器，每一所述控制器对应连接一个寄存器，且通过所述寄存器连接所述存储晶圆。
  4. 根据权利要求3所述的LLC芯片，其特征在于，所述片上网络包括多个相互连接的路由器，以形成多个节点，每个所述节点连接一个控制器，所述处理组件通过访问所述路由器的地址，进而访问对应的路由器连接的控制器，以通过所述控制器访问与其连接的存储晶圆的存储阵列，从而进行数据读写操作。
  5. 根据权利要求1所述的LLC芯片，其特征在于，所述接口逻辑单元包括多个独立的接口、控制器以及寄存器，所述存储晶圆包括多个独立的DRAM阵列，多个独立的所述接口、所述控制器与所述寄存器形成独立访问多个所述DRAM阵列的通路，多个所述处理组件分别通过对应的所述接口连接所述通路，以对独立对应的所述DRAM阵列进行非共享独立存储访问。
  6. 根据权利要求5所述的LLC芯片，其特征在于，所述接口逻辑单元包括：
    片上网络，所述片上网络连接多个所述控制器。
  7. 根据权利要求6所述的LLC芯片，其特征在于，所述接口逻辑单元包括：
    DDR控制器，所述DDR控制器连接所述片上网络，所述DDR控制器还用于连接DDR存储器，实现对DDR存储器的读写操作。
  8. 根据权利要求5所述的LLC芯片，其特征在于，多个所述处理组件中的至少一个所述处理组件通过所述通路对与其对应设置的所述DRAM阵列进行读写操作。
  9. 根据权利要求1所述的LLC芯片，其特征在于，所述存储晶圆包括至少一个DRAM晶圆，多个所述DRAM阵列分布于同一所述DRAM晶圆的不同区域；或，多个所述DRAM阵列分布于多个所述存储晶圆，对应多个所述存储晶圆层或多个所述存储晶圆的投影重叠区域。
  10. 根据权利要求1所述的LLC芯片，其特征在于，所述存储晶圆还包括多个第一键合柱，所述接口逻辑单元还包括多个第二键合柱和多个凸点，所述封装基板包括多个引线端口，
    每个所述第一键合柱与对应的所述第二键合柱连接，以使所述存储晶圆连接所述接口逻辑单元，所述接口逻辑单元通过多个所述凸点连接所述封装基板，所述封装基板通过多个所述引线端口连接多个所述处理组件。
  11. 根据权利要求7所述的LLC芯片，其特征在于，所述控制器包括缓存一致性协议控制器，所述缓存一致性协议控制器通过所述片上网络访问所述DDR控制器，以实现对所述DDR存储器的读写操作。
  12. 根据权利要求11所述的LLC芯片，其特征在于，多个所述控制器的缓存一致性协议控制器通过所述片上网络相互通讯。
  13. 根据权利要求1所述的LLC芯片，其特征在于，所述LLC芯片包括多个所述存储晶圆，多个所述存储晶圆依次堆叠设置于所述接口逻辑单元上，多个所述存储晶圆中相邻的两个所述存储晶圆通过键合的方式进行连接。
  14. 根据权利要求1所述的LLC芯片，其特征在于，所述LLC芯片还包括接口，所述接口连接所述接口逻辑单元，且所述接口用于连接所述处理组件。
  15. 一种缓存系统，其特征在于，包括：
    LLC芯片；
    处理组件；每个所述处理组件包括至少两个中央处理器、至少两个L1级缓存与一个L2级缓存，多个所述处理组件连接所述LLC芯片，以进行读写操作；
    所述LLC芯片包括存储晶圆、接口逻辑单元和封装基板，所述接口逻辑单元与 所述存储晶圆依次设置于所述封装基板上，所述存储晶圆与所述接口逻辑单元通过三维集成，并且设置于所述封装基板上，以形成所述LLC芯片；
    多个处理组件连接所述接口逻辑单元，以通过所述接口逻辑单元对所述存储晶圆进行读写操作；
    所述存储晶圆包括至少一个存储空间，多个所述处理组件对特定所述存储空间或任一所述存储空间进行读写操作，以实现非共享独立存储访问或共享存储访问；其中，所述存储晶圆的存储空间根据多个所述处理组件的访问量或访问速度划分。
  16. 根据权利要求15所述的LLC芯片，其特征在于，所述LLC芯片还包括接口，所述接口连接所述接口逻辑单元，且所述接口连接所述处理组件。
  17. 根据权利要求15所述的LLC芯片，其特征在于，所述缓存系统包括多个处理组件，每一所述处理组件包括至少两个中央处理器。
  18. 一种LLC芯片的读写方法，其特征在于，所述方法包括：
    接收中央处理器输入信息；
    根据输入信息，驱动对应的控制器；
    访问DRAM阵列，以进行读写操作。
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