WO2023029491A1 - 面板阵列短路检测方法、装置、电子设备及存储介质 - Google Patents
面板阵列短路检测方法、装置、电子设备及存储介质 Download PDFInfo
- Publication number
- WO2023029491A1 WO2023029491A1 PCT/CN2022/086952 CN2022086952W WO2023029491A1 WO 2023029491 A1 WO2023029491 A1 WO 2023029491A1 CN 2022086952 W CN2022086952 W CN 2022086952W WO 2023029491 A1 WO2023029491 A1 WO 2023029491A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- feature
- defect
- characteristic
- feature area
- area
- Prior art date
Links
- 238000001514 detection method Methods 0.000 title claims abstract description 45
- 230000007547 defect Effects 0.000 claims abstract description 142
- 238000000034 method Methods 0.000 claims abstract description 41
- 230000000737 periodic effect Effects 0.000 claims description 18
- 230000002950 deficient Effects 0.000 claims description 17
- 238000004590 computer program Methods 0.000 claims description 11
- 230000000295 complement effect Effects 0.000 claims description 3
- 230000008569 process Effects 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 6
- 238000005516 engineering process Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 9
- 238000004519 manufacturing process Methods 0.000 description 6
- 230000006870 function Effects 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 3
- 238000013473 artificial intelligence Methods 0.000 description 3
- 238000007689 inspection Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001788 irregular Effects 0.000 description 1
- 238000010801 machine learning Methods 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Images
Definitions
- the present application relates to the field of data processing technology, in particular to a panel array short circuit detection method, device, electronic equipment and storage medium.
- ADC artificial intelligence automatic defect classification system
- the panel manufacturing process usually includes thin film transistor (thin Film Transistor, TFT) panel production, color filter (Color Filter, CF) production, board combination (Cell) and modules and other processes.
- TFT thin Film Transistor
- CF color filter
- Cell board combination
- artificial intelligence is also widely used in panel production.
- the target detection model is a commonly used method in the panel quality inspection process. It can identify the type of residual defects formed during the etching process of the array panel, but it cannot accurately determine whether the type of the defect is a short circuit.
- the purpose of the present application includes providing a panel array short circuit detection method, device, electronic equipment and storage medium, which can improve the problem in the prior art that it is impossible to accurately determine whether the type of defect formed during the etching process of the array panel identified is a short circuit .
- the present application provides a panel array short circuit detection method, which adopts the following technical solution:
- a panel array short circuit detection method comprising:
- the defect feature area, good feature area and feature points of the good feature area of the panel image to be tested are obtained;
- the defect feature area, the good feature area and the feature points of the good feature area of the panel image to be tested are obtained, and based on the position of the defect feature area, the reference points associated with it are obtained, and then according to The number of intersections between the characteristic units corresponding to the reference point and the defect characteristic region is used to determine whether the defect type of the defect characteristic region is a short circuit, thereby improving the array panel etching process that cannot be accurately judged and identified in the prior art to a certain extent. It is a matter of whether the type of defect formed is a short circuit.
- the good feature area includes a first feature area and a second feature area
- the step of using the feature area of the non-defective feature unit as the reference feature area and using the target detection model to obtain the defect feature area, the good feature area and the feature points of the good feature area of the panel image to be tested includes:
- the identified first characteristic regions complement the unidentified second characteristic regions, so as to determine all good characteristic regions of the image of the panel to be tested, and determine all good characteristic regions Feature points.
- the arrangement period of the feature unit is determined, and then according to the arrangement period, it is possible to make up for defects that cannot be identified by the target detection model.
- the second feature area that is, the feature area covered by the defect feature area, to obtain a good feature area of the image of the panel to be tested.
- the step of determining the arrangement period of the characteristic units according to the identified first characteristic region and the specifications of the panel to be tested includes:
- the average value of the total length of the interval is obtained to obtain the arrangement period of the characteristic units.
- the first arrangement period obtained from the specifications of the panel to be tested determine the period rule, and then obtain the total interval length of the first characteristic region according to the adjacent first characteristic regions satisfying the period rule, so as to obtain The average value can be used to obtain the arrangement period of the characteristic units, and the combination of the specifications of the panel to be tested and the actually detected first characteristic area can make the arrangement period obtained more accurate.
- the periodic rule includes a periodic rule in the direction of the horizontal axis and a periodic rule in the direction of the vertical axis;
- X i+1 represents the abscissa of the i+1th characteristic unit in the horizontal axis direction
- Y i+1 represents the vertical coordinate of the i+1th characteristic unit in the vertical axis direction
- X i represents the i-th feature in the horizontal axis direction
- the abscissa of the unit Y i represents the ordinate of the i-th characteristic unit in the direction of the vertical axis
- T rx represents the first arrangement period in the direction of the abscissa
- T ry represents the first arrangement period in the direction of the vertical axis.
- the intervals of the first characteristic regions that meet the periodic rule are selected within a reasonable range, thereby helping to improve the accuracy of the arrangement cycle of the characteristic units.
- the total length of the interval includes the total length of the interval in the direction of the horizontal axis and the total length of the interval in the direction of the vertical axis;
- the total length of the interval in the direction of the transverse axis is:
- the total length of the interval in the direction of the vertical axis is:
- N X represents the number of adjacent first characteristic regions in the horizontal axis direction
- V X represents the total length of the interval between adjacent first characteristic regions in the horizontal axis direction
- N Y represents the number of adjacent first characteristic regions in the vertical axis direction
- V Y represents the total length of intervals between adjacent first feature regions in the direction of the vertical axis.
- the total length of the interval in the direction of the horizontal axis and the direction of the vertical axis can be quickly calculated.
- the characteristic point associated with the defect characteristic region is determined as a reference point, and the reference point is constructed based on the specification specified by the characteristic unit.
- the steps of the feature unit corresponding to the point include:
- each defect characteristic region For each defect characteristic region, according to the position of the defect characteristic region, obtain the characteristic point of the good characteristic region adjacent to and/or intersecting with the defect characteristic region, using the characteristic point as a reference point;
- the feature unit with the reference point as the center point is drawn.
- the feature points of the good feature areas intersecting or adjacent to the defect feature area are used as reference points, and then the feature units are drawn with the reference point as the center point, so that the correlation with the defect feature area can be obtained feature unit.
- the steps of taking this feature point as a reference point include:
- the feature points of the intersecting good feature area and the feature points of the adjacent good feature areas around the defect feature area are used as reference points;
- the feature points of the good feature areas adjacent to the defective feature area are used as reference points.
- the reference point can be quickly determined according to the positional relationship between the defective characteristic area and the good characteristic area.
- the detection of the number of intersections of the feature units corresponding to the reference point associated with the defect feature area is based on the number of intersections to determine the defect of the defect feature area Steps for whether the type is short circuit, including:
- the number of intersections between the defect feature area and the feature unit corresponding to the reference point associated with the defect feature area is obtained ;
- the defect type of the defect characteristic region is a short circuit according to the number of intersections of the characteristic units corresponding to the defect characteristic region and the reference point.
- the present application provides a panel array short circuit detection device, which adopts the following technical solution:
- a panel array short circuit detection device comprising:
- the identification module is used to use the feature area of the non-defective feature unit as the reference feature area, and use the target detection model to obtain the defect feature area, the good feature area and the feature points of the good feature area of the panel image to be tested;
- a processing module configured to determine the feature point associated with the defect feature area as a reference point according to the position of the defect feature area, and construct a feature unit corresponding to the reference point based on the specification specified by the feature unit;
- a judging module configured to detect the number of intersections between the defect feature area and the feature units corresponding to the associated reference points, and judge whether the defect type of the defect feature area is a short circuit based on the number of intersections.
- the present application provides an electronic device, which adopts the following technical solution:
- An electronic device includes: a memory, a processor, and a computer program stored on the memory and operable on the processor, and the processor implements the method described in the first aspect when executing the computer program.
- the present application provides a storage medium, adopting the following technical solution:
- a storage medium includes a computer program, and when the computer program runs, the electronic device where the storage medium is located is controlled to execute the method described in the first aspect.
- the panel array short-circuit detection method uses the target detection model to obtain the defect feature area, good feature area, and feature points of the good feature area of the panel image to be tested, and based on the position of the defect feature area, obtain the reference associated with it point, and then according to the intersection number of the feature unit corresponding to the reference point and the defect feature area, determine whether the defect type of the defect feature area is a short circuit, so as to improve the array that cannot be accurately judged and identified in the prior art to a certain extent It is a question of whether the type of defect formed during panel etching is a short.
- FIG. 1 is a structural block diagram of an electronic device provided in an embodiment of the present application.
- FIG. 2 is a schematic flowchart of a method for detecting a short circuit in a panel array.
- FIG. 3 is a schematic flowchart of a sub-step of step S100 in FIG. 2 .
- FIG. 4 is a schematic flowchart of a sub-step of step S120 in FIG. 3 .
- FIG. 5 is a schematic flowchart of a sub-step of step S200 in FIG. 2 .
- FIG. 6 is a schematic flowchart of a sub-step of step S210 in FIG. 5 .
- FIG. 7 is a schematic flowchart of a sub-step of step S300 in FIG. 2 .
- FIG. 8 is a structural block diagram of a panel array short circuit detection device.
- the electronic device 01 may include but not limited to a memory 03 and a processor 02 .
- both the processor 02 and the memory 03 are located in the electronic device 01 but are set separately.
- the memory 03 can be replaced by a storage medium, and both the memory 03 and the storage medium can be independent from the electronic device 01 and can be accessed by the processor 02 through the bus interface.
- the memory 03 may be integrated into the processor 02, for example, may be a cache and/or a general register.
- both the storage medium and the memory 03 can be used to store computer programs, and when the processor 02 executes the computer programs, the panel array short circuit detection method given in the embodiments of the present application can be realized.
- the electronic device 01 shown in FIG. 1 is a schematic structural diagram, and the electronic device 01 may also include more or fewer components than those shown in FIG. 1 , or have a configuration different from that shown in FIG. 1 .
- Each component shown in Fig. 1 may be implemented by hardware, software or a combination thereof.
- the electronic device 01 may be, but not limited to, a computer, a mobile phone, an IPad, a server, a notebook computer, a mobile Internet access device, and the like.
- a method for detecting a panel array short circuit including the following steps.
- Step S100 using the feature area of the non-defective feature unit as the reference feature area, using the target detection model, to obtain the defect feature area, the good feature area and the feature points of the good feature area of the panel image to be tested.
- Step S200 according to the position of the defect characteristic region, determine the characteristic point associated with the defect characteristic region as a reference point, and construct the characteristic unit corresponding to the reference point based on the specification specified by the characteristic unit.
- Step S300 detecting the number of intersections between the defect feature area and the feature units corresponding to the associated reference point, and judging whether the defect type of the defect feature area is a short circuit based on the number of intersections.
- the target detection model is used to obtain the defect feature area, the good feature area and the feature points of the good feature area of the panel image to be tested, and based on the position of the defect feature area, the reference point associated with it is obtained, Then, according to the intersection number of the characteristic unit corresponding to the reference point and the defect characteristic region, it is determined whether the defect type of the defect characteristic region is a short circuit, thereby improving the array panel etching that cannot be accurately judged and identified in the prior art to a certain extent. It is a matter of whether the type of defect formed in the process is a short circuit.
- the good feature area includes a first feature area and a second feature area.
- the first feature area is identified by the target detection model using the feature area of the non-defective feature unit as the reference feature area, that is, the first feature area is consistent with the reference feature area, and is a defect-free feature on the panel to be tested area.
- the second feature area is an area that cannot be identified by the target detection model, and is an area that cannot be identified due to defects, that is, the second feature area is an area covered by the defect feature area.
- step S100 includes the following sub-steps.
- Step S110 taking the feature area of the feature unit without defects in the panel array image as the reference feature area, using the image of the reference feature area as the reference detection feature of the target detection model, detecting the image of the panel to be tested, and identifying the image of the panel to be tested Defect feature area and first feature area.
- the panel array image may be a detected image.
- Step S120 according to the identified first characteristic area and the specification of the panel to be tested, determine the arrangement period of the characteristic units.
- Step S130 according to the layout cycle and the identified first feature area, complement the unrecognized second feature area, so as to determine all good feature areas of the panel image to be tested, and determine the feature points of all good feature areas.
- the arrangement cycle of the feature units can be determined, and then the second feature area that cannot be recognized by the target detection model due to defects can be filled according to the arrangement cycle. That is, the characteristic region covered by the defect characteristic region, so as to obtain a good characteristic region of the image of the panel to be tested.
- the target detection model is trained by using a machine learning algorithm, taking a large number of panel array images as input, and using the feature area of the defect-free feature unit as the learning target.
- step S120 includes the following sub-steps.
- step S121 according to the specifications of the panel to be tested, the first arrangement period of the characteristic units in the horizontal axis direction and the vertical axis direction is estimated, and the period rule is obtained according to the first arrangement period.
- the specification of the panel to be tested includes the length and width of the panel to be tested, and the total number of characteristic units in the length direction and the total number of characteristic units in the width direction.
- the first arrangement period in the vertical axis direction can be obtained.
- the number of intervals of the characteristic units in the length direction is equal to the value obtained by subtracting one from the total number of characteristic units in the length direction. For example, if the total number of characteristic units is N, the number of intervals is N-1.
- the first arrangement period in the horizontal axis direction can be obtained.
- Step S122 according to the period rule, obtain the adjacent first feature regions satisfying the period rule, and obtain the total distance between the adjacent first feature regions according to the feature point coordinates of the adjacent first feature regions.
- Step S123 according to the total length of the interval and the number of the adjacent first characteristic regions, average the total length of the interval to obtain the arrangement period of the characteristic units.
- the periodic rule obtained according to the specifications of the panel to be tested is used as the condition for selecting the first characteristic region, and the first characteristic region satisfying the periodic rule is selected to calculate the total length of the interval, and then the average value of the total length of the interval is obtained to obtain the rank of the characteristic unit.
- the arrangement period of the characteristic units is based on the specifications of the panel to be tested, so that the obtained arrangement period of the characteristic units can be more accurate.
- the periodic rules include periodic rules in the direction of the horizontal axis and periodic rules in the direction of the vertical axis.
- the periodic rule in the direction of the horizontal axis is:
- X i+1 indicates the abscissa of the i+1th characteristic unit in the horizontal axis direction
- Y i+1 indicates the ordinate of the i+1th characteristic unit in the vertical axis direction
- Xi i indicates the i+1th characteristic unit in the horizontal axis direction
- the abscissa of the i characteristic unit, Y i represents the ordinate of the i-th characteristic unit in the direction of the vertical axis
- T rx represents the first arrangement period in the direction of the abscissa
- T ry represents the first arrangement period in the direction of the vertical axis.
- the total length of the interval includes the total length of the interval along the horizontal axis and the total length of the interval along the vertical axis.
- the total length of the interval in the direction of the horizontal axis is:
- the total length of intervals along the vertical axis is:
- N X represents the number of adjacent first characteristic regions in the horizontal axis direction
- V X represents the total length of the interval between adjacent first characteristic regions in the horizontal axis direction
- N Y represents the number of adjacent first characteristic regions in the vertical axis direction
- V Y represents the total length of intervals between adjacent first feature regions in the direction of the vertical axis.
- step S122 and step S123 it should be understood that when there are multiple groups of adjacent first characteristic regions satisfying the periodic rule, the total length of intervals between each group of adjacent first characteristic regions can be calculated first, and then the multi-group The total length of group intervals is added and divided by the total number of intervals to obtain the arrangement period of the characteristic units. It is also possible to firstly calculate the average interval value of each group of adjacent first characteristic regions, and then add the average interval values of multiple groups of adjacent first characteristic regions and take the average value to obtain the total interval length of the characteristic units.
- FIG. 5 it is a schematic flowchart of the sub-steps of step S200, including the following steps.
- Step S210 for each defect characteristic region, according to the position of the defect characteristic region, obtain the characteristic point of the good characteristic region adjacent to and/or intersecting with the defect characteristic region, and use the characteristic point as a reference point.
- Step S220 draw the characteristic unit with the reference point as the center point according to the specification specified by the characteristic unit.
- the specification specified by the characteristic unit is the specification of the characteristic unit of the panel to be tested.
- the feature unit can be in regular shape or irregular shape. With the reference point as the center point, points are drawn around the reference point to draw multiple points centered on the reference point, and finally the points are connected, that is The feature unit with the reference point as the center point can be obtained. Specifically, the number of points when point drawing can be set according to the shape of the feature unit.
- center point in the reference point as the center point is only a name, not a limitation on its position and features.
- FIG. 6 it is a schematic flowchart of the sub-steps of step S210.
- Step S211 for each defect characteristic region, judge whether there is a good characteristic region intersecting the defect characteristic region according to the position of the defect characteristic region.
- Step S212 the feature points of the intersecting good feature area and the feature points of the adjacent good feature areas around the defective feature area are used as reference points.
- Step S213 taking the feature points of the good feature areas adjacent to the defective feature area as reference points.
- intersection includes partial intersection and coincidence.
- FIG. 7 it is a schematic flowchart of the sub-steps of step S300.
- Step S310 for each defect characteristic region, based on the position of the characteristic unit corresponding to the reference point associated with the defect characteristic region, the number of intersections between the defect characteristic region and the characteristic units corresponding to the associated reference point is obtained.
- Step S320 judging whether the number of intersections is at least two, and if so, judging that the defect type of the defect feature region is a short circuit.
- the intersection area can form a short circuit, and therefore, the defect type of the defect feature area includes a short circuit.
- step S310 and step S320 if there are two or more reference points associated with the defect feature area, then separately calculate the number of intersections between the feature units corresponding to each reference point and the defect feature area, once there is If the number of intersections between a characteristic unit and defect characteristic region is at least two, then the defect type of the curved characteristic region is a short circuit.
- FIGS. 2-7 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily performed at the same time, but may be performed at different times. These sub-steps or The execution sequence of the stages is not necessarily sequential, but may be executed alternately or alternately with other steps or substeps of other steps or at least a part of stages.
- the present application also provides a panel array short circuit detection device 07 , which includes an identification module 04 , a processing module 05 and a judging module.
- the recognition module 04 is used to use the feature area of the non-defective feature unit as the reference feature area, and use the target detection model to obtain the feature points of the defect feature area, good feature area and good feature area of the panel image to be tested.
- the processing module 05 is used to determine the feature point associated with the defect feature area as a reference point according to the position of the defect feature area, and construct a feature unit corresponding to the reference point based on the specification specified by the feature unit.
- the judging module 06 is used to detect the number of intersections between the defect feature area and the feature units corresponding to the associated reference point, and judge whether the defect type of the defect feature area is a short circuit based on the number of intersections.
- Each module in the above-mentioned clock acceleration synchronization device can be fully or partially realized by software, hardware and a combination thereof.
- the above-mentioned modules can be embedded in or independent of the processor 02 in the computer device in the form of hardware, and can also be stored in the memory 03 in the electronic device 01 in the form of software, so that the processor 02 can call and execute the corresponding operations of the above modules .
- each block in a flowchart or block diagram may represent a module, program segment, or part of code that includes one or more Executable instructions. It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures.
- each block of the block diagrams and/or flowchart illustrations, and combinations of blocks in the block diagrams and/or flowchart illustrations can be implemented by a dedicated hardware-based system that performs the specified function or action , or may be implemented by a combination of dedicated hardware and computer instructions.
- each functional module in each embodiment of the present disclosure may be integrated together to form an independent part, each module may exist independently, or two or more modules may be integrated to form an independent part.
- the functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium.
- the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, an electronic device 01, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
- the aforementioned storage media include: U disk, mobile hard disk, read-only memory 03 (ROM, Read-Only Memory), random access memory 03 (RAM, Random Access Memory), magnetic disk or optical disc, etc. can store program codes medium.
- the terms "comprising”, “comprising” or any other variation thereof are intended to cover a non-exclusive inclusion such that a process, method, article or apparatus comprising a set of elements includes not only those elements, It also includes other elements not expressly listed, or elements inherent in the process, method, article, or apparatus. Without further limitations, an element defined by the phrase “comprising a " does not exclude the presence of additional identical elements in the process, method, article or apparatus comprising said element.
Landscapes
- Liquid Crystal (AREA)
- Image Processing (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
Abstract
本申请提供一种面板阵列短路检测方法、装置、电子设备及存储介质，属于数据处理技术的领域，方法包括：以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及其特征点，进而根据缺陷特征区域的位置，确定出与缺陷特征区域有关联的特征点作为参考点，基于特征单元规定的规格，构建参考点对应的特征单元，基于此，检测出缺陷特征区域与其所关联的参考点对应的特征单元的交集个数，并基于交集个数，判断缺陷特征区域的缺陷类型是否为短路，从而能够改善现有技术中无法准确判断识别到的阵列面板蚀刻过程中形成的缺陷的类型是否为短路的问题。
Description
相关申请的交叉引用
本申请要求于2021年09月02日提交中国专利局的申请号为CN202111023791.6、名称为“面板阵列短路检测方法、装置、电子设备及存储介质”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
本申请涉及数据处理技术的领域，尤其是涉及一种面板阵列短路检测方法、装置、电子设备及存储介质。
工业制造过程中，因工艺波动、机台差异等因素，会产生各种各样形态的缺陷，若采用人工识别的方法，对产品缺陷进行识别分类，则需要大量的人力，使得人力成本过高。基于人力成本过高的考虑，现今，越来越多的电子制造商开始采用人工智能自动缺陷分类系统(ADC)来代替人力进行缺陷分类。
在面板生产制造行业内，面板的制造生产过程通常包括薄膜晶体管(thin Film Transistor，TFT)面板生产、彩色滤光片(Color Filter，CF)生产、板对合(Cell)和模组等流程。目前，人工智能也在面板生产中大量使用，在面板质检过程中，已经开始采用人工智能检测的方法。采用目标检测模型是面板质检过程中常用的手段，其能够识别阵列面板蚀刻过程中形成的残留缺陷的类型，但是无法准确判断该缺陷的类型是否为短路。
发明内容
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施方式，并配合所附附图，作详细说明如下。
本申请的目的包括，提供一种面板阵列短路检测方法、装置、电子设备及存储介质，能够改善现有技术中无法准确判断识别到的阵列面板蚀刻过程中形成的缺陷的类型是否为短路的问题。
第一方面，本申请提供一种面板阵列短路检测方法，采用如下的技术方案：
一种面板阵列短路检测方法，所述方法包括：
以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点；
根据所述缺陷特征区域的位置，确定出与所述缺陷特征区域有关联的所述特征点作为参考点，基于特征单元规定的规格，构建所述参考点对应的特征单元；
检测出所述缺陷特征区域与其所关联的所述参考点对应的特征单元的交集个数，基于所述交集个数，判断所述缺陷特征区域的缺陷类型是否为短路。
通过采用上述技术方案，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点，并基于缺陷特征区域的位置，得到与其有关联的参考点，进而根据参考点所对应的特征单元与缺陷特征区域的交集个数，来确定缺陷特征区域的缺陷类型是否为短路，从而在一定程度上能够改善现有技术中无法准确判断识别到的阵列面板蚀刻过程中形成的缺陷的类型是否为短路的问题。
在一种可行的实施方式中，所述良好特征区域包括第一特征区域和第二特征区域；
所述以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点的步骤，包括：
以面板阵列图像中无缺陷的特征单元的特征区域为参考特征区域，将所述参考特征区域的图像作为目标检测模型的参考检测特征，对待测面板图像进行检测，识别出所述待测面板图像的缺陷特征区域和第一特征区域；
根据识别出的所述第一特征区域以及待测面板的规格，确定特征单元的排布周期；
根据所述排布周期，以及识别出的所述第一特征区域，补齐未识别出的第二特征区域，以确定所述待测面板图像所有的良好特征区域，并确定所有良好特征区域的特征点。
通过采用上述技术方案，根据目标检测模型检测出的第一特征区域和待测面板的规格，确定特征单元的排布周期，进而能够根据排布周期，补齐因缺陷导致目标检测模型无法识别出的第二特征区域，即缺陷特征区域所覆盖的特征区域，以得到待测面板图像的良好特征区域。
在一种可行的实施方式中，所述根据识别出的所述第一特征区域以及待测面板的规格，确定特征单元的排布周期的步骤，包括：
根据所述待测面板的规格，估计出特征单元在横轴方向和竖轴方向的第一排布周期，根据所述第一排布周期得到周期规则；
根据所述周期规则，得到相邻且满足所述周期规则的所述第一特征区域，根据该相邻的第一特征区域的特征点坐标，得到该相邻的第一特征区域的间隔总长；
根据所述间隔总长，以及该相邻的第一特征区域数量，对所述间隔总长取平均值，得到特征单元的排布周期。
通过采用上述技术方案，根据待测面板的规格所得到的第一排布周期，确定周期规则，进而根据满足周期规则的相邻的第一特征区域，得到第一特征区域的间隔总长，从而取平均值就能够得到特征单元的排布周期，采用待测面板的规格与实际检测出的第一特征区域相结合的方式，能够使得到的排布周期更为准确。
在一种可行的实施方式中，所述周期规则包括横轴方向的周期规则和竖轴方向的周期规则；
所述横轴方向的周期规则为：
所述竖轴方向的周期规则为：
其中，X
i+1示横轴方向第i+1个特征单元的横坐标，Y
i+1表示竖轴方向第i+1个特征单元的纵坐标，X
i表示横轴方向第i个特征单元的横坐标，Y
i表示竖轴方向第i个特征单元的纵坐标，T
rx表示横轴方向的第一排布周期，T
ry表示竖轴方向的第一排布周期。
通过采用上述技术方案，通过周期规则，使筛选出的满足周期规则的第一特征区域的间隔在合理范围内，从而有助于提高特征单元的排布周期的准确度。
在一种可行的实施方式中，所述间隔总长包括横轴方向的间隔总长和竖轴方向的间隔总长；
所述横轴方向的间隔总长为：
所述竖轴方向的间隔总长为：
其中，N
X表示横轴方向相邻的第一特征区域的数量，V
X表示横轴方向的相邻的第一特征区域的间隔总长，N
Y表示竖轴方向相邻的第一特征区域的数量，V
Y表示竖轴方向相邻的第一特征区域的间隔总长。
通过采用上述技术方案，采用上述两个公式，能够快速计算出横轴方向和竖轴方向的间隔总长。
在一种可行的实施方式中，所述根据所述缺陷特征区域的位置，确定出与所述缺陷特征区域有关联的所述特征点作为参考点，基于特征单元规定的规格，构建所述参考点对应的特征单元的步骤，包括：
针对每个所述缺陷特征区域，根据该缺陷特征区域的位置，得到与所述缺陷特征区域相邻和/或相交的所述良好特征区域的特征点，以该特征点为参考点；
根据特征单元规定的规格，描绘出以所述参考点为中心点的特征单元。
通过采用上述技术方案，将与缺陷特征区域相交或相邻的良好特征区域的特征点，作为参考点，进而以参考点为中心点描绘出特征单元，从而能够得到与缺陷特征区域相关性较大的特征单元。
在一种可行的实施方式中，所述针对每个所述缺陷特征区域，根据该缺陷特征区域的位置，得到与所述缺陷特征区域相邻和/或相交的所述良好特征区域的特征点，以该特征点为参考点的步骤，包括：
针对每个所述缺陷特征区域，根据该缺陷特征区域的位置，判断所述是否有良好特征区域与该缺陷特征区域相交；
若是，则将该相交的良好特征区域的特征点，以及该缺陷特征区域四周相邻的良好特征区域的特征点作为参考点；
否则，将该缺陷特征区域四周相邻的良好特征区域的特征点作为参考点。
通过采用上述技术方案，根据缺陷特征区域与良好特征区域的位置关系能够快速确定参考点。
在一种可行的实施方式中，所述检测出所述缺陷特征区域与其有关联的所述参考点对应的特征单元的交集个数，基于所述交集个数，判断所述缺陷特征区域的缺陷类型是否为短路的步骤，包括：
针对每个所述缺陷特征区域，基于与该缺陷特征区域有关联的所述参考点对应的特征单元的位置，得到该缺陷特征区域与其所关联的所述参考点对应的特征单元的交集个数；
判断所述交集个数是否至少为两个，若是，则判定该缺陷特征区域的缺陷类型为短路。
通过采用上述技术方案，根据缺陷特征区域与参考点对应的特征单元的交集个数， 能够确定缺陷特征区域的缺陷类型是否为短路。
第二方面，本申请提供一种面板阵列短路检测装置，采用如下的技术方案：
一种面板阵列短路检测装置，包括：
识别模块，用于以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点；
处理模块，用于根据所述缺陷特征区域的位置，确定出与所述缺陷特征区域有关联的所述特征点作为参考点，基于特征单元规定的规格，构建所述参考点对应的特征单元；
判定模块，用于检测出所述缺陷特征区域与其所关联的所述参考点对应的特征单元的交集个数，基于所述交集个数，判断所述缺陷特征区域的缺陷类型是否为短路。
第三方面，本申请提供一种电子设备，采用如下的技术方案：
一种电子设备，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现第一方面所述的方法。
第四方面，本申请提供一种存储介质，采用如下的技术方案：
一种存储介质，所述存储介质包括计算机程序，所述计算机程序运行时控制所述存储介质所在的电子设备执行第一方面所述的方法。
本申请实施方式的有益效果包括，例如：
本申请提供的面板阵列短路检测方法，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点，并基于缺陷特征区域的位置，得到与其有关联的参考点，进而根据参考点所对应的特征单元与缺陷特征区域的交集个数，来确定缺陷特征区域的缺陷类型是否为短路，从而在一定程度上能够改善现有技术中无法准确判断识别到的阵列面板蚀刻过程中形成的缺陷的类型是否为短路的问题。
为了更清楚地说明本公开的技术方案，下面将对实施方式中所需要使用的附图作简单地介绍，应当理解，以下附图仅示出了本公开的某些实施方式，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1为本申请实施方式提供的电子设备的结构框图。
图2为面板阵列短路检测方法的流程示意图。
图3为图2中步骤S100的一种子步骤的流程示意图。
图4为图3中步骤S120的一种子步骤的流程示意图。
图5为图2中步骤S200的一种子步骤的流程示意图。
图6为图5中步骤S210的一种子步骤的流程示意图。
图7为图2中步骤S300的一种子步骤的流程示意图。
图8为面板阵列短路检测装置的结构框图。
附图标记说明：01-电子设备；02-处理器；03-存储器；04-识别模块；05-处理模块；06-判定模块；07-面板阵列短路检测装置。
为使本申请实施方式的目的、技术方案和优点更加清楚，下面将结合本申请实施方式中的附图，对本申请实施方式中的技术方案进行清楚、完整的描述，显然，所描述的实施方式是本申请一部分实施方式，而不是全部的实施方式。通常在此处附图中描述和示出的本申请实施方式的组件可以以各自不同的配置来布置和设计。
因此，以下对在附图中提供的本申请的实施方式的详细描述并非旨在限制要求保护的本申请的范围，而是仅仅表示本申请的选定实施方式。基于本申请中的实施方式，本领域普通技术人员在没有做出创造性劳动前提下获得的所有其他实施方式，都属于本申请保护的范围。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。此外，若出现术语“第一”、“第二”等仅用于区分描述，而不能理解为指示或暗示相对重要性。
参照图1，为本申请实施方式提供的一种电子设备的方框结构示意图，该电子设备01可以包括但不限于存储器03和处理器02。
其中，处理器02和存储器03均位于电子设备01中却二者分离设置。然而，应当理解的是，存储器03可以替换成存储介质，且存储器03和存储介质都可以是独立于电子设备01之外，且可以由处理器02通过总线接口来访问。此外，存储器03可以集成到处理器02中，例如，可以是高速缓存和/或通用寄存器。
在本实施方式中，存储介质和存储器03均可用于存储计算机程序，处理器02执行计算机程序时，能够实现本申请实施方式给出的面板阵列短路检测方法。
需要说明的是，图1所示的电子设备01的结构示意图，电子设备01还可以包括比图1中所示更多或更少的组件，或者具有与图1所示不同的配置。图1中所示的各组件可以采用硬件、软件或其组合实现。电子设备01可以是，但不限于计算机、手机、IPad、服务器、笔记本电脑、移动上网设备等。
在一种实施方式中，如图2所示，提供了一种面板阵列短路检测方法，包括如下步骤。
步骤S100，以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点。
步骤S200，根据缺陷特征区域的位置，确定出与缺陷特征区域有关联的特征点作为参考点，基于特征单元规定的规格，构建参考点对应的特征单元。
步骤S300，检测出缺陷特征区域与其所关联的参考点对应的特征单元的交集个数，基于交集个数，判断缺陷特征区域的缺陷类型是否为短路。
上述面板阵列短路检测方法中，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点，并基于缺陷特征区域的位置，得到与其有关联的参考点，进而根据参考点所对应的特征单元与缺陷特征区域的交集个数，来确定缺陷特征区域的缺陷类型是否为短路，从而在一定程度上能够改善现有技术中无法准确判断识别到的阵列面板蚀刻过程中形成的缺陷的类型是否为短路的问题。
进一步的，良好特征区域包括第一特征区域和第二特征区域。
其中，第一特征区域是目标检测模型以无缺陷特征单元的特征区域作为参考特征区域，而识别出的，即第一特性区域是与参考特征区域一致的，是待测面板上无缺陷的特征区域。而第二特征区域是目标检测模型无法识别出的区域，是因缺陷导致的无法识别出的区域，即第二特征区域为缺陷特征区域所覆盖的区域。
在一种实施方式中，如图3所示，步骤S100包括如下子步骤。
步骤S110，以面板阵列图像中无缺陷的特征单元的特征区域为参考特征区域，将参考特征区域的图像作为目标检测模型的参考检测特征，对待测面板图像进行检测，识别出待测面板图像的缺陷特征区域和第一特征区域。
其中，面板阵列图像可以为已检测过的图像。
步骤S120，根据识别出的第一特征区域以及待测面板的规格，确定特征单元的排布周期。
步骤S130，根据排布周期，以及识别出的第一特征区域，补齐未识别出的第二特征区域，以确定待测面板图像所有的良好特征区域，并确定所有良好特征区域的特征点。
根据目标检测模型检测出的第一特征区域和待测面板的规格，确定特征单元的排布周期，进而能够根据排布周期，补齐因缺陷导致目标检测模型无法识别出的第二特征区域，即缺陷特征区域所覆盖的特征区域，以得到待测面板图像的良好特征区域。
需要说明的是，目标检测模型，是采用机器学习算法，将大量的面板阵列图像作为输入，以无缺陷的特征单元的特征区域作为学习目标，训练而得到。
在一种实施方式中，如图4所示，步骤S120包括如下子步骤。
步骤S121，根据待测面板的规格，估计出特征单元在横轴方向和竖轴方向的第一排布周期，根据第一排布周期得到周期规则。
其中，待测面板的规格包括待测面板的长度与宽度，以及长度方向的特征单元总数和宽度方向的特征单元总数。
具体地，待测面板的长度减去边缘损耗后，与长度方向的特征单元的间隔数相除，即可得到竖轴方向的第一排布周期。其中，长度方向的特征单元的间隔数等于长度方向的特征单元总数减一后的值，例如，特征单元总数为N，则间隔数为N-1。同理，待测面板的宽度减去边缘损耗后，与宽度方向的特征单元的间隔数相除，即可得到横轴方向的第一排布周期。
步骤S122，根据周期规则，得到相邻且满足周期规则的第一特征区域，根据该相邻的第一特征区域的特征点坐标，得到该相邻的第一特征区域的间隔总长。
步骤S123，根据间隔总长，以及该相邻的第一特征区域数量，对间隔总长取平均值，得到特征单元的排布周期。
上述方法中，以根据待测面板的规格得到的周期规则作为选择第一特征区域的条件，选择满足周期规则的第一特征区域来计算间隔总长，再对间隔总长取平均值得到特征单元的排布周期，特征单元的排布周期以待测面板的规格为基准，从而能够是得到的特征单元的排布周期更为准确。
进一步的，周期规则包括横轴方向的周期规则和竖轴方向的周期规则。
其中，横轴方向的周期规则为：
竖轴方向的周期规则为：
其中，
表示取值系数，X
i+1示横轴方向第i+1个特征单元的横坐标，Y
i+1表示竖轴方向第i+1个特征单元的纵坐标，X
i表示横轴方向第i个特征单元的横坐标，Y
i表示竖轴方向第i个特征单元的纵坐标，T
rx表示横轴方向的第一排布周期，T
ry表示竖轴 方向的第一排布周期。
间隔总长包括横轴方向的间隔总长和竖轴方向的间隔总长。
其中，横轴方向的间隔总长为：
竖轴方向的间隔总长为：
其中，N
X表示横轴方向相邻的第一特征区域的数量，V
X表示横轴方向的相邻的第一特征区域的间隔总长，N
Y表示竖轴方向相邻的第一特征区域的数量，V
Y表示竖轴方向相邻的第一特征区域的间隔总长。
针对步骤S122和步骤S123，应当理解的是，当满足周期规则的相邻的第一特征区域为多组时，可先分别计算每一组相邻的第一特征区域的间隔总长，再将多组间隔总长相加后除以总的间隔数，得到特征单元的排布周期。也可以先分别计算每组相邻的第一特征区域的平均间隔值，再对多组相邻的第一特征区域的平均间隔值相加后取平均值，得到特征单元的间隔总长。
在一种实施方式中，如图5所示，为步骤S200的子步骤的流程示意图，包括如下步骤。
步骤S210，针对每个缺陷特征区域，根据该缺陷特征区域的位置，得到与缺陷特征区域相邻和/或相交的良好特征区域的特征点，以该特征点为参考点。
步骤S220，根据特征单元规定的规格，描绘出以参考点为中心点的特征单元。
其中，特征单元规定的规格为待测面板的特征单元的规格。
特征单元可以为规则的形状，也可以为不规则的形状，以参考点为中心点，向参考点四周进行点描绘，描绘出以参考点为中心的多个点，最后将点进行连接，即可得到以参考点为中心点的特征单元。具体地，点描绘时点的个数，可以根据特征单元的形状进行设置。
需要说明的是，以参考点为中心点中的中心点仅仅为命名，并非对其位置和特征等的限定。
在一种实施方式中，如图6所示，为步骤S210的子步骤的流程示意图。
步骤S211，针对每个缺陷特征区域，根据该缺陷特征区域的位置，判断是否有良好特征区域与该缺陷特征区域相交。
若是，则执行步骤S212。
否则，执行步骤S213。
步骤S212，将该相交的良好特征区域的特征点，以及该缺陷特征区域四周相邻的良好特征区域的特征点作为参考点。
步骤S213，将该缺陷特征区域四周相邻的良好特征区域的特征点作为参考点。
需要说明的是，相交包括部分相交和重合。
在一种实施方式中，如图7所示，为步骤S300的子步骤的流程示意图。
步骤S310，针对每个缺陷特征区域，基于与该缺陷特征区域有关联的参考点对应的特征单元的位置，得到该缺陷特征区域与其所关联的参考点对应的特征单元的交集个数。
步骤S320，判断交集个数是否至少为两个，若是，则判定该缺陷特征区域的缺陷类型为短路。
应该理解的是，若一个特征单元与缺陷特征区域的交集个数为两个及以上，则该交集区域可构成一个短路回路，因此，该缺陷特征区域的缺陷类型包括短路。
上述步骤S310和步骤S320中，若与该缺陷特征区域有关联的参考点为两个及两个以上，则单独计算每个参考点对应的特征单元与缺陷特征区域的交集个数，一旦有其中一个特征单元与缺陷特征区域的交集个数至少为两个，则该曲线特征区域的缺陷类型为短路。
应该理解的是，虽然图2-图7的流程图中的各个步骤按照箭头的指示依次显示，但是这些步骤并不是必然按照箭头指示的顺序依次执行。除非本文中有明确的说明，这些步骤的执行并没有严格的顺序限制，这些步骤可以以其它的顺序执行。而且，图2-图7中的至少一部分步骤可以包括多个子步骤或者多个阶段，这些子步骤或者阶段并不必然是在同一时刻执行完成，而是可以在不同的时刻执行，这些子步骤或者阶段的执行顺序也不必然是依次进行，而是可以与其它步骤或者其它步骤的子步骤或者阶段的至少一部分轮流或者交替地执行.
在一种实施方式中，参照图8，本申请还提供一种面板阵列短路检测装置07，该装置包括识别模块04、处理模块05和判断模块。
识别模块04，用于以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测 模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点。
处理模块05，用于根据缺陷特征区域的位置，确定出与缺陷特征区域有关联的特征点作为参考点，基于特征单元规定的规格，构建参考点对应的特征单元。
判定模块06，用于检测出缺陷特征区域与其所关联的参考点对应的特征单元的交集个数，基于交集个数，判断缺陷特征区域的缺陷类型是否为短路。
关于时钟加速同步装置的具体限定可以参见上文中对于时钟加速同步方法的限定，在此不再赘述。上述时钟加速同步装置中的各个模块可全部或部分通过软件、硬件及其组合来实现。上述各模块可以硬件形式内嵌于或独立于计算机设备中的处理器02中，也可以以软件形式存储于电子设备01中的存储器03中，以便于处理器02调用执行以上各个模块对应的操作。
在本公开所提供的几个实施方式中，应该理解到，所揭露的装置、系统图和方法，也可以通过其它的方式实现。以上所描述的装置、系统和方法实施方式仅仅是示意性的，例如，附图中的流程图和框图显示了根据本公开的多个实施方式的装置、方法和计算机程序产品的可能实现的体系架构、功能和操作。在这点上，流程图或框图中的每个方框可以代表一个模块、程序段或代码的一部分，所述模块、程序段或代码的一部分包含一个或多个用于实现规定的逻辑功能的可执行指令。也应当注意，在有些作为替换的实现方式中，方框中所标注的功能也可以以不同于附图中所标注的顺序发生。例如，两个连续的方框实际上可以基本并行地执行，它们有时也可以按相反的顺序执行，这依所涉及的功能而定。也要注意的是，框图和/或流程图中的每个方框、以及框图和/或流程图中的方框的组合，可以用执行规定的功能或动作的专用的基于硬件的系统来实现，或者可以用专用硬件与计算机指令的组合来实现。
另外，在本公开各个实施方式中的各功能模块可以集成在一起形成一个独立的部分，也可以是各个模块单独存在，也可以两个或两个以上模块集成形成一个独立的部分。
所述功能如果以软件功能模块的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，电子设备01，或者网络设备等)执行本公开各个实施方式所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器03(ROM，Read-Only Memory)、随机存取存储器03(RAM，Random Access Memory)、磁碟或者光盘等各种 可以存储程序代码的介质。需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上所述仅为本公开的可选实施方式而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。
Claims (11)
- 一种面板阵列短路检测方法，其特征在于，所述方法包括：以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点；根据所述缺陷特征区域的位置，确定出与所述缺陷特征区域有关联的所述特征点作为参考点，基于特征单元规定的规格，构建所述参考点对应的特征单元；检测出所述缺陷特征区域与其所关联的所述参考点对应的特征单元的交集个数，基于所述交集个数，判断所述缺陷特征区域的缺陷类型是否为短路。
- 根据权利要求1所述的方法，其特征在于，所述良好特征区域包括第一特征区域和第二特征区域；所述以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点的步骤，包括：以面板阵列图像中无缺陷的特征单元的特征区域为参考特征区域，将所述参考特征区域的图像作为目标检测模型的参考检测特征，对待测面板图像进行检测，识别出所述待测面板图像的缺陷特征区域和第一特征区域；根据识别出的所述第一特征区域以及待测面板的规格，确定特征单元的排布周期；根据所述排布周期，以及识别出的所述第一特征区域，补齐未识别出的第二特征区域，以确定所述待测面板图像所有的良好特征区域，并确定所有良好特征区域的特征点。
- 根据权利要求2所述的方法，其特征在于，所述根据识别出的所述第一特征区域以及待测面板的规格，确定特征单元的排布周期的步骤，包括：根据所述待测面板的规格，估计出特征单元在横轴方向和竖轴方向的第一排布周期，根据所述第一排布周期得到周期规则；根据所述周期规则，得到相邻且满足所述周期规则的所述第一特征区域，根据该相邻的第一特征区域的特征点坐标，得到该相邻的第一特征区域的间隔总长；根据所述间隔总长，以及该相邻的第一特征区域数量，对所述间隔总长取平均值，得到特征单元的排布周期。
- 根据权利要求3所述的方法，其特征在于，所述周期规则包括横轴方向的周期规则和竖轴方向的周期规则；所述横轴方向的周期规则为：
所述竖轴方向的周期规则为：
其中，表示取值系数，X i+1示横轴方向第i+1个特征单元的横坐标，Y i+1表示竖轴方向第i+1个特征单元的纵坐标，X i表示横轴方向第i个特征单元的横坐标，Y i表示竖轴方向第i个特征单元的纵坐标，T rx表示横轴方向的第一排布周期，T ry表示竖轴方向的第一排布周期。
- 根据权利要求3所述的方法，其特征在于，所述间隔总长包括横轴方向的间隔总长和竖轴方向的间隔总长；所述横轴方向的间隔总长为：
所述竖轴方向的间隔总长为：
其中，N X表示横轴方向相邻的第一特征区域的数量，V X表示横轴方向的相邻的第一特征区域的间隔总长，N Y表示竖轴方向相邻的第一特征区域的数量，V Y表示竖轴方向相邻的第一特征区域的间隔总长。 - 根据权利要求1至5任一项所述的方法，其特征在于，所述根据所述缺陷特征区域的位置，确定出与所述缺陷特征区域有关联的所述特征点作为参考点，基于特征单元规定的规格，构建所述参考点对应的特征单元的步骤，包括：针对每个所述缺陷特征区域，根据该缺陷特征区域的位置，得到与所述缺陷特征区域相邻和/或相交的所述良好特征区域的特征点，以该特征点为参考点；根据特征单元规定的规格，描绘出以所述参考点为中心点的特征单元。
- 根据权利要求6的方法，其特征在于，所述针对每个所述缺陷特征区域，根据该缺陷特征区域的位置，得到与所述缺陷特征区域相邻和/或相交的所述良好特征区域的特征点，以该特征点为参考点的步骤，包括：针对每个所述缺陷特征区域，根据该缺陷特征区域的位置，判断所述是否有良好特征区域与该缺陷特征区域相交；若是，则将该相交的良好特征区域的特征点，以及该缺陷特征区域四周相邻的良好特征区域的特征点作为参考点；否则，将该缺陷特征区域四周相邻的良好特征区域的特征点作为参考点。
- 根据权利要求1至5任一项所述的方法，其特征在于，所述检测出所述缺陷特征区域与其有关联的所述参考点对应的特征单元的交集个数，基于所述交集个数，判断所述缺陷特征区域的缺陷类型是否为短路的步骤，包括：针对每个所述缺陷特征区域，基于与该缺陷特征区域有关联的所述参考点对应的特征单元的位置，得到该缺陷特征区域与其所关联的所述参考点对应的特征单元的交集个数；判断所述交集个数是否至少为两个，若是，则判定该缺陷特征区域的缺陷类型为短路。
- 一种面板阵列短路检测装置，其特征在于，包括：识别模块，用于以无缺陷特征单元的特征区域作为参考特征区域，采用目标检测模型，得到待测面板图像的缺陷特征区域、良好特征区域以及良好特征区域的特征点；处理模块，用于根据所述缺陷特征区域的位置，确定出与所述缺陷特征区域有关联的所述特征点作为参考点，基于特征单元规定的规格，构建所述参考点对应的特征单元；判定模块，用于检测出所述缺陷特征区域与其所关联的所述参考点对应的特征单元的交集个数，基于所述交集个数，判断所述缺陷特征区域的缺陷类型是否为短路。
- 一种电子设备，其特征在于，包括：存储器、处理器及存储在存储器上并可在处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现权利要求1至8任一项所述的方法。
- 一种存储介质，其特征在于，所述存储介质包括计算机程序，所述计算机程序运行时控制所述存储介质所在的电子设备执行权利要求1至8任一项所述的方法。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202111023791.6A CN113469293B (zh) | 2021-09-02 | 2021-09-02 | 面板阵列短路检测方法、装置、电子设备及存储介质 |
| CN202111023791.6 | 2021-09-02 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| WO2023029491A1 true WO2023029491A1 (zh) | 2023-03-09 |
Family
ID=77867406
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/CN2022/086952 WO2023029491A1 (zh) | 2021-09-02 | 2022-04-15 | 面板阵列短路检测方法、装置、电子设备及存储介质 |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113469293B (zh) |
| WO (1) | WO2023029491A1 (zh) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117744193A (zh) * | 2024-02-19 | 2024-03-22 | 成都深瑞同华科技有限公司 | 一种多回路线路打断方法、装置、设备及存储介质 |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113469293B (zh) * | 2021-09-02 | 2021-11-09 | 成都数联云算科技有限公司 | 面板阵列短路检测方法、装置、电子设备及存储介质 |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111353983A (zh) * | 2020-02-28 | 2020-06-30 | 腾讯科技（深圳）有限公司 | 缺陷检测识别方法、装置、计算机可读介质及电子设备 |
| CN111932515A (zh) * | 2020-08-10 | 2020-11-13 | 成都数之联科技有限公司 | 产品残留类缺陷的短路检测方法及系统及缺陷分类系统 |
| US20210012474A1 (en) * | 2019-07-10 | 2021-01-14 | International Business Machines Corporation | Object defect detection |
| CN113469293A (zh) * | 2021-09-02 | 2021-10-01 | 成都数联云算科技有限公司 | 面板阵列短路检测方法、装置、电子设备及存储介质 |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6927847B2 (en) * | 2001-09-13 | 2005-08-09 | Hitachi High-Technologies Corporation | Method and apparatus for inspecting pattern defects |
| CA2364564A1 (en) * | 2001-12-07 | 2003-06-07 | Marc Pastor | Short-circuit locator for printed circuit boards using a visible camera and an ir camera |
| JP2004069308A (ja) * | 2002-08-01 | 2004-03-04 | Pioneer Electronic Corp | ディスプレイパネルの表示検査方法および表示検査装置 |
| CN103380366B (zh) * | 2011-03-09 | 2017-04-12 | 夏普株式会社 | 缺陷检查方法、缺陷检查装置以及基板的制造方法 |
| CN105466951B (zh) * | 2014-09-12 | 2018-11-16 | 江苏明富自动化科技股份有限公司 | 一种自动光学检测装置及其检测方法 |
| JP7118678B2 (ja) * | 2018-03-19 | 2022-08-16 | キオクシア株式会社 | 欠陥検査装置および欠陥検査方法 |
| CN110866911B (zh) * | 2019-11-14 | 2022-08-30 | 华雁智能科技(集团)股份有限公司 | 表盘缺陷检测方法、装置、图像处理设备及存储介质 |
| CN110824799B (zh) * | 2019-11-19 | 2022-04-15 | 合肥维信诺科技有限公司 | 阵列基板线路检测结构及其检测方法、阵列基板 |
| CN110967851B (zh) * | 2019-12-26 | 2022-06-21 | 成都数之联科技股份有限公司 | 一种液晶面板array图像的线路提取方法及系统 |
-
2021
- 2021-09-02 CN CN202111023791.6A patent/CN113469293B/zh active Active
-
2022
- 2022-04-15 WO PCT/CN2022/086952 patent/WO2023029491A1/zh unknown
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20210012474A1 (en) * | 2019-07-10 | 2021-01-14 | International Business Machines Corporation | Object defect detection |
| CN111353983A (zh) * | 2020-02-28 | 2020-06-30 | 腾讯科技（深圳）有限公司 | 缺陷检测识别方法、装置、计算机可读介质及电子设备 |
| CN111932515A (zh) * | 2020-08-10 | 2020-11-13 | 成都数之联科技有限公司 | 产品残留类缺陷的短路检测方法及系统及缺陷分类系统 |
| CN113469293A (zh) * | 2021-09-02 | 2021-10-01 | 成都数联云算科技有限公司 | 面板阵列短路检测方法、装置、电子设备及存储介质 |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117744193A (zh) * | 2024-02-19 | 2024-03-22 | 成都深瑞同华科技有限公司 | 一种多回路线路打断方法、装置、设备及存储介质 |
| CN117744193B (zh) * | 2024-02-19 | 2024-05-28 | 成都深瑞同华科技有限公司 | 一种多回路线路打断方法、装置、设备及存储介质 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113469293A (zh) | 2021-10-01 |
| CN113469293B (zh) | 2021-11-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| WO2023029491A1 (zh) | 面板阵列短路检测方法、装置、电子设备及存储介质 | |
| CN110060237B (zh) | 一种故障检测方法、装置、设备及系统 | |
| US10489687B2 (en) | Classification method, classification module and computer program product using the same | |
| CN110766095B (zh) | 基于图像灰度特征的缺陷检测方法 | |
| JP6584250B2 (ja) | 画像分類方法、分類器の構成方法および画像分類装置 | |
| CN107004265A (zh) | 信息处理装置、处理信息的方法、鉴别器生成装置、生成鉴别器的方法、以及程序 | |
| WO2023201924A1 (zh) | 对象缺陷检测方法、装置、计算机设备和存储介质 | |
| US20220076404A1 (en) | Defect management apparatus, method and non-transitory computer readable medium | |
| CN114693673A (zh) | 玻璃检测的方法、装置、电子设备及计算机可读存储介质 | |
| WO2024002187A1 (zh) | 缺陷检测方法、缺陷检测设备及存储介质 | |
| CN116128839A (zh) | 晶圆缺陷识别方法、装置、电子设备以及存储介质 | |
| CN110969600A (zh) | 一种产品缺陷检测方法、装置、电子设备及存储介质 | |
| CN117372424B (zh) | 一种缺陷检测方法、装置、设备及存储介质 | |
| CN116952958A (zh) | 缺陷检测方法、装置、电子设备及存储介质 | |
| KR101782364B1 (ko) | 케이평균군집화를 통한 학습기반의 비전검사 방법 | |
| CN111754502A (zh) | 基于多尺度特征融合的Faster-RCNN算法检测磁芯表面缺陷的方法 | |
| CN114359300B (zh) | 一种图像分割模型的优化方法、装置、系统及存储介质 | |
| CN115690104A (zh) | 一种晶圆裂缝检测方法、装置及存储介质 | |
| CN115393617A (zh) | 一种基于多卷积核检验的模仿式商标快速检测方法及系统 | |
| CN114565012A (zh) | 一种基于机器视觉的电机磁瓦表面缺陷检测方法 | |
| CN113901996A (zh) | 设备屏幕透图检测模型训练方法及设备屏幕透图检测方法 | |
| CN113971649A (zh) | 一种面板缺陷检测模型的生成方法、检测方法及终端设备 | |
| CN110781973B (zh) | 物品识别模型训练方法、物品识别方法、装置及电子设备 | |
| CN110599456A (zh) | 一种医学图像的特定区域的提取方法 | |
| CN110874837A (zh) | 一种基于局部特征分布的缺陷自动检测方法 |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| NENP | Non-entry into the national phase |
Ref country code: DE |