WO2023029441A1 - 多口存储器的数据读写方法、装置、存储介质和电子设备 - Google Patents

多口存储器的数据读写方法、装置、存储介质和电子设备 Download PDF

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WO2023029441A1
WO2023029441A1 PCT/CN2022/081866 CN2022081866W WO2023029441A1 WO 2023029441 A1 WO2023029441 A1 WO 2023029441A1 CN 2022081866 W CN2022081866 W CN 2022081866W WO 2023029441 A1 WO2023029441 A1 WO 2023029441A1
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memory
data
written
sub
write
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PCT/CN2022/081866
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English (en)
French (fr)
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牛忠华
刘衡祁
王志忠
施伟祥
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深圳市中兴微电子技术有限公司
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • Embodiments of the present disclosure relate to the communication field, and in particular, relate to a data reading and writing method, device, storage medium and electronic equipment of a multi-port memory.
  • the memory usually has one write port and one read port. If it is to be expanded to write multiple ports and read multiple ports, multiple memories need to be combined.
  • RAM Random Access Memory
  • 1R1W cache RAM 4 times the same specification of 1R1W cache RAM, and the two writes are respectively written into four 1R1W RAMs, and the RAM is identified by controlling the RAM.
  • the data is the latest data. 4 times the 1R1W RAM, superimposed control RAM, the area power consumption is very large.
  • the method for reading and writing data of a multi-port memory in the related art occupies a large amount of memory (such as an occupied area) and requires a large amount of power consumption.
  • Embodiments of the present disclosure provide a data reading and writing method, device, storage medium and electronic equipment for a multi-port memory, so as to at least solve the problems of large occupied area and power consumption of the multi-port memory in the related art.
  • a method for reading and writing data of a multi-port memory including: splitting the target memory into multiple sub-memory, wherein each of the sub-memory includes a read port and a write port; Writing multiple data to be written into the multiple sub-memory of the target memory at the same time.
  • a device for reading and writing data of a multi-port memory including: a splitting unit configured to split the target memory into a plurality of sub-memory, wherein each of the sub-memory includes a A read port and a write port; a write unit configured to simultaneously write a plurality of data to be written into the plurality of sub-memory of the target memory.
  • a computer-readable storage medium wherein a computer program is stored in the computer-readable storage medium, wherein the computer program is configured to perform any one of the above-mentioned methods when running Steps in the examples.
  • an electronic device including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to perform any of the above Steps in the method examples.
  • each sub-memory since one memory is split into multiple sub-memory, and each sub-memory includes a read port and a write port, it can solve the problems of multi-port memory occupying an area and large power consumption, so as to reduce the number of The effect of memory footprint and power consumption.
  • FIG. 1 is a schematic diagram of an electronic device according to an embodiment of the present disclosure
  • FIG. 2 is a flow chart of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure
  • FIG. 3 is a memory structure diagram of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure
  • FIG. 4 is a flow chart of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure
  • FIG. 5 is a flowchart of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure
  • FIG. 6 is a flow chart of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure
  • FIG. 7 is a flow chart of a method for reading and writing data of a multi-port memory according to an embodiment of the present disclosure
  • FIG. 8 is a flow chart of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure
  • FIG. 9 is a memory structure diagram of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure.
  • FIG. 10 is a memory structure diagram of a method for reading and writing data of a multi-port memory according to an embodiment of the disclosure
  • Fig. 11 is a schematic structural diagram of a device for reading and writing data of a multi-port memory according to an embodiment of the disclosure.
  • FIG. 1 is a block diagram of a hardware structure of a mobile terminal according to a method for reading and writing data of a multi-port memory according to an embodiment of the present disclosure.
  • the mobile terminal may include one or more (only one is shown in Figure 1) processors 102 (processors 102 may include but not limited to processing devices such as microprocessor MCU or programmable logic device FPGA, etc.) and a memory 104 for storing data, wherein the above-mentioned mobile terminal may also include a transmission device 106 and an input and output device 108 for communication functions.
  • FIG. 1 is only for illustration, and it does not limit the structure of the above mobile terminal.
  • the mobile terminal may also include more or fewer components than those shown in FIG. 1 , or have a different configuration from that shown in FIG. 1 .
  • the memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the multi-port memory data reading and writing method in the embodiment of the present disclosure, and the processor 102 runs the computer program stored in the memory 104. program, so as to execute various functional applications and data processing, that is, to realize the above-mentioned method.
  • the memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • the memory 104 may further include a memory that is remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal through a network. Examples of the aforementioned networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
  • the transmission device 106 is used to receive or transmit data via a network.
  • the specific example of the above network may include a wireless network provided by the communication provider of the mobile terminal.
  • the transmission device 106 includes a network interface controller (NIC for short), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (Radio Frequency, referred to as RF) module, which is used to communicate with the Internet in a wireless manner.
  • RF Radio Frequency
  • Fig. 2 is a flow chart of a method for reading and writing data of a multi-port memory according to an embodiment of the present disclosure. As shown in Fig. 2 , the process includes the following steps:
  • Step S202 splitting the target memory into multiple sub-memory, wherein each of the sub-memory includes a read port and a write port;
  • Step S204 writing multiple data to be written into the multiple sub-memory of the target memory at the same time.
  • the overall target memory in this embodiment may be a memory with 1 read port and 1 write port, and the memory is split into multiple sub-storages, and each sub-storage includes a read port and a write port.
  • the multiple data to be written can be written into multiple sub-memory, thereby increasing the writing speed. Since the multi-port memory of the method does not need multiple memory combinations, the occupied area and power consumption of the multi-port memory are reduced.
  • the simultaneously writing multiple data to be written into the multiple sub-memory of the target memory includes:
  • the plurality of data to be written is to be written into a target sub-memory of the sub-memory
  • writing one of the plurality of data to be written to the target In the sub-memory write the remaining data to be written into the auxiliary memory at the same time
  • the auxiliary memory is a memory configured for the target memory, and the auxiliary memory is used to store the remaining data to be written input data.
  • an auxiliary storage may be configured for the sub-storage. If there are multiple data to be written that need to be written into the same sub-memory, one data to be written can be written into the sub-memory, and other data to be written can be written into the auxiliary memory.
  • the writing the remaining data to be written into the auxiliary storage includes:
  • the auxiliary memory may be set according to the amount of data to be written. For example, if 4 pieces of data to be written need to be written into one memory, then 3 auxiliary memories can be configured, 1 piece of data to be written into the memory, and the remaining 3 pieces of data to be written into the auxiliary memory in memory.
  • the method further includes:
  • the data in the auxiliary memory is transferred to the target sub-memory.
  • the data written into the auxiliary memory needs to be written into the sub-memory, so as to avoid data loss in the auxiliary memory due to overwriting of newly written data.
  • each of the target memories is split into multiple sub-memory and equipped with an auxiliary memory, and the multiple data to be written are simultaneously written into the
  • the multiple sub-memory of the target memory includes:
  • each target storage includes a sub-storage and an auxiliary storage.
  • each target memory When writing the data to be written into the target memory, each target memory must write the same data.
  • the method also includes:
  • the data when multiple pieces of data to be read are read from the target memory at the same time, the data may be read from multiple target memories at the same time. For example, if 3 pieces of data need to be read, then one piece of data is read from each of the 3 target memories.
  • the target memory RAM is split into N sub-memory RAMs of small size 1R1W to provide higher read and write capabilities through splitting.
  • the write address of the four-port RAM it is determined which small-sized 1R1W RAM is written. At this time, whether the two small-sized RAMs based on the four-port RAM are the same is divided into two cases.
  • two-read and two-write capabilities are provided by splitting a small-sized 1R1W RAM and adding a small amount of redundant RAM.
  • the number of RAM bits required by this disclosure is (N+1)/2N of the existing scheme. Area power consumption is strongly related to the number of RAM bits.
  • the area power consumption is saved by 37.5%, and when N becomes larger, the area power consumption saving value becomes larger, and the maximum value of the area power consumption saving is 50%.
  • the reduction in area reduces the cost of ASIC chips. The reduction in power consumption can improve user experience.
  • FIG. 3 The components of this embodiment are shown in FIG. 3 below, and consist of four parts: storage unit 0, storage unit 1, write control unit, and read control unit.
  • the storage unit 0 is composed of a small size RAM divided into N blocks and a redundant RAM, and receives a write request from the write control unit to complete data updating. Receive the 1-way read request from the read control unit, and output the read data.
  • the storage unit 1 is composed of a small size RAM and a redundant RAM divided into N blocks, and receives a write request from the write control unit to complete data updating. Receive the 1-way read request from the read control unit, and output the read data.
  • the write control unit receives two channels of write data, and completes the distribution of the write data to the small-sized RAM.
  • the small-size RAM selected by the two write channels conflicts, the arbitration of writing data between the small-size RAM and the redundant RAM is completed, and the updated data is output to the storage unit.
  • the read control unit receives two channels of read data, and completes the distribution of the read data to the small-size RAM and the redundant RAM. Receive the return of the read data from the small-size RAM and the redundant RAM, complete the arbitration of the read data from the small-size RAM and the redundant RAM, and output the latest read data.
  • a four-port RAM with a depth of D and a width of W When the depth of the RAM is D and the width is W, the number of RAM bits required by the existing solution is D*W*4, and the number of RAM bits required by this disclosure is D/N *(N+1)*W*2. The number of RAM bits required by this disclosure is (N+1)/2N of the existing scheme.
  • the area power consumption is saved by about 50%. When N is equal to 4, the area power consumption is saved by 37.5%, and when N becomes larger, the area power saving value increases, and the maximum value of the area power saving is 50%.
  • Table 1 records the corresponding relationship of configuration items in this embodiment.
  • the write control unit has two write interfaces, which are write 0 interface and write 1 interface respectively.
  • the write data received from the write 0 interface or the write 1 interface needs to be written into the small-sized RAMs of the same number in the storage unit 0 and the storage unit 1 through the write control unit at the same time.
  • the read control unit has two read interfaces, namely a read 0 interface and a read 1 interface.
  • the read instruction received from the read 0 interface the data can be read from the small size RAM corresponding to the number in the storage unit 0; for the read instruction received from the read 1 interface, the data can be read from the corresponding numbered RAM in the storage unit 1 Read data in small size RAM.
  • Step 101 Mapping between the write command received by the write 0 interface and the small-sized RAM in the storage unit. For example, when the first write instruction is received from the write 0 interface, the first write instruction indicates that the first data is written into the first write address, and the first write address is P bits, the above mapping The rules may include, but are not limited to: determine the low Q bit in the first write address as the number of the small-size RAM to be written in storage unit 0, and determine the high (P-Q) bit in the first write address as the number to be written in The writing address of the small-sized RAM to be written, wherein, P is a natural number greater than 1, and Q is a natural number equal to 1 or greater than 1. For example, for memory cell 0, it can be mapped by the following formula:
  • X represents the serial number of the small size RAM to be written in storage unit 0
  • waddr0 represents the first write address
  • waddr0[log2N-1:0] represents the low log2N bits in the first write address
  • waddr0[log2D- 1: log2N] indicates the number of bits in the first write address except for the lower log2N bits
  • waddr0s indicates the write address of the small-sized RAM numbered X in storage unit 0.
  • Step 102 Write the mapping between the write command received by the write 1 interface and the small-sized RAM in the storage unit. For example, when a second write instruction is received from the write 1 interface, the second write instruction indicates that the second data is written into the second write address, and the second write address is a P bit, the above mapping
  • the rules may include, but are not limited to: determine the low Q bit in the second write address as the number of the small-size RAM to be written in the storage unit 1, and determine the high (P-Q) bit in the second write address as the number to be written.
  • the writing address of the small-sized RAM to be written wherein, P is a natural number greater than 1, and Q is a natural number equal to 1 or greater than 1. For example, for storage unit 1, it can be mapped by the following formula:
  • Y represents the serial number of the small-size RAM to be written in storage unit 1
  • waddr1 represents the second write address
  • waddr1[log2N-1:0] represents the low log2N bits in the second write address
  • waddr1[log2D- 1: log2N] indicates the number of bits in the second write address except for the lower log2N bits
  • waddr1s indicates the write address of the small-size RAM numbered Y in storage unit 1 .
  • Step 103 Execute the write command received by the write 0 interface. For example, write the data wdata0 to be written in the first write instruction into the small-sized RAM with the number X in the storage unit 0 and the write address Waddr0s, and then jump to step 104 .
  • Step 104 Determine whether Val[waddr0s] is 1 and whether Tag[waddr0s] is equal to X. If Val[waddr0s] is 1 and Tag[waddr0s] is equal to X (case 1), then jump to step 105, where Val is 1 to indicate that the data on the corresponding address in the redundant RAM is valid, and Tag is used to indicate redundant RAM The data on the corresponding address in the remaining RAM is the data on which small-sized RAM in the storage unit.
  • Step 105 Clear Val[waddr0s] to 0.
  • Step 106 Determine whether X is equal to Y. If X is equal to Y, go to step 110, otherwise go to step 107. Wherein, step 106 can be but not limited to be the next step of step 105, and step 106 can also be but not limited to be in step 104; If Val[waddr0s] is not 1 and/or Tag[waddr0s] is not equal to X (case 2) skip steps.
  • Step 107 Execute the write command received by the write 1 interface. For example, write the data wdata1 to be written in the second write command into the small-sized RAM with the number Y in the storage unit 1 and the write address waddr1s, and then jump to step 108 .
  • Step 108 Determine whether Val[waddr1s] is 1 and whether Tag[waddr1s] is equal to Y. If Val[waddr1s] is 1 and Tag[waddr1s] is equal to Y, then jump to step 109 .
  • Step 109 Clear Val[waddr1s] to 0.
  • Step 110 Determine whether one of the following two conditions is met:
  • Tag[waddr1s] is equal to Y and Wal[waddr1s] is 1;
  • step 111 If it is judged that one of the above two conditions is satisfied, go to step 111 .
  • Step 111 Execute the write command received by the write 1 interface. For example, write the data wdata1 to be written in the second write instruction into the redundant RAM whose write address is waddr1s in the storage unit 1, and then jump to step 112 .
  • Step 112 Set Val[waddr1s] to 1, and set Tag[waddr1s] to Y.
  • Step 113 Read the data on the read address waddr1s in the redundant RAM to obtain the read data wdata_com, wherein, step 113 can be but not limited to be the next step of step 112, and step 113 can also be but not limited to be that step 110 does not satisfy Jump step for either of the two conditions.
  • Step 114 Execute the write command received by the write 1 interface. For example, write the data wdata1 to be written in the second write instruction into the redundant RAM whose write address is waddr1s in the storage unit 1, and then jump to step 115 .
  • Step 115 Complete the writing of the moved data in the redundant RAM. For example, set the write address of RAM Slice tag[waddr1s] to waddr1s, and write data wdata_com;
  • Step 116 Set Val[waddr1s] to 1, and set Tag[waddr1s] to Y.
  • Step 117 end.
  • the reading process corresponding to the read 0 interface in this embodiment is further described in conjunction with FIG. 7, and the specific steps are as follows:
  • Step 118 Mapping between the read command received by the read 0 interface and the small-sized RAM in the storage unit 0.
  • the above mapping rule may be It is not limited to include: determining the low Q bit in the first read address as the number of the small size RAM to be read in storage unit 0, and determining the high (P-Q) bit in the first read address as the number of the small size RAM to be read.
  • P is a natural number greater than 1
  • Q is a natural number equal to 1 or greater than 1. For example, for memory cell 0, it can be mapped by the following formula:
  • M represents the serial number of the small size RAM to be read in storage unit 0
  • raddr0 represents the first read address
  • raddr0[log2N-1:0] represents the low log2N bits in the first read address
  • raddr0[log2D- 1: log2N] indicates the number of bits in the first read address except for the low log2N bits
  • raddr0s indicates the read address of the small-sized RAM numbered X in the storage unit 0.
  • step 118 may be but not limited to be the next step of step 117 .
  • Step 119 Determine whether Val[raddr0s] is equal to 1 and whether Tag[raddr0s] is equal to M. If Val[raddr0s] is equal to 1 and Tag[raddr0s] is equal to M, then jump to step 201, otherwise jump to step 202;
  • Step 201 Read the data in the redundant RAM whose reading address is raddr0s in the storage unit 0.
  • Step 202 Read the data in the small size RAM numbered M in the storage unit 0 and whose read address is raddr0s.
  • Step 203 Obtain the read data.
  • Step 204 end.
  • the reading process corresponding to the reading 1 interface in this embodiment is further described in conjunction with FIG. 8, and the specific steps are as follows:
  • Step 301 read the mapping between the read instruction received by the 1 interface and the small-sized RAM in the storage unit 1 .
  • the above mapping rule may be It is not limited to include: determining the low Q bit in the second read address as the number of the small size RAM to be read in the storage unit 0, and determining the high (P-Q) bit in the second read address as the number to be read.
  • P is a natural number greater than 1
  • Q is a natural number equal to 1 or greater than 1.
  • the mapping can be done by the following formula:
  • N raddr1[log2N-1:0]
  • raddr1s raddr1[log2D-1:log2N]
  • N represents the serial number of the small-size RAM to be read in storage unit 1
  • raddr1 represents the second read address
  • raddr1[log2N-1:0] represents the low log2N bits in the second read address
  • raddr1[log2D- 1: log2N] indicates the number of bits in the second read address except for the lower log2N bits
  • raddr1s indicates the read address of the small-sized RAM numbered Y in the storage unit 1 .
  • Step 302 Determine whether Val[raddr1s] is equal to 1 and whether Tag[raddr1s] is equal to N. If Val[raddr1s] is equal to 1 and Tag[raddr1s] is equal to N, then go to step 303 , otherwise go to step 304 .
  • Step 303 Read the data in the redundant RAM whose read address is raddr1s in the storage unit 1.
  • Step 304 Read the data in the small size RAM with the number N in the storage unit 1 and the read address raddr1s.
  • Step 305 Obtain the read data.
  • Step 306 end.
  • it may also include multi-port RAMs with one port, two ports for writing and three readings.
  • the implementation component consists of four parts: storage unit 0, storage unit 1, storage unit 2, write control unit, and read control unit.
  • the storage unit 0 is composed of a small size RAM divided into N blocks and a redundant RAM, and receives a write request from the write control unit to complete data updating. Receive the 1-way read request from the read control unit, and output the read data.
  • the storage unit 1 is composed of a small size RAM and a redundant RAM divided into N blocks, and receives a write request from the write control unit to complete data updating. Receive the 1-way read request from the read control unit, and output the read data.
  • the storage unit 2 is composed of a small size RAM divided into N blocks and a redundant RAM, and receives a write request from the write control unit to complete data updating. Receive the 1-way read request from the read control unit, and output the read data.
  • the write control unit receives two channels of write data, and completes the distribution of the write data to the small-sized RAM.
  • the small-size RAM selected by the two write channels conflicts, the arbitration of writing data between the small-size RAM and the redundant RAM is completed, and the updated data is output to the storage unit.
  • the read control unit receives three channels of read data, and completes the distribution of the read data to small-size RAM and redundant RAM. Receive the return of the read data from the small-size RAM and the redundant RAM, complete the arbitration of the read data from the small-size RAM and the redundant RAM, and output the latest read data.
  • a two-write and three-read RAM with a depth of D and a width of W The number of RAM bits required by the existing solution is D*W*6, and the number of RAM bits required by this disclosure is D/N*(N+1)*W* 3. The number of RAM bits required by this disclosure is (N+1)/2N of the existing scheme.
  • the area power consumption is saved by about 50%. When N is equal to 4, the area power consumption is saved by 37.5%, and when N becomes larger, the area power saving value increases, and the maximum value of the area power saving is 50%.
  • This embodiment can also include one, three write, two read multi-port RAMs.
  • the implementation component is shown in Figure 10, which consists of four parts: storage unit 0, storage unit 1, write control unit, and read control unit.
  • the storage unit 0 is composed of a small size RAM divided into N blocks and a redundant RAM, and receives a write request from the write control unit to complete data updating. Receive the 1-way read request from the read control unit, and output the read data.
  • the storage unit 1 is composed of a small size RAM and a redundant RAM divided into N blocks, and receives a write request from the write control unit to complete data updating. Receive the 1-way read request from the read control unit, and output the read data.
  • the write control unit receives three channels of write data, and completes the distribution of the write data to the small-sized RAM.
  • the small-size RAM selected by the three writes conflicts, the arbitration of writing data between the small-size RAM and the redundant RAM is completed, and the update data is output to the storage unit.
  • the read control unit receives two channels of read data, and completes the distribution of the read data to the small-size RAM and the redundant RAM. Receive the return of the read data from the small-size RAM and the redundant RAM, complete the arbitration of the read data from the small-size RAM and the redundant RAM, and output the latest read data.
  • a three-write, two-read RAM with a depth of D and a width of W the number of RAM bits required by the existing solution is D*W*6, and the number of RAM bits required by this disclosure is D/N*(N+2)*W *2.
  • the number of RAM bits required by this disclosure is (N+2)/3N of the existing solution, where N is greater than or equal to 4.
  • the method according to the above embodiments can be implemented by means of software plus a necessary general-purpose hardware platform, and of course also by hardware, but in many cases the former is better implementation.
  • the technical solution of the present disclosure can be embodied in the form of a software product in essence or the part that contributes to the related technology.
  • the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk, etc.) ) includes several instructions to make a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) execute the methods described in various embodiments of the present disclosure.
  • a device for reading and writing data of a multi-port memory is also provided.
  • the device is used to implement the above embodiments and preferred implementation modes, and those that have been explained will not be repeated here.
  • the term "module” may be a combination of software and/or hardware that realizes a predetermined function.
  • the devices described in the following embodiments are preferably implemented in software, implementations in hardware, or a combination of software and hardware are also possible and contemplated.
  • Fig. 11 is a structural block diagram of a device for reading and writing data of a multi-port memory according to an embodiment of the disclosure. As shown in Fig. 11, the device includes:
  • a splitting unit 1102 configured to split the target memory into multiple sub-storages, where each of the sub-storages includes a read port and a write port;
  • the writing unit 1104 is configured to simultaneously write multiple data to be written into the multiple sub-memory of the target memory.
  • the above-mentioned modules can be realized by software or hardware. For the latter, it can be realized by the following methods, but not limited to this: the above-mentioned modules are all located in the same processor; or, the above-mentioned modules can be combined in any combination The forms of are located in different processors.
  • Embodiments of the present disclosure also provide a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps in any one of the above method embodiments when running.
  • the above-mentioned computer-readable storage medium may include but not limited to: U disk, read-only memory (Read-Only Memory, referred to as ROM), random access memory (Random Access Memory, referred to as RAM) , mobile hard disk, magnetic disk or optical disk and other media that can store computer programs.
  • ROM read-only memory
  • RAM random access memory
  • mobile hard disk magnetic disk or optical disk and other media that can store computer programs.
  • Embodiments of the present disclosure also provide an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.
  • the electronic device may further include a transmission device and an input and output device, wherein the transmission device is connected to the processor, and the input and output device is connected to the processor.
  • each module or each step of the above-mentioned disclosure can be realized by a general-purpose computing device, and they can be concentrated on a single computing device, or distributed in a network composed of multiple computing devices In fact, they can be implemented in program code executable by a computing device, and thus, they can be stored in a storage device to be executed by a computing device, and in some cases, can be executed in an order different from that shown here. Or described steps, or they are fabricated into individual integrated circuit modules, or multiple modules or steps among them are fabricated into a single integrated circuit module for implementation. As such, the present disclosure is not limited to any specific combination of hardware and software.

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Abstract

一种多口存储器的数据读写方法，包括：将目标存储器拆分为多个子存储器，其中，每一个子存储器包括一个读端口和一个写端口（S202）；将多个待写入数据同时写入到目标存储器的多个子存储器中（S204）。解决了多口存储器面积和功耗增大的问题，进而达到了减少多口存储器的占用面积和功耗的效果。还公开了一种多口存储器的数据读写装置、存储介质和电子设备。

Description

多口存储器的数据读写方法、装置、存储介质和电子设备
相关申请的交叉引用
本公开基于2021年08月31日提交的发明名称为“多口存储器的数据读写方法、装置、存储介质和电子设备”的中国专利申请CN202111017394.8，并且要求该专利申请的优先权，通过引用将其所公开的内容全部并入本公开。
技术领域
本公开实施例涉及通信领域，具体而言，涉及一种多口存储器的数据读写方法、装置、存储介质和电子设备。
背景技术
在相关技术中存储器通常为一个写入口一个读取口，如果要扩展为多口写入多口读取，则需要多个存储器进行组合。
例如，传统的四口随机存取存储器(Random Access Memory，简称为RAM)使用4倍同等规格的1R1W缓存RAM，两个写分别写入4个1R1W的RAM中，通过控制RAM来识别哪个RAM中的数据是最新的数据。4倍的1R1W的RAM，叠加控制RAM，面积功耗都很大。
概括而言，相关技术中的多口存储器的数据读写方法对存储器的占用(如占用面积)以及所需的功耗较大。
发明内容
本公开实施例提供了一种多口存储器的数据读写方法、装置、存储介质和电子设备，以至少解决相关技术中多口存储器占用面积和功耗大的问题。
根据本公开的一个实施例，提供了一种多口存储器的数据读写方法，包括：将目标存储器拆分为多个子存储器，其中，每一个所述子存储器包括一个读端口和一个写端口；将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中。
根据本公开的另一个实施例，提供了一种多口存储器的数据读写装置，包括：拆分单元，设置为将目标存储器拆分为多个子存储器，其中，每一个所述子存储器包括一个读端口和一个写端口；写入单元，设置为将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中。
根据本公开的又一个实施例，还提供了一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，其中，所述计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
根据本公开的又一个实施例，还提供了一种电子装置，包括存储器和处理器，所述存储器中存储有计算机程序，所述处理器被设置为运行所述计算机程序以执行上述任一项方法实施例中的步骤。
通过本公开，由于将一个存储器拆分为多个子存储器，而每一个子存储器又包括了一个读端口和一个写端口，因此，可以解决多口存储器占用面积和功耗大的问题，达到降低多口存储器的占用面积和功耗的效果。
附图说明
图1是根据本公开实施例的电子设备的示意图；
图2是根据本公开实施例的多口存储器的数据读写方法的流程图；
图3是根据本公开实施例的多口存储器的数据读写方法的存储器结构图；
图4是根据本公开实施例的多口存储器的数据读写方法的流程图；
图5是根据本公开实施例的多口存储器的数据读写方法的流程图；
图6是根据本公开实施例的多口存储器的数据读写方法的流程图；
图7是根据本公开实施例的多口存储器的数据读写方法的流程图；
图8是根据本公开实施例的多口存储器的数据读写方法的流程图；
图9是根据本公开实施例的多口存储器的数据读写方法的存储器结构图；
图10是根据本公开实施例的多口存储器的数据读写方法的存储器结构图；
图11是根据本公开实施例的多口存储器的数据读写装置的结构示意图。
具体实施方式
下文中将参考附图并结合实施例来详细说明本公开的实施例。
需要说明的是，本公开的说明书和权利要求书及上述附图中的术语“第一”、“第二”等是用于区别类似的对象，而不必用于描述特定的顺序或先后次序。
本申请实施例中所提供的方法实施例可以在移动终端、计算机终端或者类似的运算装置中执行。以运行在移动终端上为例，图1是本公开实施例的一种多口存储器的数据读写方法的移动终端的硬件结构框图。如图1所示，移动终端可以包括一个或多个(图1中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)和用于存储数据的存储器104，其中，上述移动终端还可以包括用于通信功能的传输设备106以及输入输出设备108。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述移动终端的结构造成限定。例如，移动终端还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
存储器104可用于存储计算机程序，例如，应用软件的软件程序以及模块，如本公开实施例中的多口存储器的数据读写方法对应的计算机程序，处理器102通过运行存储在存储器104内的计算机程序，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至移动终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括移动终端的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，简称为NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，简称为RF)模块，其用于通过无线方式与互联网进行通讯。
图2是根据本公开实施例的多口存储器的数据读写方法的流程图，如图2所示，该流程包括如下步骤：
步骤S202，将目标存储器拆分为多个子存储器，其中，每一个所述子存储器包括一个读 端口和一个写端口；
步骤S204，将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中。
可选地，本实施例总的目标存储器可以为一个1读端口1写端口的存储器，将该存储器拆分成多个子存储器，每一个子存储器包括了一个读端口和一个写端口。在写入多个待写入数据时，可以将多个待写入数据写入到多个子存储器中，从而提高了写入的速度。该方法的多口存储器由于不需要多个存储器组合，因此，降低了多口存储器的占用面积和功耗。
作为一种可选的示例，所述将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中包括：
确定所述多个待写入数据中每一个待写入数据将被写入的子存储器；
在所述多个待写入数据将被写入到所述子存储器中的一个目标子存储器的情况下，将所述多个待写入数据中的一个待写入数据写入到所述目标子存储器中，同时将剩余的所述待写入数据写入到辅助存储器中，其中，所述辅助存储器为为所述目标存储器配置的存储器，所述辅助存储器用于存储剩余的所述待写入数据。
可选地，本实施例中，可以为子存储器配置辅助存储器。如果存在多个待写入数据需要写入到同一个子存储器中，则可以将一个待写入数据写入到子存储器中，将其他的待写入数据写入到辅助存储器中。
作为一种可选的示例，所述将剩余的所述待写入数据写入到辅助存储器中包括：
将剩余的所述待写入数据中每一个待写入数据写入到一个所述辅助存储器中。
可选地，本实施例中，可以按照待写入数据的数量设置辅助存储器。例如，4个待写入数据需要写入到一个存储器中，则可以配置3个辅助存储器，将1个待写入数据写入到存储器中，将剩余的3个待写入数据写入到辅助存储器中。
作为一种可选的示例，在将剩余的所述待写入数据写入到所述辅助存储器中之后，所述方法还包括：
在所述辅助存储器中再次被写入数据前，将所述辅助存储器中的数据转移到所述目标子存储器中。
可选地，本实施例中，写入到辅助存储器中的数据需要写入到子存储器中，避免辅助存储器中的数据因为新写入的数据被覆盖导致数据丢失。
作为一种可选的示例，所述目标存储器为多个，每一个所述目标存储器被拆分为多个子存储器且配备有辅助存储器，所述将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中包括：
将每一个所述目标存储器作为当前存储器，将所述多个待写入数据同时写入到所述当前存储器的所述多个子存储器中。
可选地，本实施例中，可以配置多个目标存储器，每一个目标存储器包括了子存储器和辅助存储器。在将待写入数据写入到目标存储器中时，每一个目标存储器都要写入相同的数 据。
作为一种可选的示例，所述方法还包括：
在从多个所述目标存储器中同时读取多个待读取数据的情况下，同时从每一个所述目标存储器中读取一个不同的待读取数据。
可选地，本实施例中，当从目标存储器同时读取多个待读取数据时，可以从多个目标存储器中同时读取数据。例如，需要读取3个数据，则从3个目标存储器中每一个目标存储器读取一个数据。
可选地，本实施例中，把目标存储器RAM拆分成N份小规格的1R1W的子存储器RAM，通过拆分提供更高的读写能力。根据四口RAM的写地址决定写入哪个小规格的1R1W的RAM。此时，基于四口RAM的两个写写入的小规格RAM的是否是同一个，分为两种情况。
当四口RAM的两个写写入的小规格的RAM不同时，可以直接提供两倍的写能力。
当四口RAM的两个写写入的小规格的RAM相同时，一个写写入选定的小规格RAM，另一个写写入辅助存储器也就是冗余RAM的对应地址，把冗余RAM中存储的数据搬移到对应的小规格RAM中。通过两个小规格RAM加冗余RAM，提供两倍的写能力。
本实施例通过拆分后的小规格的1R1W的RAM，加上少量的冗余RAM来提供两读两写的能力。一个深度为D(D表示允许存储的存储单元数量，例如，存储地址可以用10比特表示时，D＝1024)，宽度为W(W表示一个存储单元上允许存储的数据的位数，例如，位数为10时，W＝10)的四口RAM，现有方案需要的RAM bit数为D*W*4，本实施例需要的RAM bit数为D/N*(N+1)*W*2。本公开需要的RAM bit数是现有方案的(N+1)/2N。面积功耗和RAM bit数强相关。当N等于4时，面积功耗节省了37.5％，当N变大时，面积功耗节省值变大，节省的最大值为50％。面积的降低使ASIC芯片的成本降低。功耗的降低可以提升用户体验。
本实施例的组件如下图3所示，由存储单元0，存储单元1，写控制单元，读控制单元四部分组成。
存储单元0由切分成N块的小规格RAM和冗余RAM组成，接收写控制单元的写请求，完成数据的更新。接收读控制单元的1路读请求，输出读数据。
存储单元1由切分成N块的小规格RAM和冗余RAM组成，接收写控制单元的写请求，完成数据的更新。接收读控制单元的1路读请求，输出读数据。
写控制单元接收两路写数据，完成写数据到小规格RAM的分发。当两路写选择的小规格RAM冲突时，完成小规格RAM和冗余RAM写数据的仲裁，输出更新数据给存储单元。
读控制单元接收两路读数据，完成读数据到小规格RAM和冗余RAM的分发。接收小规格RAM和冗余RAM的读数据返回，完成小规格RAM和冗余RAM读数据的仲裁，输出最新的读数据。
一个深度为D，宽度为W的四口RAM，当RAM深度为D，宽度为W时，现有方案需要的RAM bit数为D*W*4，本公开需要的RAM bit数为D/N*(N+1)*W*2。本公开需要的RAM bit数是现有方案的(N+1)/2N。面积功耗节省了50％左右。当N等于4时，面积功耗节省了37.5％，当N变大时，面积功耗节省值增加，节省的最大值为50％。
表1中记录了本实施例的配置项的对应关系。
表1
Figure PCTCN2022081866-appb-000001
结合图3可知，写控制单元具有2个写入接口，分别为写0接口和写1接口。从写0接 口或写1接口接收到的写入数据，需要通过写控制单元同时写入到存储单元0和存储单元1中相同编号的小规格RAM。此外，在图3中，读控制单元具有2个读取接口，分别为读0接口和读1接口。对于从读0接口接收到的读取指令，可以从存储单元0中对应编号的小规格RAM中读取数据，对于从读1接口接收到的读取指令，可以从存储单元1中对应编号的小规格RAM中读取数据。
接下来结合图4进一步描述本实施例中的写入流程，具体步骤如下：
步骤101：写0接口接收到的写入指令与存储单元中的小规格RAM之间的映射。例如，在从写0接口接收到第一写入指令、第一写入指令指示将第一数据写入到第一写入地址中、且第一写入地址为P位的情况下，上述映射规则可以但不限于包括：将第一写入地址中的低Q位确定为存储单元0中待写入的小规格RAM的编号，将第一写入地址中的高(P-Q)位确定为待写入的小规格RAM的写入地址，其中，P为大于1的自然数，Q为等于1或大于1的自然数。例如，对于存储单元0，可以通过以下公式进行映射：
X＝waddr0[log2N-1：0]，waddr0s＝waddr0[log2D-1：log2N]；
其中，X表示存储单元0中待写入的小规格RAM的编号，waddr0表示第一写入地址，waddr0[log2N-1：0]表示第一写入地址中的低log2N位，waddr0[log2D-1：log2N]表示第一写入地址中除低log2N位之外的位数，waddr0s表示存储单元0中编号为X的小规格RAM的写入地址。
步骤102：写1接口接收到的写入指令与存储单元中的小规格RAM之间的映射。例如，在从写1接口接收到第二写入指令、第二写入指令指示将第二数据写入到第二写入地址中、且第二写入地址为P位的情况下，上述映射规则可以但不限于包括：将第二写入地址中的低Q位确定为存储单元1中待写入的小规格RAM的编号，将第二写入地址中的高(P-Q)位确定为待写入的小规格RAM的写入地址，其中，P为大于1的自然数，Q为等于1或大于1的自然数。例如，对于存储单元1，可以通过以下公式进行映射：
Y＝waddr1[log2N-1：0]，waddr1s＝waddr1[log2D-1：log2N]；
其中，Y表示存储单元1中待写入的小规格RAM的编号，waddr1表示第二写入地址，waddr1[log2N-1：0]表示第二写入地址中的低log2N位，waddr1[log2D-1：log2N]表示第二写入地址中除低log2N位之外的位数，waddr1s表示存储单元1中编号为Y的小规格RAM的写入地址。
步骤103：执行写0接口接收到的写入指令。例如，将第一写入指令中待写入的数据wdata0写入到存储单元0中的编号为X的、且写入地址为Waddr0s的小规格RAM中，然后跳转到步骤104。
步骤104：判断Val[waddr0s]是否为1且Tag[waddr0s]是否等于X。如果Val[waddr0s]为1且Tag[waddr0s]等于X(情况1)，则跳转到步骤105，其中，Val为1用于表示冗余RAM中对应地址上的数据有效，Tag用于表示冗余RAM中对应地址上的数据是存储单元中的第几个小规格RAM上的数据。
步骤105：将Val[waddr0s]清0。
进一步，以图4所示场景为基础，继续结合图5描述本公开实施例中的写如流程，具体步骤如下：
步骤106：判断X是否等于Y。如果X等于Y，则跳转到步骤110，否则跳转到步骤107。其中，步骤106可以但不限于为步骤105的下一步骤，步骤106还可以但不限于为步骤104中；如果Val[waddr0s]不为1和/或Tag[waddr0s]不等于X(情况2)的跳转步骤。
步骤107：执行写1接口接收到的写入指令。例如，将第二写入指令中待写入的数据wdata1写入到存储单元1中的编号为Y的、且写入地址为waddr1s的小规格RAM中，然后跳转到步骤108。
步骤108：判断Val[waddr1s]是否为1且Tag[waddr1s]是否等于Y。如果Val[waddr1s]为1且Tag[waddr1s]等于Y，则跳转到步骤109。
步骤109：将Val[waddr1s]清0。
步骤110：判断是否满足下面两个条件中的一个：
1)Val[waddr1s]为0；
2)Tag[waddr1s]等于Y且Wal[waddr1s]为1；
如果判断出满足上述两个条件中的一个，则跳转到步骤111。
步骤111：执行写1接口接收到的写入指令。例如，将第二写入指令中待写入的数据wdata1写入到存储单元1中的写入地址为waddr1s的冗余RAM中，然后跳转到步骤112。
步骤112：将Val[waddr1s]置1，并将Tag[waddr1s]置Y。
进一步，基于如图5所示的场景，继续结合图6描述本公开实施例中的写如流程，具体步骤如下：
步骤113：读取冗余RAM中读取地址waddr1s上的数据，得到读数据wdata_com，其中，步骤113可以但不限于为步骤112的下一步骤，步骤113还可以但不限于为步骤110不满足两个条件中的任一个的跳转步骤。
步骤114：执行写1接口接收到的写入指令。例如，将第二写入指令中待写入的数据wdata1写入到存储单元1中的写入地址为waddr1s的冗余RAM中，然后跳转到步骤115。
步骤115：完成冗余RAM中的搬移数据的写入。例如，将RAM Slice tag[waddr1s]的写 入地址设置为waddr1s，并写入数据wdata_com；
步骤116：将Val[waddr1s]置1，并将Tag[waddr1s]置Y。
步骤117：结束。
可选地，接下来结合图7进一步描述本实施例中的读0接口对应的读取流程，具体步骤如下：
步骤118：读0接口接收到的读取指令与存储单元0中的小规格RAM之间的映射。例如，在从读0接口接收到第一读取指令、第一读取指令指示从第一读取地址中读取数据、且第一读取地址为P位的情况下，上述映射规则可以但不限于包括：将第一读取地址中的低Q位确定为存储单元0中待读取的小规格RAM的编号，将第一读取地址中的高(P-Q)位确定为待读取的小规格RAM的读取地址，其中，P为大于1的自然数，Q为等于1或大于1的自然数。例如，对于存储单元0，可以通过以下公式进行映射：
M＝raddr0[log2N-1：0]，raddr0s＝raddr0[log2D-1：log2N]；
其中，M表示存储单元0中待读取的小规格RAM的编号，raddr0表示第一读取地址，raddr0[log2N-1：0]表示第一读取地址中的低log2N位，raddr0[log2D-1：log2N]表示第一读取地址中除低log2N位之外的位数，raddr0s表示存储单元0中编号为X的小规格RAM的读取地址。
可选地，步骤118可以但不限于为步骤117的下一步骤。
步骤119：判断Val[raddr0s]是否等于1且Tag[raddr0s]是否等于M。如果Val[raddr0s]等于1且Tag[raddr0s]等于M，则跳转到步骤201，否则跳转到步骤202；
步骤201：读取存储单元0中读取地址为raddr0s的冗余RAM中的数据。
步骤202：读取存储单元0中编号为M的、且读取地址为raddr0s的小规格RAM中的数据。
步骤203：获取读取到的数据。
步骤204：结束。
可选地，接下来结合图8进一步描述本实施例中的读1接口对应的读取流程，具体步骤如下：
步骤301：读1接口接收到的读取指令与存储单元1中的小规格RAM之间的映射。例如，在从读1接口接收到第二读取指令、第二读取指令指示从第二读取地址中读取数据、且第二读取地址为P位的情况下，上述映射规则可以但不限于包括：将第二读取地址中的低Q位确定为存储单元0中待读取的小规格RAM的编号，将第二读取地址中的高(P-Q)位确定为待读取的小规格RAM的读取地址，其中，P为大于1的自然数，Q为等于1或大于1的自然数。例 如，对于存储单元1，可以通过以下公式进行映射：
N＝raddr1[log2N-1：0]，raddr1s＝raddr1[log2D-1：log2N]；
其中，N表示存储单元1中待读取的小规格RAM的编号，raddr1表示第二读取地址，raddr1[log2N-1：0]表示第二读取地址中的低log2N位，raddr1[log2D-1：log2N]表示第二读取地址中除低log2N位之外的位数，raddr1s表示存储单元1中编号为Y的小规格RAM的读取地址。
步骤302：判断Val[raddr1s]是否等于1且Tag[raddr1s]是否等于N。如果Val[raddr1s]等于1且Tag[raddr1s]等于N，则跳转到步骤303，否则跳转到步骤304。
步骤303：读取存储单元1中读取地址为raddr1s的冗余RAM中的数据。
步骤304：读取存储单元1中编号为N的、且读取地址为raddr1s的小规格RAM中的数据。
步骤305：获取读取到的数据。
步骤306：结束。
本实施例中，还可以包括一口、两口写三读的多口RAM。
通过增加一份存储单元，很容易拓展成两写三读多口RAM。新增的存储单元读写方式和其他两份存储单元一致。
可选地，实现组件如下图9所示，由存储单元0，存储单元1，存储单元2，写控制单元，读控制单元四部分组成。
存储单元0由切分成N块的小规格RAM和冗余RAM组成，接收写控制单元的写请求，完成数据的更新。接收读控制单元的1路读请求，输出读数据。
存储单元1由切分成N块的小规格RAM和冗余RAM组成，接收写控制单元的写请求，完成数据的更新。接收读控制单元的1路读请求，输出读数据。
存储单元2由切分成N块的小规格RAM和冗余RAM组成，接收写控制单元的写请求，完成数据的更新。接收读控制单元的1路读请求，输出读数据。
写控制单元接收两路写数据，完成写数据到小规格RAM的分发。当两路写选择的小规格RAM冲突时，完成小规格RAM和冗余RAM写数据的仲裁，输出更新数据给存储单元。
读控制单元接收三路读数据，完成读数据到小规格RAM和冗余RAM的分发。接收小规格RAM和冗余RAM的读数据返回，完成小规格RAM和冗余RAM读数据的仲裁，输出最新的读数据。
一个深度为D，宽度为W的两写三读RAM，现有方案需要的RAM bit数为D*W*6，本公开需要的RAM bit数为D/N*(N+1)*W*3。本公开需要的RAM bit数是现有方案的(N+1)/2N。 面积功耗节省了50％左右。当N等于4时，面积功耗节省了37.5％，当N变大时，面积功耗节省值增加，节省的最大值为50％。
本实施例还可以包括一，三写两读多口RAM。
通过增加每个存储单元增加一个冗余RAM，很容易拓展成三写两读多口RAM。新增冗余RAM后，可以提供两份冗余RAM写。当3个写冲突到一个RAM slice时，一个写写入RAM slice时，另外两个写分别写入两个冗余RAM。如果此时冗余RAM中存储有数据，把数据搬移到对应的RAM slice中。通过增加冗余RAM，增加上述冲突处理，可以从四口RAM拓展成三写两读的RAM。
实现组件如图10所示，由存储单元0，存储单元1，写控制单元，读控制单元四部分组成。
存储单元0由切分成N块的小规格RAM和冗余RAM组成，接收写控制单元的写请求，完成数据的更新。接收读控制单元的1路读请求，输出读数据。
存储单元1由切分成N块的小规格RAM和冗余RAM组成，接收写控制单元的写请求，完成数据的更新。接收读控制单元的1路读请求，输出读数据。
写控制单元接收三路写数据，完成写数据到小规格RAM的分发。当三路写选择的小规格RAM冲突时，完成小规格RAM和冗余RAM写数据的仲裁，输出更新数据给存储单元。
读控制单元接收两路读数据，完成读数据到小规格RAM和冗余RAM的分发。接收小规格RAM和冗余RAM的读数据返回，完成小规格RAM和冗余RAM读数据的仲裁，输出最新的读数据。
一个深度为D，宽度为W的三写两读RAM，，现有方案需要的RAM bit数为D*W*6，本公开需要的RAM bit数为D/N*(N+2)*W*2。本公开需要的RAM bit数是现有方案的(N+2)/3N，其中N大于等于4。当N等于4时，面积功耗节省了50％，当N变大时，面积功耗节省值增加，节省的最大值为66％。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到根据上述实施例的方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本公开的技术方案本质上或者说对相关技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端设备(可以是手机，计算机，服务器，或者网络设备等)执行本公开各个实施例所述的方法。
在本实施例中还提供了一种多口存储器的数据读写装置，该装置用于实现上述实施例及优选实施方式，已经进行过说明的不再赘述。如以下所使用的，术语“模块”可以实现预定功能的软件和/或硬件的组合。尽管以下实施例所描述的装置较佳地以软件来实现，但是硬件， 或者软件和硬件的组合的实现也是可能并被构想的。
图11是根据本公开实施例的多口存储器的数据读写装置的结构框图，如图11所示，该装置包括：
拆分单元1102，设置为将目标存储器拆分为多个子存储器，其中，每一个所述子存储器包括一个读端口和一个写端口；
写入单元1104，设置为将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中。
需要说明的是，上述各个模块是可以通过软件或硬件来实现的，对于后者，可以通过以下方式实现，但不限于此：上述模块均位于同一处理器中；或者，上述各个模块以任意组合的形式分别位于不同的处理器中。
本实施例的其他示例请参见上述示例，在此不再赘述。
本公开的实施例还提供了一种计算机可读存储介质，该计算机可读存储介质中存储有计算机程序，其中，该计算机程序被设置为运行时执行上述任一项方法实施例中的步骤。
在一个示例性实施例中，上述计算机可读存储介质可以包括但不限于：U盘、只读存储器(Read-Only Memory，简称为ROM)、随机存取存储器(Random Access Memory，简称为RAM)、移动硬盘、磁碟或者光盘等各种可以存储计算机程序的介质。
本公开的实施例还提供了一种电子装置，包括存储器和处理器，该存储器中存储有计算机程序，该处理器被设置为运行计算机程序以执行上述任一项方法实施例中的步骤。
在一个示例性实施例中，上述电子装置还可以包括传输设备以及输入输出设备，其中，该传输设备和上述处理器连接，该输入输出设备和上述处理器连接。
本实施例中的具体示例可以参考上述实施例及示例性实施方式中所描述的示例，本实施例在此不再赘述。
显然，本领域的技术人员应该明白，上述的本公开的各模块或各步骤可以用通用的计算装置来实现，它们可以集中在单个的计算装置上，或者分布在多个计算装置所组成的网络上，它们可以用计算装置可执行的程序代码来实现，从而，可以将它们存储在存储装置中由计算装置来执行，并且在某些情况下，可以以不同于此处的顺序执行所示出或描述的步骤，或者将它们分别制作成各个集成电路模块，或者将它们中的多个模块或步骤制作成单个集成电路模块来实现。这样，本公开不限制于任何特定的硬件和软件结合。
以上所述仅为本公开的优选实施例而已，并不用于限制本公开，对于本领域的技术人员来说，本公开可以有各种更改和变化。凡在本公开的原则之内，所作的任何修改、等同替换、改进等，均应包含在本公开的保护范围之内。

Claims (14)

  1. 一种多口存储器的数据读写方法，包括：
    将目标存储器拆分为多个子存储器，其中，每一个所述子存储器包括一个读端口和一个写端口；
    将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中。
  2. 根据权利要求1所述的方法，其中，所述将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中包括：
    确定所述多个待写入数据中每一个待写入数据将被写入的子存储器；
    在所述多个待写入数据将被写入到所述子存储器中的一个目标子存储器的情况下，将所述多个待写入数据中的一个待写入数据写入到所述目标子存储器中，同时将剩余的所述待写入数据写入到辅助存储器中，其中，所述辅助存储器为为所述目标存储器配置的存储器，所述辅助存储器用于存储剩余的所述待写入数据。
  3. 根据权利要求2所述的方法，其中，所述将剩余的所述待写入数据写入到辅助存储器中包括：
    将剩余的所述待写入数据中每一个待写入数据写入到一个所述辅助存储器中。
  4. 根据权利要求2所述的方法，其中，在将剩余的所述待写入数据写入到所述辅助存储器中之后，所述方法还包括：
    在所述辅助存储器中再次被写入数据前，将所述辅助存储器中的数据转移到所述目标子存储器中。
  5. 根据权利要求1所述的方法，其中，所述目标存储器为多个，每一个所述目标存储器被拆分为多个子存储器且配备有辅助存储器，所述将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中包括：
    将每一个所述目标存储器作为当前存储器，将所述多个待写入数据同时写入到所述当前存储器的所述多个子存储器中。
  6. 根据权利要求5所述的方法，其中，所述方法还包括：
    在从多个所述目标存储器中同时读取多个待读取数据的情况下，同时从每一个所述目标存储器中读取一个不同的待读取数据。
  7. 一种多口存储器的数据读写装置，包括：
    拆分单元，设置为将目标存储器拆分为多个子存储器，其中，每一个所述子存储器包括一个读端口和一个写端口；
    写入单元，设置为将多个待写入数据同时写入到所述目标存储器的所述多个子存储器中。
  8. 根据权利要求7所述的装置，其中，所述写入单元包括：
    确定模块，设置为确定所述多个待写入数据中每一个待写入数据将被写入的子存储器；
    第一写入模块，设置为在所述多个待写入数据将被写入到所述子存储器中的一个目标子存储器的情况下，将所述多个待写入数据中的一个待写入数据写入到所述目标子存储器中，同时将剩余的所述待写入数据写入到辅助存储器中，其中，所述辅助存储器为为所述目标存储器配置的存储器，所述辅助存储器用于存储剩余的所述待写入数据。
  9. 根据权利要求8所述的装置，其中，所述第一写入模块包括：
    写入子模块，设置为将剩余的所述待写入数据中每一个待写入数据写入到一个所述辅助存储器中。
  10. 根据权利要求8所述的装置，其中，所述写入单元还包括：
    转移模块，设置为在将剩余的所述待写入数据写入到所述辅助存储器中之后，在所述辅助存储器中再次被写入数据前，将所述辅助存储器中的数据转移到所述目标子存储器中。
  11. 根据权利要求7所述的装置，其中，所述目标存储器为多个，每一个所述目标存储器被拆分为多个子存储器且配备有辅助存储器，所述写入单元包括：
    第二写入模块，设置为将每一个所述目标存储器作为当前存储器，将所述多个待写入数据同时写入到所述当前存储器的所述多个子存储器中。
  12. 根据权利要求11所述的装置，其中，所述装置还包括：
    读取单元，设置为在从多个所述目标存储器中同时读取多个待读取数据的情况下，同时从每一个所述目标存储器中读取一个不同的待读取数据。
  13. 一种计算机可读存储介质，所述计算机可读存储介质中存储有计算机程序，其中，所述计算机程序被处理器执行时实现所述权利要求1至6任一项中所述的方法的步骤。
  14. 一种电子装置，包括存储器、处理器以及存储在所述存储器上并可在所述处理器上运行的计算机程序，所述处理器执行所述计算机程序时实现所述权利要求1至6任一项中所述的方法的步骤。
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