WO2023029393A1

WO2023029393A1 - Balanced detector and frequency modulation continuous wave radar

Info

Publication number: WO2023029393A1
Application number: PCT/CN2022/077585
Authority: WO
Inventors: 毛剑豪; 朱剑雄; 向少卿
Original assignee: 上海禾赛科技有限公司
Priority date: 2021-08-31
Filing date: 2022-02-24
Publication date: 2023-03-09
Also published as: CN115728723A

Abstract

A balanced detector and a frequency modulation continuous wave radar. The balanced detector comprises: a first detector (PD1), a second detector (PD2), an amplification unit (10) and a direct-current bypass, wherein a second end of the first detector (PD1) is coupled to a first end of the second detector (PD2); an input end of the amplification unit (10) is coupled to the second end of the first detector (PD1) and the first end of the second detector (PD2), and is coupled to the direct-current bypass; the direct-current bypass is adapted to guide direct-current components output by the first detector (PD1) and the second detector (PD2); and the direct-current components and the direct-current bypass form a loop, so as to stabilize a voltage at the input end of the amplification unit (10). By means of the above structure, the effect of unequal direct-current components of different detectors on a balanced detector can be prevented, thereby improving the signal-to-noise ratio of an output signal of the balanced detector.

Description

Balanced detector and FM continuous wave radar

This application claims the priority of the Chinese patent application with the application number 202111016005.X and the title of the invention "Balanced Detector and FM Continuous Wave Radar" filed with the China Patent Office on August 31, 2021, the entire contents of which are hereby incorporated by reference In this application.

technical field

The invention relates to the technical field of radar, in particular to a balanced detector and a frequency modulation continuous wave radar.

Background technique

According to the modulation and detection methods of the transmission link, laser communication and detection can be divided into two basic methods: coherent and non-coherent. Coherent laser communication/detection has the advantages of high conversion gain, full frequency and phase information, good filtering performance, and can be applied to the detection of weak signals. However, in coherent detection, the noise of the local oscillator, the relative intensity noise (Relative Intensity Noise, RIN) of the laser, the impact of shot noise and temperature difference still cannot be eliminated. In order to better utilize the optical power of the local oscillator, suppress the RIN, and further improve the system sensitivity, various balanced detectors based on coherent detection technology are widely used.

Referring to FIG. 1 , a schematic diagram of a conventional coherent detection of a balanced detector is shown. The local oscillator light Alo and the return light signal As are respectively introduced into the coupler by the waveguide, and Alo and As interfere in the coupler, and the light intensity of the coherent light can be expressed as

in

and

is the DC light component,

is an exchange-related item. The coupler outputs light, such as I1 and I2 shown in Figure 1, where the DC optical signals of I1 and I2 have equal amplitudes and opposite phases. I1 and I2 are respectively irradiated on the detector PD1 and detector PD2 to generate photocurrents i ₁ and i ₂ , wherein the DC components of i ₁ and i ₂ have the same magnitude and opposite direction, and can cancel each other out; the AC components have the same amplitude and opposite phase , the balanced detector outputs the differential value of the AC component of the photocurrent generated by the two detectors, thereby weakening the influence of common mode noise.

The basic structure of the balanced detector is to connect a transimpedance amplifier (Trans-Impedance Amplifier, TIA) to the output i in Fig. 1, and convert the difference between the photocurrent AC components output by the detector PD1 and the detector PD2 into a voltage output. However, the operating voltage of the TIA is usually low (generally below 5V), and due to the difference in the two-way light splitting of the coupler and the difference in the responsivity of the detector PD1 and the detector PD2, the current i ₁ generated by the detector PD1 The DC component of the current _i2 generated by the detector PD2 is different, so that the current input to the TIA contains a DC component, and there is a gap of about 100 μA between the DC component generated by the detector PD1 and the DC component generated by the detector PD2. If the gain of the TIA is 50K, when a DC current of 100μA is input to the TIA, a voltage of 5V will be generated, which will cause the TIA to be in a saturated state all the time, so that the balanced detector cannot output a valid signal.

In order to avoid the TIA being in a saturated state all the time, an existing balanced detector is shown in Fig. 2 . In FIG. 2 , the first terminal of the detector PD1 is connected to V+, the second terminal of the detector PD2 is connected to V-, and the amplitudes of V+ and V- are equal and opposite in phase. The balanced detector is amplified by a two-stage amplifying circuit. Taking the total gain of 50K as an example, the first-stage amplifying circuit adopts TIA with a gain of 2K, and the second stage uses an amplifying circuit with a gain of 25 times to achieve a total gain of 50K. Since the gain of the first-stage amplifying circuit is small, even if there is a DC component at its input, the amplified DC component will not cause the TIA to be in a saturated state. A DC blocking capacitor C is installed at the output of the first-stage amplifying circuit to filter out the DC component in the output of the first-stage amplifying circuit. At this time, the DC component input by the second-stage amplifying circuit is almost 0, which can be ignored.

However, the balanced detector adopting two-stage amplifying circuits will amplify the noise of both amplifying circuits, and the signal-to-noise ratio of the output signal of the balanced detector is low.

Contents of the invention

One of the objectives of the embodiments of the present invention is to improve the signal-to-noise ratio of the output signal of the balanced detector while avoiding the influence of the unequal DC components of the two detectors on the balanced detector.

To achieve the above object, an embodiment of the present invention provides a balanced detector, including: a first detector, a second detector, an amplification unit, and a DC bypass, wherein: the second end of the first detector is connected to the The first end of the second detector is coupled; the input end of the amplifying unit is coupled to the second end of the first detector and the first end of the second detector, and is bypassed with the DC coupling; the DC bypass is adapted to guide the DC components of the output of the first detector and the second detector; the DC component forms a loop with the DC bypass to stabilize the input of the amplification unit terminal voltage.

Optionally, the second terminal of the first detector outputs a first DC component directed to the input terminal of the amplifying unit, and the first terminal of the second detector outputs a second DC component directed to its first terminal, The direction of the first DC component is opposite to that of the second DC component; when the first DC component is greater than the second DC component, the compensation voltage of the DC bypass decreases; when the first DC component When the DC component is smaller than the second DC component, the compensation voltage of the DC bypass increases.

Optionally, the DC bypass includes a seventh resistor and a compensation module; when the first DC component is greater than the second DC component, the compensation voltage at the output end of the compensation module decreases; when the first DC component When a DC component is smaller than the second DC component, the compensation voltage at the output terminal of the compensation module increases.

Optionally, the amplifying unit includes a first differential amplifier; the compensation module includes an integrating circuit; the first input terminal of the integrating circuit is coupled to the first output terminal of the first differential amplifier, and the second The input terminal is coupled to the second output terminal of the first differential amplifier, and the output terminal thereof is coupled to the seventh resistor.

Optionally, the integration circuit includes: a first integration unit, a first integration capacitor, and a second integration capacitor, wherein: the first integration unit, its first input terminal is connected to the first output of the first differential amplifier terminal, its second input terminal is coupled to the second output terminal of the first differential amplifier, and its output terminal is coupled to the first terminal of the seventh resistor; the first integrating capacitor, its first terminal is coupled to the first input terminal of the first integration unit, and its second terminal is grounded; the first terminal of the second integration capacitor is coupled to the second input terminal of the first integration unit, and its second terminal is coupled to the second input terminal of the first integration unit. The two terminals are coupled to the output terminal of the second integrating capacitor.

Optionally, the first output terminal of the first differential amplifier is a positive output terminal, the second output terminal of the first differential amplifier is a negative output terminal; the first input terminal of the first integration unit is The positive input terminal, the second input terminal of the first integrating unit is a negative input terminal.

Optionally, the first end of the seventh resistor is coupled to the output end of the compensation module, and the second end is coupled to the input end of the amplification unit.

Optionally, a first end of the DC bypass is coupled to the input end of the amplifying unit, and a second end thereof is grounded.

Optionally, when the first DC component is greater than the second DC component, the DC bypass guides the DC component to form a loop with the second end of the DC bypass.

Optionally, the DC bypass includes: a third DC blocking capacitor and a sixth resistor, wherein: the first terminal of the third DC blocking capacitor is connected to the second terminal of the first detector, the The first end of the second detector is coupled, and its second end is coupled to the input end of the amplifying unit; the first end of the sixth resistor is coupled to the first end of the third DC blocking capacitor. , the second end of which is grounded.

Optionally, the balance detector further includes: a first DC blocking capacitor and a second DC blocking capacitor, wherein: the first terminal of the first DC blocking capacitor is coupled to the first output terminal of the amplification unit , the second end of which is coupled to the first output end of the balanced detector; the second DC blocking capacitor, whose first end is coupled to the second output end of the amplifying unit, and whose second end is coupled to the The second output terminal of the balance detector is coupled.

Optionally, the balanced detector further includes: a buffer circuit coupled to the amplifying unit.

Optionally, the buffer circuit includes: a buffer unit, a first feedback unit, and a second feedback unit, wherein: the first input end of the buffer unit is coupled to the first end of the first feedback unit, Its first output end is coupled to the second end of the first feedback unit, its second input end is coupled to the first end of the second feedback unit, and its second output end is coupled to the second feedback unit The second end is coupled.

Optionally, the first feedback unit includes a first compensation capacitor and a first feedback resistor, wherein: the first end of the first compensation capacitor is coupled to the first end of the first feedback unit, and its The second end is coupled to the second end of the first feedback unit; the first end of the first feedback resistor is coupled to the first end of the first compensation capacitor, and the second end thereof is connected to the first end of the first compensation capacitor. The second end of a compensation capacitor is coupled.

Optionally, the second feedback unit includes a second compensation capacitor and a second feedback resistor, wherein: the first end of the second compensation capacitor is coupled to the first end of the second feedback unit, and its The second terminal is coupled to the second terminal of the second feedback unit; the first terminal of the second feedback resistor is coupled to the first terminal of the second compensation capacitor, and the second terminal is coupled to the first terminal of the second compensation capacitor. The second terminals of the two compensation capacitors are coupled.

Optionally, the buffer circuit further includes: a fourth resistor and a fifth resistor, wherein: the first terminal of the fourth resistor is coupled to the first output terminal of the amplifying unit, and the second terminal of the fourth resistor is coupled to the first output terminal of the amplifying unit. The first input end of the buffer unit is coupled; the fifth resistor, its first end is coupled to the second output end of the amplification unit, and its second end is coupled to the second input end of the buffer unit .

Optionally, the buffer unit includes a second differential amplifier.

An embodiment of the present invention also provides a frequency-modulated continuous wave radar, including: a light source, a beam splitter, a mixer, and any one of the balance detectors described above, wherein: the light source is suitable for emitting light, and the light It is a frequency-modulated continuous laser; the beam splitter is suitable for separating the local oscillator light and the probe light from the light; the mixer is suitable for combining the echo light and the local oscillator light of the probe light reflected by obstacles The beat frequency light signal is obtained by mixing; the balance detector is suitable for receiving the beat frequency light signal and converting it into an electrical signal.

Compared with the prior art, the technical solutions of the embodiments of the present invention have the following beneficial effects:

The DC bypass is coupled to the input end of the amplifying unit. By setting the DC bypass, the DC components output by the first detector and the second detector are guided, so that the DC component and the DC bypass form a loop, thereby ensuring the input of the amplifying unit. The voltage at the terminal is stable so that the amplifying unit is not affected by the DC component. Therefore, only one stage of amplification unit needs to be provided in the balanced detector, so the signal-to-noise ratio of the output signal of the balanced detector is high.

Further, the two differential output terminals of the first differential amplifier are respectively coupled to the two input terminals of the first integration unit, the input terminals of the first differential amplifier are coupled to the output terminals of the first integration unit, and the The voltage difference output by the two differential output terminals of the first differential amplifier is fed back to the input terminal of the first differential amplifier, so as to guide the direction of the first DC component and the second DC component, and ensure the voltage stability of the input terminal of the first differential amplifier.

In addition, a buffer circuit is provided, which can limit the output bandwidth of the amplifying unit, reduce the amplitude of out-of-band output signals, increase system stability and attenuate unnecessary interference signals.

Description of drawings

Fig. 1 is the coherent detection principle diagram of existing a kind of balanced detector;

Fig. 2 is the structural representation of existing a kind of balance detector;

Fig. 3 is a schematic structural view of a balanced detector in an embodiment of the present invention;

Fig. 4 is the working principle diagram of a kind of balance detector in the embodiment of the present invention;

Fig. 5 is the working principle diagram of another kind of balance detector in the embodiment of the present invention;

Fig. 6 is a schematic structural diagram of another balanced detector in an embodiment of the present invention;

Fig. 7 is a schematic structural diagram of another balanced detector in an embodiment of the present invention;

Fig. 8 is a schematic structural diagram of another balanced detector in an embodiment of the present invention;

Fig. 9 is a schematic structural diagram of another balanced detector in an embodiment of the present invention;

Fig. 10 is a schematic structural diagram of a frequency modulation continuous wave radar in an embodiment of the present invention.

Detailed ways

As mentioned in the background art above, in the prior art, the signal-to-noise ratio of the output signal of the balanced detector using two-stage TIA is low.

In the embodiment of the present invention, the DC bypass is coupled to the input end of the amplifying unit, and by setting the DC bypass, the DC components output by the first detector and the second detector are guided, so that the DC components and the DC bypass form a The loop ensures the stability of the voltage at the input end of the amplifying unit, so that the amplifying unit is not affected by the DC component. Therefore, only one stage of amplification unit needs to be provided in the balanced detector, so the signal-to-noise ratio of the output signal of the balanced detector is high.

In order to make the above objects, features and beneficial effects of the present invention more comprehensible, specific embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings.

An embodiment of the present invention provides a balanced detector, and the balanced detector provided in the embodiment of the present invention will be described in detail below.

In a specific implementation, the balanced detector may include a first detector, a second detector, an amplification unit, and a DC bypass.

In the embodiment of the present invention, the first end of the first detector can be connected to the first power supply, the second end of the second detector can be connected to the second power supply, and the second end of the first detector can be connected to the second end of the second detector. One end is coupled. The output voltage of the first power supply is equal to and opposite to the output voltage of the second power supply.

The input terminal of the amplifying unit can be coupled with the second terminal of the first detector and the first terminal of the second detector, and be coupled with the DC bypass.

The DC bypass can guide the DC component output by the first detector and the DC component output by the second detector, and the DC component can form a loop with the DC bypass, thereby stabilizing the voltage at the input end of the amplifying unit.

In the embodiment of the present invention, the second terminal of the first detector outputs the first DC component, and the first DC component is directed to the input terminal of the amplifying unit. That is to say, the second terminal of the first detector outputs the first DC component, and the first DC component is output to the input terminal of the amplifying unit. The first end of the second detector outputs a second DC component, and the second DC component points to the first end of the second detector. When the first DC component is greater than the second DC component, the compensation voltage of the DC bypass decreases; otherwise, when the first DC component is smaller than the second DC component, the compensation voltage of the DC bypass increases.

In the embodiment of the present invention, the DC bypass may include a seventh resistor and a compensation module. The input terminal of the compensation module is coupled to the output terminal of the amplifying unit, and the output terminal of the compensation module is coupled to the seventh resistor. The seventh resistor can be coupled between the compensation module and the input end of the amplifying unit.

Preferably, when the first DC component is greater than the second DC component, the compensation voltage output by the output terminal of the compensation module decreases; more preferably, when the first DC component is smaller than the second DC component, the output terminal of the compensation module outputs The compensation voltage rises.

The structure of the above balance detector will be described in detail below. Referring to FIG. 3 , it shows a circuit structure diagram of a balanced detector in an embodiment of the present invention.

In the embodiment of the present invention, the first end of the first detector PD1 is connected to the first power supply, the second end of the first detector PD1 is coupled to the first end of the second detector PD2, and the output voltage of the first power supply is V1; the second terminal of the second detector PD2 is connected to the second power supply, and the output voltage of the second power supply is V2.

In a specific embodiment of the present invention, V1-V2 can make the first detector PD1 and the second detector PD2 respectively work in a linear state.

The output voltage V1 of the first power supply may be in reverse phase to the output voltage V2 of the second power supply, and the amplitude of V1 is equal to V2. Alternatively, the output voltage V1 of the first power supply can be in reverse phase to the output voltage V2 of the second power supply, but the amplitude of V1 is not equal to that of V2.

The amplifying unit includes a first differential amplifier 10, and the first differential amplifier 10 includes an input terminal, a first output terminal OUT+ and a second output terminal OUT−. In the DC bypass, the compensation module includes an integrating circuit. The integrating circuit includes a first integrating unit 20 , a first integrating capacitor C11 and a second integrating capacitor C12 .

The input terminal of the first differential amplifier 10 can be coupled with the second terminal of the first detector PD1 and the first terminal of the second detector PD2; the first output terminal OUT+ of the first differential amplifier 10 is the The positive output terminal is coupled to the first input terminal of the first integration unit 20; the second output terminal OUT- of the first differential amplifier 10 is the negative output terminal of the first differential amplifier 10, and is connected to the first integration unit 20 The second input end is coupled.

The first input terminal of the first integration unit 20 is the positive input terminal "+" of the first integration unit, and the second input terminal of the first integration unit 20 is the negative input terminal "-" of the second integration unit.

The output terminal of the first integrating unit 20 is coupled to the first terminal of the seventh resistor R7, and the second terminal of the seventh resistor R7 is coupled to the input terminal of the first differential amplifier 10.

A first terminal of the first integrating capacitor C11 is coupled to the first input terminal of the first integrating unit 20 , and a second terminal of the first integrating capacitor C11 is grounded.

A first terminal of the second integrating capacitor C12 is coupled to the second input terminal of the first integrating unit 20 , and a second terminal of the second integrating capacitor C12 is coupled to the output terminal of the second integrating unit.

In a specific implementation, the DC bypass may also include a first resistor R21 and a second resistor R22, wherein: the first end of the first resistor R21 is coupled to the first output end of the first differential amplifier 10, and the first end of the first resistor R21 The second terminal is coupled to the first input terminal of the first integrating unit 20, and the first terminal of the first integrating capacitor C11 is coupled to the second terminal of the first resistor R21; the first terminal of the second resistor R22 is coupled to the first terminal of the first integrating capacitor C11. The second output end of the differential amplifier 10 is coupled, the second end of the second resistor R22 is coupled to the second input end of the first integrating unit 20, and the first end of the second integrating capacitor C12 is connected to the first end of the second resistor R22. Two-terminal coupling.

The working principle of the balanced detector provided in FIG. 3 will be described below with reference to FIGS. 4 to 5 .

In a specific implementation, the output currents of the first detector PD1 and the second detector PD2 respectively include a DC component and an AC component. For the convenience of describing the technical solution of the present invention, only the DC component will be described below.

The direct current output by the first detector PD1 includes the first direct current component, the direct current output by the second detector PD2 includes the second direct current component, and the direction of the first direct current component and the second direct current component are the same, both of which are V1 pointing to V2 direction.

If the first DC component is greater than the second DC component, then in the total output current of the first detector PD1 and the second detector PD2, there is a DC component directed towards the input terminal of the first differential amplifier 10, at this time, the first differential amplifier The output voltage of the positive output terminal of 10 decreases, and the output voltage of the negative output terminal of the first differential amplifier 10 is greater than the output voltage of its positive output terminal, that is: the input voltage of the negative input terminal of the first integration unit 20 is greater than the first The input voltage of the positive input terminal of the integrating unit 20 .

When the input voltage of the negative input terminal of the first integration unit 20 was greater than the input voltage of its positive input terminal, the output voltage of the first integration unit 20 decreased, and the voltage at point B (i.e. the output terminal of the first integration unit 20) was less than A Point (that is, the input terminal of the first differential amplifier 10), so as shown in _FIG . end guide to form the compensation loop shown in Figure 4 i ₁ (that is, the total output DC current is guided from point A to point B).

Conversely, if the first DC component<the second DC component, then in the total output current of the first detector PD1 and the second detector PD2, there is a DC component whose direction is opposite to that of the first differential amplifier 10. At this time, the second The output voltage of the positive output terminal of a differential amplifier 10 increases, and the output voltage of the positive output terminal of the first differential amplifier 10 is greater than the output voltage of its negative output terminal, that is: the input voltage of the positive input terminal of the first integration unit 20 is greater than The input voltage of the negative input terminal of the first integration unit 20 .

Referring to FIG. 5 , if the DC bypass is not used, a DC component i ₂ ′ directed from the input terminal of the first differential amplifier 10 to PD2 will be generated, causing the voltage at the input terminal of the first differential amplifier 10 to change.

With the DC bypass of the present invention, when the input voltage of the positive input terminal of the first integration unit 20 is greater than the input voltage of the negative input terminal of the first integration unit 20, the output terminal voltage of the first integration unit 20 rises, point B The voltage is higher than the voltage at point A, so that the total output DC current of the first detector PD1 and the second detector PD2 is guided to the input end of the first differential amplifier 10, forming a compensation loop shown in _i2 in FIG. 5, ( That is, the total output current is guided from point B to point A).

If the first DC component is equal to the second DC component, there is no DC component in the total output current of the first detector PD1 and the second detector PD2, and the output voltage amplitude of the positive output terminal of the first differential amplifier 10 is the same as The voltage amplitudes output to the negative output terminals are equal, and the output terminal of the first integration unit 20 outputs stably. At this time, the voltage at point B is the same as that at point A.

It can be seen that through the above-mentioned DC bypass, no matter whether the total output DC current is directed from point B to point A or from point A to point B, it can be compensated through the DC bypass, so that the voltage at the input terminal of the first differential amplifier 10 remains Stablize. No matter how the output currents of the two detectors change, the voltage at the input terminal of the first differential amplifier 10 can always be stabilized at the initial set voltage, and will not fluctuate due to the influence of the total output DC current of the two detectors. Therefore, the first differential amplifier 10 will not be saturated due to the DC component in the total output current of the two detectors, so that AC information can be output stably and reliably during detection.

In the embodiment of the present invention, the first end of the DC bypass may also be coupled to the input end of the amplifying unit, and the second end of the DC bypass is grounded. When the first DC component is greater than the second DC component, the DC bypass can guide the DC component to form a loop with the second end of the DC bypass, thereby stabilizing the voltage at the input end of the amplifying unit.

Referring to FIG. 6 , a schematic structural diagram of another balanced detector in an embodiment of the present invention is shown.

The DC bypass may include a third DC blocking capacitor C23 and a sixth resistor R26, wherein:

The first end of the third DC blocking capacitor C23 is coupled to the second end of the first detector PD1 and the first end of the second detector PD2, and the second end of the third DC blocking capacitor C23 is connected to the input end of the amplification unit 10 coupling;

A first end of the sixth resistor R26 is coupled to a first end of the third DC blocking capacitor C23, and a second end of the sixth resistor R26 is grounded.

By setting the third DC-blocking capacitor C23 , it can play a role of DC-blocking and prevent the DC component from being input to the amplifying unit 10 . The sixth resistor R26 is used to conduct direct current.

When the first DC component is greater than the second DC component, there is a DC component directed toward the input terminal of the first differential amplifier 10 in the total output current of the first detector PD1 and the second detector PD2. The aforementioned DC component towards the input terminal of the first differential amplifier 10 is guided to the ground through the DC bypass, so as to keep the voltage at the input terminal of the first differential amplifier 10 stable.

In a specific implementation, the balanced detector may further include a buffer circuit. The buffer circuit can be coupled to the output terminal of the amplifying unit to limit the output bandwidth of the amplifying unit within a preset bandwidth range.

Referring to FIG. 7 , it shows a schematic structural diagram of another balanced detector in an embodiment of the present invention.

In a specific implementation, the buffer circuit may include a buffer unit 30 , a first feedback unit and a second feedback unit. In an embodiment of the present invention, the buffer unit 30 may be a second differential amplifier.

In the embodiment of the present invention, the first input end of the buffer unit 30 is coupled to the first end of the first feedback unit, the second input end of the buffer unit 30 is coupled to the first end of the second feedback unit, and the buffer unit 30 The first output end of the buffer unit 30 is coupled to the second end of the first feedback unit, and the second output end of the buffer unit 30 is coupled to the second end of the second feedback unit.

Specifically, the first input terminal of the buffer unit 30 is a positive input terminal, and the second input terminal is a negative input terminal.

Specifically, the first output end of the buffer unit 30 serves as the first output end of the balance detector, and the second output end of the buffer unit 30 serves as the second output end of the balance detector.

In the embodiment of the present invention, the first feedback unit may include a first compensation capacitor C31 and a first feedback resistor R31, wherein:

The first end of the first compensation capacitor C31 is coupled to the first end of the first feedback unit, and the second end of the first compensation capacitor C31 is coupled to the second end of the first feedback unit;

The first end of the first feedback resistor R31 is coupled to the first end of the first compensation capacitor C31, and the second end of the first feedback resistor R31 is coupled to the second end of the first compensation capacitor C31.

It can be seen from FIG. 7 that the first compensation capacitor C31 and the first feedback resistor R31 are connected in parallel.

In the embodiment of the present invention, the second feedback unit may include a second compensation capacitor C32 and a second feedback resistor R32, wherein:

The first end of the second compensation capacitor C32 is coupled to the first end of the second feedback unit, and the second end of the second compensation capacitor C32 is coupled to the second end of the second feedback unit;

The first end of the second feedback resistor R32 is coupled to the first end of the second compensation capacitor C32, and the second end of the second feedback resistor R32 is coupled to the second end of the second compensation capacitor C32.

It can be seen from FIG. 7 that the second compensation capacitor C32 and the second feedback resistor R32 are connected in parallel.

In the embodiment of the present invention, the system bandwidth can be limited within a certain range through the bandwidth limiting circuit, and the corresponding high frequency cutoff frequency f can be approximated as:

Wherein, the capacitance values of the first compensation capacitor and the second compensation capacitor are equal, and C is the capacitance value of the first compensation capacitor C31/the second compensation capacitor C32; the resistance value of the first feedback resistor is equal to the resistance value of the second feedback resistor, R is the resistance value of the first feedback resistor R331/the second feedback resistor R32.

By setting the buffer circuit, the system bandwidth can be limited, the out-of-band output signal amplitude can be reduced, the system stability can be increased, and unnecessary interference signals can be attenuated. Further, by selecting different capacitance values C, the high-frequency cutoff frequency of the bandwidth limiting circuit can be adjusted to adjust the system bandwidth. In addition, the buffer circuit can also play a buffer role, so that the output level of the balanced detector matches the sampling circuit of the subsequent stage.

In a specific implementation, the buffer circuit may further include a fourth resistor R24 and a fifth resistor R25, wherein:

The first terminal of the fourth resistor R24 is coupled to the first output terminal of the first differential amplifier 10, and the second terminal of the fourth resistor R24 is coupled to the first input terminal of the buffer unit 30;

A first end of the fifth resistor R25 is coupled to the second output end of the first differential amplifier 10 , and a second end of the fifth resistor R25 is coupled to the second input end of the buffer unit 30 .

Continuing to refer to FIG. 7 , in a specific implementation, the balanced detector further includes a third resistor R23 . The third resistor R23 can perform impedance matching between the first differential amplifier 10 and the buffer unit 30 .

In a specific implementation, the balanced detector may also include a first DC blocking capacitor and a second DC blocking capacitor, wherein:

The first end of the first DC blocking capacitor is coupled to the first output end of the amplifying unit, and the second end of the first DC blocking capacitor is used as the first output end of the balance detector;

The first end of the second DC blocking capacitor is coupled to the second output end of the amplifying unit, and the second end of the second DC blocking capacitor serves as the second output end of the balance detector.

By setting the first DC-blocking capacitor and the second DC-blocking capacitor, the DC levels in the output signals of the two output ends of the amplifying unit can be isolated, and the influence of the DC level on the buffer circuit and the subsequent sampling circuit can be eliminated.

Referring to FIG. 8 , a schematic structural diagram of another balanced detector in an embodiment of the present invention is shown.

In FIG. 8, the balanced detector may further include a first DC blocking capacitor C21 and a second DC blocking capacitor C22, wherein:

The first end of the first DC blocking capacitor C21 is coupled to the first output terminal OUT+ of the first differential amplifier 10, and the second end of the first DC blocking capacitor C21 is used as the first output end of the balance detector; the second DC blocking capacitor The first terminal of C22 is coupled to the second output terminal OUT- of the first differential amplifier 10 , and the second terminal of the second DC blocking capacitor C22 is used as the second output terminal of the balanced detector.

Referring to FIG. 9 , it shows a schematic structural diagram of another balanced detector in an embodiment of the present invention. Compared with FIG. 7 , in FIG. 9 , the first DC blocking capacitor C21 and the second DC blocking capacitor C2 are added on the basis of FIG. 7 .

To sum up, in the embodiment of the present invention, the DC bypass is coupled to the input end of the amplifying unit, and by setting the DC bypass, the DC components output by the first detector and the second detector are guided, so that the DC components and The DC bypass forms a loop, thereby ensuring the stability of the voltage at the input end of the amplifying unit, so that the amplifying unit is not affected by the DC component. Therefore, only one stage of amplification unit needs to be provided in the balanced detector, so the signal-to-noise ratio of the output signal of the balanced detector is high.

Referring to FIG. 10 , it shows a schematic structural diagram of a frequency modulation continuous wave radar in an embodiment of the present invention. The frequency modulated continuous wave radar may include: a light source 110, a beam splitter 120, a mixer 150, and a balanced detector 160, wherein:

The light source 110 is suitable for emitting light, and the light is a frequency-modulated continuous laser;

The beam splitter 120 is adapted to separate local oscillator light and probe light from the light;

The mixer 150 is adapted to mix the echo light reflected by the obstacle with the local oscillator light to obtain a beat frequency light signal;

The balance detector 160 is adapted to receive the beat frequency optical signal and convert it into an electrical signal.

In the embodiment of the present invention, the mixer 150 may specifically be the coupler in FIG. 1 , the local oscillator light and the echo light are mixed in the coupler to obtain the beat frequency optical signal, and the coupler converts the beat frequency optical signal at a ratio of 50:50 The output of the splitting ratio can obtain two beams of light with the same amplitude and opposite phase. The specific structure of the optical balance detector 160 can refer to the optical balance detection provided by the above-mentioned embodiments of the present invention. The two beams of light output by the coupler are respectively received by the first detector PD1 and the second detector PD2, and converted into electrical signals, which are received by the first detector PD1 and the second detector PD2 respectively. The output of the amplification unit will not be described here.

In the embodiment of the present invention, the FM CW radar further includes an amplifier 130. As shown in FIG. 10, the amplifier 130 is coupled to the downstream of the optical path of the optical splitter 120 to amplify the detection light output by the optical splitter 120, thereby increasing the detection light power, Improve the range finding capability of the radar. In other embodiments of the present invention, the amplifier 130 may be coupled between the light source 110 and the beam splitter 120 to amplify the light emitted by the light source, and then separate the local oscillator light and the probe light.

In the embodiment of the present invention, the frequency-modulated continuous wave radar is a coaxial radar, that is, the detection light and the echo light can share an optical system (not shown in the figure), and the optical system is, for example, a collimating lens or a lens group. The frequency-modulated continuous wave radar further includes an isolation The device 140 is suitable for isolating the transmitting and receiving optical circuits. After being amplified, the detection light is input from the first port of the isolator 140 and output from the second port, and then emitted after being collimated by the optical system; the echo light reflected by the obstacle is received by the radar, focused by the optical system and then input through the second port The isolator 140. The isolator 140 outputs the echo light from the third port, so as to isolate the echo optical path from the detection optical path. The echo light output from the third port and the local oscillator light output from the optical splitter 120 are input into the mixer 150 to obtain a beat frequency optical signal.

The isolator 140 is not limited to the circulator shown in FIG. 10 , and may be other optical isolation devices.

The frequency modulation continuous wave radar of the present invention adopts the balanced detector provided by the embodiment of the present invention to guide the DC components output by the first detector and the second detector, so that the DC component and the DC bypass form a loop, thereby ensuring the amplification The voltage at the cell input is stable. Even if there is a splitting difference in the mixer 150 and there is a DC component in the total output current of the two detectors, the voltage at the input terminal of the amplifying unit is not affected by the DC component and can be stabilized at the initial set voltage, thereby stably and accurately Output AC signal. Furthermore, the frequency modulation continuous wave radar of the present invention can obtain obstacle distance and speed information after processing and calculation according to the communication information in the beat frequency optical signal, and has high detection accuracy.

Although the present invention is disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, so the protection scope of the present invention should be based on the scope defined in the claims.

Claims

A balanced detector, characterized in that it includes: a first detector, a second detector, an amplification unit, and a DC bypass, wherein:

The second end of the first detector is coupled to the first end of the second detector;

The input terminal of the amplifying unit is coupled to the second terminal of the first detector and the first terminal of the second detector, and is coupled to the DC bypass;

The DC bypass is adapted to guide the DC components output by the first detector and the second detector; the DC component forms a loop with the DC bypass to stabilize the voltage at the input terminal of the amplifying unit.
The balanced detector according to claim 1, wherein the second terminal of the first detector outputs the first DC component directed to the input terminal of the amplifying unit, and the first terminal of the second detector outputs The second DC component pointing to its first end, the direction of the first DC component is opposite to the direction of the second DC component; when the first DC component is greater than the second DC component, the DC bypass The compensation voltage of the bypass circuit decreases; when the first DC component is smaller than the second DC component, the compensation voltage of the DC bypass increases.
The balance detector according to claim 2, wherein the DC bypass includes a seventh resistor and a compensation module; when the first DC component is greater than the second DC component, the compensation module outputs The compensation voltage at the terminal decreases; when the first DC component is smaller than the second DC component, the compensation voltage at the output terminal of the compensation module increases.
The balance detector according to claim 3, wherein the amplifying unit includes a first differential amplifier; the compensation module includes an integrating circuit; and the integrating circuit has a first input terminal connected to the first differential amplifier. The first output terminal is coupled to the first differential amplifier, the second input terminal is coupled to the second output terminal of the first differential amplifier, and the output terminal is coupled to the seventh resistor.
The balance detector according to claim 4, wherein the integrating circuit comprises: a first integrating unit, a first integrating capacitor and a second integrating capacitor, wherein:

The first integrating unit has its first input terminal coupled to the first output terminal of the first differential amplifier, its second input terminal coupled to the second output terminal of the first differential amplifier, and its output terminal coupled with the first end of the seventh resistor;

The first integration capacitor has a first terminal coupled to the first input terminal of the first integration unit, and a second terminal connected to ground;

The first end of the second integration capacitor is coupled to the second input end of the first integration unit, and the second end is coupled to the output end of the second integration capacitor.
The balanced detector according to claim 5, wherein the first output terminal of the first differential amplifier is a positive output terminal, and the second output terminal of the first differential amplifier is a negative output terminal; The first input terminal of the first integration unit is a positive input terminal, and the second input terminal of the first integration unit is a negative input terminal.
The balanced detector according to any one of claims 3 to 6, characterized in that, the first end of the seventh resistor is coupled to the output end of the compensation module, and the second end is coupled to the amplifying unit. The input terminal is coupled.
The balanced detector according to claim 2, characterized in that, the first end of the DC bypass is coupled to the input end of the amplification unit, and the second end thereof is grounded.
The balance detector according to claim 8, wherein when the first direct current component is greater than the second direct current component, the direct current bypass guides the direct current component and the second direct current component of the direct current bypass ends form a loop.
The balanced detector according to claim 9, wherein the DC bypass includes: a third DC blocking capacitor and a sixth resistor, wherein:

The first end of the third blocking capacitor is coupled to the second end of the first detector and the first end of the second detector, and the second end is coupled to the input end of the amplification unit. catch;

The first end of the sixth resistor is coupled to the first end of the third DC blocking capacitor, and the second end thereof is grounded.
The balance detector according to claim 1, further comprising: a first DC blocking capacitor and a second DC blocking capacitor, wherein:

The first DC-blocking capacitor has its first terminal coupled to the first output terminal of the amplifying unit, and its second terminal coupled to the first output terminal of the balance detector;

The first end of the second DC blocking capacitor is coupled to the second output end of the amplifying unit, and the second end is coupled to the second output end of the balance detector.
The balanced detector according to claim 1, further comprising: a buffer circuit coupled to the amplifying unit.
The balance detector according to claim 12, wherein the buffer circuit comprises: a buffer unit, a first feedback unit and a second feedback unit, wherein:

The first input end of the buffer unit is coupled to the first end of the first feedback unit, the first output end is coupled to the second end of the first feedback unit, and the second input end is coupled to the first feedback unit. The first terminal of the second feedback unit is coupled, and the second output terminal thereof is coupled to the second terminal of the second feedback unit.
The balance detector according to claim 13, wherein the first feedback unit includes a first compensation capacitor and a first feedback resistor, wherein:

The first compensation capacitor has its first end coupled to the first end of the first feedback unit, and its second end coupled to the second end of the first feedback unit;

The first end of the first feedback resistor is coupled to the first end of the first compensation capacitor, and the second end thereof is coupled to the second end of the first compensation capacitor.
The balance detector according to claim 13, wherein the second feedback unit includes a second compensation capacitor and a second feedback resistor, wherein:

The first end of the second compensation capacitor is coupled to the first end of the second feedback unit, and the second end is coupled to the second end of the second feedback unit;

The first end of the second feedback resistor is coupled to the first end of the second compensation capacitor, and the second end is coupled to the second end of the second compensation capacitor.
The balanced detector according to claim 13, wherein the buffer circuit further comprises: a fourth resistor and a fifth resistor, wherein:

The first end of the fourth resistor is coupled to the first output end of the amplification unit, and the second end is coupled to the first input end of the buffer unit;

The first end of the fifth resistor is coupled to the second output end of the amplification unit, and the second end is coupled to the second input end of the buffer unit.
13. The balanced detector of claim 13, wherein said buffer unit includes a second differential amplifier.
A frequency-modulated continuous wave radar, characterized in that it includes: a light source, a beam splitter, a mixer, and a balanced detector according to any one of claims 1 to 17, wherein:

The light source is suitable for emitting light, and the light is a frequency-modulated continuous laser;

said beam splitter adapted to separate local oscillator light and probe light from said light;

The mixer is adapted to mix the echo light reflected by the obstacle with the local oscillator light to obtain a beat frequency light signal;

The balanced detector is adapted to receive the beat frequency optical signal and convert it into an electrical signal.