WO2023029059A1 - Procédé d'élimination du silicium polycristallin plaqué sur la face arrière d'une batterie n-topcon - Google Patents

Procédé d'élimination du silicium polycristallin plaqué sur la face arrière d'une batterie n-topcon Download PDF

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WO2023029059A1
WO2023029059A1 PCT/CN2021/116811 CN2021116811W WO2023029059A1 WO 2023029059 A1 WO2023029059 A1 WO 2023029059A1 CN 2021116811 W CN2021116811 W CN 2021116811W WO 2023029059 A1 WO2023029059 A1 WO 2023029059A1
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phosphorus
silicon wafer
silicon
amorphous silicon
polysilicon
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PCT/CN2021/116811
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English (en)
Chinese (zh)
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廖晖
赵文祥
王文睿
杜振星
何胜
徐伟智
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正泰新能科技有限公司
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Publication of WO2023029059A1 publication Critical patent/WO2023029059A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to the technical field of N-TOPCon batteries, in particular to a method for removing polysilicon plating around N-TOPCon batteries.
  • N-type tunneling oxide passivation contact (N-TOPCon) battery refers to a type of battery that is passivated by tunneling oxide layer and doped polysilicon.
  • the passivation mechanism is: ultra-thin silicon oxide is directly in contact with the silicon substrate , neutralize the dangling bonds on the silicon surface, and perform excellent chemical passivation: due to the difference in the Fermi level between the heavily doped polysilicon layer and the silicon substrate, the energy band bends on the surface of the silicon substrate, which can more effectively block the minority carrier. By doing so, the selective collection of carriers is achieved without affecting the transport of many carriers.
  • N-TOPCon batteries Compared with traditional PERC batteries, N-TOPCon batteries have a full-area passivation of the back surface, without direct contact between metal and silicon, which is conducive to improving the short-circuit voltage of the battery, comprehensively collecting carriers, reducing life sensitivity, and benefiting Increasing the fill factor will play a positive role in promoting industrial upgrading.
  • N-TOPCon cells In the preparation process of N-TOPCon cells, it is usually used to deposit intrinsic amorphous silicon first, and then perform phosphorus-doped annealing on the amorphous silicon to form doped polysilicon.
  • APCVD/ Intrinsic amorphous silicon deposited by LPCVD method often has a certain width of surrounding amorphous silicon on the front side, which is transformed into polysilicon after phosphorus-doped annealing. Since the polysilicon layer has a high light absorption coefficient, once it appears on the front side of the cell, it will be It affects the absorption of sunlight on the front of the battery, and the conductivity of polysilicon will cause serious leakage at the edge of the battery. Therefore, dewinding plating is required during the preparation of N-TOPCon batteries.
  • patent CN202010667851.7 discloses a removal method and application of TOPCon battery wrap-around polysilicon, wherein the method of removing wrap-around plating is: after phosphorus diffusion annealing crystallizes the amorphous silicon layer into a phosphorus-doped polysilicon layer, uses hydrofluoric acid The PSG on the surface of the coated polysilicon layer on the front and side of the silicon substrate is removed by floating in water, and then the coated polysilicon layer on the front and side of the silicon substrate is removed by etching with an alkaline solution.
  • this method can remove the surrounding polysilicon and prevent it from affecting the performance of the battery, it also has the following problems: in the process of phosphorus deposition after the deposition of amorphous silicon, the width of the surrounding plating of phosphorus diffused on the front side of the silicon wafer is often larger than that of amorphous silicon. Therefore, a P-BSG-rich region with a certain width will be formed in the contact area between amorphous silicon and borosilicate glass (BSG), that is, a borophosphosilicate glass (BPSG) region. It is severely corroded by hydrofluoric acid and lye, affecting the appearance of the battery and adversely affecting battery performance (including short-circuit current, open-circuit voltage, fill factor and battery efficiency).
  • BSG borosilicate glass
  • the present invention provides a method for removing polysilicon plating around an N-TOPCon battery.
  • the method can prevent the BPSG area on the front side of the silicon wafer from being corroded during the dewinding plating by adding the BPSG corrosion-resistant treatment step before the dewinding plating, can obtain a better battery appearance, and can make the battery have better performance .
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • the surrounding amorphous silicon will be formed on the front of the cell.
  • the inventors found that during the subsequent phosphorus deposition process, the plating width of phosphorus diffused on the front side of the silicon wafer is often greater than that of amorphous silicon, thus forming a BPSG region with a certain width in the contact area between amorphous silicon and BSG.
  • BPSG has poor acid and alkali resistance, so it will be corroded by hydrofluoric acid and alkaline solution in the subsequent dewinding plating process, resulting in poor appearance of the battery.
  • the present invention carries out anti-corrosion treatment on BPSG after phosphorus deposition to improve its acid resistance and alkali resistance, and then utilizes hydrofluoric acid to remove PSG on the surface of polysilicon coating around it, and removes polysilicon coating around it with alkali solution. , can prevent the BPSG area on the front side of the silicon wafer from being corroded during the dewinding plating process, improve the appearance of the battery, and make the battery have a higher short-circuit current, open-circuit voltage, fill factor and battery efficiency.
  • step (5) the phosphorus doping and corrosion-resistant treatment can be realized through scheme A or scheme B, and the specific process includes the following steps:
  • Scheme A Anneal the phosphorus-deposited silicon wafer once to complete phosphorus doping and amorphous silicon crystallization; in a nitrogen atmosphere, perform a second anneal on the silicon wafer after the first anneal to reduce the concentration of phosphorus in the borophosphosilicate glass. At the same time, the concentration makes the network structure of the borophosphosilicate glass region denser;
  • Option B Remove the phosphosilicate glass on the front side of the phosphorus-deposited silicon wafer, and then perform phosphorus doping and crystallization of amorphous silicon.
  • phosphorus doping and amorphous silicon crystallization can be performed, which can reduce the concentration of P on the front of the silicon wafer in the BSG area, and avoid P erosion on the front of the silicon wafer during the subsequent phosphorus doping process.
  • BPSG is formed in the BSG area, because after removing the front PSG, the front side remains BSG, and BSG has higher acid and alkali resistance than BPSG, so it can prevent it from being corroded during dewinding plating.
  • the temperature of the primary annealing is 800-850°C.
  • the temperature of the secondary annealing is 850-1000° C., and the time is 10-50 minutes.
  • the secondary annealing temperature is too low or the time is too short, it will be difficult to improve the density of BPSG; if the secondary annealing temperature is too high or the time is too long, it will cause the P on the front side to penetrate the BSG deep into the silicon substrate , affecting the quality of the PN junction.
  • a hydrofluoric acid solution with a concentration of 0.5-3 wt% is used to remove the borophosphosilicate glass on the front side of the phosphorus-deposited silicon wafer.
  • the temperature for phosphorus doping and amorphous silicon crystallization is 800-1000° C., and the time is 5-60 minutes.
  • the phosphorus deposition temperature is 750-850° C.
  • the time is 20-50 minutes
  • the phosphorus source flow rate is 1000-4000 sccm.
  • the concentration of the hydrofluoric acid solution is 3-10 wt%.
  • the alkali solution is NaOH solution, KOH solution or tetramethylammonium hydroxide (TMAH) solution, and the concentration is 3-15wt%.
  • TMAH tetramethylammonium hydroxide
  • step (2) the borosilicate glass and diffusion junction on the back of the boron-doped silicon wafer are removed by chain single-sided etching.
  • the present invention improves the BPSG compactness (plan A) or replaces the mode of BPSG (plan B) with BSG by secondary annealing, improves the corrosion resistance of the silicon chip front BPSG, can Prevent it from being corroded by hydrofluoric acid and alkaline solution during the dewinding plating process, improve the appearance of the battery, and make the N-TOPCon battery have higher short-circuit current, open-circuit voltage, fill factor and battery efficiency.
  • Fig. 1 is the front photo of the silicon chip obtained in embodiment 1;
  • FIG. 2 is a front photo of the silicon wafer obtained in Comparative Example 1 (the framed part in the figure is the corrosion area).
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • Scheme A Anneal the phosphorus-deposited silicon wafer once at 800-850°C to complete phosphorus doping and crystallization of amorphous silicon; in a nitrogen atmosphere, anneal the silicon wafer after the first anneal at 850-1000°C Anneal for 10 to 50 minutes to reduce the concentration of phosphorus in the borophosphosilicate glass and make the network structure of the borophosphosilicate glass more compact;
  • Scheme B Use a hydrofluoric acid solution with a concentration of 0.5-3wt% to remove the phosphosilicate glass on the front side of the phosphorus-deposited silicon wafer, and then perform phosphorus doping and amorphous silicon crystallization at 800-1000°C for 5-60 minutes;
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • a method for removing polysilicon around a N-TOPCon battery comprising the following steps:
  • Comparative example 1 does not adopt the method of the present invention to carry out anti-corrosion treatment to borophosphosilicate glass before going around plating, and in going around plating process, there is corrosion in the BPSG region of silicon chip front; And embodiment 3 and 6 No corrosion occurred on the front side of the obtained silicon wafer. Moreover, it can be seen from Table 1 that the open circuit voltage, short circuit current, fill factor and battery efficiency of the N-TOPCon battery made of the silicon wafer finally obtained in Comparative Example 1 are lower than those of Example 3 and Example 6.
  • the present invention can prevent the BPSG region on the front side of the silicon chip from being corroded when going around and plating by increasing the step of BPSG corrosion-resistant treatment before going around and plating, can obtain a better battery appearance, and make the battery have better performance.
  • Example 1 and Comparative Example 2 are 850°C and 800°C respectively, and the rest of the process is the same. There is corrosion on the front side of the silicon wafer obtained in Comparative Example 2; and, as can be seen from Table 1, the performance of the N-TOPCon battery prepared by using the silicon wafer of Comparative Example 2 is lower than that of Example 1. This is because when the secondary annealing temperature is too low, it will be difficult to improve the density of BPSG.
  • Example 3 and Comparative Example 3 were 1000°C and 1050°C respectively, and the rest of the processes were the same. It can be seen from Table 1 that the performance of the N-TOPCon battery made by using the silicon wafer of Comparative Example 3 is lower than that of Example 3. This is because when the secondary annealing temperature is too high, the P on the front side will penetrate the BSG deep into the silicon substrate, affecting the quality of the PN junction.
  • the concentration of the hydrofluoric acid solution adopted in step (5) of embodiment 4 and comparative example 4 is respectively 0.5wt% and 0.1wt%, and all the other processes are the same.
  • Raw materials used in the present invention, equipment, if not specified, are commonly used raw materials, equipment in this area; Method used in the present invention, if not specified, are conventional methods in this area.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
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Abstract

La présente invention se rapporte au domaine technique des batteries N-TOPCon, et concerne un procédé d'élimination du silicium polycristallin plaqué sur la face arrière d'une batterie N-TOPCon. Le procédé comprend les étapes suivantes consistant à : déposer une couche d'oxyde tunnel et du silicium amorphe intrinsèque sur la face arrière d'une tranche de silicium ; soumettre le silicium amorphe intrinsèque à un dopage au phosphore, et effectuer un recuit primaire de manière à cristalliser le silicium amorphe intrinsèque en silicium polycristallin dopé au phosphore ; soumettre la tranche de silicium résultant du recuit primaire à un traitement anticorrosion BPSG ; et nettoyer séquentiellement la face avant de la tranche de silicium soumise au traitement anticorrosion à l'aide d'une solution d'acide fluorhydrique et d'une solution alcaline pour éliminer le silicium polycristallin plaqué sur la face arrière. Dans la présente invention, en ajoutant l'étape du traitement anticorrosion BPSG avant d'éliminer le placage sur la face arrière, la corrosion d'une zone BPSG sur la face avant de la tranche de silicium peut être évitée pendant l'élimination du placage sur la face arrière ; par conséquent, une batterie d'apparence relativement bonne est obtenue, et la batterie présente des performances relativement bonnes.
PCT/CN2021/116811 2021-08-31 2021-09-07 Procédé d'élimination du silicium polycristallin plaqué sur la face arrière d'une batterie n-topcon WO2023029059A1 (fr)

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CN114883443A (zh) * 2022-03-28 2022-08-09 普乐新能源科技(徐州)有限公司 poly-Si绕镀去除方法及在TopCon电池制备的应用
CN115274936A (zh) * 2022-08-29 2022-11-01 通威太阳能(金堂)有限公司 太阳电池及其制造方法
CN115411150A (zh) * 2022-09-29 2022-11-29 通威太阳能（成都）有限公司 太阳电池及其制备方法

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