WO2023029011A1 - 用于设计译码器的方法和电子设备 - Google Patents

用于设计译码器的方法和电子设备 Download PDF

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Publication number
WO2023029011A1
WO2023029011A1 PCT/CN2021/116552 CN2021116552W WO2023029011A1 WO 2023029011 A1 WO2023029011 A1 WO 2023029011A1 CN 2021116552 W CN2021116552 W CN 2021116552W WO 2023029011 A1 WO2023029011 A1 WO 2023029011A1
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decoding
test
decoder
circuit
neural network
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PCT/CN2021/116552
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English (en)
French (fr)
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李旻
徐强
黄宇
王泽中
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华为技术有限公司
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Priority to PCT/CN2021/116552 priority Critical patent/WO2023029011A1/zh
Priority to CN202180101960.5A priority patent/CN117940781A/zh
Publication of WO2023029011A1 publication Critical patent/WO2023029011A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer

Definitions

  • the present disclosure relates to the field of electronics, and more particularly to methods and electronic devices for designing decoders.
  • chip testing is to pick out defective chips. Because the cost of such defective chips entering the market will be far greater than the cost of chip testing, chip testing is a crucial part of the chip manufacturing process.
  • a design for testability (DFT) structure such as a scan chain (scan chain) can be added to the chip at the chip design stage, and a chip with the DFT structure can be manufactured.
  • Automatic test pattern generation (ATPG) tools can be used to generate chip test patterns (test patterns), and automatic test equipment (automatic test equipment, ATE) can be used to input test patterns for chips to be tested.
  • ATE automatic test equipment
  • test compression techniques have been developed.
  • the conventional test compression technology has problems such as too many coding bits.
  • embodiments of the present disclosure aim to provide a method, device and device for designing a decoder, and a test circuit for testing a circuit to be tested, wherein the decoder is designed as a part of the test circuit.
  • the decoder in the test circuit is used to test the circuit under test in the same chip.
  • a method for designing a decoder designed to be located in a test circuit includes: at least based on netlist data representing the circuit to be tested, determining an initialization decoder; and at least based on a first test vector set for testing the circuit to be tested, connecting the decoding circuit in the initialization decoder Modifications are made to obtain a target decoder for a test circuit configured to be coupled in a chip to a circuit under test.
  • a decoder with optimized input connection number and/or connection mode can be obtained.
  • connections of the decoder are optimized for the circuit under test, the number and/or complexity of encoding bits associated with the input connections can be reduced compared to conventional balanced XOR gate networks.
  • the coded bit pattern received by the decoder is also optimized. Accordingly, the coding success rate can be improved. In addition, the overhead of computing resources can also be reduced.
  • the initialization decoder includes at least one decoding layer, each decoding layer in the at least one decoding layer includes a plurality of decoding circuits, and determining the initialization decoder includes: using Netlist data to determine the number of scan chains in the circuit to be tested; use the number of scan chains to calculate the number of layers of at least one decoding layer; use the number of scan chains and the number of layers to calculate a decoding array, the decoding array includes at least one decoding The number of decoding circuits in each decoding layer in the layer; and based on the number of layers and the decoding array, an initialization decoder is constructed.
  • the multiple decoding circuits include an accumulator and a comparator coupled to the accumulator, and constructing the initialization decoder includes: setting multiple decoding layers arranged in series according to the number of layers ; according to the decoding array, a corresponding number of decoding circuits are set in each decoding layer in multiple decoding layers; Each accumulator in the next decoding layer in the decoding layer is connected to each other to build an initialization decoder.
  • the decoding circuit can be implemented with a relatively simple circuit structure, thereby reducing the circuit implementation cost of the decoder.
  • the design cost of the decoder can be reduced.
  • modifying the connection of multiple decoding circuits in the initialization decoder to obtain a target decoder for testing circuits includes: The characteristics of the circuit under test, the first test vector set is expanded into the second test vector set, the characteristics of the circuit under test include the scan chain distribution of multiple scan chains of the circuit under test in the test cycle or the unknown state in the test cycle at least one of the unknown state distributions; and modifying connections of a plurality of decoding circuits in the initialization decoder using at least a second set of test vectors to obtain a target decoder.
  • expanding the first set of test vectors into the second set of test vectors based on the characteristics of the circuit to be tested includes: using scan chain distribution or unknown state distribution to determine the During the frequency of use; based on the frequency of use and a predetermined power threshold, randomly generate a plurality of random test vectors; and add a plurality of random test vectors to the first test vector set to generate a second test vector set, wherein the test in the second test vector set The proportion of designated bits in the vector is uniformly distributed, and the designated bit represents the bit with the first value in the test vector.
  • expanding the first test vector set into the second test vector set based on the characteristics of the circuit to be tested includes: randomly merging a plurality of test vectors in the first test vector set to generate multiple random test vectors; a plurality of random test vectors are added to the first test vector set to generate the second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bits Bit represents the bit with the value of the first bit in the test vector.
  • At least using the second test vector set to modify the connection of multiple decoding circuits in the initialization decoder to obtain the target decoder includes: using a binary neural network model to represent Initialize the decoder; use the first set of test vector sets in the second test vector set to train the binary neural network model to obtain a candidate binary neural network; use the second set of test vector sets in the second test vector set to train the candidate binary neural network The value neural network is verified to obtain a target binary neural network; and based on the target binary neural network, a target decoder is determined.
  • the target decoder is determined by using the training-verification method, so as to further improve the decoding accuracy of the target decoder.
  • using the first group of test vector sets in the second test vector set to train the binary neural network model to obtain candidate binary neural networks includes: The initial connection between each layer is initialized to the real number domain to obtain a continuous domain neural model, the multiple weights between the various layers in the continuous domain neural model are respectively located between the first value and the second value and in the continuous domain neural model Multiple threshold constants between the various layers of , respectively, are greater than the first value; iteratively perform the following at least once: use the test vector set in the first set of test vector sets to train the continuous neural model to obtain the intermediate in the real number domain space A neural network; checking whether the output of the intermediate neural network satisfies the objective function value; and if the output of the intermediate neural network does not satisfy the objective function value, the intermediate neural network is updated using a gradient descent algorithm to modify the values of multiple weights and multiple the value of the threshold constant; and if the output of the intermediate neural network satisfies the objective function value, converting the intermediate neural network into a binary
  • converting the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network includes: comparing the values of multiple weights with weight thresholds: if the first If the value of a weight is lower than the weight threshold, the two decoding layers associated with the first weight are disconnected, or if the value of the second weight among the multiple weights is lower than the weight threshold, then the two decoding layers associated with the second weight are disconnected.
  • the two decoding layers are connected.
  • the target decoder can be determined in a simple and flexible manner by using the weight value to determine the connection relationship between the decoding circuits in the decoding layer represented by the binary neural network.
  • a computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for executing the method of the first aspect .
  • a computer program product includes a plurality of programs, the plurality of programs are configured to be executed by one or more processors, the plurality of programs include instructions for the method of the first aspect .
  • an electronic device comprises: one or more processors; a memory comprising computer instructions which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of the first aspect.
  • an electronic device in a fifth aspect of the present disclosure, includes: an initialization unit and a modification unit.
  • the initialization unit is used to determine an initialization decoder based at least on the netlist data representing the circuit to be tested.
  • a modifying unit configured to modify the connection of the decoding circuit in the initialization decoder to obtain a target decoder for the test circuit based at least on the first test vector set for testing the circuit to be tested, and the test circuit is configured to couple to the circuit under test in the chip.
  • connections of the decoder are optimized for the circuit under test, the number and/or complexity of encoding bits associated with the input connections can be reduced compared to conventional balanced XOR gate networks.
  • the coded bit pattern received by the decoder is also optimized. Accordingly, the coding success rate can be improved. In addition, the overhead of computing resources can also be reduced.
  • the initialization decoder includes at least one decoding layer, and each decoding layer in the at least one decoding layer includes a plurality of decoding circuits, and the initialization unit is further used to: use the netlist data to determine the number of scan chains in the circuit to be tested; use the number of scan chains to calculate the number of layers of at least one decoding layer; use the number of scan chains and the number of layers to calculate a decoding array, the decoding array includes at least one decoding layer The number of decoding circuits in each decoding layer; and based on the number of layers and the decoding array, an initialization decoder is constructed.
  • the plurality of decoding circuits include an accumulator and a comparator coupled to the accumulator, and the initialization unit is further configured to: set the plurality of decoding layers arranged in series according to the number of layers; Decoding array, a corresponding number of decoding circuits are set in each decoding layer in multiple decodings; and each comparator of the upper decoding layer in multiple decoding layers Each accumulator in the next decoding layer in is connected to each other to build the initialization decoder.
  • the decoding circuit can be implemented with a relatively simple circuit structure, thereby reducing the circuit implementation cost of the decoder.
  • the design cost of the decoder can be reduced.
  • the modifying unit is further configured to: amplify the first set of test vectors into a second set of test vectors based on the characteristics of the circuit to be tested, where the characteristics of the circuit to be tested include multiple At least one of the scan chain distribution of the scan chains in the test cycle or the unknown state distribution of the unknown state in the test cycle; and at least use the second test vector set to initialize the connection of a plurality of decoding circuits in the decoder Modifications are made to obtain the target decoder.
  • the modifying unit is further configured to: use scan chain distribution or unknown state distribution to determine the frequency of use of multiple scan chains during the test period; based on the frequency of use and a predetermined power threshold, randomly generate multiple Random test vectors; and adding a plurality of random test vectors to the first test vector set to generate a second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is evenly distributed, and the specified bits represent The bit with the value of the first bit in the test vector.
  • the modifying unit is further configured to: randomly combine a plurality of test vectors in the first test vector set to generate a plurality of random test vectors; and transfer the plurality of random test vectors to the first test vector Add collectively to generate a second test vector set, wherein the ratio of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bit represents the bit with the first value in the test vector.
  • the modifying unit is further used to: use the binary neural network model to represent the initialization decoder; use the first set of test vector sets in the second test vector set to train the binary neural network model Obtaining a candidate binary neural network; using a second set of test vector sets in a second test vector set to verify the candidate binary neural network to obtain a target binary neural network; and based on the target binary neural network, determine a target decoding device.
  • the target decoder is determined by using the training-verification method, so as to further improve the decoding accuracy of the target decoder.
  • the modifying unit is further used to: initialize the initial connections between the layers in the binary neural network model to the real number domain to obtain a continuous domain neural model, where the a plurality of weights between layers respectively between a first value and a second value and a plurality of threshold constants between layers in the continuous domain neural model respectively greater than the first value; iteratively performing the following at least once: using The test vector set in the first set of test vector sets trains the continuous neural model to obtain the intermediate neural network in the real number domain space; checks whether the output of the intermediate neural network satisfies the objective function value; and if the output of the intermediate neural network does not satisfy the target function value, then use the gradient descent algorithm to update the intermediate neural network to modify the values of multiple weights and multiple threshold constants; and if the output of the intermediate neural network satisfies the objective function value, convert the intermediate neural network to binary value discrete domain to obtain candidate binary neural networks.
  • the modifying unit is further configured to: compare the values of the multiple weights with the weight threshold respectively: if the value of the first weight among the multiple weights is lower than the weight threshold, then the first weight The two associated decoding layers are disconnected, or if the value of the second weight among the plurality of weights is lower than the weight threshold, the two associated decoding layers of the second weight are connected.
  • the target decoder can be determined in a simple and flexible manner by using the weight value to determine the connection relationship between the decoding circuits in the decoding layer represented by the binary neural network.
  • a circuit for testing a circuit under test includes a first decoder, coupled to the circuit under test and configured to decode a plurality of first encoded bits into a plurality of first decoded bits, the first decoder includes at least one decoding layer, Each decoding layer of the at least one decoding layer includes a plurality of decoding circuits, each decoding circuit including an accumulator and a comparator coupled to the accumulator. Since the connections of the decoder are optimized for the circuit under test, the number and/or complexity of encoding bits associated with the input connections can be reduced compared to conventional balanced XOR gate networks. In addition, the coded bit pattern received by the decoder is also optimized. Accordingly, the coding success rate can be improved. In addition, the overhead of computing resources can also be reduced.
  • At least one decoding layer includes: a first decoding layer configured to output a plurality of first intermediate bits based on a plurality of first encoded bits; and a second decoding layer , configured to output a plurality of first decoding bits based on the plurality of first intermediate bits, the number of the plurality of first decoding bits being greater than the number of the plurality of first intermediate bits.
  • each decoding layer in at least one decoding layer includes a first decoding circuit and a second decoding circuit, the connection of the first decoding circuit and the connection of the second decoding circuit Connections are different.
  • multiple decoding circuits of the last decoding layer in at least one decoding layer are respectively coupled to multiple scan chains of the circuit to be tested via multiple first AND gates; or The multiple decoding circuits of the last decoding layer in the at least one decoding layer are respectively coupled to the multiple second AND gates with the multiple scan chains.
  • the circuit further includes a second decoder, coupled to the circuit under test and configured to decode a plurality of second encoded bits into a plurality of second decoded bits
  • the second decoder includes at least one decoding layer, each decoding layer in the at least one decoding layer includes a plurality of decoding circuits, each decoding circuit includes an accumulator and a comparator coupled to the accumulator.
  • Fig. 1 shows a schematic circuit diagram of a conventional decoder.
  • Figure 2 shows a schematic diagram of an environment in which some embodiments of the present disclosure may be implemented.
  • Fig. 3 shows a schematic diagram of an initial encoding and decoding system according to some embodiments of the present disclosure.
  • FIG. 4 shows a schematic diagram of an object coding system according to some embodiments of the present disclosure.
  • FIG. 5 shows a schematic flowchart of a method for designing a test circuit according to some embodiments of the present disclosure.
  • Fig. 6 shows a schematic flowchart of a method for obtaining candidate binary neural networks according to some embodiments of the present disclosure.
  • Fig. 7 shows a schematic block diagram of an electronic device according to some embodiments of the present disclosure.
  • Fig. 8 shows a schematic block diagram of an example device that may be used to implement embodiments of the present disclosure.
  • the term “comprising” and its similar expressions should be interpreted as an open inclusion, that is, “including but not limited to”.
  • the term “based on” should be understood as “based at least in part on”.
  • the term “one embodiment” or “the embodiment” should be read as “at least one embodiment”.
  • the terms “first”, “second”, etc. may refer to different or the same object.
  • the term “and/or” means at least one of the two items associated with it. For example "A and/or B" means A, B, or A and B. Other definitions, both express and implied, may also be included below.
  • the user inputs the configuration to the EDA software, the EDA software generates the logic circuit, and then the chip is obtained through plate making and tape-out.
  • the chip can be installed on the ATE and the test stimulus can be input to the input pin of the IC chip by the ATE. By comparing the response of the output pin of the chip with the expected response, it can be judged whether the chip is qualified or not.
  • test compression technology is proposed to achieve test coverage while compressing test vectors.
  • the test compression technique is based on scan chains.
  • the scan chain technology essentially connects the flip-flops in the sequential circuit into multiple "shift registers (scan cells)", and the input and output values of each shift register can be observed separately.
  • the feasibility of the test compression technique is based on the fact that a single original test vector generated by ATPG contains the input values of all the shift registers in the scan chain, and only a few of the shift registers are valid values. Therefore, the original test vector can be compressed and decompressed by stimulating a decompression module (decompressor) to recover an effective value.
  • the output value on the scan chain can also be compressed by a response compression module (compactor). The output compressed value is sent to the ATE through the output pin, and the ATE compares the output compressed value with the expected value to locate the position of the shift register of the scan chain where the error occurs.
  • the compression ratio of the input value and output value of the scan chain shift register can often reach hundreds or even thousands, thus greatly reducing the storage capacity of the test vector. But at the same time, it also introduces two core problems in the field of test compression.
  • the first question concerns power consumption. There are few effective values (sparseness) in the original input value of the shift register, so the shift power consumption on the scan chain in the input stage is also very small. However, the input compressed values are often no longer sparse after decompression. In the process of directly shifting the decompressed value to the corresponding shift register, unbearable shift power consumption will be generated.
  • the second problem addresses the masking of unknown states (X states) generated during testing. Since the functions of some circuit modules are unknown, some unpredictable unknown values (unknown values) will be output, and these unknown values are called X states. Distributed on the scan chain are circuits that generate X states that are distributed across the scan chain output values. When compressing in response to the compression module, these X states will cover up the effective values of other circuits that are simultaneously compressed, thus causing unobservable relevant positions in the circuit. This will result in a decrease in fault coverage and an increase in the number of test vectors.
  • the conventional solution solves the above two problems by introducing a low power consumption control module and a mask control module respectively.
  • the low power consumption control module and the mask control module are similar in function, and both are a decoder.
  • the decoding output of the low-power control module controls the input value of the scan chain. When the decoding output is 0, input a fixed value to the shift register in the controlled scan chain, otherwise, input a fixed value to the shift register in the controlled scan chain. Enter the output value of the decompression module.
  • the decoding output of the mask control module controls the input value of the corresponding scan chain to the response compression module.
  • the decoding output When the decoding output is 0, the input value of the controlled scan chain to the response compression module is clamped to a fixed value, otherwise, the The output value of the controlled scan chain is input to the response compression module.
  • the decoding output of the two control modules is connected to each scan chain, and the corresponding scan chain is turned on or off by setting the decoding output value to 1 or 0.
  • the low-power control block turns on the scan chains containing valid input values to allow the excitation decompression block to input shift values into the scan chains in the circuit under test, while the mask control block sets the scan chains containing the X-state outputs Set it to the off state to prevent the output of the X state of the scan chain in the circuit under test.
  • a network of exclusive-or gates may be used to form a decoder.
  • FIG. 1 shows a schematic circuit diagram of a conventional decoder 100 .
  • the decoder 100 is a network of balanced logic gates, and the logic gates used are exclusive OR gates (XOR).
  • the number of input connections of each logic gate in the balanced logic gate network is the same, for example in FIG. 1 each XOR has three input connections.
  • the decoder 100 includes 6 encoding bits X1, X2...X6 and 12 decoding bits Y1, Y2...Y12.
  • Each XOR has three input connections that respectively receive three of the six encoded bits X1, X2...X6.
  • Each XOR performs an XOR operation based on the logic values of the three coded bit values to generate one decoded bit among the 12 decoded bits Y1, Y2...Y12.
  • the logic gate network may also be based on XOR and AND gates.
  • this structure uses three encoded bits to perform an XOR operation to represent the control state of the corresponding scan chain. For low-power control modules, when the input shift power consumption threshold set by the user is low, this structure will use more coding bits, and at the same time, multiple output values of the XOR network structure will be further ANDed. operation to control a scan chain.
  • this balanced XOR gate network structure has equal control strength for each scan chain, but the frequency of use of each scan chain in the actual automatic test pattern generation process is different. Therefore, the use of such balanced logic gate networks results in wasted or insufficient encoding capacity.
  • this structure uses more coding bits, and the consumption of computing resources such as hardware and software overhead is relatively large.
  • a circuit for testing a circuit under test includes at least one decoder.
  • Each decoder includes at least one decoding layer, and each decoding layer includes a plurality of decoding circuits.
  • Each decoding circuit includes an accumulator and a comparator coupled to the accumulator.
  • BNN binary neural network
  • test circuit of the present disclosure can reduce the use of coding bits, improve the coding ability, and No waste will result from this.
  • one of the prerequisites for optimization may be the coding success rate
  • the test circuit of the present disclosure uses relatively few coding bits, and consumes relatively little computational resources such as hardware and software overhead.
  • FIG. 2 shows a schematic diagram of an environment 200 in which some embodiments of the present disclosure may be implemented.
  • the chip 200 includes a circuit to be tested 11, a low-power shift register 16, a mask register 18, a decompression module 12, a compression module 13, a low-power controller 14, a mask controller 15, multiple A number of AND gates 7-1, 7-2...7-N and a plurality of AND gates 9-1, 9-2...9-N, wherein N represents an integer greater than 1.
  • low power consumption shift register 16, mask register 18, decompression module 12, compression module 13, low power consumption controller 14, mask controller 15, multiple AND gates 7-1, 7- 2...7-N and multiple AND gates 9-1, 9-2...9-N are used to test the circuit 11 to be tested.
  • the test circuit of the chip 200 may include at least one of the low power consumption controller 14 or the mask controller 15 .
  • the test circuit of the chip 200 may further include a low-power shift register 16, a mask register 18, a decompression module 12, a compression module 13, a plurality of AND gates 7-1, 7-2.... .7-N and a plurality of AND gates 9-1, 9-2... 9-N.
  • the ATE inputs ATPG test vectors to the low-power shift register 16 of the chip 200 through a small number of input pins of the chip 200 .
  • the ATPG test vector includes the input compressed value of the decompression module 12, that is, the compressed seed, the encoded value of the low power consumption controller 14, the encoded value of the mask controller 15, and the like.
  • the input compressed value is injected into the decompression module 12 via the low power shift register 16 and the mask register 18 .
  • the encoded value of the low power controller 14 is injected into the low power controller 14 via the low power shift register 16, and the encoded value of the mask controller 15 is injected via the low power shift register 16 and the mask register 18 Mask controller 15.
  • the low power controller 14 decodes the coded value to open the appropriate scan chain.
  • the decompression module 12 decompresses the input compressed value of the low-power shift register 16 , and fills the decompressed value into the corresponding shift register by shifting under the control of the low-power controller 14 .
  • the mask controller 15 decodes the encoded value, masks the X state in the scan chain output value by using the decoded bit value, and sends the processed output value to the response compression module 13 for compression.
  • the circuit 11 to be tested includes a plurality of scan chains 11-1, 11-2 ... 11-N (hereinafter individually or collectively referred to as 11), and the number of scan chains is related to a plurality of AND gates 7-1, 7 -2...7-N (hereinafter individually or collectively referred to as 7) and a plurality of AND gates 9-1, 9-2...9-N (hereinafter individually or collectively referred to as 9) respectively correspond.
  • Each scan chain may include one or more sequential logic circuits, such as registers, in the circuit under test.
  • the network of sequential logic XOR gates generates a shifted output in response to the shifted output.
  • the low-power controller 14 includes a low-power register 141 and a decoder 142, and the decoder 142 generates a control signal by decoding to control one or more of the AND gates 7-1, 7-2....7-N An AND gate is turned on or off. For example, in a plurality of cycles, the decoder 142 may continuously generate a logic value "1" for the AND gate 7-1, so that the decompressed value is sequentially shifted and input to the scan chain 11-1.
  • the decoder 142 can output “0” to turn off the AND gates 7-2 . . . 7-N, so that the scan chains 11-2 . . . 11-N continue to receive “0”. Since the scan chains 11 - 2 . . . 11 -N have no logic value changes, the sequential logic gates in the chip do not operate. Since the sequential logic gates are not operating, power consumption during testing can be reduced.
  • the mask controller 15 includes a mask register 151 and a mask decoder 152, and the mask decoder 152 generates a control signal by decoding to control one of the AND gates 9-1, 9-2...9-N. Multiple AND gates are turned on or off. Similarly, the mask decoder 152 can generate a control signal to close the AND gate corresponding to the scan chain having the X state among the AND gates 9 - 1 , 9 - 2 . . . 9 -N through decoding.
  • the decompression module 12 can be any circuit capable of expanding a small number of test stimuli into a large number of scan chain test vectors and outputting the test vectors.
  • the decompression module 12 may for example be based on a random signal generator.
  • the decompression module 12 may include a pseudo-random sequence generator 121 and a phase shifter 122 based on a logic gate network.
  • the pseudo-random sequence generator 121 can decompress the injected input compressed value for the first time to generate a pseudo-random sequence with a larger bit width, and the phase shifter 122 decodes the modified pseudo-random sequence to obtain each scan corresponding to each period The shift value for the chain.
  • the pseudo-random sequence state space generated by the pseudo-random sequence generator 121 is preferred, and the maximum number of pseudo-random sequences is fixed. This also determines the upper limit of the solution space that the uncompressed structure can utilize. Therefore, designing a better phase shifter 122 under the premise of a limited and fixed decompression structure decompression space is also a core issue of the decompression module.
  • a phase shifter 122 based on an unbalanced logic gate network is provided, wherein the inputs of at least some logic gates in the unbalanced logic gate network may have different numbers of input connections.
  • the response compression module 13 may be any circuit capable of receiving test responses and performing logic operations on the received test responses to output from a small number of output channels.
  • the response compression module 13 may be, for example, a compression module based on a multiple-input signature register (MISR) or a logic gate network such as an exclusive-or gate (XOR) network.
  • MISR multiple-input signature register
  • XOR exclusive-or gate
  • FIG. 3 shows a schematic diagram of an initial encoding and decoding system 300 according to some embodiments of the present disclosure.
  • the initial coding system 300 can be designed using electronic equipment such as a computer.
  • the initial coding system 300 includes an initial encoding input unit 310 , an encoder 320 , an initial decoding input unit 330 , a decoder 340 and an initial decoding output unit 350 .
  • the initial code input unit 310 includes a plurality of initial bit inputs I11, I12, I13, I14, I15, I16...I1A to receive a plurality of initial bits, where A represents an integer greater than 1.
  • the plurality of initial bits may be derived from a first set of test vectors, and the first set of test vectors may be obtained from an original set of test vectors comprising a plurality of test data.
  • the specific method for forming the first test vector set will be described below.
  • the encoder 320 includes at least one encoding layer, wherein in case of including a plurality of encoding layers, the plurality of encoding layers are connected in series to form a plurality of encoding layers arranged in stages.
  • the encoder 320 comprises two encoding layers 321 and 322 . It should be understood that this is for illustration only and not limiting the scope of the present disclosure. Encoder 320 may include other numbers of encoding layers, such as one encoding layer or three or more encoding layers.
  • the first encoding layer 321 includes a plurality of encoding circuits X11, X12, X13, X14...X1B
  • the second encoding layer 322 includes a plurality of encoding circuits X21, X22...X2C, where B and C represent integers greater than 1, respectively.
  • Each encoding layer includes multiple encoding circuits.
  • the multi-level encoding layers in the encoder 320 may be arranged in a manner that the number of encoding circuits decreases step by step. For example, the number of encoding circuits included in the first-level encoding layer 321 is greater than the number of encoding circuits included in the second-level encoding layer 322 . That is, the numerical value of B is greater than the numerical value of C.
  • each initial bit in the initial encoding input unit 310 is respectively provided to a plurality of encoding circuits in the first-level encoding layer 321 in the encoder 320 .
  • the input of the first initial bit I11 is provided to each encoding circuit in the first-level encoding layer 321 .
  • the input of the second initial bit I12 is also provided to each encoding circuit in the first-level encoding layer 321 , and so on. Only for the clarity of illustration, the input I12, I13, I14, I15, I16...I1A of a plurality of initial bits are not shown in Fig. 3 and are connected to each encoding circuit in the first-level encoding layer 321 , but it can be understood that such a connection exists in the initial encoding and decoding system 300 .
  • each coding circuit in the first-level coding layer 321 is connected to each coding circuit in the plurality of coding circuits X21 , X22 . . . X2C in the second-level coding layer 322 .
  • each encoding circuit includes an accumulator and a comparator.
  • the first encoding circuit X11 in the first-level encoding layer 321 includes a first accumulator X111 and a first comparator 112 connected to the first accumulator X111.
  • the first accumulator X111 can accumulate multiple input values, and the first comparator 112 can compare the accumulated value with a predetermined value and output the comparison result to the second-level coding layer 322 .
  • Multiple encoding circuits in the second-level encoding layer 322 may perform similar operations.
  • the last encoding layer in the encoder 320 may provide a plurality of encoded outputs to the initial decoding input 330 .
  • the initial decoding input unit 330 includes a plurality of initial intermediate bits Z1, Z2 . . . ZD, wherein D represents an integer greater than 1. In one embodiment, the value of D is less than the value of C. Alternatively, the value of D may be equal to the value of C.
  • the decoder 340 includes at least one decoding layer, wherein in the case of including a plurality of decoding layers, the plurality of decoding layers are connected in series to form a plurality of decoding layers arranged in stages.
  • the decoder 340 includes two decoding layers 341 and 342 . It should be understood that this is for illustration only and not limiting the scope of the present disclosure.
  • the decoder 340 may include other numbers of coding layers, such as one coding layer or three or more coding layers.
  • the first decoding layer 341 includes a plurality of encoding circuits Y11, Y12...Y1E
  • the second decoding layer 342 includes a plurality of decoding circuits Y21, Y22, Y23, Y24...Y2F, wherein E and F represent respectively greater than 1 an integer of .
  • Each decoding layer includes multiple decoding circuits.
  • the multi-level encoding layers in the decoder 340 may be arranged in a manner that the number of decoding circuits increases step by step. For example, the number of decoding circuits included in the first-level decoding layer 341 is less than the number of decoding circuits included in the second-level decoding layer 342 . That is, the numerical value of E is smaller than the numerical value of F.
  • each initial intermediate bit in the initial decoding input unit 330 is respectively provided to each of the plurality of decoding circuits Y11, Y12...Y1E in the first-level decoding layer 341 in the decoder 340 decoding circuit.
  • the input of the first initial middle bit Z1 is provided to each decoding circuit in the first-level decoding layer 341 .
  • the input of the second initial bit Z2 is also provided to each decoding circuit in the first-level decoding layer 341 , and so on.
  • the input Z2...ZD of a plurality of initial intermediate bits is not shown in Fig. 3 to be connected to the connection of each decoding circuit in the first-level decoding layer 341, but it can be understood that, Such connections exist in the initial codec system 300 .
  • each decoding circuit in the first-level decoding layer 341, such as the first decoding circuit Y11 is connected to each of the plurality of decoding circuits Y21, Y22 ... Y2F in the second-level decoding layer 342 a decoding circuit.
  • each decoding circuit includes an accumulator and a comparator.
  • the first decoding circuit Y11 in the first-stage decoding layer 341 includes a first accumulator X111 similar to the first-stage encoder X11 and a first comparator 112 connected to the first accumulator X111.
  • the first accumulator X111 can accumulate multiple input values, and the first comparator 112 can compare the accumulated value with a predetermined value and output the comparison result to the second decoding layer 342 .
  • Multiple decoding circuits in the second-level decoding layer 342 can perform similar operations.
  • the last decoding layer in the decoder 340 which is the second decoding layer 342 in FIG. 3 , may provide multiple decoded outputs to the initial decoding output section 350 .
  • the initial decoding output unit 350 includes a plurality of initial output bits O11, O12, O13, O14, O15, O16...O1G, wherein G represents an integer greater than 1.
  • the numerical value of G is greater than the numerical value of F.
  • the numerical value of G may be equal to the numerical value of F. Since the initial decoding output unit 350 corresponds to a plurality of scan chains in the circuit under test 11 , the value of G may be the same as the number of scan chains in the circuit under test 11 .
  • the target encoding and decoding system can be obtained by changing the connection relationship between each encoding circuit and decoding circuit in the initial encoding and decoding system 300 in FIG. 3 .
  • BNN can be used to change the connection relationship between the encoding circuit and the decoding circuit of the initial encoding and decoding system 300 to obtain an optimized target encoding and decoding system.
  • FIG. 4 shows a schematic diagram of an object coding system 400 according to some embodiments of the present disclosure.
  • the target codec system 400 can be designed using an electronic device such as a computer.
  • the object encoding and decoding system 400 includes an object encoding input unit 410 , an encoder 420 , an object decoding input unit 430 , a decoder 440 and an object decoding output unit 450 .
  • the target encoding and decoding system 400 in FIG. 4 has a similar structure to the initial encoding and decoding system 300, except that the connection modes of each encoding circuit and decoding circuit are different due to optimization. For example, the first encoded bits in the target encoding input part 410 are only provided to the first encoding circuit X11 and the encoding circuit X1B in the first encoding layer 421 .
  • the output of the first encoding circuit X11 in the first encoding layer 421 is optimized to be supplied only to the encoding circuits X21 , X22 and X2C in the second encoding layer 422 .
  • the output of the encoding circuit X21 in the second encoding layer 422 is optimized to be provided only to the decoding inputs Z2 and ZD in the target decoding input section 430 .
  • the target decoding input Z1 output in the target decoding input part 430 is optimized to be provided only to the decoding circuits Y11, Y12, and Y1E in the first decoding layer 441, and the decoding circuits in the first decoding layer 441
  • the output of the circuit Y11 is optimized to be provided only to the decoding circuits Y21 , Y24 and Y2F in the second decoding layer 442 .
  • the output of the decoding circuit Y21 in the second decoding layer 442 is optimized to be supplied only to the target decoding outputs O11 and O1G in the target decoding output section 450 . It can be understood that the optimized connection illustrated above is only for illustration, rather than limiting the scope of the present disclosure.
  • the target code input unit 410 and the encoder 420 are shown separately in FIG. 3 , and the target decode output unit 450 and the decoder 440 are shown separately, this is only for illustration, rather than limiting the scope of the present disclosure. Limit.
  • the target encoding input 410 may be part of the encoder 420 and the target decoding output 450 may be part of the decoder 440 .
  • the decoder 440 includes at least one decoding layer, wherein in case of including a plurality of decoding layers, the plurality of decoding layers are connected in series to form a plurality of decoding layers arranged in stages.
  • the decoder 440 includes two decoding layers 441 and 442 . It should be understood that this is for illustration only and not limiting the scope of the present disclosure. Decoder 440 may include other numbers of coding layers, such as one coding layer or three or more coding layers.
  • the first decoding layer 441 includes a plurality of encoding circuits Y11, Y12...Y1E
  • the second decoding layer 442 includes a plurality of decoding circuits Y21, Y22, Y23, Y24...Y2F, where E and F represent respectively greater than 1 an integer of .
  • Each decoding layer includes multiple decoding circuits.
  • the multi-level encoding layers in the decoder 440 can be arranged in a manner that the number of decoding circuits increases step by step. For example, the number of decoding circuits included in the first-level decoding layer 441 is less than the number of decoding circuits included in the second-level decoding layer 442 . That is, the numerical value of E is smaller than the numerical value of F.
  • each first encoded bit in the target decoding input unit 430 is respectively provided to a plurality of decoding circuits Y11 , Y12 and Y1E in the first-level decoding layer 341 in the decoder 340 .
  • the input of the first encoded bit Z2 is also provided to at least one decoding circuit in the first-level decoding layer 341 , and so on. Only for the clarity of illustration, the input Z2...ZD of a plurality of first coded bits is not shown in Fig. 4 and is connected to the connection of each decoding circuit in the first-level decoding layer 441, but it can be understood that , such a connection exists in the target codec system 400 .
  • each decoding circuit in the first-level decoding layer 441 is selectively connected to at least one decoding circuit in the second-level decoding layer 342 .
  • each decoding circuit includes an accumulator and a comparator, similar to that in FIG. 3 .
  • the last decoding layer in the decoder 440 which is the second decoding layer 442 in FIG. 4 , may provide a plurality of first decoding bits to the target decoding output unit 450 .
  • the target decoding output unit 450 includes a plurality of target output bits O11 , O12 , O13 , O14 , O15 , O16 . . . O1G, wherein G represents an integer greater than 1.
  • the numerical value of G is greater than the numerical value of F.
  • the numerical value of G may be equal to the numerical value of F. Since the target decoding output unit 450 corresponds to a plurality of scan chains in the circuit under test 11 , the value of G may be the same as the number of scan chains in the circuit under test 11 .
  • the codec system 400 needs to restore the bit data output from the target decoding output unit 450 to the bit data input to the target encoding input unit 410 as much as possible.
  • the decoder 440 obtained by the electronic device may be considered as a decoder that meets the requirements.
  • the design of the decoder 440 can be integrated into the chip design including the circuit 11 to be tested, and put into chip manufacturing.
  • an object decoder such as decoder 440 may be used to implement low power decoder 142 and/or mask decoder 152 .
  • the electronic device can also be used to design a plurality of candidate decoders, and select a target decoder based on some additional factors or other factors, as described in detail below.
  • FIG. 5 shows a schematic flowchart of a method 500 for designing a test circuit according to some embodiments of the present disclosure.
  • the method 500 can be executed by an electronic device such as a computer. It can be understood that the various aspects described above with respect to FIGS. 2-4 can be selectively applied to the method 500 .
  • the method 500 will be described below in conjunction with the features in FIGS. 2-4 .
  • the electronic device may determine an initialization decoder based at least on netlist data representing the circuit 11 under test.
  • Netlist data can describe various characteristics of the circuit, such as the properties of each device in the circuit and the connection relationship between them. For example, the number of scan chains used for testing in the circuit under test 11 can be determined based on the netlist data.
  • the initialization decoder includes at least one decoding layer, and each decoding layer in the at least one decoding layer includes a plurality of decoding circuits.
  • the initialization decoder may be decoder 340 in FIG. 3 . Therefore, in one embodiment, the initialization decoder may be determined based on the number of scan chains.
  • the electronic device can use the netlist data to determine the number N of scan chains in the circuit under test.
  • the number N of scan chains can be used to determine the number of encoding layers LE in the encoder 320 and the number of decoding layers LD in the decoder 340 of the coding system 300 shown in FIG. 3 .
  • the number of encoding layers LE and the number of decoding layers LD can be calculated using the following equation (1).
  • D0 represents a predetermined value, which can be preset based on the circuit 11 to be tested. Alternatively, other ways can also be used to determine the number of layers.
  • the electronic device can then use the scan chain number N and the layer number LE or LD to calculate the encoding or decoding array.
  • the encoding array includes the number of encoding circuits of at least one encoding layer in each encoding layer, and the decoding array indicates the number of decoding circuits in at least one decoding layer in each decoding layer.
  • the following formula (2) can be used to determine the layer number relationship of the encoder.
  • del represents the number of encoding circuits in the el-th layer
  • del +1 represents the number of encoding circuits in the el+1-th layer. Since the number of encoding circuits included in each layer is different (decreasing step by step), an encoding array can be established to represent the number of encoding circuits in each layer.
  • the following formula (3) can be used to determine the layer number relationship of the decoder.
  • d d1 represents the number of decoding circuits in the d1-th layer
  • d d1+1 represents the number of decoding circuits in the d1+1-th layer. Since the number of decoding circuits included in each layer is different (increasing step by step), a decoding array can be established to represent the number of decoding circuits in each layer.
  • each decoding circuit and encoding circuit has a basically similar structure, such as accumulators and comparators coupled in series, based on the number of layers and the decoding array, the electronic device can construct an initial decoder, or based on the number of layers and encoding array, Electronics can build to initialize the encoder.
  • the plurality of decoding circuits includes an accumulator and a comparator coupled to the accumulator.
  • the electronic device may set a plurality of decoding layers arranged in series according to the layer number L D . According to the decoding array, the electronic device sets a corresponding number of decoding circuits in each of the plurality of decoding layers. Further, the electronic device can connect each comparator of the upper decoding layer in the multiple decoding layers with each accumulator in the next decoding layer in the multiple decoding layers to construct an initialization decoder. It will be appreciated that the electronics may be similarly arranged for the encoder.
  • the electronic device may modify connections of multiple decoding circuits in the initialization decoder based at least on the first test vector set for testing the circuit to be tested, so as to obtain a target decoder for testing the circuit.
  • the test circuit is configured to be coupled to the circuit under test in the chip.
  • the target decoder may be, for example, the target decoder 440 of FIG. 4 .
  • a target encoder such as target encoder 420, may also be obtained.
  • the design of the encoder 420 is in one
  • the chip design including the circuit under test 11 may not be incorporated in the embodiment.
  • the encoder 420 can be realized by software in the electronic device without implementing it as a hardware circuit.
  • the decoder 440 may be implemented in a chip as the low power decoder 142 or the mask decoder 152 .
  • the first test pattern set is, for example, automatic test pattern generation (ATPG) data.
  • BNN may be used to optimize the connection relationship of the decoding circuits of the initial decoder 340 .
  • BNN it usually requires a large amount of training data.
  • the ATPG data obtained by performing fault sampling on the original circuit under test usually includes a plurality of test data packets.
  • the amount of such test data is usually difficult to meet the requirements of BNN training. If using ATPG data that meets the training requirements of BNN, it needs to consume a lot of sampling cost and time, which is usually not desired. Therefore, in some embodiments of the present disclosure, the first test vector set such as ATPG data can be augmented to obtain the second test vector set for BNN training.
  • ATPG data includes, for example, scan chain distributions and/or unknown state distributions.
  • the scan chain distribution of the scan chains of the circuit under test 11 in the test cycle can be used to separately carry out the connection relationship of a plurality of decoding circuits used to form the low-power decoder 142. modified to obtain the target decoder used to form the low power decoder 142 .
  • the connection relationship of the plurality of decoding circuits used to form the mask decoder 152 can be respectively modified by using the unknown state distribution of the unknown states in the test period. Further, the connection relationship of a plurality of decoding circuits used to form the mask decoder 152 can also be modified by using the unknown state distribution and the second test vector set to obtain the target for forming the mask decoder 152. decoder.
  • the electronic device can use scan chain distribution or unknown state distribution to determine multiple scan chains The frequency of use during the test period, based on the frequency of use and the predetermined power threshold, randomly generating a plurality of random test vectors, and adding the plurality of random test vectors to the first set of test vectors to generate a second set of test vectors.
  • the ratio of specified bits in the test vectors in the second test vector set is evenly distributed.
  • the specified bit represents the bit with the first bit value in the test vector, for example, a logic value "1". In other words, the specified bits satisfy the uniform distribution shown in the following formula (4).
  • S represents a specified bit
  • Pth represents a predetermined power threshold. Therefore, according to the frequency of use of the scan chains in the first test vector set, the first test vector set to the second test vector set can be randomly amplified in such a manner that the designated bits are uniformly distributed.
  • the predetermined power threshold represents the maximum number of scan chains that can be turned on in one cycle, because when this threshold is exceeded, too much energy is injected into the chip under test, which may cause damage or failure of the chip.
  • the electronic device in order to expand the first set of test vectors into the second set of test vectors, can randomly combine multiple test vectors in the first set of test vectors to generate multiple random test vectors, and A plurality of random test vectors are added to the first set of test vectors to generate a second set of test vectors.
  • the ratio of the specified bits in the test vectors in the second test vector set is normally distributed, and the specified bits represent the bits with the first bit value in the test vectors, for example, the bits with logic value "1".
  • the specified bits can satisfy the normal distribution shown in the following formula (5).
  • randomly merging a plurality of test vectors in the first test vector set to generate a plurality of random test vectors may include at least one of the following two methods: 1) Randomly select some data packets from the first test vector set for merging , extract the scan chain usage of the merged data, and form a 0/1 vector as a generated random test vector; or 2) randomly select some data packets in the first test vector set as the background, and perform a test with the remaining data packets one by one Incremental merging, the intermediate results obtained by each incremental merging are also retained, and the usage of the scan chain is extracted to form a 0/1 vector as a random test vector.
  • the second test vector set can still basically follow the characteristics of the first test vector set, such as the usage frequency or distribution of scan chains. Therefore, using the second test vector set for training not only satisfies the requirement of BNN for a large amount of training data, but also ensures that the trained decoder is optimized for the circuit 11 to be tested.
  • the electronic device may first extract the unknown state distribution of the circuit under test.
  • a masked BNN learning data set is generated, and the masked BNN learning data set includes an observation data set and an unknown state masking data set.
  • Each element of the observation data set and the unknown state masking data set is a binary vector, and the length of the vector is the total number of scan chains.
  • the data set amplification method for the mask decoder 152 includes: the scan chain output value corresponding to the merged data packet forming the random test vector must be observed, extracting the scan chain number, and numbering the binary vector The value of the corresponding position is set to 1, and the value of the other positions is 0.
  • the set of these binary vectors is the observation data set. Extract the scan chain number of the unknown state that prevents the output value of these scan chains from being observed, set the value of the position corresponding to the number in the binary vector to 1, and the value of the rest of the position to 0, the set of these binary vectors is the unknown state Mask the dataset. In this way, the second set of test vectors for the mask decoder 152 can also be obtained.
  • test data set expansion method is also used to amplify the test data set, which reduces from The amount of ATPG data extracted reduces design and simulation costs.
  • BNN Due to the layer structure properties of BNN, electronic devices use a binary neural network model to represent either an initial encoder or an initial decoder.
  • a layer in each BNN corresponds to an encoding layer in the initial encoder or a decoding layer in the initial decoder.
  • the electronic device uses the first set of test vectors in the second set of test vectors to train the binary neural network model to obtain candidate binary neural networks.
  • the electronic device may use the second set of test vectors in the second test vector set to verify the candidate binary neural network to obtain the target binary neural network.
  • the second set of test vectors is divided into two parts, one of which is a training set and the other is a validation set.
  • the electronic device can determine the target binary neural network as the target decoder.
  • the aforementioned BNN model cannot be directly trained. It is necessary to convert the corresponding BNN model into a continuous model, which has the same characteristics as discrete
  • the BNN model has the same structure, but its connection weights and comparison thresholds are continuous. Specifically, the connection between the decoding circuit in each decoding layer and the decoding circuit in another layer is represented in the continuous model as a continuous value with a connection weight between 0 and 1, and the comparator compares the threshold Can be represented as continuous values greater than 0.
  • the relationship between the input X i+1 of the i+1 layer and the input X i of the i layer is simulated by the following formula (6):
  • mean(X i ) represents the mean value of each element of X i
  • var(X i ) represents the variance of Xi i
  • w represents the weight connection matrix from layer i to layer i+1
  • C represents a vector, where The kth component represents the threshold in the kth comparator.
  • the data sets used in low-power BNN and masked BNN have the same format and the same form of optimization objective function is used, they use the same BNN training algorithm.
  • the encoder BNN and decoder BNN can be combined as shown in Figure 3, and the corresponding continuous model can be trained at the same time.
  • the training algorithm adopts an optimization algorithm of stochastic gradient descent.
  • Fig. 6 shows a schematic flowchart of a method 600 for obtaining candidate BNNs according to some embodiments of the present disclosure. It can be understood that the method 600 may be a specific implementation manner of at least a part of step 504 of the method 500 in FIG. 5 . The method 600 does not limit the method 500, and each step in the method 500 may have other implementation manners. The method 600 may be executed by an electronic device having computing capabilities, such as a computer.
  • the electronic device initializes initial connections between layers in the binary neural network model to the real number domain to obtain a continuous domain neural model.
  • the multiple weights between the layers in the continuous domain neural model are respectively between 0 and 1 and the multiple threshold constants between the various layers in the continuous domain neural model are respectively greater than 0.
  • the continuous neural model is trained using the test vectors in the first set of test vectors to obtain an intermediate neural network in the real number domain space.
  • Xj represents the input bit of the target code input part, such as the input bit at the target code input part 410 in Figure 4, Indicates the output bits of the target decoding output unit, such as the output bits at the target decoding output unit 450 in FIG.
  • Code mapping, or the decoding function p represents the number of scan chains.
  • the objective function value can have different expressions.
  • the percentage of the number of scan chains in the open state after encoding and decoding to the total number of scan chains can be set to satisfy the following formula (8):
  • the training from the initial BNN to the target BNN is actually a multi-objective optimization problem, because it includes both the constraints and objectives for the low-power decoder, and the constraints and objectives for the mask decoder. Target.
  • a weighted approach can be used for comprehensive optimization.
  • multi-objective optimization can be performed using Equation 10 below.
  • X represents the binary vector to be encoded
  • ⁇ indicates the weight coefficient, which can be preset according to the actual circuit. For example, ⁇ lies between 0 and 1.
  • the electronic device uses a gradient descent algorithm to update the intermediate neural network at 608 to modify the values of multiple weights and multiple threshold constants. If the output of the intermediate neural network satisfies the objective function value, the electronic device converts the intermediate neural network into a binary discrete domain at 610 to obtain a candidate binary neural network. In the case of satisfying the objective function value, the intermediate neural network can be expressed by the following formula (11).
  • X i represents the input of the i-th layer
  • X i+1 represents the input of the i+1-th layer
  • a i+1 represents the weight connection matrix
  • C i+1 represents the comparison threshold.
  • the electronic device may further convert the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network.
  • the weights may be compared with weight thresholds respectively. If the weight value is greater than the predetermined threshold, it is considered that the connection between two decoding circuits corresponding to different decoding layers actually exists or needs to be reserved, and the associated two decoding layers can be connected.
  • the weight is smaller than the threshold, it is considered that the connection between two decoding circuits corresponding to different decoding layers does not actually exist or does not need to be reserved, and the connection between the two associated decoding layers can be disconnected.
  • a target codec system such as the codec system 400 shown in FIG. 4 can be obtained.
  • the electronic device can generate the target decoder in the target codec system as a part of the netlist of the circuit for testing the circuit 11 to be tested, and merge the netlist data of the test circuit with the netlist data of the circuit to be tested , for manufacturing a chip including a circuit to be tested and a test circuit (for example, a low-power decoder 142 and a mask decoder 152 ).
  • a test circuit for example, a low-power decoder 142 and a mask decoder 152 .
  • the densely connected initial coding system can be simplified into a sparsely connected target coding system, so that fewer coding bits can be used to achieve greater coding success rate.
  • test data set expansion method is also used to amplify the test data set, which reduces The amount of data extracted from ATPG is reduced, thereby reducing design and simulation costs.
  • the BNN training model is used here to describe the optimization process from the initial decoder to the target decoder, the present disclosure is not limited thereto.
  • Other machine learning methods such as evolutionary algorithms can also be used to optimize the initial decoder.
  • an evolutionary algorithm can be used to hybridize, mutate, and/or increase or decrease the number of connection circuits of each decoding circuit in the initial decoder, to evaluate the evolved decoder, and to select a target decoder based on the evaluation result. device.
  • FIG. 7 shows a schematic block diagram of an electronic device 700 according to some embodiments of the present disclosure.
  • the electronic device 700 may include a plurality of modules for performing corresponding steps in the method 500 or 600 as discussed in FIG. 5 or FIG. 6 .
  • an electronic device 700 includes an initialization unit 702 and a modification unit 704 .
  • the initialization unit 702 is used to determine an initialization decoder at least based on the netlist data representing the circuit to be tested, the initialization decoder includes at least one decoding layer, and each decoding layer in the at least one decoding layer includes a plurality of decoding circuits .
  • the modifying unit 704 is configured to modify the connection of multiple decoding circuits in the initialization decoder to obtain a target decoder for testing the circuit based at least on the first test vector set for testing the circuit to be tested.
  • the circuit is configured to be coupled in the chip to the circuit under test.
  • the initialization unit is further used to use netlist data to determine the number of scan chains in the circuit to be tested; use the number of scan chains to calculate the number of layers of at least one decoding layer; use the number of scan chains and the number of layers to calculate A decoding array, the decoding array includes the number of decoding circuits in each decoding layer in at least one decoding layer; and an initialization decoder is constructed based on the number of layers and the decoding array.
  • the plurality of decoding circuits includes an accumulator and a comparator coupled to the accumulator.
  • the initialization unit is further used to set a plurality of decoding layers arranged in series according to the number of layers; according to the decoding array, set a corresponding number of decoding circuits in each decoding layer in the plurality of decoding; and set multiple Each comparator in the upper decoding layer in the decoding layer is connected to each accumulator in the lower decoding layer in the plurality of decoding layers to construct an initialization decoder.
  • the modifying unit is further configured to amplify the first set of test vectors into a second set of test vectors based on the characteristics of the circuit to be tested. At least one of the distribution of scan chains in the scan chain or the distribution of unknown states in the test cycle; and at least using the second set of test vectors to modify the connection of a plurality of decoding circuits in the initialization decoder to obtain the target decoding Encoder.
  • the modification unit is further used to determine the frequency of use of the plurality of scan chains during the test period using the scan chain distribution or the unknown state distribution; based on the frequency of use and a predetermined power threshold, randomly generate a plurality of random test vectors; A plurality of random test vectors are added in the first test vector set to generate the second test vector set, wherein the ratio of the specified bits in the test vectors in the second test vector set is evenly distributed, and the specified bit indicates that the test vector has the first The bits of the bit value.
  • the modifying unit is further used to randomly combine a plurality of test vectors in the first test vector set to generate a plurality of random test vectors; and add a plurality of random test vectors to the first test vector set to generate a second The set of test vectors, wherein the proportion of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bit represents the bit with the first value in the test vector.
  • the modifying unit is further configured to use the binary neural network model to represent the initialization decoder; use the first set of test vector sets in the second test vector set to train the binary neural network model to obtain candidate binary neural network models network; using a second test vector set in the second test vector set to verify the candidate binary neural network to obtain a target binary neural network; and determine a target decoder based on the target binary neural network.
  • the modifying unit is further used to initialize the initial connections between the various layers in the binary neural network model to the real number domain, so as to obtain the continuous domain neural model, and the multiple connections between the various layers in the continuous domain neural model weights are between 0 and 1 and multiple threshold constants between layers in the continuous domain neural model are respectively greater than 0; iteratively perform the following at least once: Use the test vector set in the first set of test vector sets for the continuous
  • the neural model is trained to obtain the intermediate neural network in the real number domain space; check whether the output of the intermediate neural network satisfies the objective function value; and if the output of the intermediate neural network does not satisfy the objective function value, use the gradient descent algorithm to evaluate the intermediate neural network updating to modify the values of multiple weights and multiple threshold constants; and if the output of the intermediate neural network satisfies the objective function value, converting the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network.
  • the modifying unit is further configured to compare the values of the plurality of weights with weight thresholds respectively: if the value of the first weight among the plurality of weights is lower than the weight threshold, the two translations associated with the first weight The coding layer is disconnected, or if the value of the second weight among the plurality of weights is lower than the weight threshold, the two decoding layers associated with the second weight are connected.
  • FIG. 8 shows a schematic block diagram of an example device 800 that may be used to implement embodiments of the present disclosure.
  • Device 800 may be used to implement electronic device 700 .
  • device 800 includes a computing unit 801 that may be loaded into RAM and/or ROM in accordance with computer program instructions stored in random access memory (RAM) and/or read only memory (ROM) 802 or from storage unit 807 802 to perform various appropriate actions and processes.
  • RAM and/or ROM 802 various programs and data necessary for the operation of device 800 may also be stored.
  • the computing unit 801 and the RAM and/or ROM 802 are connected to each other via a bus 803.
  • An input/output (I/O) interface 804 is also connected to the bus 803 .
  • I/O input/output
  • the I/O interface 804 includes: an input unit 805, such as a keyboard, a mouse, etc.; an output unit 806, such as various types of displays, speakers, etc.; a storage unit 807, such as a magnetic disk, an optical disk, etc. ; and a communication unit 808, such as a network card, a modem, a wireless communication transceiver, and the like.
  • the communication unit 808 allows the device 800 to exchange information/data with other devices over a computer network such as the Internet and/or various telecommunication networks.
  • the computing unit 801 may be various general-purpose and/or special-purpose processing components having processing and computing capabilities. Some examples of computing units 801 include, but are not limited to, central processing units (CPUs), graphics processing units (GPUs), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processing processor (DSP), and any suitable processor, controller, microcontroller, etc.
  • the calculation unit 801 executes various methods and processes described above, such as the method 500 and/or the method 600 .
  • method 500 and/or method 600 may be implemented as a computer software program tangibly embodied on a machine-readable medium, such as storage unit 807 .
  • part or all of the computer program may be loaded and/or installed onto device 800 via RAM and/or ROM and/or communication unit 808 .
  • the computer program When the computer program is loaded into RAM and/or ROM and executed by computing unit 801, one or more steps of method 500 and/or method 600 described above may be performed.
  • the computing unit 801 may be configured to execute the method 500 and/or the method 600 in any other suitable manner (for example, by means of firmware).
  • Program codes for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special purpose computer, or other programmable data processing devices, so that the program codes, when executed by the processor or controller, make the functions/functions specified in the flow diagrams and/or block diagrams Action is implemented.
  • the program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
  • a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device.
  • a machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium.
  • a machine-readable medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing.
  • machine-readable storage media would include one or more wire-based electrical connections, portable computer discs, hard drives, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM or flash memory), optical fiber, compact disk read only memory (CD-ROM), optical storage, magnetic storage, or any suitable combination of the foregoing.
  • RAM random access memory
  • ROM read only memory
  • EPROM or flash memory erasable programmable read only memory
  • CD-ROM compact disk read only memory
  • magnetic storage or any suitable combination of the foregoing.

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Abstract

本公开涉及一种用于设计译码器的方法、装置和设备。该方法包括基于网表数据形成初始译码器，以及通过使用测试向量集来训练二值神经网络模型，并且基于所得的二值神经网络来修改初始译码器中的每个译码层的译码电路的连接关系以获得目标译码器。由于目标译码器的各个译码层的输入连接是经过BNN迭代更新得到，因此各个译码电路的连接被优化，并且针对该目标译码器的编码成功率也相应地被提高。

Description

用于设计译码器的方法和电子设备 技术领域
本公开涉及电子领域，更具体而言涉及用于设计译码器的方法和电子设备。
背景技术
在芯片的制造过程和封装过程中不可避免的会因为各种原因(如工艺、材料等)导致芯片存在缺陷，这种缺陷会导致芯片无法正常工作。芯片测试的主要任务就是挑选出有缺陷的芯片。因为这种有缺陷的芯片流入市场后带来的开销将远远大于芯片测试的开销，因此芯片测试是芯片制造过程中至关重要的一环。
具体地，可以在芯片设计阶段向芯片中添加诸如扫描链(scan chain)之类的可测试性设计(design for testablility,DFT)结构，并且制造具有DFT结构的芯片。可以利用自动测试向量生成(automatic test pattern generation,ATPG)工具生成芯片测试向量(test pattern)，并利用自动测试设备(automatic test equipment,ATE)对待测芯片输入测试向量。通过比较被测芯片的回应与预期回应是否一致，可以在生产完成后立即进行质量检测。
随着芯片集成度和复杂度的不断提高，所需的测试向量集也随之快速增长。这导致芯片测试时间也增加了数倍，而测试时间的增加同时也极大增加了测试成本。为了缓解该问题，研究出了测试压缩技术。然而，常规的测试压缩技术存在编码比特位较多等问题。
发明内容
鉴于上述问题，本公开的实施例旨在提供一种用于设计译码器的方法、装置和设备以及对待测电路进行测试的测试电路，其中译码器被设计为测试电路的一部分。测试电路中的译码器用于对同一芯片中的待测电路进行测试。
根据本公开的第一方面，提供一种用于设计译码器的方法，译码器被设计为位于测试电路中。该方法包括：至少基于表示待测电路的网表数据，确定初始化译码器；以及至少基于用于对待测电路进行测试的第一测试向量集，对初始化译码器中的译码电路的连接进行修改以获得用于测试电路的目标译码器，测试电路被配置为在芯片中耦合至待测电路。通过使用测试向量集来改变译码器的译码电路的连接，可以获得输入连接数目和/或连接方式被优化的译码器。由于译码器的连接针对待测电路被优化，因此相比于常规的均衡异或门网络，可以减少与输入连接相关联的编码比特位的数目和/或复杂度。此外，译码器所接收的编码比特位组合也被优化。相应地，可以提高编码成功率。此外，还可以减少计算资源的开销。
在第一方面的一种可能实现方式中，初始化译码器包括至少一个译码层，至少一个译码层中的每个译码层包括多个译码电路，确定初始化译码器包括：使用网表数据来确定待测电路中的扫描链数目；使用扫描链数目来计算至少一个译码层的层数；使用扫描链数目和层数来计算译码数组，译码数组包括至少一个译码层中的译码电路在每个译码层的数目；以及基于层数和译码数组，构建初始化译码器。通过使用扫描链数目来确定层数，可以确保提供合适的译码层的数量，从而在保证译码成功率的前提下减少译码器的硬件实现成本，并且相应地减少译码开销。
在第一方面的一种可能实现方式中，多个译码电路包括累加器以及与累加器耦合的比较 器，构建初始化译码器包括：根据层数，设置被串联布置的多个译码层；根据译码数组，在多个译码层中的每个译码层中设置相应数目的译码电路；以及将多个译码层中上一级译码层的每个比较器与多个译码层中的下一级译码层中的每个累加器彼此连接，以构建初始化译码器。通过使用累加器和比较器，可以以相对简单的电路结构实现译码电路，从而减少译码器的电路实现成本。此外，由于译码电路均使用相同或相似的架构，因此可以减少译码器的设计成本。
在第一方面的一种可能实现方式中，至少基于第一测试向量集对初始化译码器中的多个译码电路的连接进行修改以获得用于测试电路的目标译码器包括：基于待测电路的特征，将第一测试向量集扩增为第二测试向量集，待测电路的特征包括待测电路的多个扫描链在测试周期中的扫描链分布或未知态在测试周期中的未知态分布中的至少一项；以及至少使用第二测试向量集对初始化译码器中的多个译码电路的连接进行修改以获得目标译码器。通过扩增测试向量集，可以避免通过大量的自动测试向量生成来获得二值神经网络所需的大量测试数据，从而减少测试成本并且能确保测试的准确性。
在第一方面的一种可能实现方式中，基于待测电路的特征将第一测试向量集扩增为第二测试向量集包括：使用扫描链分布或未知态分布确定多个扫描链在测试周期期间的使用频率；基于使用频率和预定功率阈值，随机生成多个随机测试向量；以及向第一测试向量集中添加多个随机测试向量以生成第二测试向量集，其中第二测试向量集中的测试向量中的指定比特位的比例是均匀分布的，指定比特位表示测试向量中具有第一位值的比特位。通过基于使用频率的方式添加随机测试向量集，可以获得符合测试向量特征的大量随机测试向量，从而确保二值神经网络获得的译码器的译码准确性。
在第一方面的一种可能实现方式中，基于待测电路的特征将第一测试向量集扩增为第二测试向量集包括：将第一测试向量集中的多个测试向量随机合并以生成多个随机测试向量；将多个随机测试向量向第一测试向量集中添加以生成第二测试向量集，其中第二测试向量集中的测试向量中的指定比特位的比例是正态分布的，指定比特位表示测试向量中具有第一位值的比特位。通过基于随机合并的方式添加随机测试向量集，可以获得符合测试向量特征的大量随机测试向量，从而确保二值神经网络获得的译码器的译码准确性。
在第一方面的一种可能实现方式中，至少使用第二测试向量集对初始化译码器中的多个译码电路的连接进行修改以获得目标译码器包括：使用二值神经网络模型表示初始化译码器；使用第二测试向量集中的第一组测试向量集对二值神经网络模型进行训练以获得候选二值神经网络；使用第二测试向量集中的第二组测试向量集对候选二值神经网络进行验证，以获得目标二值神经网络；以及基于目标二值神经网络，确定目标译码器。通过使用训练-验证的方式来确定目标译码器，从而进一步提高目标译码器的译码准确性。
在第一方面的一种可能实现方式中，使用第二测试向量集中的第一组测试向量集对二值神经网络模型进行训练以获得候选二值神经网络包括：将二值神经网络模型中的各个层之间的初始连接初始化到实数域，以获得连续域神经模型，连续域神经模型中的各个层之间的多个权重分别位于第一值和第二值之间并且连续域神经模型中的各个层之间的多个阈值常数分别大于第一值；迭代地执行以下项至少一次：使用第一组测试向量集中的测试向量集对连续神经模型进行训练以获得在实数域空间中的中间神经网络；检查中间神经网络的输出是否满足目标函数值；以及如果中间神经网络的输出不满足目标函数值，则使用梯度下降算法对中间神经网络进行更新，以修改多个权重的值和多个阈值常数的值；以及如果中间神经网络的 输出满足目标函数值，则将中间神经网络转换为二值离散域，以获得候选二值神经网络。通过将二值神经网络转换为实数域并且通过迭代的方式训练二值神经网络，可以准确且快速地确定候选的二值神经网络。
在第一方面的一种可能实现方式中，将中间神经网络转换为二值离散域以获得候选二值神经网络包括：将多个权重的值分别与权重阈值比较：如果多个权重中的第一权重的值低于权重阈值，则将第一权重所关联的两个译码层断开，或如果多个权重中的第二权重的值低于权重阈值，则将第二权重所关联的两个译码层连接。通过使用权重的值来确定二值神经网络所表示的译码层中各个译码电路之间的连接关系，可以以简易且灵活的方式确定目标译码器。
在本公开的第二方面，提供一种计算机可读存储介质，存储多个程序，多个程序被配置为一个或多个处理器执行，多个程序包括用于执行第一方面的方法的指令。通过使用测试向量集来改变译码器的译码电路的连接，可以获得输入连接数目和/或连接方式被优化的译码器。由于译码器的连接针对待测电路被优化，因此相比于常规的均衡异或门网络，可以减少与输入连接相关联的编码比特位的数目和/或复杂度。此外，译码器所接收的编码比特位组合也被优化。相应地，可以提高编码成功率。此外，还可以减少计算资源的开销。
在本公开的第三方面，提供一种计算机程序产品，计算机程序产品包括多个程序，多个程序被配置为一个或多个处理器执行，多个程序包括用于第一方面的方法的指令。通过使用测试向量集来改变译码器的译码电路的连接，可以获得输入连接数目和/或连接方式被优化的译码器。由于译码器的连接针对待测电路被优化，因此相比于常规的均衡异或门网络，可以减少与输入连接相关联的编码比特位的数目和/或复杂度。此外，译码器所接收的编码比特位组合也被优化。相应地，可以提高编码成功率。此外，还可以减少计算资源的开销。
在本公开的第四方面，提供一种电子设备。电子设备包括：一个或多个处理器；包括计算机指令的存储器，计算机指令在由电子设备的一个或多个处理器执行时使得电子设备执行第一方面的方法。通过使用测试向量集来改变译码器的译码电路的连接，可以获得输入连接数目和/或连接方式被优化的译码器。由于译码器的连接针对待测电路被优化，因此相比于常规的均衡异或门网络，可以减少与输入连接相关联的编码比特位的数目和/或复杂度。此外，译码器所接收的编码比特位组合也被优化。相应地，可以提高编码成功率。此外，还可以减少计算资源的开销。
在本公开的第五方面，提供一种电子设备。电子设备包括：初始化单元和修改单元。初始化单元用于至少基于表示待测电路的网表数据确定初始化译码器。修改单元，用于至少基于用于对待测电路进行测试的第一测试向量集，对初始化译码器中的译码电路的连接进行修改以获得用于测试电路的目标译码器，测试电路被配置为在芯片中耦合至待测电路。通过使用测试向量集来改变译码器的译码电路的连接，可以获得输入连接数目和/或连接方式被优化的译码器。由于译码器的连接针对待测电路被优化，因此相比于常规的均衡异或门网络，可以减少与输入连接相关联的编码比特位的数目和/或复杂度。此外，译码器所接收的编码比特位组合也被优化。相应地，可以提高编码成功率。此外，还可以减少计算资源的开销。
在第五方面的一种实现方式中，初始化译码器包括至少一个译码层，至少一个译码层中的每个译码层包括多个译码电路，初始化单元进一步用于：使用网表数据来确定待测电路中的扫描链数目；使用扫描链数目来计算至少一个译码层的层数；使用扫描链数目和层数来计算译码数组，译码数组包括至少一个译码层中的译码电路在每个译码层的数目；以及基于层数和译码数组，构建初始化译码器。通过使用扫描链数目来确定层数，可以确保提供合适的 译码层的数量，从而在保证译码成功率的前提下减少译码器的硬件实现成本，并且相应地减少译码开销。
在第五方面的一种实现方式中，多个译码电路包括累加器以及与累加器耦合的比较器，初始化单元进一步用于：根据层数，设置被串联布置的多个译码层；根据译码数组，在多个译码中的每个译码层中设置相应数目的译码电路；以及将多个译码层中上一级译码层的每个比较器与多个译码层中的下一级译码层中的每个累加器彼此连接，以构建初始化译码器。通过使用累加器和比较器，可以以相对简单的电路结构实现译码电路，从而减少译码器的电路实现成本。此外，由于译码电路均使用相同或相似的架构，因此可以减少译码器的设计成本。
在第五方面的一种实现方式中，修改单元进一步用于：基于待测电路的特征，将第一测试向量集扩增为第二测试向量集，待测电路的特征包括待测电路的多个扫描链在测试周期中的扫描链分布或未知态在测试周期中的未知态分布中的至少一项；以及至少使用第二测试向量集对初始化译码器中的多个译码电路的连接进行修改以获得目标译码器。通过扩增测试向量集，可以避免通过大量的自动测试向量生成来获得二值神经网络所需的大量测试数据，从而减少测试成本并且能确保测试的准确性。
在第五方面的一种实现方式中，修改单元进一步用于：使用扫描链分布或未知态分布确定多个扫描链在测试周期期间的使用频率；基于使用频率和预定功率阈值，随机生成多个随机测试向量；以及向第一测试向量集中添加多个随机测试向量以生成第二测试向量集，其中第二测试向量集中的测试向量中的指定比特位的比例是均匀分布的，指定比特位表示测试向量中具有第一位值的比特位。通过基于使用频率的方式添加随机测试向量集，可以获得符合测试向量特征的大量随机测试向量，从而确保二值神经网络获得的译码器的译码准确性。
在第五方面的一种实现方式中，修改单元进一步用于：将第一测试向量集中的多个测试向量随机合并以生成多个随机测试向量；以及将多个随机测试向量向第一测试向量集中添加以生成第二测试向量集，其中第二测试向量集中的测试向量中的指定比特位的比例是正态分布的，指定比特位表示测试向量中具有第一位值的比特位。通过基于随机合并的方式添加随机测试向量集，可以获得符合测试向量特征的大量随机测试向量，从而确保二值神经网络获得的译码器的译码准确性。
在第五方面的一种实现方式中，修改单元进一步用于：使用二值神经网络模型表示初始化译码器；使用第二测试向量集中的第一组测试向量集对二值神经网络模型进行训练以获得候选二值神经网络；使用第二测试向量集中的第二组测试向量集对候选二值神经网络进行验证，以获得目标二值神经网络；以及基于目标二值神经网络，确定目标译码器。通过使用训练-验证的方式来确定目标译码器，从而进一步提高目标译码器的译码准确性。
在第五方面的一种实现方式中，修改单元进一步用于：将二值神经网络模型中的各个层之间的初始连接初始化到实数域，以获得连续域神经模型，连续域神经模型中的各个层之间的多个权重分别位于第一值和第二值之间并且连续域神经模型中的各个层之间的多个阈值常数分别大于第一值；迭代地执行以下项至少一次：使用第一组测试向量集中的测试向量集对连续神经模型进行训练以获得在实数域空间中的中间神经网络；检查中间神经网络的输出是否满足目标函数值；以及如果中间神经网络的输出不满足目标函数值，则使用梯度下降算法对中间神经网络进行更新，以修改多个权重的值和多个阈值常数的值；以及如果中间神经网络的输出满足目标函数值，则将中间神经网络转换为二值离散域，以获得候选二值神经网络。通过将二值神经网络转换为实数域并且通过迭代的方式训练二值神经网络，可以准确且快速 地确定候选的二值神经网络。
在第五方面的一种实现方式中，修改单元进一步用于：将多个权重的值分别与权重阈值比较：如果多个权重中的第一权重的值低于权重阈值，则将第一权重所关联的两个译码层断开，或如果多个权重中的第二权重的值低于权重阈值，则将第二权重所关联的两个译码层连接。通过使用权重的值来确定二值神经网络所表示的译码层中各个译码电路之间的连接关系，可以以简易且灵活的方式确定目标译码器。
在本公开的第六方面，提供一种用于对待测电路进行测试的电路。该电路包括第一译码器，耦合至待测电路并且被配置为将多个第一编码比特位译码为多个第一译码比特位，第一译码器包括至少一个译码层，至少一个译码层中的每个译码层包括多个译码电路，每个译码电路包括累加器和与累加器耦合的比较器。由于译码器的连接针对待测电路被优化，因此相比于常规的均衡异或门网络，可以减少与输入连接相关联的编码比特位的数目和/或复杂度。此外，译码器所接收的编码比特位组合也被优化。相应地，可以提高编码成功率。此外，还可以减少计算资源的开销。
在第六方面的一种实现方式中，至少一个译码层包括：第一译码层，被配置为基于多个第一编码比特位输出多个第一中间比特位；以及第二译码层，被配置为基于多个第一中间比特位输出多个第一译码比特位，多个第一译码比特位的数目多于多个第一中间比特位的数目。
在第六方面的一种实现方式中，至少一个译码层中的每个译码层包括第一译码电路和第二译码电路，第一译码电路的连接和第二译码电路的连接不同。
在第六方面的一种实现方式中，至少一个译码层中的最后一级译码层的多个译码电路分别经由多个第一与门与待测电路的多个扫描链耦合；或至少一个译码层中的最后一级译码层的多个译码电路分别与多个扫描链耦合至多个第二与门。
在第六方面的一种实现方式中，该电路还包括第二译码器，耦合至待测电路并且被配置为将多个第二编码比特位译码为多个第二译码比特位，第二译码器包括至少一个译码层，至少一个译码层中的每个译码层包括多个译码电路，每个译码电路包括累加器和与累加器耦合的比较器。通过使用累加器和比较器，可以以相对简单的电路结构实现译码电路，从而减少译码器的电路实现成本。此外，由于译码电路均使用相同或相似的架构，因此可以减少译码器的设计成本。
应当理解，发明内容部分中所描述的内容并非旨在限定本公开的实施例的关键或重要特征，亦非用于限制本公开的范围。本公开的其它特征将通过以下的描述变得容易理解。
附图说明
结合附图并参考以下详细说明，本公开各实施例的上述和其他特征、优点及方面将变得更加明显。在附图中，相同或相似的附图标记表示相同或相似的元素，其中：
图1示出了一种常规译码器的示意电路图。
图2示出了本公开的一些实施例可以实施于其中的环境示意图。
图3示出了根据本公开的一些实施例的初始编译码系统的示意图。
图4示出了根据本公开的一些实施例的目标编译码系统的示意图。
图5示出了根据本公开的一些实施例的用于设计测试电路的方法的流程示意图。
图6示出了根据本公开的一些实施例的用于获得候选二值神经网络的方法的流程示意图。
图7示出了根据本公开的一些实施例的电子设备的示意框图。
图8示出了可以用来实施本公开的实施例的示例设备的示意性框图。
具体实施方式
下面将参照附图更详细地描述本公开的实施例。虽然附图中显示了本公开的某些实施例，然而应当理解的是，本公开可以通过各种形式来实现，而且不应该被解释为限于这里阐述的实施例，相反提供这些实施例是为了更加透彻和完整地理解本公开。应当理解的是，本公开的附图及实施例仅用于示例性作用，并非用于限制本公开的保护范围。
在本公开的实施例的描述中，术语“包括”及其类似用语应当理解为开放性包含，即“包括但不限于”。术语“基于”应当理解为“至少部分地基于”。术语“一个实施例”或“该实施例”应当理解为“至少一个实施例”。术语“第一”、“第二”等等可以指代不同的或相同的对象。术语“和/或”表示由其关联的两项的至少一项。例如“A和/或B”表示A、B、或者A和B。下文还可能包括其他明确的和隐含的定义。
应理解，本申请实施例提供的技术方案，在以下具体实施例的介绍中，某些重复之处可能不再赘述，但应视为这些具体实施例之间已有相互引用，可以相互结合。
在芯片的电子设计自动化(electronic design automation，EDA)设计过程中，用户向EDA软件输入配置，由EDA软件生成逻辑电路，然后通过制版和流片得到芯片。在对芯片进行测试的过程中，可以将芯片安装在ATE并且由ATE向IC芯片的输入管脚输入测试激励。通过比较芯片的输出管脚的响应与期望响应，可以判断芯片是否合格。如上所述，随着芯片集成度和复杂度的不断提高，所需的测试向量集也随之快速增长。这导致了芯片测试成本的增加。为了控制测试成本，测试压缩技术被提出以实现在压缩测试向量的同时保证测试覆盖率(test coverage)。测试压缩技术是基于扫描链的。扫描链技术本质上是将时序电路中的触发器连接成多个“移位寄存器(scan cells)”，每一个移位寄存器的输入输出值都可以被单独观测。
测试压缩技术的可行性基于以下事实：由ATPG生成的单个原始测试向量包含扫描链上所有移位寄存器的输入值，而只有少部分移位寄存器上的输入值才是有效值。因此可以将原始测试向量进行压缩，并通过激励解压缩模块(decompressor)进行解压恢复出有效值。另外，扫描链上的输出值也可以经过响应压缩模块(compactor)进行压缩。输出压缩值通过输出管脚送入ATE，ATE将输出压缩值与期望值进行比对定位出发生错误的扫描链移位寄存器位置。
在测试压缩技术中，对于扫描链移位寄存器的输入值和输出值的压缩比率往往可以达到成百上千，因此极大缩小了测试向量的存储量。但与此同时也引入了两个测试压缩领域最核心的问题。第一个问题针对功耗。移位寄存器原始输入值中有效值很少(具有稀疏性)，因此在输入阶段扫描链上的移位功耗也很少。但是输入压缩值经解压缩后往往不再具有稀疏性。在将解压缩后的值直接移位到对应的移位寄存器上的过程中，将会产生无法忍受的移位功耗。这会造成芯片测试的良率下降、测试稳定性降低，甚至会造成芯片在测试中过热而被烧毁等后果。第二个问题针对测试过程中生成的未知态(X态)的掩盖。由于某些电路模块功能未知，会输出一些无法预测的未知值(unknown value)，这些未知值称为X态。扫描链上分布着一些产生X态的电路，这些X态分布在扫描链输出值上。在响应压缩模块进行压缩时，这些X态会将同步进行压缩的其他电路有效值掩盖，从而造成电路中相关位置的不可观测。这会造成故障覆盖率下降、测试向量数目增加等后果。
常规方案通过分别引入低功耗控制模块和掩码控制模块来解决以上两个问题。低功耗控制模块和掩码控制模块在功能上是相似的，都是一个译码器。低功耗控制模块的译码输出控 制扫描链的输入值，当译码输出为0时，向所控制的扫描链中移位寄存器输入固定值，否则，向所控制的扫描链中移位寄存器输入解压缩模块的输出值。掩码控制模块的译码输出控制对应扫描链向响应压缩模块的输入值，当译码输出为0时，将所控制扫描链向响应压缩模块的输入值钳位为一个固定值，否则，将所控制扫描链的输出值输入响应压缩模块。这两个控制模块的译码输出连接到每一条扫描链上，并通过将译码输出值置为1或0实现对应扫描链的打开或者关闭。低功耗控制模块将含有有效输入值的扫描链置为打开状态以允许激励解压缩模块输入移位值至待测电路中的扫描链中，而掩码控制模块将含有X态输出的扫描链置为关闭状态以阻止待测电路中的扫描链的X态的输出。例如，在一些常规方案中，可以使用异或门网络来形成译码器。
图1示出了一种常规译码器100的示意电路图。译码器100是均衡逻辑门网络，并且采用的逻辑门是异或门(XOR)。均衡逻辑门网络中的每个逻辑门的输入连接的数目是相同的，例如在图1中，每个XOR具有三个输入连接。在图1中，译码器100包括6个编码比特位X1、X2……X6和12个译码比特位Y1、Y2……Y12。每个XOR具有分别接收6个编码比特位X1、X2……X6中的三个编码比特位的三个输入连接。每个XOR基于三个编码比特值的逻辑值进行异或操作生成12个译码比特位Y1、Y2……Y12中的一个译码比特位。在另一些实施例中，逻辑门网络还可以是基于XOR和AND门的。在一般情况下，这种结构使用三个编码比特做XOR操作后的值表示对应扫描链的控制状态。对于低功耗控制模块，当用户设定的输入移位功耗阈值较低时，这种结构用到的编码比特位会更多，同时也会将XOR网络结构的多个输出值进一步做AND操作来控制一条扫描链。然而，这种均衡异或门网络结构对于每条扫描链的控制力度是均等的，然而实际自动测试向量生成过程中对每条扫描链的使用频率是不同的。因此，使用这种均衡逻辑门网络会导致编码能力的浪费或不足。此外，为了保证编码成功率，这种结构用到的编码位较多，硬件和软件开销等计算资源的消耗比较大。
在本公开的一些实施例中，提供一种用于对待测电路进行测试的电路。该电路包括至少一个译码器。每个译码器包括至少一个译码层，并且每个译码层包括多个译码电路。每个译码电路包括累加器和与累加器耦合的比较器。通过优化译码层中的每个译码电路的连接关系，例如通过二值神经网络(binary neural network，BNN)对每个译码电路的连接关系进行优化，可以使用具有更少编码比特位的编码数据来进行译码，从而获得更强大的编码能力。相比于常规的XOR网络结构，本公开的测试电路对于每条扫描链的控制力度是经过优化而不同的，因此，使用本公开的测试电路可以减少编码比特位的使用，提升编码能力，并且不会因此导致浪费。此外，由于优化的前提之一可以是编码成功率，因此本公开的测试电路使用的编码位相对较少，并且硬件和软件开销等计算资源的消耗相对较小。
图2示出了本公开的一些实施例可以实施于其中的环境200的示意图。如图2所示，芯片200包括待测电路11、低功耗移位寄存器16、掩码寄存器18、解压缩模块12、压缩模块13、低功耗控制器14、掩码控制器15、多个与门7-1、7-2…..7-N和多个与门9-1、9-2……9-N，其中N表示大于1的整数。在芯片200中，低功耗移位寄存器16、掩码寄存器18、解压缩模块12、压缩模块13、低功耗控制器14、掩码控制器15、多个与门7-1、7-2…..7-N和多个与门9-1、9-2……9-N用于对待测电路11进行测试。因此，在一个实施例中，芯片200的测试电路可以包括低功耗控制器14或掩码控制器15中的至少一项。在另一实施例中，芯片200的测试电路可以还包括低功耗移位寄存器16、掩码寄存器18、解压缩模块12、压缩模块13、多个与门7-1、7-2…..7-N和多个与门9-1、9-2……9-N。在对芯片200进行实际测试时，ATE 通过芯片200的少量输入管脚向芯片200的低功耗移位寄存器16输入ATPG测试向量。ATPG测试向量包含解压缩模块12的输入压缩值，即压缩种子(compressed seed)、低功耗控制器14的编码值和掩码控制器15的编码值等。输入压缩值经由低功耗移位寄存器16和掩码寄存器18被注入解压缩模块12。低功耗控制器14的编码值经由低功耗移位寄存器16被注入低功耗控制器14，并且掩码控制器15的编码值经由低功耗移位寄存器16和掩码寄存器18被注入掩码控制器15。在输入阶段，低功耗控制器14将编码值进行译码，以打开合适的扫描链。解压缩模块12将低功耗移位寄存器16的输入压缩值解压，并将解压后的值在低功耗控制器14的控制下通过移位填充到对应的移位寄存器上。
在输出阶段，掩码控制器15将编码值进行译码，通过使用译码比特值对扫描链输出值中X态进行掩盖，并将处理后的输出值送入响应压缩模块13进行压缩。在一个实施例中，待测电路11包括多个扫描链11-1、11-2……11-N(下文单独或统称为11)，扫描链的数目与多个与门7-1、7-2…..7-N(下文单独或统称为7)和多个与门9-1、9-2……9-N(下文单独或统称为9)分别对应。每个扫描链可以包括一个或多个待测电路中的时序逻辑电路，例如寄存器。该时序逻辑异或门网络响应于移位输出而生成移位输出。低功耗控制器14包括低功耗寄存器141和译码器142，译码器142通过译码生成控制信号以控制与门7-1、7-2…..7-N中的一个或多个与门的导通或关断。例如，在多个周期内，译码器142可以持续生成逻辑值“1”给与门7-1，以使得解压值被陆续移位输入至扫描链11-1。与此同时，译码器142可以输出“0”以关断与门7-2…..7-N，以使得扫描链11-2……11-N持续接收“0”。由于扫描链11-2……11-N没有逻辑值改变，因此芯片中的时序逻辑门没有操作。由于时序逻辑门不进行操作，因此可以降低测试过程中的功耗。掩码控制器15包括掩码寄存器151和掩码译码器152，掩码译码器152通过译码生成控制信号以控制与门9-1、9-2……9-N中的一个或多个与门的导通或关断。类似地，掩码译码器152通过译码可以产生控制信号以关闭与门9-1、9-2……9-N中的与具有X态的扫描链对应的与门。
应理解，本申请实施例不对解压缩模块12的结构进行限定。解压缩模块12可以是任何能够实现将少量测试激励扩展为大量扫描链测试向量并将测试向量输出的电路。解压缩模块12例如可以基于随机信号发生器。在本公开的一些实施例中，解压缩模块12可以包括伪随机序列生成器121和基于逻辑门网络的相位移码器122。伪随机序列生成器121可以将注入的输入压缩值进行第一次解压，生成位宽更大的伪随机序列，相位移码器122将改伪随机序列进行译码，得到对应各个周期的各扫描链的移位值。对于给定的伪随机序列位宽，伪随机序列生成器121生成的伪随机序列状态空间是优选的，且伪随机序列的最大数目是固定的。这也同时决定了解压缩结构所能利用的解空间上限。因此，在有限且固定的解压缩结构解空间的前提下设计更优的相位移码器122，也是解压缩模块的一个核心问题。在本公开的一些实施例中，提供基于非均衡逻辑门网络的相位移码器122，其中该非均衡逻辑门网络中的至少一些逻辑门的输入可以具有不同的输入连接数目。
类似地，本申请实施例不对响应压缩模块13的结构进行限定。响应压缩模块13可以是任何能够接收测试响应并将接收到的测试响应进行逻辑运算以从少量的输出通道输出的电路。响应压缩模块13例如可以是基于多输入特征寄存器(multiple-input signature register，MISR)或者诸如异或门(XOR)网络之类的逻辑门网络的压缩模块。
图3示出了根据本公开的一些实施例的初始编译码系统300的示意图。可以使用诸如计算机之类的电子设备来设计初始编译码系统300。初始编译码系统300包括初始编码输入部 310、编码器320、初始译码输入部330、译码器340和初始译码输出部350。初始编码输入部310包括多个初始比特位的输入I11、I12、I13、I14、I15、I16……I1A，以接收多个初始比特位，其中A表示大于1的整数。多个初始比特位可以源自第一测试向量集，第一测试向量集可以由包括多个测试数据包括的原始测试向量集获得。下文将描述关于第一测试向量集的具体形成方法。
编码器320包括至少一个编码层，其中在包括多个编码层的情形下，多个编码层串联连接以形成逐级布置的多个编码层。在图3示出了编码器320包括两个编码层321和322。可以理解，这仅是示意而非对本公开的范围进行限制。编码器320可以包括其它数目的编码层，例如一个编码层或是三个或更多个编码层。第一编码层321包括多个编码电路X11、X12、X13、X14……X1B，并且第二编码层322包括多个编码电路X21、X22……X2C，其中B和C分别表示大于1的整数。
每个编码层包括多个编码电路。在一个实施例中，编码器320中的多级编码层可以按编码电路的数目逐级递减的方式布置。例如，第一级编码层321中包括的编码电路的数目多于第二级编码层322中包括的编码电路的数目。即，B的数值大于C的数值。
初始编码输入部310中的每个初始比特位的输入分别被提供给编码器320中的第一级编码层321中的多个编码电路。例如，第一初始比特位I11的输入被提供给第一级编码层321中的每个编码电路。第二初始比特位I12的输入也同样被提供给第一级编码层321中的每个编码电路，以此类推。仅为了图示的清楚性，在图3中未示出多个初始比特位的输入I12、I13、I14、I15、I16……I1A连至第一级编码层321中的每个编码电路的连接，但是可以理解，在初始编译码系统300中存在这样的连接。
类似地，第一级编码层321中的每个编码电路，例如第一编码电路X11，连至第二级编码层322中的多个编码电路X21、X22……X2C中每个编码电路。在图3的编码器320中，每个编码电路包括一个累加器和一个比较器。例如，第一级编码层321中的第一编码电路X11包括第一累加器X111和与第一累加器X111连接的第一比较器112。第一累加器X111可以将多个输入的值进行累加，第一比较器112可以将累加值与预定值进行比较并且输出比较结果给第二级编码层322。第二级编码层322中的多个编码电路可以进行类似操作。
编码器320中的最后一级编码层，在图3中为第二级编码层322，可以将多个编码输出提供至初始译码输入部330。初始译码输入部330包括多个初始中间比特位Z1、Z2……ZD，其中D表示大于1的整数。在一个实施例中，D的数值小于C的数值。备选地，D的数值可以等于C的数值。
译码器340包括至少一个译码层，其中在包括多个译码层的情形下，多个译码层串联连接以形成逐级布置的多个译码层。在图3示出了译码器340包括两个译码层341和342。可以理解，这仅是示意而非对本公开的范围进行限制。译码器340可以包括其它数目的译码层，例如一个译码层或是三个或更多个译码层。第一译码层341包括多个编码电路Y11、Y12……Y1E，并且第二译码层342包括多个译码电路Y21、Y22、Y23、Y24……Y2F，其中E和F分别表示大于1的整数。
每个译码层包括多个译码电路。在一个实施例中，译码器340中的多级编码层可以按译码电路的数目逐级递增的方式布置。例如，第一级译码层341中包括的译码电路的数目少于第二级译码层342中包括的译码电路的数目。即，E的数值小于F的数值。
初始译码输入部330中的每个初始中间比特位的输入分别被提供给译码器340中的第一 级译码层341中的多个译码电路Y11、Y12……Y1E中的每个译码电路。例如，第一初始中间比特位Z1的输入被提供给第一级译码层341中的每个译码电路。第二初始比特位Z2的输入也同样被提供给第一级译码层341中的每个译码电路，以此类推。仅为了图示的清楚性，在图3中未示出多个初始中间比特位的输入Z2……ZD连至第一级译码层341中的每个译码电路的连接，但是可以理解，在初始编译码系统300中存在这样的连接。
类似地，第一级译码层341中的每个译码电路，例如第一译码电路Y11，连至第二级译码层342中的多个译码电路Y21、Y22……Y2F中每个译码电路。在图3的译码器340中，每个译码电路包括一个累加器和一个比较器。例如，第一级译码层341中的第一译码电路Y11包括与第一级编码器X11类似的第一累加器X111和与第一累加器X111连接的第一比较器112。第一累加器X111可以将多个输入的值进行累加，第一比较器112可以将累加值与预定值进行比较并且输出比较结果给第二级译码层342。第二级译码层342中的多个译码电路可以进行类似操作。
译码器340中的最后一级译码层，在图3中为第二级译码层342，可以将多个译码输出提供至初始译码输出部350。初始译码输出部350包括多个初始输出比特位O11、O12、O13、O14、O15、O16……O1G，其中G表示大于1的整数。在一个实施例中，G的数值大于F的数值。备选地，G的数值可以等于F的数值。由于初始译码输出部350与待测电路11中的多个扫描链相对应，因此G的数值可以与待测电路11中的扫描链的数目相同。
在图3的初始编译码系统300中，在一个实施例中，可以通过改变图3中的初始编译码系统300的各个编码电路和译码电路的连接关系来获得目标编译码系统。例如，可以使用BNN对初始编译码系统300的编码电路和译码电路的连接关系进行改变，以获得优化的目标编译码系统。图4示出了根据本公开的一些实施例的目标编译码系统400的示意图。可以使用诸如计算机之类的电子设备来设计目标编译码系统400。目标编译码系统400包括目标编码输入部410、编码器420、目标译码输入部430、译码器440和目标译码输出部450。图4的目标编译码系统400具有与初始编译码系统300相似的架构，不同之处在于各个编码电路和译码电路的连接方式因被优化而有所不同。例如，目标编码输入部410中的第一编码比特位仅被提供至第一编码层421中的第一编码电路X11和编码电路X1B。例如，第一编码层421中的第一编码电路X11的输出被优化为仅提供至第二编码层422中的编码电路X21、X22和X2C。例如，第二编码层422中的编码电路X21的输出被优化为仅提供至目标译码输入部430中的译码输入Z2和ZD。例如，目标译码输入部430中的目标译码输入Z1输出被优化为仅提供至第一译码层441中的译码电路Y11、Y12和Y1E，并且第一译码层441中的译码电路Y11的输出被优化为仅提供至第二译码层442中的译码电路Y21、Y24和Y2F。例如，第二译码层442中的译码电路Y21的输出被优化为仅提供至目标译码输出部450中的目标译码输出O11和O1G。可以理解，上述举例说明的优化连接仅是用于示例说明，而非对本公开的范围进行限制。针对不同的待测电路11，可以具有不同的连接关系。此外，虽然在图3中将标编码输入部410和编码器420单独示出，并且将目标译码输出部450和译码器440单独示出，但是这仅是示意，而非对本公开的范围进行限制。在一些实施例中，目标编码输入部410可以是编码器420的一部分，并且目标译码输出部450可以是译码器440的一部分。
译码器440包括至少一个译码层，其中在包括多个译码层的情形下，多个译码层串联连接以形成逐级布置的多个译码层。在图4示出了译码器440包括两个译码层441和442。可以理解，这仅是示意而非对本公开的范围进行限制。译码器440可以包括其它数目的译码层， 例如一个译码层或是三个或更多个译码层。第一译码层441包括多个编码电路Y11、Y12……Y1E，并且第二译码层442包括多个译码电路Y21、Y22、Y23、Y24……Y2F，其中E和F分别表示大于1的整数。
每个译码层包括多个译码电路。在一个实施例中，译码器440中的多级编码层可以按译码电路的数目逐级递增的方式布置。例如，第一级译码层441中包括的译码电路的数目少于第二级译码层442中包括的译码电路的数目。即，E的数值小于F的数值。
目标译码输入部430中的每个第一编码比特位的输入分别被提供给译码器340中的第一级译码层341中的多个译码电路Y11、Y12和Y1E。第一编码比特位Z2的输入也同样被提供给第一级译码层341中的至少一个译码电路，以此类推。仅为了图示的清楚性，在图4中未示出多个第一编码比特位的输入Z2……ZD连至第一级译码层441中的每个译码电路的连接，但是可以理解，在目标编译码系统400中存在这样的连接。
类似地，第一级译码层441中的每个译码电路选择性地连接至第二级译码层342中的至少一个译码电路。在图4的译码器440中，每个译码电路包括一个累加器和一个比较器，与图3类似。译码器440中的最后一级译码层，在图4中为第二级译码层442，可以将多个第一译码比特位提供至目标译码输出部450。目标译码输出部450包括多个目标输出比特位O11、O12、O13、O14、O15、O16……O1G，其中G表示大于1的整数。在一个实施例中，G的数值大于F的数值。备选地，G的数值可以等于F的数值。由于目标译码输出部450与待测电路11中的多个扫描链相对应，因此G的数值可以与待测电路11中的扫描链的数目相同。
为了确保编码成功率，在从目标编码输入部410到目标译码输入部430的缩减比特的编码过程和从目标译码输入部430到目标译码输出部450的增加比特位的译码过程，编译码系统400需要将在目标译码输出部450输出的比特数据尽可能的恢复为在目标编码输入部410输入的比特数据。在满足这样的需求的情形下，电子设备所获得的译码器440可以认为是满足要求的译码器。在此基础之上，可以将译码器440的设计融入包括待测电路11的芯片设计，并且付诸于芯片制造。例如，可以将诸如译码器440之类的目标译码器用于实现低功耗译码器142和/或掩码译码器152。在一些实施例中，还可以使用电子设备设计多个备选译码器，并且基于额外的一些因素或其它因素来选择目标译码器，如下文具体描述。
图5示出了根据本公开的一些实施例的用于设计测试电路的方法500的流程示意图。方法500可以由诸如计算机之类的电子设备执行。可以理解，上面针对图2-图4所描述的各个方面可以选择性的适用于方法500。下面将结合图2-图4中的特征来描述方法500。
在502，电子设备可以至少基于表示待测电路11的网表数据确定初始化译码器。网表数据可以描述电路的各个特征，例如电路中各个器件的性质和彼此之间的连接关系。例如，可以基于网表数据确定待测电路11中用于测试的扫描链的数目。在一个实施例中，初始化译码器包括至少一个译码层，至少一个译码层中的每个译码层包括多个译码电路。例如，初始化译码器可以是图3中的译码器340。因此，在一个实施例中，可以基于扫描链的数目来确定初始化译码器。
在一个实施例中，电子设备可以使用网表数据来确定待测电路中的扫描链数目N。扫描链数目N可以用于确定图3中所示的编译码系统300的编码器320中的编码层数L E和译码器340中的译码层数L D。例如，可以使用下式(1)来计算编码层数L E和译码层数L D。
L E＝L D＝log(N/D 0)      (1)
其中D0表示预定值，可以基于待测电路11而预先设置。备选地，也可以使用其它方式 确定层数。
电子设备继而可以使用使用扫描链数目N和层数L E或L D来计算编码或译码数组。编码数组包括至少一个编码层的编码电路在每个编码层的数目，译码数组表示至少一个译码层中的译码电路在每个译码层的数目。在一个实施例中，可以使用下式(2)来确定编码器的层数关系。
Figure PCTCN2021116552-appb-000001
其中d el表示第el层中的编码电路的数目，并且d el+1表示第el+1层中的编码电路的数目。由于每层包括的编码电路的数目不同(逐级递减)，因此可以建立编码数组来表示每层中的编码电路的数目。
在一个实施例中，可以使用下式(3)来确定译码器的层数关系。
Figure PCTCN2021116552-appb-000002
其中d dl表示第dl层中的译码电路的数目，并且d dl+1表示第dl+1层中的译码电路的数目。由于每层包括的译码电路的数目不同(逐级递增)，因此可以建立译码数组来表示每层中的译码电路的数目。
备选地，也可以使用其它方式确定各层之中的编码电路或译码电路的数目。本公开对此不进行限制。由于每个译码电路和编码电路具有基本上相似的结构，例如串联耦合的累加器和比较器，因此基于层数和译码数组，电子设备可以构建初始化译码器，或基于层数和编码数组，电子设备可以构建初始化编码器。
在一个实施例中，多个译码电路包括累加器以及与累加器耦合的比较器。电子设备可以根据层数L D，设置被串联布置的多个译码层。根据译码数组，电子设备在多个译码层中的每个译码层中设置相应数目的译码电路。进一步地，电子设备可以将多个译码层中上一级译码层的每个比较器与多个译码层中的下一级译码层中的每个累加器彼此连接，以构建初始化译码器。可以理解，对于编码器，电子设备可以类似地设置。
在504，电子设备可以至少基于用于对待测电路进行测试的第一测试向量集对初始化译码器中的多个译码电路的连接进行修改，以获得用于测试电路的目标译码器。测试电路被配置为在芯片中耦合至待测电路。在一个实施例中，目标译码器例如可以是图4的目标译码器440。此外，还可以获得目标编码器，例如目标编码器420。可以理解，在一种具体实现方式中，由于待测电路11仅需译码器440对其进行测试，并且实际的测试向量可以被直接提供至译码器440，因此编码器420的设计在一个实施例中可以不融入包括待测电路11的芯片设计。换言之，编码器420可以在电子设备中通过软件实现，而无需将其实施为硬件电路。译码器440可以在芯片中被实施为低功耗译码器142或掩码译码器152。在一个实施例中，第一测试向量集例如是自动测试向量生成(automatic test pattern generation，ATPG)数据。
为了获得目标译码器440，在本公开的一个实施例中，可以使用BNN来对初始译码器340的译码电路的连接关系进行优化。对于BNN而言，其通常需要大量的训练数据。然而，通过对于原始待测电路进行故障采样所获得的ATPG数据通常包括多个测试数据包。然而这样的测试数据量通常难于满足BNN训练的要求。如果使用满足BNN训练要求的ATPG数据，则需要消耗大量的采样成本和时间，而这通常是不期望的。因此，在本公开的一些实施例中，可以对诸如ATPG数据之类的第一测试向量集进行扩增来获得用于BNN训练的第二测试向量集。ATPG数据例如包括扫描链分布和/或未知态分布。对于低功耗译码器142而言，可以使 用待测电路11的扫描链在测试周期中的扫描链分布对用于形成低功耗译码器142的多个译码电路的连接关系分别进行修改以获得用于形成低功耗译码器142的目标译码器。对于掩码译码器152而言，可以使用未知态在测试周期中的未知态分布对用于形成掩码译码器152的多个译码电路的连接关系分别进行修改。进一步，还可以使用未知态分布和第二测试向量集来对用于形成掩码译码器152的多个译码电路的连接关系分别进行修改以获得用于形成掩码译码器152的目标译码器。
为了实现将第一测试向量集扩增为第二测试向量集，在一个实施例中，针对低功耗译码器142而言，电子设备可以使用扫描链分布或未知态分布确定多个扫描链在测试周期期间的使用频率，基于使用频率和预定功率阈值，随机生成多个随机测试向量，以及向第一测试向量集中添加多个随机测试向量以生成第二测试向量集。在一个实施例中，第二测试向量集中的测试向量中的指定比特位的比例是均匀分布的。指定比特位表示测试向量中具有第一位值的比特位，例如逻辑值“1”。换言之，指定比特位满足如下式(4)所示的均匀分布。
S～U(0,Pth)     (4)
其中S表示指定比特位，Pth表示预定功率阈值。因此，通过根据第一测试向量集中的扫描链的使用频率，按指定比特位被均匀分布的方式可以随机扩增第一测试向量集至第二测试向量集。预定功率阈值表示可以在一个周期中可以打开的扫描链的最大的数目，这是因为当超过该阈值时，过多的能量被注入待测芯片，这可能会导致芯片的损坏或失效。
在另一个实施例中，为了实现将第一测试向量集扩增为第二测试向量集，电子设备可以将第一测试向量集中的多个测试向量随机合并以生成多个随机测试向量，以及将多个随机测试向量向第一测试向量集中添加以生成第二测试向量集。第二测试向量集中的测试向量中的指定比特位的比例是正态分布的，指定比特位表示测试向量中具有第一位值的比特位，例如具有逻辑值“1”的比特位。指定比特位可以满足如下式(5)所示的正态分布。
S～N(μ,σ 2)   (5)
其中S表示指定比特位，μ表示指定比特位的均值，σ 2表示其方差。具体而言，将第一测试向量集中的多个测试向量随机合并以生成多个随机测试向量可以包括如下两种方式中至少一种：1)从第一测试向量集中随机选取部分数据包进行合并，提取合并后数据的扫描链使用情况，形成一个0/1向量以作为生成的随机测试向量；或2)随机选取第一测试向量集中的部分数据包作为背景，逐一与剩下的数据包进行增量合并，每次增量合并得到的中间结果也保留下来，提取扫描链使用情况形成0/1向量，作为随机测试向量。
通过使得指定比特位满足均匀分布或正态分布，可以使得第二测试向量集仍能基本上遵循第一测试向量集的特征，例如扫描链的使用频率或分布。因此，使用第二测试向量集来训练，即满足了BNN对于大量训练数据的需求，也确保了训练出来的译码器是针对待测电路11优化的。
在一个实施例中，对于掩码译码器152而言，电子设备可以首先提取待测电路的未知态分布。根据上面针对低功耗BNN学习数据集(随机测试向量集)生成掩码BNN学习数据集，掩码BNN学习数据集包含观测数据集和未知态掩蔽数据集。观测数据集和未知态掩蔽数据集每个元素是一个二值向量，向量长度为扫描链总数。具体而言，针对掩码译码器152的数据集扩增方法包括：形成随机测试向量的合并数据包对应的扫描链输出值必须要被观测到，提取扫描链编号，将二值向量中编号对应位置的值设置为1，其余位置的值为0，这些二值向量组成的集合即为观测数据集。提取阻碍这些扫描链输出值被观测的未知态所在的扫描链编号， 将二值向量中编号对应位置的值设置为1，其余位置的值为0，这些二值向量组成的集合即为未知态掩蔽数据集。这样，也可以获得针对掩码译码器152的第二测试向量集。针对BNN的大量训练和验证数据量的需求，在本公开的一些实施例中，在保持数据一致性的前提下，还使用测试数据集的扩增方式来扩增测试数据集，这减少了从ATPG数据的提取量，从而减少了设计和仿真成本。
由于BNN的层结构属性，因此电子设备使用二值神经网络模型表示初始化编码器或初始化译码器。每个BNN中的一个层对应于初始化编码器中的一个编码层或初始化译码器中的一个译码层。为了便于描述，下文仅针对译码器的情形进行描述，编码器具有相似的情形，并且不重复赘述。电子设备继而使用第二测试向量集中的第一组测试向量集对二值神经网络模型进行训练以获得候选二值神经网络。电子设备在获得候选二值神经网络之后，可以使用第二测试向量集中的第二组测试向量集对候选二值神经网络进行验证，以获得目标二值神经网络。换言之，第二测试向量集被分为两个部分，其中一个部分是训练集，并且另一部分是验证集。当目标二值申请网络满足性能要求时，电子设备可以将目标二值神经网络确定为目标译码器。
由于BNN中权值参数都是二值离散的，而算法上不能处理这种离散情形，因此不能直接对前述的BNN模型进行训练，需要将对应的BNN模型转化为一个连续模型，它具有与离散BNN模型相同的结构，但是其连接权值和比较阈值是连续的。具体而言，各个译码层中的译码电路与另一层中的译码电路的连接在连续模型中被表示为连接权值为0到1之间的连续值，并且比较器中比较阈值可以表示为大于0的连续值。例如，在一个实施例中，第i+1层输入X i+1与第i层输入X i的关系用以下式(6)模拟：
Figure PCTCN2021116552-appb-000003
其中，mean(X i)表示X i各元素的均值，var(X i)表示X i的方差，w表示从第i层到第i+1层的权值连接矩阵，C表示一个向量，其中第k个分量表示第k个比较器中的阈值。
由于低功率BNN和掩码BNN中使用到的数据集格式一致，并且采用了同样形式的优化目标函数，因此它们采用同样的BNN训练算法。在BNN训练时，可以将编码器BNN和译码器BNN按照图3的方式组合起来，同时训练对应的连续模型。在一个实施例中，训练算法采用随机梯度下降的优化算法。
图6示出了根据本公开的一些实施例的用于获得候选BNN的方法600的流程示意图。可以理解，方法600可以是图5中的方法500的步骤504的至少一部分的一种具体实现方式。方法600并不对方法500进行限制，方法500中的各个步骤可以具有其它实现方式。方法600可以由诸如计算机之类的具有计算能力的电子设备执行。
在602，电子设备将二值神经网络模型中的各个层之间的初始连接初始化到实数域，以获得连续域神经模型。连续域神经模型中的各个层之间的多个权重分别位于0和1之间并且连续域神经模型中的各个层之间的多个阈值常数分别大于0。
在604，使用第一组测试向量集中的测试向量对连续神经模型进行训练以获得在实数域空间中的中间神经网络。
在606，检查中间神经网络的输出是否满足目标函数值。对于BNN而言，期望编码和译码后能够恢复扫描链的打开状态，这可以由下式(7)进行表示。
Figure PCTCN2021116552-appb-000004
其中，Xj表示目标编码输入部的输入比特位，例如图4中的目标编码输入部410处的输入比特位，
Figure PCTCN2021116552-appb-000005
表示目标译码输出部的输出比特位，例如图4中的目标译码输出部450处的输出比特位，e表示编码映射，或表示编码函数，X表示待编码的二值向量，d表示译码映射，或表示译码函数，p表示扫描链数目。针对不同的应用场景，目标函数值可以具有不同的表现形式。在一个实施例中，针对低功率BNN，编码译码后处于打开状态的扫描链数量占扫描链总数量的百分比可以被设置为满足下式(8)：
Figure PCTCN2021116552-appb-000006
对于掩码BNN，为了满足译码代价最小，可以按下式(9)进行约束。
Figure PCTCN2021116552-appb-000007
因此，针对从初始BNN到目标BNN的训练实际上是一种多目标优化问题，这是因为这既包括针对低功耗译码器的约束和目标，也包括针对掩码译码器的约束和目标。可以使用加权的方式来综合优化。在一个实施例中，可以使用下式10来进行多目标优化。
Figure PCTCN2021116552-appb-000008
其中X表示要编码的二值向量，
Figure PCTCN2021116552-appb-000009
表示编码译码后的二值向量。
Figure PCTCN2021116552-appb-000010
表示编码不成功的扫描链的数目，
Figure PCTCN2021116552-appb-000011
表示编码译码后额外打开/关闭的扫描链的数目，β表示权重系数，并且可以根据实际电路预设。例如，β位于0和1之间。
如果中间神经网络的输出不满足目标函数值，则电子设备在608使用梯度下降算法对中间神经网络进行更新，以修改多个权重的值和多个阈值常数的值。如果中间神经网络的输出满足目标函数值，则电子设备在610将中间神经网络转换为二值离散域，以获得候选二值神经网络。在满足目标函数值的情形下，中间神经网络可以以下式(11)表示。
X i+1＝sign(A t+iX i-C i+1)    (II)
其中X i表示第i层输入，X i+1表示第i+1层输入，A i+1表示权值连接矩阵，C i+1表示比较阈值。在一个实施例中，在确定处中间神经网络的情形下，电子设备可以进一步地将中间神经网络转换为二值离散域，以获得候选二值神经网络。具体而言，可以将权值分别与权值阈值进行比较。如果权值大于预定阈值，则认为对应于不同译码层之间的两个译码电路之间的该连接实际存在或需要保留，可以将所关联的两个译码层连接。如果权值小于阈值，则认为对应于不同译码层之间的两个译码电路之间的该连接实际不存在或不需要保留，可以将所关联的两个译码层的连接断开。由此，可以获得例如图4所示的编译码系统400的目标编译码系统。
电子设备可以将目标编译码系统中的目标译码器生成为用于对待测电路11进行测试的电路的网表的一部分，并且将该测试电路的网表数据与待测电路的网表数据合并，以用于制造包括待测电路和测试电路(例如低功耗译码器142和掩码译码器152)的芯片。在本公开的一些实施例中，通过使用BNN，可以将稠密连接的初始编译码系统简化为稀疏连接的目标编译码系统，从而可以使用更少的编码比特位来实现更大的编码成功率。此外，针对BNN的大量训练和验证数据量的需求，在本公开的一些实施例中，在保持数据一致性的前提下，还使用测试数据集的扩增方式来扩增测试数据集，这减少了从ATPG数据的提取量，从而减少了设计和仿真成本。
虽然在此使用BNN训练模型来描述从初始译码器到目标译码器的优化过程，但是本公开 不限于此。还可以使用诸如进化算法之类的其它机器学习方法来优化初始译码器。例如，可以使用进化算法对初始译码器中的各个译码电路的连接电路进行杂交、变异和/或增减连接数目，对进化后的译码器进行评估，以及基于评估结果选择目标译码器。
图7示出了根据本公开的一些实施例的电子设备700的示意框图。电子设备700可以包括多个模块，以用于执行如图5或图6中所讨论的方法500或600中的对应步骤。如图7所示，电子设备700包括初始化单元702和修改单元704。初始化单元702用于至少基于表示待测电路的网表数据确定初始化译码器，初始化译码器包括至少一个译码层，至少一个译码层中的每个译码层包括多个译码电路。修改单元704用于至少基于用于对待测电路进行测试的第一测试向量集，对初始化译码器中的多个译码电路的连接进行修改以获得用于测试电路的目标译码器，测试电路被配置为在芯片中耦合至待测电路。
在一些实施例中，初始化单元进一步用于使用网表数据来确定待测电路中的扫描链数目；使用扫描链数目来计算至少一个译码层的层数；使用扫描链数目和层数来计算译码数组，译码数组包括至少一个译码层中的译码电路在每个译码层的数目；以及基于层数和译码数组，构建初始化译码器。
在一些实施例中，多个译码电路包括累加器以及与累加器耦合的比较器。初始化单元进一步用于根据层数，设置被串联布置的多个译码层；根据译码数组，在多个译码中的每个译码层中设置相应数目的译码电路；以及将多个译码层中上一级译码层的每个比较器与多个译码层中的下一级译码层中的每个累加器彼此连接，以构建初始化译码器。
在一些实施例中，修改单元进一步用于基于待测电路的特征，将第一测试向量集扩增为第二测试向量集，待测电路的特征包括待测电路的多个扫描链在测试周期中的扫描链分布或未知态在测试周期中的未知态分布中的至少一项；以及至少使用第二测试向量集对初始化译码器中的多个译码电路的连接进行修改以获得目标译码器。
在一些实施例中，修改单元进一步用于使用扫描链分布或未知态分布确定多个扫描链在测试周期期间的使用频率；基于使用频率和预定功率阈值，随机生成多个随机测试向量；以及向第一测试向量集中添加多个随机测试向量以生成第二测试向量集，其中第二测试向量集中的测试向量中的指定比特位的比例是均匀分布的，指定比特位表示测试向量中具有第一位值的比特位。
在一些实施例中，修改单元进一步用于将第一测试向量集中的多个测试向量随机合并以生成多个随机测试向量；以及将多个随机测试向量向第一测试向量集中添加以生成第二测试向量集，其中第二测试向量集中的测试向量中的指定比特位的比例是正态分布的，指定比特位表示测试向量中具有第一位值的比特位。
在一些实施例中，修改单元进一步用于使用二值神经网络模型表示初始化译码器；使用第二测试向量集中的第一组测试向量集对二值神经网络模型进行训练以获得候选二值神经网络；使用第二测试向量集中的第二组测试向量集对候选二值神经网络进行验证，以获得目标二值神经网络；以及基于目标二值神经网络，确定目标译码器。
在一些实施例中，修改单元进一步用于将二值神经网络模型中的各个层之间的初始连接初始化到实数域，以获得连续域神经模型，连续域神经模型中的各个层之间的多个权重分别位于0和1之间并且连续域神经模型中的各个层之间的多个阈值常数分别大于0；迭代地执行以下项至少一次：使用第一组测试向量集中的测试向量集对连续神经模型进行训练以获得在实数域空间中的中间神经网络；检查中间神经网络的输出是否满足目标函数值；以及如果 中间神经网络的输出不满足目标函数值，则使用梯度下降算法对中间神经网络进行更新，以修改多个权重的值和多个阈值常数的值；以及如果中间神经网络的输出满足目标函数值，则将中间神经网络转换为二值离散域，以获得候选二值神经网络。
在一些实施例中，修改单元进一步用于将多个权重的值分别与权重阈值比较：如果多个权重中的第一权重的值低于权重阈值，则将第一权重所关联的两个译码层断开，或如果多个权重中的第二权重的值低于权重阈值，则将第二权重所关联的两个译码层连接。
图8示出了可以用来实施本公开的实施例的示例设备800的示意性框图。设备800可以用于实现电子设备700。如图所示，设备800包括计算单元801，其可以根据存储在随机存取存储器(RAM)和/或只读存储器(ROM)802的计算机程序指令或者从存储单元807加载到RAM和/或ROM 802中的计算机程序指令，来执行各种适当的动作和处理。在RAM和/或ROM 802中，还可存储设备800操作所需的各种程序和数据。计算单元801和RAM和/或ROM 802通过总线803彼此相连。输入/输出(I/O)接口804也连接至总线803。
设备800中的多个部件连接至I/O接口804，包括：输入单元805，例如键盘、鼠标等；输出单元806，例如各种类型的显示器、扬声器等；存储单元807，例如磁盘、光盘等；以及通信单元808，例如网卡、调制解调器、无线通信收发机等。通信单元808允许设备800通过诸如因特网的计算机网络和/或各种电信网络与其他设备交换信息/数据。
计算单元801可以是各种具有处理和计算能力的通用和/或专用处理组件。计算单元801的一些示例包括但不限于中央处理单元(CPU)、图形处理单元(GPU)、各种专用的人工智能(AI)计算芯片、各种运行机器学习模型算法的计算单元、数字信号处理器(DSP)、以及任何适当的处理器、控制器、微控制器等。计算单元801执行上文所描述的各个方法和处理，例如方法500和/或方法600。例如，在一些实施例中，方法500和/或方法600可被实现为计算机软件程序，其被有形地包含于机器可读介质，例如存储单元807。在一些实施例中，计算机程序的部分或者全部可以经由RAM和/或ROM和/或通信单元808而被载入和/或安装到设备800上。当计算机程序加载到RAM和/或ROM并由计算单元801执行时，可以执行上文描述的方法500和/或方法600的一个或多个步骤。备选地，在其他实施例中，计算单元801可以通过其他任何适当的方式(例如，借助于固件)而被配置为执行方法500和/或方法600。
用于实施本公开的方法的程序代码可以采用一个或多个编程语言的任何组合来编写。这些程序代码可以提供给通用计算机、专用计算机或其他可编程数据处理装置的处理器或控制器，使得程序代码当由处理器或控制器执行时使流程图和/或框图中所规定的功能/操作被实施。程序代码可以完全在机器上执行、部分地在机器上执行，作为独立软件包部分地在机器上执行且部分地在远程机器上执行或完全在远程机器或服务器上执行。
在本公开的上下文中，机器可读介质可以是有形的介质，其可以包含或存储以供指令执行系统、装置或设备使用或与指令执行系统、装置或设备结合地使用的程序。机器可读介质可以是机器可读信号介质或机器可读储存介质。机器可读介质可以包括但不限于电子的、磁性的、光学的、电磁的、红外的、或半导体系统、装置或设备，或者上述内容的任何合适组合。机器可读存储介质的更具体示例会包括基于一个或多个线的电气连接、便携式计算机盘、硬盘、随机存取存储器(RAM)、只读存储器(ROM)、可擦除可编程只读存储器(EPROM或快闪存储器)、光纤、便捷式紧凑盘只读存储器(CD-ROM)、光学储存设备、磁储存设备、或上述内容的任何合适组合。
此外，虽然采用特定次序描绘了各操作，但是这应当理解为要求这样操作以所示出的特 定次序或以顺序次序执行，或者要求所有图示的操作应被执行以取得期望的结果。在一定环境下，多任务和并行处理可能是有利的。同样地，虽然在上面论述中包含了若干具体实现细节，但是这些不应当被解释为对本公开的范围的限制。在单独的实施例的上下文中描述的某些特征还可以组合地实现在单个实现中。相反地，在单个实现的上下文中描述的各种特征也可以单独地或以任何合适的子组合的方式实现在多个实现中。
尽管已经采用特定于结构特征和/或方法逻辑动作的语言描述了本主题，但是应当理解所附权利要求书中所限定的主题未必局限于上面描述的特定特征或动作。相反，上面所描述的特定特征和动作仅仅是实现权利要求书的示例形式。

Claims (26)

  1. 一种用于设计译码器的方法，所述译码器被设计为位于测试电路中，所述方法包括：
    至少基于表示待测电路的网表数据，确定初始化译码器；以及
    至少基于用于对所述待测电路进行测试的第一测试向量集，对所述初始化译码器中的译码电路的连接进行修改以获得用于所述测试电路的目标译码器，所述测试电路被配置为在芯片中耦合至所述待测电路。
  2. 根据权利要求1所述的方法，其中所述初始化译码器包括至少一个译码层，所述至少一个译码层中的每个译码层包括多个译码电路，确定所述初始化译码器包括：
    使用所述网表数据来确定所述待测电路中的扫描链数目；
    使用所述扫描链数目来计算所述至少一个译码层的层数；
    使用所述扫描链数目和所述层数来计算译码数组，所述译码数组包括所述至少一个译码层中的译码电路在每个译码层的数目；以及
    基于所述层数和所述译码数组，构建所述初始化译码器。
  3. 根据权利要求2所述的方法，其中，所述多个译码电路包括累加器以及与所述累加器耦合的比较器，构建所述初始化译码器包括：
    根据所述层数，设置被串联布置的多个译码层；
    根据所述译码数组，在所述多个译码层中的每个译码层中设置相应数目的译码电路；以及
    将所述多个译码层中上一级译码层的每个比较器与所述多个译码层中的下一级译码层中的每个累加器彼此连接，以构建所述初始化译码器。
  4. 根据权利要求1-3中任一项所述的方法，其中至少基于第一测试向量集对所述初始化译码器中的多个译码电路的连接进行修改以获得用于所述测试电路的目标译码器包括：
    基于所述待测电路的特征，将所述第一测试向量集扩增为第二测试向量集，所述待测电路的特征包括所述待测电路的多个扫描链在测试周期中的扫描链分布或未知态在所述测试周期中的未知态分布中的至少一项；以及
    至少使用所述第二测试向量集对所述初始化译码器中的多个译码电路的连接进行修改以获得目标译码器。
  5. 根据权利要求4所述的方法，其中基于所述待测电路的特征将所述第一测试向量集扩增为第二测试向量集包括：
    使用所述扫描链分布或所述未知态分布确定所述多个扫描链在所述测试周期期间的使用频率；
    基于所述使用频率和预定功率阈值，随机生成所述多个随机测试向量；以及
    向所述第一测试向量集中添加所述多个随机测试向量以生成所述第二测试向量集，其中所述第二测试向量集中的测试向量中的指定比特位的比例是均匀分布的，所述指定比特位表示测试向量中具有第一位值的比特位。
  6. 根据权利要求4所述的方法，其中基于所述待测电路的特征将所述第一测试向量集扩增为第二测试向量集包括：
    将所述第一测试向量集中的多个测试向量随机合并以生成多个随机测试向量；
    将所述多个随机测试向量向所述第一测试向量集中添加以生成所述第二测试向量集，其 中所述第二测试向量集中的测试向量中的指定比特位的比例是正态分布的，所述指定比特位表示测试向量中具有第一位值的比特位。
  7. 根据权利要求4-6中任一项所述的方法，其中至少使用所述第二测试向量集对所述初始化译码器中的多个译码电路的连接进行修改以获得目标译码器包括：
    使用二值神经网络模型表示所述初始化译码器；
    使用所述第二测试向量集中的第一组测试向量集对所述二值神经网络模型进行训练以获得候选二值神经网络；
    使用所述第二测试向量集中的第二组测试向量集对所述候选二值神经网络进行验证，以获得目标二值神经网络；以及
    基于所述目标二值神经网络，确定所述目标译码器。
  8. 根据权利要求7所述的方法，其中使用所述第二测试向量集中的第一组测试向量集对所述二值神经网络模型进行训练以获得候选二值神经网络包括：
    将所述二值神经网络模型中的各个层之间的初始连接初始化到实数域，以获得连续域神经模型，所述连续域神经模型中的各个层之间的多个权重分别位于第一值和第二值之间并且连续域神经模型中的各个层之间的多个阈值常数分别大于第一值；
    迭代地执行以下项至少一次：
    使用所述第一组测试向量集中的测试向量集对所述连续神经模型进行训练以获得在所述实数域空间中的中间神经网络；
    检查所述中间神经网络的输出是否满足目标函数值；以及
    如果所述中间神经网络的输出不满足所述目标函数值，则使用梯度下降算法对所述中间神经网络进行更新，以修改所述多个权重的值和所述多个阈值常数的值；以及
    如果所述中间神经网络的输出满足所述目标函数值，则将所述中间神经网络转换为二值离散域，以获得所述候选二值神经网络。
  9. 根据权利要求8所述的方法，其中将所述中间神经网络转换为二值离散域以获得所述候选二值神经网络包括：
    将所述多个权重的值分别与权重阈值比较：
    如果所述多个权重中的第一权重的值低于权重阈值，则将所述第一权重所关联的两个译码层断开，或
    如果所述多个权重中的第二权重的值低于权重阈值，则将所述第二权重所关联的两个译码层连接。
  10. 一种计算机可读存储介质，存储多个程序，所述多个程序被配置为一个或多个处理器执行，所述多个程序包括用于执行权利要求1-9中任一项所述的方法的指令。
  11. 一种计算机程序产品，所述计算机程序产品包括多个程序，所述多个程序被配置为一个或多个处理器执行，所述多个程序包括用于执行权利要求1-9中任一项所述的方法的指令。
  12. 一种电子设备，包括：
    一个或多个处理器；
    包括计算机指令的存储器，所述计算机指令在由所述电子设备的所述一个或多个处理器执行时使得所述电子设备执行权利要求1-9中任一项所述的方法。
  13. 一种电子设备，包括：
    初始化单元，用于至少基于表示待测电路的网表数据确定初始化译码器；以及
    修改单元，用于至少基于用于对所述待测电路进行测试的第一测试向量集，对所述初始化译码器中的译码电路的连接进行修改以获得用于所述测试电路的目标译码器，所述测试电路被配置为在芯片中耦合至所述待测电路。
  14. 根据权利要求13所述的电子设备，其中所述初始化译码器包括至少一个译码层，所述至少一个译码层中的每个译码层包括多个译码电路，所述初始化单元进一步用于：
    使用所述网表数据来确定所述待测电路中的扫描链数目；
    使用所述扫描链数目来计算所述至少一个译码层的层数；
    使用所述扫描链数目和所述层数来计算译码数组，所述译码数组包括所述至少一个译码层中的译码电路在每个译码层的数目；以及
    基于所述层数和所述译码数组，构建所述初始化译码器。
  15. 根据权利要求14所述的电子设备，其中，所述多个译码电路包括累加器以及与所述累加器耦合的比较器，所述初始化单元进一步用于：
    根据所述层数，设置被串联布置的多个译码层；
    根据所述译码数组，在所述多个译码中的每个译码层中设置相应数目的译码电路；以及
    将所述多个译码层中上一级译码层的每个比较器与所述多个译码层中的下一级译码层中的每个累加器彼此连接，以构建所述初始化译码器。
  16. 根据权利要求13-15中任一项所述的电子设备，其中所述修改单元进一步用于：
    基于所述待测电路的特征，将所述第一测试向量集扩增为第二测试向量集，所述待测电路的特征包括所述待测电路的多个扫描链在测试周期中的扫描链分布或未知态在所述测试周期中的未知态分布中的至少一项；以及
    至少使用所述第二测试向量集对所述初始化译码器中的多个译码电路的连接进行修改以获得目标译码器。
  17. 根据权利要求16所述的电子设备，其中所述修改单元进一步用于：
    使用所述扫描链分布或所述未知态分布确定所述多个扫描链在所述测试周期期间的使用频率；
    基于所述使用频率和预定功率阈值，随机生成所述多个随机测试向量；以及
    向所述第一测试向量集中添加所述多个随机测试向量以生成所述第二测试向量集，其中所述第二测试向量集中的测试向量中的指定比特位的比例是均匀分布的，所述指定比特位表示测试向量中具有第一位值的比特位。
  18. 根据权利要求16所述的电子设备，其中所述修改单元进一步用于：
    将所述第一测试向量集中的多个测试向量随机合并以生成多个随机测试向量；以及
    将所述多个随机测试向量向所述第一测试向量集中添加以生成所述第二测试向量集，其中所述第二测试向量集中的测试向量中的指定比特位的比例是正态分布的，所述指定比特位表示测试向量中具有第一位值的比特位。
  19. 根据权利要求16-18中任一项所述的电子设备，其中所述修改单元进一步用于：
    使用二值神经网络模型表示所述初始化译码器；
    使用所述第二测试向量集中的第一组测试向量集对所述二值神经网络模型进行训练以获得候选二值神经网络；
    使用所述第二测试向量集中的第二组测试向量集对所述候选二值神经网络进行验证，以 获得目标二值神经网络；以及
    基于所述目标二值神经网络，确定所述目标译码器。
  20. 根据权利要求19所述的电子设备，其中所述修改单元进一步用于：
    将所述二值神经网络模型中的各个层之间的初始连接初始化到实数域，以获得连续域神经模型，所述连续域神经模型中的各个层之间的多个权重分别位于第一值和第二值之间并且连续域神经模型中的各个层之间的多个阈值常数分别大于所述第一值；
    迭代地执行以下项至少一次：
    使用所述第一组测试向量集中的测试向量集对所述连续神经模型进行训练以获得在所述实数域空间中的中间神经网络；
    检查所述中间神经网络的输出是否满足目标函数值；以及
    如果所述中间神经网络的输出不满足所述目标函数值，则使用梯度下降算法对所述中间神经网络进行更新，以修改所述多个权重的值和所述多个阈值常数的值；以及
    如果所述中间神经网络的输出满足所述目标函数值，则将所述中间神经网络转换为二值离散域，以获得所述候选二值神经网络。
  21. 根据权利要求20所述的电子设备，其中所述修改单元进一步用于：
    将所述多个权重的值分别与权重阈值比较：
    如果所述多个权重中的第一权重的值低于权重阈值，则将所述第一权重所关联的两个译码层断开，或
    如果所述多个权重中的第二权重的值低于权重阈值，则将所述第二权重所关联的两个译码层连接。
  22. 一种用于对待测电路进行测试的电路，包括：
    第一译码器，耦合至所述待测电路并且被配置为将多个第一编码比特位译码为多个第一译码比特位，所述第一译码器包括至少一个译码层，所述至少一个译码层中的每个译码层包括多个译码电路，每个译码电路包括累加器和与所述累加器耦合的比较器。
  23. 根据权利要求22所述的电路，其中所述至少一个译码层包括：
    第一译码层，被配置为基于所述多个第一编码比特位输出多个第一中间比特位；以及
    第二译码层，被配置为基于所述多个第一中间比特位输出所述多个第一译码比特位，所述多个第一译码比特位的数目多于所述多个第一中间比特位的数目。
  24. 根据权利要求22或23所述的电路，其中所述至少一个译码层中的每个译码层包括第一译码电路和第二译码电路，所述第一译码电路的连接和所述第二译码电路的连接不同。
  25. 根据权利要求22-24中任一项所述的电路，其中所述至少一个译码层中的最后一级译码层的多个译码电路分别经由多个第一与门与所述待测电路的多个扫描链耦合；或
    所述至少一个译码层中的最后一级译码层的多个译码电路分别与所述多个扫描链耦合至多个第二与门。
  26. 根据权利要求22-25中任一项所述的电路，还包括：
    第二译码器，耦合至所述待测电路并且被配置为将多个第二编码比特位译码为多个第二译码比特位，所述第二译码器包括至少一个译码层，所述至少一个译码层中的每个译码层包括多个译码电路，每个译码电路包括累加器和与所述累加器耦合的比较器。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004219186A (ja) * 2003-01-14 2004-08-05 Ricoh Co Ltd 半導体集積回路
CN1560914A (zh) * 2004-02-19 2005-01-05 中国科学院计算技术研究所 一种即插即用片上测试向量生成电路及方法
CN103091620A (zh) * 2012-12-29 2013-05-08 江苏东大集成电路系统工程技术有限公司 一种针对扫描测试中捕获功耗的优化方法
CN111381148A (zh) * 2018-12-29 2020-07-07 无锡华润矽科微电子有限公司 实现芯片测试的系统及方法
CN112805577A (zh) * 2019-12-30 2021-05-14 成都海光集成电路设计有限公司 芯片、芯片测试方法及电子设备

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004219186A (ja) * 2003-01-14 2004-08-05 Ricoh Co Ltd 半導体集積回路
CN1560914A (zh) * 2004-02-19 2005-01-05 中国科学院计算技术研究所 一种即插即用片上测试向量生成电路及方法
CN103091620A (zh) * 2012-12-29 2013-05-08 江苏东大集成电路系统工程技术有限公司 一种针对扫描测试中捕获功耗的优化方法
CN111381148A (zh) * 2018-12-29 2020-07-07 无锡华润矽科微电子有限公司 实现芯片测试的系统及方法
CN112805577A (zh) * 2019-12-30 2021-05-14 成都海光集成电路设计有限公司 芯片、芯片测试方法及电子设备

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