WO2023028917A1

WO2023028917A1 - Method for manufacturing self-aligned quadruple patterned semiconductor apparatus, and semiconductor apparatus

Info

Publication number: WO2023028917A1
Application number: PCT/CN2021/115959
Authority: WO
Inventors: 陈庆煌; 黄雪维; 张日清; 常文瑞
Original assignee: 华为技术有限公司
Priority date: 2021-09-01
Filing date: 2021-09-01
Publication date: 2023-03-09
Also published as: CN117751427A

Abstract

Disclosed in the embodiments of the present application are a method for manufacturing a self-aligned quadruple patterned semiconductor apparatus, and a semiconductor apparatus. The method for manufacturing a self-aligned quadruple patterned semiconductor apparatus comprises: sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer and a first patterned hard mask layer on a surface of a layer to be etched; performing photoetching on the first patterned hard mask layer, so as to form a second patterned hard mask layer; on the basis of the second patterned hard mask layer as a mask, etching the second anti-reflection layer and the first sacrificial layer, so as to form a second patterned sacrificial layer; removing the second patterned hard mask layer and the second anti-reflection layer, and forming a third patterned hard mask layer on the basis of the second patterned sacrificial layer; performing photoetching on the third patterned hard mask layer, so as to form a fourth patterned hard mask layer; and on the basis of the fourth patterned hard mask layer, etching the first anti-reflection layer and the layer to be etched, so as to form a patterned layer to be etched. By implementing the embodiments of the present application, the degree of freedom of circuit pattern design can be improved.

Description

Method for fabricating self-aligned quadruple patterned semiconductor device and semiconductor device

technical field

The present application relates to the field of semiconductor technology, in particular to a method for fabricating a self-aligned quadruple patterned semiconductor device and the semiconductor device.

Background technique

Multiple patterning (Multiple Patterning) is a method currently used in photolithography technology, which can reduce the characteristic size of circuit patterns (such as: line width and spacing) and increase the density of circuit patterns. Common self-aligned patterning techniques in multiple pattern exposure techniques include self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, SAQP) technique. The self-aligned quadruple patterning technology uses one exposure to transfer the circuit pattern of the printing mandrel to be prepared onto the hard mask, and then deposits the spacer (Spacer) sidewall twice at the hard mask using atomic layer deposition technology. , and then top-down etch spacers to open the print mandrel and bottom layer. Wherein, the distance between the sidewalls of the second spacer is the distance between the metal lines of the final circuit pattern.

However, the circuit pattern generated by the self-aligned quadruple patterning technique is defined by two spacer depositions, and the size of the spacers formed in the manufacturing process of the spacers in the prior art is relatively fixed, and there is no way to further As a result, the feature size of its circuit pattern (such as: line width and spacing) is limited within a certain range, and the density of the circuit pattern cannot be further improved. Moreover, if the circuit diagram is produced by direct multiple exposures, the accuracy of the overlay error of the circuit pattern during each exposure is particularly high, and the design also needs to carefully consider the problem of pattern splitting, which increases the difficulty of circuit design. The degree of freedom in design of circuit patterns is largely limited.

Therefore, how to improve the density and freedom of circuit pattern design in the self-aligned quadruple patterning technology is an urgent problem to be solved.

Contents of the invention

Embodiments of the present application provide a method for fabricating a self-aligned quadruple patterned semiconductor device and the semiconductor device, so as to increase the density and freedom of circuit pattern design.

In a first aspect, an embodiment of the present application provides a method for fabricating a self-aligned quadruple patterned semiconductor device, including:

Step 1, sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer and a first patterned hard mask layer on the surface of the layer to be etched, the first patterned hard mask layer includes the first a patterned sacrificial layer and a first sidewall layer covering all sidewalls of the first patterned sacrificial layer;

Step 2, performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer;

Step 3: Etching the second anti-reflection layer and the first sacrificial layer based on the second patterned hard mask layer as a mask to form a second patterned sacrificial layer;

Step 4, removing the second patterned hard mask layer and the second anti-reflection layer, and forming a third patterned hard mask layer based on the second patterned sacrificial layer, the third patterned hard mask layer The mask layer includes the second patterned sacrificial layer and a second sidewall layer covering all sidewalls of the second patterned sacrificial layer;

Step 5, performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer;

Step 6, etching the first anti-reflection layer and the layer to be etched based on the fourth patterned hard mask layer as a mask to form a patterned layer to be etched;

Step seven, removing the fourth patterned hard mask layer and the first anti-reflection layer.

Implementing the method provided in the first aspect, unlike the prior art where a patterned hard mask is formed by depositing spacers twice, the embodiment of the present application adds a step of pattern photolithography between the sidewalls deposited twice for spacers, That is, the circuit pattern is prepared by multiple times of photolithography and two alternate ways of depositing spacers, and finally photolithography is used to define the pattern that needs to be opened to form a patterned hard mask. First of all, if adjacent metal lines are made on the same layer of photomask, they cannot be made very close to each other, but if adjacent metal lines are made on two different layers of photomask, the distance between each other It can be very close. In this way, multiple photolithography is performed in the self-aligned quadruple patterning technology, and the adjacent metal lines are distributed on different photomasks, so that the desired effect can be achieved before, and the density of the circuit pattern design can be improved. Secondly, since the patterned hard mask layer is formed after one photolithography, the sidewall layer is often made by depositing spacers based on the pattern during photolithography. The materials of the sidewall layer are different, and the etching speed is different, which greatly reduces the accuracy requirement for the overlay error of the circuit pattern during the second photolithography, and reduces the difficulty of circuit design. Moreover, the circuit pattern is ultimately a pattern defined by multiple photolithography patterns, and the length, width, or mutual spacing can be freely adjusted compared with the pattern defined by the spacer.

In a possible implementation manner, the step of sequentially forming the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer and the first patterned hard mask layer on the surface of the layer to be etched includes: The surface of the layer to be etched is sequentially deposited to form the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, the second sacrificial layer and the first patterned photoresist layer; based on the The first patterned photoresist layer is used as a mask to etch the second sacrificial layer, and the first patterned sacrificial layer is formed on the second sacrificial layer; the first patterned photoresist layer is removed; The first patterned sacrificial layer is deposited and etched to form the first sidewall layer covering all sidewalls of the first patterned sacrificial layer. Implementing the embodiment of the present application, the second sacrificial layer is opened by photolithography and spacer deposition, a first patterned hard mask layer is formed, and a pattern corresponding to the first patterned photoresist layer is produced.

In a possible implementation manner, the first patterned photoresist layer includes: a spin-on-carbon layer, a spin-on-glass layer, and a patterned photoresist layer stacked in sequence, wherein the spin-on-carbon layer is stacked On the side of the second sacrificial layer away from the second anti-reflection layer, the spin-on-glass layer is between the spin-on-carbon layer and the patterned photoresist layer. In the embodiment of the present application, the three-layer structure of the photoresist can stably and accurately transfer the pattern formed by the photoresist to the second sacrificial layer through the photolithography process.

In a possible implementation manner, the step of performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer includes: depositing and forming a second patterned hard mask layer covering the first patterned hard mask layer A second patterned photoresist layer; based on the second patterned photoresist layer as a mask, the first patterned hard mask layer is etched to form the second patterned hard mask layer; removing the second patterned photoresist layer. In the embodiment of the present application, the photolithography process may first form a patterned photoresist layer covering the patterned hard mask layer, then use the patterned photoresist layer as a mask to further open the sacrificial layer, and finally remove the patterned photoresist layer. layered.

In a possible implementation manner, the step of performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer includes: forming the third patterned hard mask layer according to The third patterned photoresist layer is subjected to photolithography to form the fourth patterned hard mask layer. In the embodiment of the present application, the photolithography process may first form a patterned photoresist layer covering the patterned hard mask layer, then use the patterned photoresist layer as a mask to further open the sacrificial layer, and finally remove the patterned photoresist layer. layered.

In a possible implementation manner, the step of performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer includes: forming the third patterned hard mask layer according to Perform photolithography on the third patterned photoresist layer to form a fifth patterned hard mask layer; perform photolithography on the fifth patterned hard mask layer according to the fourth patterned photoresist layer to form the fourth patterned hard mask layer mask layer. In the embodiment of the present application, if the case is complicated, multiple photolithography can be selected to form the fourth patterned hard mask layer, and the freedom of circuit pattern design can be guaranteed through multiple photolithography.

In a possible implementation manner, in the horizontal direction, the line widths of the patterns of the third patterned photoresist layer and the fourth patterned photoresist layer are respectively equal to the width of the second sidewall layer or greater than twice the width of the second sidewall layer. Different from the prior art that the line width of the pattern must be equal to the width of the second side wall layer, the line width of the pattern in the embodiment of the present application can also be greater than twice the width of the second side wall layer.

In a possible implementation manner, in the horizontal direction, the line widths of the patterns of the second patterned photoresist layer, the third patterned photoresist layer, and the fourth patterned photoresist layer are smaller than or equal to the adjacent The spacing between the first sidewall layers or between the adjacent second sidewall layers. In the embodiment of the present application, the line width of the circuit pattern prepared after the first sidewall layer cannot exceed the distance between the first sidewall layer and the adjacent second sidewall layer.

In a possible implementation manner, the second patterned photoresist layer includes one or more first grooves; the first patterned sacrificial layer is deposited and etched to form a groove covering the first pattern. Before the first sidewall layer step of patterning all the sidewalls of the sacrificial layer, it also includes: forming a fifth patterned photoresist layer on the surface of the first patterned sacrificial layer, and the fifth patterned photoresist layer includes a or a plurality of second grooves, the position of each of the second grooves is the same as the position of each of the first grooves; based on the fifth patterned photoresist layer as a mask, according to the second The trench etches the first patterned sacrificial layer to form the etched first patterned sacrificial layer; and removes the fifth patterned photoresist layer. Implementing the embodiment of the present application, since the position of the first trench is different from that of the second trench, and after the step of removing the first patterned photoresist layer, when the first sidewall layer is prepared, the insulation of the sidewall layer The material will cover the first patterned sacrificial layer after etching, thereby also covering the second trench, and then when the pattern formed by the first trench is subsequently prepared, the insulating material at the second trench will block the first trench The formed pattern lines can obtain one or more discontinuous grooves with different lengths, and then obtain circuit pattern lines with different lengths.

In a possible implementation manner, the first patterned photoresist layer includes one or more third grooves; the first patterned sacrificial layer is deposited and etched to form a groove covering the first pattern. The first sidewall layer of all the sidewalls of the sacrificial layer, after the step, also includes: depositing and forming a sixth patterned photoresist layer covering the first patterned hard mask layer, the sixth patterned photoresist layer The layer includes one or more fourth grooves, the position of each of the fourth grooves is the same as the position of each of the third grooves; based on the sixth patterned photoresist layer as a mask for the The first patterned hard mask layer is etched to form an etched first patterned hard mask layer; the first patterned hard mask layer covering the sixth patterned photoresist layer and the etched first patterned hard mask layer are formed by deposition. The oxide layer of the mask layer; removing the sixth patterned photoresist layer and the oxide layer covering the sixth patterned photoresist layer; performing photolithography on the first patterned hard mask layer The step of forming a second patterned hard mask layer includes: performing photolithography on the etched first patterned hard mask layer and the remaining oxide layer to form the second patterned hard mask layer. Implementing the embodiment of the present application, since the position of the third trench is the same as that of the fourth trench, depositing and forming an oxide at the position of the fourth trench can block the third trench, thereby forming multiple long and short trenches. Different grooves, and then obtain lines of circuit patterns with different lengths.

In the second aspect, the embodiment of the present application provides a self-aligned quadruple-patterned semiconductor device, including a substrate, the above-mentioned first aspect stacked on the substrate, and any combination of the implementation methods of the first aspect. A semiconductor device fabricated by the method described above.

In a third aspect, an embodiment of the present application provides an electronic device, which includes the first aspect and the semiconductor device and the circuit board provided in any implementation manner of the first aspect. The semiconductor device is electrically connected to the circuit board, and the electronic device is used to implement the functions of the semiconductor device in the first aspect described above.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiment of the present application or the background art, the following will describe the drawings that need to be used in the embodiment of the present application or the background art.

FIG. 1 is a flowchart of steps of a method for fabricating a self-aligned quadruple-patterned semiconductor device provided by an embodiment of the present application.

FIG. 2 is a cross-sectional view of a set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

3 and 4 are cross-sectional views of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

FIG. 5 is a cross-sectional view of a group of patterned photoresist layers provided by an embodiment of the present application.

FIG. 6 is a cross-sectional view of a set of semiconductor devices for forming a first sidewall layer according to an embodiment of the present application.

7-10 are cross-sectional views of a group of semiconductor devices for making Cut line A provided by the embodiment of the present application.

FIG. 11 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

FIG. 12 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

13-15 are device cross-sectional views of a group of semiconductor devices for making Cut line B provided by the embodiment of the present application.

FIG. 16 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

FIG. 17 is a device cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

FIG. 18 is a device cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

FIG. 19 is a device cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

FIG. 20 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

FIG. 21 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

22-24 are cross-sectional views of a group of semiconductor devices for making Cut line C provided by the embodiment of the present application.

FIG. 25 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application.

26-30 are cross-sectional views of a set of semiconductor devices for manufacturing line D and Cut line D provided by the embodiment of the present application.

Explanation of reference signs:

10 semiconductor devices;

101 layer to be etched; 102 first anti-reflection layer; 103 first sacrificial layer; 104 second anti-reflection layer; 105 first patterned hard mask layer; 106 second sacrificial layer, 107 first patterned photoresist layer ;

the first sidewall layer 1052; the first patterned sacrificial layer 1051;

1071 spin-on-carbon layer; 1072 spin-on-glass layer; 1073 patterned photoresist layer;

108 sixth patterned photoresist layer; 109 oxide layer;

115 second patterned hard mask layer; 1031 second patterned sacrificial layer; 1032 third patterned hard mask layer; 1033 second sidewall layer; 1132 fourth patterned hard mask layer;

201 second patterned photoresist layer; 202 fifth patterned photoresist layer;

203 third patterned photoresist layer; 204 seventh patterned photoresist layer;

205 a fourth patterned photoresist layer;

111 patterned layer to be etched;

LA third groove; CA fourth groove;

LB first groove; CB second groove;

LC fifth groove; CC sixth groove;

LD seventh groove; CD eighth groove.

Detailed ways

The embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

The terms "first", "second", "third" and "fourth" in the specification and claims of the present application and the drawings are used to distinguish different objects, rather than to describe a specific order . Furthermore, the terms "include" and "have", as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but optionally also includes unlisted steps or units, or optionally further includes For other steps or units inherent in these processes, methods, products or apparatuses.

It should be understood that in this application, "at least one (item)" means one or more, and "multiple" means two or more. "And/or" is used to describe the association relationship of associated objects, indicating that there can be three types of relationships, for example, "A and/or B" can mean: only A exists, only B exists, and A and B exist at the same time , where A and B can be singular or plural. The character "/" generally indicates that the contextual objects are an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one item (piece) of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c ", where a, b, c can be single or multiple.

For the convenience of description, the embodiments of the present application may use spatial relation words such as "below", "below", "below", "below", "above", "on" and so on to describe the space shown in the drawings. The relationship of one element or feature to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of up and down. Other orientations (rotated 90 degrees or at other orientations) are possible for the device and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

Reference herein to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those skilled in the art that the embodiments described herein can be combined with other embodiments.

First, in order to facilitate the understanding of the embodiments of the present application, the technical problems and application scenarios to be solved by the embodiments of the present application are specifically analyzed below.

Multiple patterning (Multiple Patterning) is a method currently used in photolithography technology, which can reduce the characteristic size of circuit patterns (such as: line width and spacing) and increase the density of circuit patterns. Common self-aligned patterning techniques in multiple pattern exposure techniques include self-aligned quadruple patterning (Self-Aligned Quadruple Patterning, SAQP) technique. The self-aligned quadruple patterning technology uses one exposure to transfer the circuit pattern of the printing mandrel to the hard mask, and then deposits the spacer (Spacer) sidewall twice using atomic layer deposition technology, and then engraves from top to bottom. Etch spacers to open the print mandrel and bottom layer. Wherein, the space between the sidewalls of the second spacer is the line width of the metal line of the final circuit pattern.

For example: please refer to step 1 to step 8, which are the process steps of the self-aligned quadruple patterning technology in the prior art. in:

Step 1: sequentially depositing a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a second sacrificial layer on the surface of the layer to be etched;

Step 2: performing photolithography on the second sacrificial layer, and forming a patterned second sacrificial layer on the second sacrificial layer;

Step 3: removing the patterned photoresist layer; depositing and etching the patterned second sacrificial layer to form a first sidewall layer;

Step 4: removing the patterned second sacrificial layer;

Step 5: Etching the second anti-reflection layer and the first sacrificial layer based on the first sidewall layer as a mask to form a patterned first sacrificial layer;

Step 6: removing the second anti-reflection layer; depositing and etching the patterned second sacrificial layer to form a second sidewall layer;

Step 7: removing the patterned first sacrificial layer;

Step 8: Etching the first anti-reflection layer and the layer to be etched based on the second sidewall layer as a mask to form a patterned layer to be etched.

It can be known from the above steps that the circuit pattern generated by the self-aligned quadruple patterning technique is finally defined by the second deposited spacer (ie, the second sidewall layer). However, the size of the spacers formed in the Spacer manufacturing process in the prior art is relatively fixed, and there is no way to further reduce it, resulting in the feature size (such as: line width and spacing) of the final formed circuit pattern being fixed. Therefore, when the circuit pattern is initially designed, it is necessary to consider the size of the spacer that can be deposited to determine the line width of the circuit pattern. Moreover, if the circuit diagram is produced by direct multiple exposures, the accuracy of the overlay error of the circuit pattern during each exposure is particularly high, and the design also needs to carefully consider the problem of pattern splitting, which increases the difficulty of circuit design. The degree of freedom in design of circuit patterns is largely limited.

Therefore, in order to improve the density and freedom of circuit pattern design in the self-aligned quadruple patterning technology, without being limited by the manufacturing process of the spacers, the embodiment of the present application adds a The step of pattern lithography, that is, the circuit pattern is prepared by alternating multiple photolithography and two deposition spacers, and finally photolithography is used to define the pattern that needs to be opened to form a patterned hard mask. First of all, if adjacent metal lines are made on the same layer of photomask, they cannot be made very close to each other, but if adjacent metal lines are made on two different layers of photomask, the distance between each other It can be very close. In this way, multiple photolithography is performed in the self-aligned quadruple patterning technology, and the adjacent metal lines are distributed on different photomasks, so that the desired effect can be achieved before, and the density of the circuit pattern design can be improved. Secondly, since the patterned hard mask layer is formed after one photolithography, the sidewall layer is often made by depositing spacers based on the pattern during photolithography. The materials of the sidewall layer are different, and the etching speed is different, which greatly reduces the accuracy requirement for the overlay error of the circuit pattern during the second photolithography, and reduces the difficulty of circuit design. Moreover, the circuit pattern is ultimately a pattern defined by multiple photolithography patterns, and the length, width, or mutual spacing can be freely adjusted compared with the pattern defined by the spacer.

In addition, implementing the self-aligned quadruple patterning technology provided in the embodiments of the present application and the self-aligned quadruple patterned semiconductor device can be applied to semiconductor devices that produce various circuit patterns through the self-aligned quadruple patterning technology In the process of self-aligned quadruple patterning technology, photolithography is used to define the pattern that needs to be opened between and after the two spacer deposition and etching in the self-aligned quadruple patterning process flow, and the final circuit pattern is formed, which improves the circuit design. The density and degree of freedom greatly reduce the difficulty of circuit design. Wherein, for specific implementation manners, reference may be made to each of the following embodiments correspondingly, and the embodiments of the present application will not be repeated here.

Secondly, the embodiment of the present application provides a manufacturing method of a semiconductor device, which can increase the density and degree of freedom of circuit design, and reduce the difficulty of circuit design. Since the metal lines adjacent to the circuit pattern are made on the same photomask, they cannot be made very close to each other, but if the adjacent metal lines are made on two different photomasks, the distance between each other It can be very close. In this way, multiple photolithography is performed in the self-aligned quadruple patterning technology, and the adjacent metal lines are distributed on different photomasks, so that the desired effect can be achieved before, and the density of the circuit pattern design can be improved. Next, the lines in the circuit pattern formed by three photolithography are divided into three pattern lines, line A, line B, and line C, and a semiconductor device is fabricated by the self-aligned quadruple patterning technology provided by the embodiment of the present application as an example. Description The embodiment of the present application provides a method for fabricating a self-aligned quadruple patterned semiconductor device. Among them, the three pattern lines of line A, line B and line C are respectively pattern lines made in different photolithography stages.

Please refer to FIG. 1. FIG. 1 is a flowchart of steps of a method for fabricating a self-aligned quadruple patterned semiconductor device provided in an embodiment of the present application. The method includes:

Step S1, sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer and a first patterned hard mask layer on the surface of the layer to be etched.

Specifically, a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer are sequentially formed on the surface of the layer to be etched, and the first patterned hard mask layer includes the first A patterned sacrificial layer and a first sidewall layer covering all sidewalls of the first patterned sacrificial layer. The process used may be a selective deposition process, such as electroless plating; physical vapor deposition, chemical vapor deposition, or atomic layer deposition may also be used. It should be noted that step S1 is aimed at the preparation of line A in the first sidewall layer and the circuit pattern.

Please refer to FIG. 2 . FIG. 2 is a cross-sectional view of a set of self-aligned quadruple-patterned semiconductor devices according to an embodiment of the present application, and the cross-sectional view includes a top view and a side view. It should be noted that, as shown in FIG. 2 , the schematic diagram of the semiconductor device 10, in the semiconductor device 10, a first anti-reflection layer 102, a first sacrificial layer 103, and a second anti-reflection layer are stacked on the surface of the layer 101 to be etched. 104 and a first patterned hard mask layer 105, the first patterned hard mask layer 105 includes a first patterned sacrificial layer 1051 and a first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer. Optionally, the layer to be etched 101 is stacked on the substrate 100 . Wherein, the first patterned hard mask layer 105 includes one or more grooves LA (corresponding to line A), and the one or more grooves LA can be used to make pattern lines corresponding to line A, and the first patterned hard mask layer Layer 105 includes a first patterned sacrificial layer 1051 and a first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer.

In addition, it should be noted that, in the semiconductor device 10, the horizontal direction (that is, the left-right direction) is the X-axis direction, and the direction perpendicular to the thickness of the layer to be etched 101 is the Y-axis direction (that is, the vertical direction). , the front-rear direction perpendicular to the X-axis direction and the Y-axis direction is the Z-axis direction. Along the X-axis direction, that is, the width direction of the layer to be etched 101, the first anti-reflection layer 102, the first sacrificial layer 103, the second anti-reflection layer 104 and the first patterned hard mask layer 105; along the Y The axis direction is the thickness direction of the layer to be etched 101, the first anti-reflection layer 102, the first sacrificial layer 103, the second anti-reflection layer 104 and the first patterned hard mask layer 105; along the Z-axis direction, That is, the length direction of the layer to be etched 101 , the first anti-reflection layer 102 , the first sacrificial layer 103 , the second anti-reflection layer 104 and the first patterned hard mask layer 105 . In addition, cross-sectional views and process flow diagrams of semiconductor devices and other related devices in the present application and related embodiments below are also applicable to the coordinate system (X axis, X axis and Z axis) shown in FIG. 2 .

Optionally, the step of sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer and a first patterned hard mask layer on the surface of the layer to be etched includes: The surface of the layer is sequentially deposited to form the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, the second sacrificial layer and the first patterned photoresist layer; The etching layer is used as a mask to etch the second sacrificial layer, forming the first patterned sacrificial layer on the second sacrificial layer; removing the first patterned photoresist layer; Depositing and etching the first patterned sacrificial layer to form the first sidewall layer covering all sidewalls of the first patterned sacrificial layer. Opening the second sacrificial layer by photolithography and spacer deposition, forming a first patterned hard mask layer, and making a pattern corresponding to the first patterned photoresist layer.

Please refer to accompanying drawings 3 and 4, which are cross-sectional views of another set of self-aligned quadruple-patterned semiconductor devices provided by the embodiment of the present application. It should be noted that, as shown in FIG. 3 , the first anti-reflection layer 102, the first sacrificial layer 103, the second anti-reflection layer 104, The second sacrificial layer 106 and the first patterned photoresist layer 107; as shown in FIG. 4, the second sacrificial layer 106 is etched based on the first patterned photoresist layer 107 as a mask, in the The second sacrificial layer forms the first patterned sacrificial layer 1051; removes the first patterned photoresist layer 107; deposits and etches the first patterned sacrificial layer 1051 to form The first sidewall layer 1052 of the entire sidewall.

Optionally, the first patterned photoresist layer includes: a spin-on-carbon layer, a spin-on-glass layer, and a patterned photoresist layer stacked in sequence, wherein the spin-on-carbon layer is stacked on the second The sacrificial layer is away from the side of the second anti-reflection layer, and the spin-on-glass layer is between the spin-on-carbon layer and the patterned photoresist layer. Referring to FIG. 5 , FIG. 5 is a cross-sectional view of a set of patterned photoresist layers provided by an embodiment of the present application. As shown in FIG. 5 , the first patterned photoresist layer 107 includes a spin-on-carbon layer 1071 , a spin-on-glass layer 1072 and a patterned photoresist layer 1073 stacked in sequence. It should be noted that the pattern formed by the patterned photoresist layer 1073 is a part of the final circuit pattern. The patterned photoresist layer 1073 can be obtained by exposure or etching. The spin-on-carbon layer 1071 may be spin-on carbon, the material of the spin-on-glass layer 1072 is glass spin-on material, and the patterned photoresist layer is photoresist with one or more grooves. The three-layer structure of the photoresist can stably and accurately transfer the pattern formed by the photoresist to the second sacrificial layer through the photolithography process. In addition, it should be noted that the embodiment of the present application does not specifically limit the structural material of the patterned photoresist layer, for example, the patterned photoresist layer may include a spin-coated double-layer photoresist structure.

Optionally, the depositing and etching on the first patterned sacrificial layer to form the first sidewall layer covering all sidewalls of the first patterned sacrificial layer includes: Depositing the sacrificial layer to form an insulating material covering the first patterned sacrificial layer, etching the insulating material covering the horizontal direction of the first patterned sacrificial layer, and retaining the insulating material covering all sidewalls of the first patterned sacrificial layer the first sidewall layer. Wherein, the projection of the first sidewall layer in the vertical direction at least covers the projection of the first patterned sacrificial layer in the vertical direction. Please refer to FIG. 6 , which is a cross-sectional view of a set of semiconductor devices for forming a first sidewall layer according to an embodiment of the present application. It should be noted that, as shown in FIG. 6 , an insulating material covering the first patterned sacrificial layer is deposited on the first patterned sacrificial layer 1051; The insulating material in the direction, as shown in FIG. 2 above, retains the first sidewall layer 1052 covering all the sidewalls of the first patterned sacrificial layer 1051 . Wherein, the fabrication of the first sidewall layer may adopt a spacer process, the spacer process refers to conformally depositing an insulating material first, and then using anisotropic etching to retain the insulating material of the sidewall, exposing the bottom region (for example, the second resist reflective layer 104, etc.).

In addition, after the pattern line corresponding to line A is made, the length of the pattern line corresponding to line A can be adjusted. Here, in the embodiment of the present application, after preparing the pattern line corresponding to line A, the pattern line can be backfilled to realize the adjustment of the length of the pattern line. Optionally, the first patterned photoresist layer includes one or more third grooves; the first patterned sacrificial layer is deposited and etched to form grooves covering all sides of the first patterned sacrificial layer. The first sidewall layer of the wall, after the step, also includes: depositing and forming a sixth patterned photoresist layer covering the first patterned hard mask layer, and the sixth patterned photoresist layer includes one or more a fourth groove, the position of each of the fourth grooves is the same as that of each of the third grooves; based on the sixth patterned photoresist layer as a mask for the first patterned hard The mask layer is etched to form the first patterned hard mask layer after etching; the oxidation layer covering the sixth patterned photoresist layer and the first patterned hard mask layer after the etching is deposited and formed. object layer; removing the sixth patterned photoresist layer and the oxide layer covering the sixth patterned photoresist layer; performing photolithography on the first patterned hard mask layer to form a second patterned The hard mask layer step includes: performing photolithography on the etched first patterned hard mask layer and the remaining oxide layer to form the second patterned hard mask layer. Since the position of the third trench is the same as that of the fourth trench, depositing and forming an oxide at the position of the fourth trench can block the third trench, thereby forming a plurality of trenches of different lengths, Further, lines of circuit patterns with different lengths are obtained.

It should be noted that the first patterned photoresist layer includes one or more third grooves (such as: LA), and the third grooves can be used to prepare one or more pattern lines belonging to line A in the circuit pattern. Please refer to the accompanying drawings 7-10, which are cross-sectional views of a set of semiconductor devices for making Cut line A provided by the embodiment of the present application. Depositing and etching the first patterned sacrificial layer 1051 to form the first sidewall layer 1052 covering all the sidewalls of the first patterned sacrificial layer 1051, after the steps, further include:

As shown in FIG. 7, a sixth patterned photoresist layer 108 covering the first patterned hard mask layer 105 is deposited and formed, and the sixth patterned photoresist layer 108 includes one or more fourth grooves CA (Cut line A), the position of each of the fourth groove CA is the same as that of the third groove LA, that is, in order to adjust the line length (length in the Z-axis direction) of the line A pattern, the first The position of the fourth trench CA coincides with the position of the third trench LA.

As shown in FIG. 8 , based on the sixth patterned photoresist layer 108 as a mask, the first patterned hard mask layer 105 is etched to form the etched first patterned hard mask layer 105 . That is, the first patterned hard mask layer 105 is etched according to the position of the fourth trench CA, wherein, in order to block the lines of the line A pattern, the line length of the line A pattern is adjusted, and the fourth trench CA is at X The width in the axial direction may be greater than or equal to the width of a region of the third trench LA not covered by the first sidewall layer in the X-axis direction.

In addition, in order to block the lines of the line A pattern, an oxide layer 109 needs to be deposited and formed at the fourth trench CA to disconnect the electrical connection of the line A. As shown in FIG. 9 , deposit and form an oxide layer 109 covering the sixth patterned photoresist layer 108 and the etched first patterned hard mask layer 105, wherein the fourth trench CA The oxide layer 109 at needs to cover and cover the bottom area of the fourth trench CA, and can serve as a mask in subsequent processes. For example, the vertical thickness of the oxide layer 109 at the fourth trench CA is greater than or equal to the thickness of the first patterned hard mask layer 105 .

As shown in FIG. 10 , the sixth patterned photoresist layer 108 and the oxide layer 109 covering the sixth patterned photoresist layer are removed, that is, the oxide layer 109 at the fourth trench CA remains, so as to prevent Break the lines of the line A pattern. Wherein, the embodiment of the present application does not specifically limit the length of the fourth groove CA in the Z-axis direction. For example, the length of the fourth groove CA in the Z-axis direction may be smaller than the length of the third groove LA in the Z-axis direction. length in the direction. Finally, the step of performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer includes: the etched first patterned hard mask layer 105 and the remaining The oxide layer 109 (at the fourth trench) is photolithographically formed to form the second patterned hard mask layer 115 . For this step, reference may be made to the related description of step S2 below, and details are not described here in this embodiment of the present application.

Step S2, performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer.

Specifically, performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer. Please refer to FIG. 11 . FIG. 11 is a device cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application. As shown in FIG. 11 , based on the cross-sectional view of the semiconductor provided in FIG. 10 , photolithography is performed on the first patterned hard mask layer 105 to form a second patterned hard mask layer 115 . It should be noted that the second patterned hard mask layer 115 includes one or more trenches LA (corresponding to line A) formed after the first photolithography and one or more trenches LB (corresponding to line A) after the current photolithography. line B), the one or more trenches LB can be used to make pattern lines corresponding to line B, that is, the second patterned hard mask layer 115 also includes a patterned sacrificial layer not covered by sidewalls. It should be noted that step S2 is aimed at the preparation of line B in the circuit pattern. It should also be noted that, since the materials of the first sidewall layer 1052 and the first patterned sacrificial layer 1051 in the formed first patterned hard mask layer 105 are different after the first photolithography (preparation of line A), so When photoetching the circuit pattern (preparing line B) again, the speed of etching the first sidewall layer 1052 is different from that of the first patterned sacrificial layer 1051. For example, the speed of etching the first patterned sacrificial layer 1051 is faster. The first patterned sacrificial layer 1051 will be etched preferentially at the moment, avoiding too much influence on line A when preparing line B, thereby greatly reducing the accuracy requirements for the overlay error of the circuit pattern during photolithography again, reducing the the difficulty of circuit design.

Optionally, the step of performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer includes: depositing and forming a second pattern covering the first patterned hard mask layer photoresist layer; based on the second patterned photoresist layer as a mask, the first patterned hard mask layer is etched to form the second patterned hard mask layer; the second patterned hard mask layer is removed. Pattern the photoresist layer. Please refer to FIG. 12 . FIG. 12 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application. It should be noted that, as shown in FIG. 12 , the second patterned photoresist layer 201 covering the first patterned hard mask layer 105 is deposited and formed; based on the second patterned photoresist layer 201 as a mask pair The first patterned hard mask layer is etched to form the second patterned hard mask layer 115 (as shown in FIG. 11 ); the second patterned photoresist layer 201 is removed.

In addition, after the pattern line corresponding to line B is made, the length of the pattern line corresponding to line B can be adjusted. Different from the adjustment of the line A backfill method in the embodiment of this application (preparing line A first and then cutting line A), this application can prepare Cut line B by digging in advance, that is, first prepare Cut line B and then prepare line B . Therefore, before preparing the pattern line corresponding to line B, the pattern line can be cut to realize the adjustment of the length of the pattern line. Since the Cut line B is formed before the preparation of the line B, in order to ensure that the Cut line B can block the electrical connection of the line B, the Cut line B needs to be completed before the preparation of the spacer (that is, the formation of the first sidewall layer), To ensure that insulating material can be deposited at Cut line B to block the electrical connection of line B. This application takes the preparation of Cut line B before the preparation of the first patterned hard mask layer as an example for illustration. Optionally, the second patterned photoresist layer includes one or more first trenches; the first patterned sacrificial layer is deposited and etched to form grooves covering all sides of the first patterned sacrificial layer. Before the step of forming the first side wall layer of the wall, it also includes: forming a fifth patterned photoresist layer on the surface of the first patterned sacrificial layer, and the fifth patterned photoresist layer includes one or more second Grooves, the position of each of the second grooves is the same as that of each of the first grooves; based on the fifth patterned photoresist layer as a mask, according to the second grooves to the Etching the first patterned sacrificial layer to form the etched first patterned sacrificial layer; removing the fifth patterned photoresist layer.

It should be noted that the second patterned photoresist layer includes one or more first grooves (such as: LB), and the first grooves can be used to prepare one or more pattern lines belonging to line B in the circuit pattern. Please refer to the accompanying drawings 13-15, which are cross-sectional views of a set of semiconductor devices for making Cut line B provided by the embodiment of the present application. Before the step of depositing and etching the first patterned sacrificial layer to form the first sidewall layer covering all the sidewalls of the first patterned sacrificial layer, the step further includes: as shown in FIG. 13 , in the The fifth patterned photoresist layer 202 is formed on the surface of the first patterned sacrificial layer 1051, and the fifth patterned photoresist layer 202 includes one or more second grooves CB, and the position of each second groove CB The position of each first trench LB is the same, and in addition, the length of the second trench CB in the X-axis direction is greater than or equal to the length of the first trench LB in the X-axis direction.

As shown in FIG. 14 , based on the fifth patterned photoresist layer 202 as a mask, the first patterned sacrificial layer 1051 is etched according to the second trench CB to form a first pattern after etching. the sacrificial layer 1051; remove the fifth patterned photoresist layer 202. Since the first patterned sacrificial layer 1051 is deposited and etched to form the first sidewall layer 1052 covering all sidewalls of the first patterned sacrificial layer 1051 before the first patterned sacrificial layer 1051 is prepared The pattern corresponding to the second trench CB, therefore, as shown in FIG. 15 , when preparing the first sidewall layer 1052, the insulating material of the sidewall layer will cover the first patterned sacrificial layer 1051 after etching, thereby also covering the second trench CB, and then when the pattern formed by the first trench LB is subsequently prepared, the insulating material at the second trench CB will block the pattern lines formed by the first trench LB, thereby obtaining one or more discontinuous Grooves of different lengths, that is, different lengths of circuit pattern lines (for line B) are obtained.

It should also be noted that the preparation process of the Cut line B can also be prepared before the step of forming the first patterned sacrificial layer, that is, the Cut line B is prepared before the line A, the Cut line A and the line B. For example: a fifth patterned photoresist layer is formed on the surface of the second sacrificial layer, the fifth patterned photoresist layer includes one or more second grooves, and the position of each second groove is the same as that of each The positions of the two first trenches are the same; based on the fifth patterned photoresist layer as a mask, the second sacrificial layer is etched according to the second trench to form a second sacrificial layer after etching. layer; removing the fifth patterned photoresist layer. Then prepare line A, Cut line A and line B in sequence.

Since the preparation process of Cut line B needs to be before depositing the first side wall layer, line B can only be prepared after Cut line B is prepared. Please refer to FIG. 16 . FIG. 16 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application. As shown in Figure 16, based on the semiconductor cross-sectional view provided in Figure 15 above (semiconductor cross-sectional view prepared by line A, Cut line A and Cut line B), based on the first patterned hard mask formed by the second sacrificial layer after etching The film layer 105 is subjected to photolithography to form a second patterned hard mask layer 115 . It should be noted that the first patterned hard mask layer 105 is based on the first patterned hard mask layer 105 formed after etching and photolithography of the second sacrificial layer, and the second patterned hard mask layer 115 includes the original One or more grooves LA (corresponding to line A) formed after one lithography, one or more grooves LB (corresponding to line B) after the current lithography, Cut line A for the pattern line corresponding to line A, and , for the Cut line B corresponding to the pattern line of line B, the preparation method of the Cut line A can refer to the relevant descriptions in the above-mentioned FIGS.

Step S3 , etching the second anti-reflection layer and the first sacrificial layer based on the second patterned hard mask layer as a mask to form a second patterned sacrificial layer.

Specifically, etching the second anti-reflection layer and the first sacrificial layer based on the second patterned hard mask layer as a mask to form a second patterned sacrificial layer. Please refer to FIG. 17 . FIG. 17 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application. Based on the second patterned hard mask layer 115 as a mask, the second anti-reflection layer 104 and the first sacrificial layer 103 are etched, as shown in FIG. Second, pattern the sacrificial layer 1031 . Wherein, the relevant description of the second patterned sacrificial layer 1031 can refer to the relevant description of the first patterned sacrificial layer 1051 , which will not be repeated in this embodiment of the present application. Wherein, the cross-sectional view of the semiconductor shown in FIG. 17 is a schematic cross-sectional view after removing the second patterned hard mask layer 115 and the second anti-reflection layer 104 .

Step S4, removing the second patterned hard mask layer and the second anti-reflection layer, and forming a third patterned hard mask layer based on the second patterned sacrificial layer.

Specifically, please refer to FIG. 18 . FIG. 18 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application. As shown in FIG. 18 , the second patterned hard mask layer 115 and the second anti-reflection layer 104 are removed, and a third patterned hard mask layer 1032 is formed based on the second patterned sacrificial layer 1031 . The third patterned hard mask layer 1032 includes the second patterned sacrificial layer 1031 and a second sidewall layer 1033 covering all sidewalls of the second patterned sacrificial layer 1031 . It should be noted that step S4 is for the preparation of the second sidewall layer.

Optionally, please refer to FIG. 19 . FIG. 19 is a device cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application. As shown in FIG. 19 , the step of forming a third patterned hard mask layer 1032 based on the second patterned sacrificial layer 1031 includes: depositing on the second patterned sacrificial layer 1031 to form a mask covering the second patterned sacrificial layer 1031 of the insulating material; etching the insulating material covering the horizontal direction of the second patterned sacrificial layer 1031, leaving the second sidewall layer 1033 covering all the sidewalls of the second patterned sacrificial layer 1031, this The process is the second spacer deposition process. Wherein, the fabrication of the second sidewall layer 1033 also adopts a spacer process, and the spacer process refers to conformally depositing an insulating material first, and then adopts anisotropic etching to retain the insulating material of the sidewall, exposing the bottom region (for example, the second an anti-reflection layer 102, etc.). For the relevant description of the second sidewall layer 1033 , reference may be made to the relevant description of the first sidewall layer 1052 , which will not be repeated in this embodiment of the present application.

Step S5, performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer.

Specifically, photolithography is performed on the third patterned hard mask layer to form a fourth patterned hard mask layer. Please refer to FIG. 20 . FIG. 20 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices according to an embodiment of the present application. As shown in FIG. 20 , based on the semiconductor cross-sectional view provided in FIG. 18 , photolithography is performed on the third patterned hard mask layer 1032 to form a fourth patterned hard mask layer 1132 . It should be noted that the third patterned hard mask layer 1032 includes one or more trenches LA (corresponding to line A) formed after the first photolithography, and one or more trenches LB (corresponding to line A) after the second photolithography. Corresponding to line B) and the second sidewall layer 1033 formed after the second spacer deposition; the fourth patterned hard mask layer 1132 includes one or more grooves LA formed after the first photolithography (corresponding to line A ), one or more grooves LB (corresponding to line B) formed after the second lithography and the second sidewall layer 1033 formed after the second spacer deposition, and one or more grooves formed after the current lithography Groove LC (corresponding to line C), the one or more grooves LC can be used to make the pattern lines corresponding to line C, that is, the fourth patterned hard mask layer 1132 also includes a patterned sacrificial layer not covered by sidewalls . It should be noted that step S5 is aimed at the preparation of line C in the circuit pattern.

In the case that the circuit pattern is not complicated, the circuit pattern can be formed by three photolithography (line A, line B and line C) preparations. Optionally, the step of performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer includes: performing photolithography on the etching layer to form the fourth patterned hard mask layer. In the embodiment of the present application, the photolithography process may first form a patterned photoresist layer covering the patterned hard mask layer, then use the patterned photoresist layer as a mask to further open the sacrificial layer, and finally remove the patterned photoresist layer. layered.

For example: Please refer to FIG. 21 , which is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices provided by an embodiment of the present application. As shown in FIG. 21 , the step of performing photolithography on the third patterned hard mask layer according to the third patterned photoresist layer to form the fourth patterned hard mask layer includes: depositing and forming The third patterned photoresist layer 203 of the third patterned hard mask layer 1032; based on the third patterned photoresist layer 203 as a mask, the third patterned hard mask layer 1032 is etched to form The fourth patterned hard mask layer 1132 (as shown in FIG. 20 ); removing the third patterned photoresist layer 203 .

It should be noted that, optionally, in the horizontal direction (that is, in the X-axis direction), the line widths of the third patterned photoresist layer patterns are respectively equal to or greater than twice the width of the second sidewall layer The width of the second sidewall layer. That is, the size of the pattern defined by the second photolithography (the width of LB on the X axis) is equal to the width of the second sidewall layer or greater than twice the width of the second sidewall layer. Different from the prior art that the line width of the pattern must be equal to the width of the second side wall layer, the line width of the pattern in the embodiment of the present application may also be greater than twice the width of the second side wall layer.

It should also be noted that, optionally, in the horizontal direction (that is, in the X-axis direction), the patterns of the second patterned photoresist layer, the third patterned photoresist layer, and the fourth patterned photoresist layer The line width is less than or equal to the distance between adjacent first sidewall layers or between adjacent second sidewall layers. In the embodiment of the present application, the line width of the circuit pattern prepared after the first sidewall layer cannot exceed the distance between the first sidewall layer and the adjacent second sidewall layer. It does not straddle or exceed the distance between corresponding positions of two spacers (that is, the distance between corresponding positions of adjacent first sidewall layers 1052 or adjacent second sidewall layers 1033 ).

In addition, after the pattern line corresponding to line C is made, the length of the pattern line corresponding to line C can also be adjusted. Cut line B is prepared by cutting line B in advance in the embodiment of the present application, and Cut line C can be prepared by cutting line C in advance in the embodiment of the present application, so as to realize the adjustment of the length of line C of the pattern line. Since the Cut line C is formed before the preparation of the line B, in order to ensure that the Cut line C can block the electrical connection of the line C, the Cut line C needs to be completed before preparing the spacer (that is, forming the second side wall layer 1033) , to ensure that insulating material can be deposited at Cut line C to block the electrical connection of line C. For example, the third patterned photoresist layer 203 includes one or more fifth trenches LC.

It should be noted that the third patterned photoresist layer 203 includes one or more fifth grooves (such as: LC), which can be used to prepare one or more pattern lines belonging to line C in the circuit pattern . Please refer to the accompanying drawings 22-24, which are cross-sectional views of a set of semiconductor devices for making Cut line C provided by the embodiment of the present application. Before the step of depositing the second patterned sacrificial layer 1031 to form an insulating material covering the second patterned sacrificial layer 1031, it also includes: as shown in FIG. 22 , on the surface of the second patterned sacrificial layer 1031 A seventh patterned photoresist layer 204 is formed, and the seventh patterned photoresist layer 204 includes one or more sixth trenches CC, and the position of each sixth trench CC is the same as that of each fifth trench The positions of the grooves LC are the same; in addition, the length of the sixth groove CC in the X-axis direction is greater than or equal to the length of the fifth groove LC in the X-axis direction.

As shown in FIG. 23 , based on the seventh patterned photoresist layer 204 as a mask, the second patterned sacrificial layer 1031 is etched according to the sixth trench CC to form a second pattern after etching. the sacrificial layer 1031; remove the seventh patterned photoresist layer 204. Since the second patterned sacrificial layer 1031 is deposited and etched to form the second sidewall layer 1033 covering all the sidewalls of the second patterned sacrificial layer 1031 before the second patterned sacrificial layer 1031 is prepared The pattern corresponding to the second trench CC, therefore, as shown in FIG. 19 above, when preparing the second sidewall layer 1033, the insulating material of the sidewall layer will cover the etched second patterned sacrificial layer 1031, thereby also covering the second Two grooves CC, and then when the pattern formed by the first groove LC is subsequently prepared, the insulating material at the second groove CC will block the pattern lines formed by the first groove LC, thereby obtaining a discontinuous one or more grooves of different lengths, that is, to obtain circuit pattern lines of different lengths (for line C).

Since the preparation 102 process of Cut line C needs to be before depositing the second sidewall layer, line C can only be prepared after Cut line C is prepared. Based on the semiconductor cross-sectional view provided in Figure 23 above (semiconductor cross-sectional view prepared by line A, line B, Cut line A, Cut line B, and Cut line C), as shown in Figure 24, based on the second patterned sacrifice after etching Layer 1031 performs photolithography on third patterned hard mask layer 1032 to form fourth patterned hard mask layer 1132 . It should be noted that the preparation process of the Cut line C can also refer to the preparation process of the above-mentioned Cut line B, which will not be repeated in the embodiments of this application.

Step S6 , etching the first anti-reflection layer and the layer to be etched based on the fourth patterned hard mask layer as a mask to form a patterned layer to be etched.

Specifically, the first anti-reflection layer and the layer to be etched are etched based on the fourth patterned hard mask layer as a mask to form a patterned layer to be etched. For example, when the layer to be etched is a metal material, the circuit pattern on the fourth patterned hard mask layer can be transferred to the layer to be etched by etching to form a plurality of metal lines and form electrical connections. Please refer to FIG. 25 . FIG. 25 is a cross-sectional view of another set of self-aligned quadruple-patterned semiconductor devices according to an embodiment of the present application. As shown in FIG. 25 , based on the fourth patterned hard mask layer 1132 as a mask, the first anti-reflection layer 102 and the layer to be etched 101 are etched to form a patterned layer to be etched 111 .

Step S7, removing the fourth patterned hard mask layer and the first anti-reflection layer.

Specifically, as shown in FIG. 25 , the fourth patterned hard mask layer 1132 and the first anti-reflection layer 102 are removed to obtain a patterned layer to be etched.

Different from the patterned hard mask formed by depositing spacers twice in the prior art, the embodiment of the present application adds a step of pattern photolithography between the sidewalls deposited twice, that is, through multiple photolithography and The circuit pattern is prepared by alternately depositing spacers twice, and finally photolithography is used to define the pattern that needs to be opened to form a patterned hard mask. First of all, if adjacent metal lines are made on the same layer of photomask, they cannot be made very close to each other, but if adjacent metal lines are made on two different layers of photomask, the distance between each other It can be very close. In this way, multiple photolithography is performed in the self-aligned quadruple patterning technology, and the adjacent metal lines are distributed on different photomasks, so that the desired effect can be achieved before, and the density of the circuit pattern design can be improved. Secondly, since the patterned hard mask layer is formed after one photolithography, the sidewall layer is often made by depositing spacers based on the pattern during photolithography. The materials of the sidewall layer are different, and the etching speed is different, which greatly reduces the accuracy requirement for the overlay error of the circuit pattern during the second photolithography, and reduces the difficulty of circuit design. Moreover, the circuit pattern is ultimately a pattern defined by multiple photolithography patterns, and the length, width, or mutual spacing can be freely adjusted compared with the pattern defined by the spacer.

The above step S1-step S7 takes the lines in the circuit pattern divided into three pattern lines, line A, line B and line C as an example, to illustrate that the embodiment of the present application provides a self-aligned quadruple patterned semiconductor The method of making the device. In addition, the embodiments of the present application are based on a method for fabricating a self-aligned quadruple patterned semiconductor device provided in the above embodiments, for example, the four pattern lines of line A, line B, line C and line D are respectively in different photolithography stages Make patterned lines. Taking four times as an example, please refer to the description of the following related steps:

Step 1, on the surface of the layer to be etched, the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, the second sacrificial layer and the first patterned photoresist layer are deposited sequentially (preparation of the patterned photolithography layer of LA layer), the first patterned photoresist layer includes one or more third grooves.

Step 2: Etching the second sacrificial layer based on the first patterned photoresist layer as a mask, etching the second sacrificial layer according to the third groove, and forming a first patterned mask layer on the second sacrificial layer .

Step 3, removing the first patterned photoresist layer (the preparation of LA is completed).

Step 4, forming a fifth patterned photoresist layer (a patterned photoresist layer for preparing CB) on the surface of the first patterned sacrificial layer, and the fifth patterned photoresist layer includes one or more second grooves.

Step 5: Based on the fifth patterned photoresist layer as a mask, the first patterned sacrificial layer is etched according to the second groove to form the etched first patterned sacrificial layer.

Step six, removing the fifth patterned photoresist layer.

Step 7, after etching, the first patterned sacrificial layer is deposited and etched to form a first sidewall layer covering all sidewalls of the first patterned sacrificial layer to obtain a first patterned hard mask layer (first sidewall layer and CB preparation is complete).

Step 8, depositing and forming a sixth patterned photoresist layer covering the first patterned hard mask layer (preparing a patterned photoresist layer for CA), the sixth patterned photoresist layer includes one or more fourth grooves, The position of each fourth groove is the same as the position of each third groove.

Step 9: Etching the first patterned hard mask layer based on the sixth patterned photoresist layer as a mask to form an etched first patterned hard mask layer.

Step ten, depositing and forming an oxide layer covering the sixth patterned photoresist layer and the etched first patterned hard mask layer.

Step eleven, removing the sixth patterned photoresist layer and the oxide layer covering the sixth patterned photoresist layer (CA preparation is completed).

Step 12, depositing and forming a second patterned photoresist layer covering the etched first patterned hard mask layer and the remaining oxide layer (preparing the patterned photoresist layer of LB), the second patterned photoresist layer It includes one or more first grooves, and the position of each second groove is the same as that of each first groove.

Step 13: Etching the etched first patterned hard mask layer and the remaining oxide layer based on the second patterned photoresist layer as a mask to form a second patterned hard mask layer.

Step fourteen, removing the second patterned photoresist layer (the preparation of LB is completed).

Step fifteen, etching the second anti-reflection layer and the first sacrificial layer based on the second patterned hard mask layer as a mask to form a second patterned sacrificial layer.

Step sixteen, removing the second patterned hard mask layer and the second anti-reflection layer.

Step seventeen, forming a seventh patterned photoresist layer (preparing CC and CD patterned photoresist layers) on the surface of the second patterned sacrificial layer, the seventh patterned photoresist layer includes one or more sixth grooves and Eighth groove.

Step eighteen, based on the seventh patterned photoresist layer as a mask, etch the second patterned sacrificial layer according to the sixth groove to form the etched second patterned sacrificial layer.

Step nineteen, removing the seventh patterned photoresist layer.

Step 20, after etching, the second patterned sacrificial layer is deposited and etched to form a second sidewall layer covering all sidewalls of the second patterned sacrificial layer after etching, to obtain a third patterned hard mask layer (the second Two sidewall layers, CC and CD are prepared).

Step 21, depositing and forming a third patterned photoresist layer (patterned photoresist layer for preparing LC) covering the third patterned hard mask layer, the third patterned photoresist layer includes one or more fifth grooves The position of each fifth groove is the same as the position of each sixth groove.

Step 22: Etching the third patterned hard mask layer based on the third patterned photoresist layer as a mask to form a fifth patterned hard mask layer.

Step 23, removing the third patterned photoresist layer (the LC preparation is completed).

Step 24, depositing and forming a fourth patterned photoresist layer (patterned photoresist layer for preparing LD) covering the fifth patterned hard mask layer, the fourth patterned photoresist layer includes one or more seventh grooves The position of each seventh groove is the same as the position of each eighth groove.

Step 25: Etching the fifth patterned hard mask layer based on the fourth patterned photoresist layer as a mask to form a fourth patterned hard mask layer.

Step twenty-six, removing the fourth patterned photoresist layer (the LD is prepared).

Step 27: Etching the first anti-reflection layer and the layer to be etched based on the fourth patterned hard mask layer as a mask to form a patterned layer to be etched.

Step 28, removing the fourth patterned hard mask layer and the first anti-reflection layer.

For steps 24 to 26, the step of performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer includes: Perform photolithography according to the third patterned photoresist layer to form a fifth patterned hard mask layer; perform photolithography on the fifth patterned hard mask layer according to the fourth patterned photoresist layer to form the fourth pattern hard mask layer. Wherein, performing photolithography on the third patterned hard mask layer according to the third patterned photoresist layer to form the fifth patterned hard mask layer, this process is the preparation of the line C pattern lines in the circuit pattern (as mentioned above Relevant descriptions of Fig. 20-Fig. 21); carry out photolithography on the fifth patterned hard mask layer according to the fourth patterned photoresist layer to form the fourth patterned hard mask layer. Preparation of patterned lines in line D. In the embodiment of the present application, the preparation process of line D and line C is similar. Please refer to accompanying drawings 26-30, which are cross-sectional views of a set of semiconductor devices for manufacturing line D and Cut line D provided by the embodiment of the present application. in,

As shown in FIG. 26, based on the relevant description in FIG. 22 above, a seventh patterned photoresist layer 204 is formed on the surface of the second patterned sacrificial layer 1031, and the seventh patterned photoresist layer 204 includes one or more The sixth groove CC and one or more eighth groove CD (preparing Cut line C and Cut line D simultaneously), the position of each said sixth groove CC and the position of each said fifth groove LC Similarly, the position of each of the eighth trenches CD is the same as the position of each of the seventh trenches LD. In addition, the length of the sixth trench CC in the X-axis direction is greater than or equal to the length of the fifth trench LC in the X-axis direction, and the length of the eighth trench CD in the X-axis direction is greater than or equal to that of the seventh trench. The length of the groove LD in the X-axis direction.

As shown in FIG. 27 , based on the relevant description of FIG. 23 above, the seventh patterned photoresist layer 204 is a mask, and the second patterned sacrificial layer is formed according to the sixth trench CC and the eighth trench CD. The layer 1031 is etched to form the etched second patterned sacrificial layer 1031 ; and the seventh patterned photoresist layer 204 is removed.

As shown in FIG. 28 , photolithography is performed on the fifth patterned hard mask layer according to the fourth patterned photoresist layer to form the fourth patterned hard mask layer. First, deposit and form a fourth patterned photoresist layer 205 (patterned photoresist layer for preparing LD) covering the fifth patterned hard mask layer, the fourth patterned photoresist layer 205 includes one or more seventh grooves LD, the position of each of the seventh trenches LD is the same as the position of each of the eighth trenches CD. In addition, performing photolithography on the third patterned hard mask layer according to the third patterned photoresist layer to form a fifth patterned hard mask layer, this process is the preparation of line C pattern lines in the circuit pattern (as mentioned above 20-21 ), the embodiment of the present application will not repeat them.

As shown in FIG. 29 , based on the fourth patterned photoresist layer 205 as a mask, the fifth patterned hard mask layer is etched to form a fourth patterned hard mask layer. The fourth patterned photoresist layer is removed (the LD is prepared).

As shown in FIG. 30, according to the semiconductor device shown in FIG. 29 above, the first anti-reflection layer and the layer to be etched are etched based on the fourth patterned hard mask layer as a mask to form The layer to be etched is patterned, and the fourth patterned hard mask layer and the first anti-reflection layer are removed.

In the horizontal direction, the line widths of the patterns of the third patterned photoresist layer and the fourth patterned photoresist layer are respectively equal to the width of the second sidewall layer or greater than twice the width of the second sidewall layer The width of the layer. Unlike the prior art, the line width of the pattern must be equal to the width of the second sidewall layer, that is, the width of the LC and LD prepared by the third photolithography and the fourth photolithography in the X-axis direction is equal to the second sidewall layer width or greater than twice the width of the second sidewall layer.

It should be noted that for Step 1 to Step 23, and Step 27 to Step 28, it is a kind of preparation provided by the embodiment of this application. Please refer to the relevant descriptions of Step S1-Step S7 above, and this application will not repeat them. .

It should also be noted that the specific splitting method of the circuit pattern and the number of photolithography during preparation need to be determined according to the specific situation, which is not specifically limited in this embodiment of the present application.

It should also be noted that the embodiment of the present application also provides a semiconductor device prepared based on the above-mentioned self-aligned quadruple-patterned semiconductor device manufacturing method, including a substrate and any one of the above-mentioned methods stacked on the substrate. items of semiconductor devices. For example, patterned layers to be etched can also be stacked on the substrate to form electrical connections, so as to realize corresponding functions.

It should also be noted that the embodiment of the present application further provides an electronic device, and the electronic device includes any semiconductor device and a circuit board provided in the foregoing embodiments. The semiconductor device is electrically connected to the circuit board, and the electronic equipment is used to realize related functions.

In the foregoing embodiments, the descriptions of each embodiment have their own emphases, and for parts not described in detail in a certain embodiment, reference may be made to relevant descriptions of other embodiments.

It should be noted that for the foregoing method embodiments, for the sake of simple description, they are expressed as a series of action combinations, but those skilled in the art should know that the present application is not limited by the described action sequence. Depending on the application, certain steps may be performed in other orders or simultaneously. Secondly, those skilled in the art should also know that the embodiments described in the specification belong to preferred embodiments, and the actions and modules involved are not necessarily required by this application.

In the several embodiments provided in this application, it should be understood that the disclosed device can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the above units is only a logical function division. In actual implementation, there may be other division methods, for example, multiple units or components can be combined or integrated. to another system, or some features may be ignored, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical or other forms.

The units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the above integrated units are realized in the form of software function units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or part of the contribution to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, server or network device, etc., specifically, a processor in the computer device) execute all or part of the steps of the above-mentioned methods in various embodiments of the present application. Wherein, the foregoing storage medium may include: U disk, mobile hard disk, magnetic disk, optical disc, read-only memory (Read-Only Memory, abbreviated: ROM) or random access memory (Random Access Memory, abbreviated: RAM) and the like. A medium that can store program code.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions described in each embodiment are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application.

Claims

A method for fabricating a self-aligned quadruple patterned semiconductor device, comprising:

A first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer, and a first patterned hard mask layer are sequentially formed on the surface of the layer to be etched, and the first patterned hard mask layer includes a first patterned a sacrificial layer and a first sidewall layer covering all sidewalls of the first patterned sacrificial layer;

performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer;

Etching the second anti-reflection layer and the first sacrificial layer based on the second patterned hard mask layer as a mask to form a second patterned sacrificial layer;

removing the second patterned hard mask layer and the second anti-reflection layer, and forming a third patterned hard mask layer based on the second patterned sacrificial layer, the third patterned hard mask layer comprising the second patterned sacrificial layer and a second sidewall layer covering all sidewalls of the second patterned sacrificial layer;

performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer;

Etching the first antireflection layer and the layer to be etched based on the fourth patterned hard mask layer as a mask to form a patterned layer to be etched;

removing the fourth patterned hard mask layer and the first anti-reflection layer.
The method according to claim 1, wherein the step of sequentially forming a first anti-reflection layer, a first sacrificial layer, a second anti-reflection layer and a first patterned hard mask layer on the surface of the layer to be etched, include:

sequentially depositing the first anti-reflection layer, the first sacrificial layer, the second anti-reflection layer, the second sacrificial layer and the first patterned photoresist layer on the surface of the layer to be etched;

Etching the second sacrificial layer based on the first patterned photoresist layer as a mask, forming the first patterned sacrificial layer on the second sacrificial layer;

removing the first patterned photoresist layer;

Depositing and etching on the first patterned sacrificial layer to form the first sidewall layer covering all sidewalls of the first patterned sacrificial layer.
The method according to claim 2, wherein the first patterned photoresist layer comprises: a spin-on-carbon layer, a spin-on-glass layer, and a patterned photoresist layer stacked in sequence, wherein the spin-coated A carbon layer is stacked on a side of the second sacrificial layer away from the second anti-reflection layer, and the spin-on-glass layer is between the spin-on-carbon layer and the patterned photoresist layer.
The method according to any one of claim 2, wherein the step of performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer comprises:

depositing a second patterned photoresist layer overlying the first patterned hard mask layer;

Etching the first patterned hard mask layer based on the second patterned photoresist layer as a mask to form the second patterned hard mask layer;

removing the second patterned photoresist layer.
The method according to claim 4, wherein the step of performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer comprises:

Perform photolithography on the third patterned hard mask layer according to the third patterned photoresist layer to form the fourth patterned hard mask layer.
The method according to claim 4, wherein the step of performing photolithography on the third patterned hard mask layer to form a fourth patterned hard mask layer comprises:

performing photolithography on the third patterned hard mask layer according to the third patterned photoresist layer to form a fifth patterned hard mask layer;

Perform photolithography on the fifth patterned hard mask layer according to the fourth patterned photoresist layer to form the fourth patterned hard mask layer.
The method according to claim 6, characterized in that, in the horizontal direction, the line widths of the patterns of the third patterned photoresist layer and the fourth patterned photoresist layer are respectively equal to those of the second side wall layer The width of or greater than twice the width of the second sidewall layer.
The method according to claim 6 or 7, characterized in that, in the horizontal direction, the line widths of the patterns of the second patterned photoresist layer, the third patterned photoresist layer and the fourth patterned photoresist layer are less than Or equal to the distance between adjacent first sidewall layers or between adjacent second sidewall layers.
The method according to claim 4, wherein the second patterned photoresist layer comprises one or more first trenches; the first patterned sacrificial layer is deposited and etched to form a groove covering the Before the step of the first sidewall layer of all sidewalls of the first patterned sacrificial layer, it also includes:

A fifth patterned photoresist layer is formed on the surface of the first patterned sacrificial layer, the fifth patterned photoresist layer includes one or more second grooves, and the position of each second groove is the same as that of each The positions of the first grooves are the same;

Based on the fifth patterned photoresist layer as a mask, etching the first patterned sacrificial layer according to the second groove to form a first patterned sacrificial layer after etching;

removing the fifth patterned photoresist layer.
The method according to any one of claims 2-4, wherein the first patterned photoresist layer comprises one or more third grooves; the depositing and engraving on the first patterned sacrificial layer Forming the first sidewall layer covering all the sidewalls of the first patterned sacrificial layer by etching, after the step, also includes:

Depositing and forming a sixth patterned photoresist layer covering the first patterned hard mask layer, the sixth patterned photoresist layer includes one or more fourth grooves, each of the fourth grooves The location is the same as the location of each of the third grooves;

Etching the first patterned hard mask layer based on the sixth patterned photoresist layer as a mask to form an etched first patterned hard mask layer;

Depositing an oxide layer covering the sixth patterned photoresist layer and the etched first patterned hard mask layer;

removing the sixth patterned photoresist layer and the oxide layer covering the sixth patterned photoresist layer;

The step of performing photolithography on the first patterned hard mask layer to form a second patterned hard mask layer includes:

performing photolithography on the etched first patterned hard mask layer and the remaining oxide layer to form the second patterned hard mask layer.
A self-aligned quadruple-patterned semiconductor device, characterized by comprising a substrate and a semiconductor device manufactured by the method according to any one of claims 1-10 stacked on the substrate.