CN117912937A - Self-aligned double patterning method, semiconductor device and electronic equipment - Google Patents
Self-aligned double patterning method, semiconductor device and electronic equipment Download PDFInfo
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Abstract
The invention discloses a self-aligned double patterning method, a semiconductor device and electronic equipment, and relates to the technical field of semiconductors, so that the steps of the existing SADP process are simplified, and the process cost is reduced. The self-aligned double patterning method comprises the following steps: a hard mask layer and an electron beam negative photoresist layer are sequentially formed on a substrate. And exposing and developing the electron beam negative glue layer by using electron beams, and forming a plurality of sacrificial mandrels on the electron beam negative glue layer. A photoresist layer is formed on the outer periphery of the plurality of sacrificial mandrels. And carrying out gray scale photoetching treatment on the photoresist layer based on a preset mask plate, and forming a plurality of corresponding target sacrificial wall structures on the side wall of each sacrificial mandrel. Etching the hard mask layer based on the plurality of target sacrificial wall structures to form a target pattern on the hard mask layer. The semiconductor device comprises at least one patterned structure, and the patterned structure is manufactured and formed by adopting the self-aligned double patterning method provided by the technical scheme.
Description
Technical Field
The present invention relates to the field of semiconductor technologies, and in particular, to a self-aligned double patterning method, a semiconductor device, and an electronic device.
Background
In semiconductor device fabrication, double patterning, also known as double exposure or double exposure, is based on the principle of dividing data of the same pattern layer into two or two reticles for separate imaging.
With the development of integrated circuit manufacturing technology, the photolithography technology faces a great challenge, and the requirements on layout design are also more stringent. For example, to ensure the quality of pattern transfer, design rules tend to align the lines of the same layer of pattern in one direction. Nevertheless, when the pitch of the lines aligned in the same direction approaches 80nm, the limit of single exposure of 193nm immersion lithography has also been reached; if the pitch is less than 80nm, dual or multiple patterning techniques must be employed before more advanced lithographic machines can be used for mass production.
Currently, in the conventional self-aligned double patterning (self-Aligned Double Patterning, SADP) process, a reactive ion etching process is also required to etch back the deposited isolation layer (spacer) material, so that the steps of the double patterning process are complicated.
Disclosure of Invention
The invention aims to provide a self-aligned double patterning method, a semiconductor device and electronic equipment, so as to simplify the steps of the existing SADP process and reduce the process cost.
In order to achieve the above object, the present invention provides the following technical solutions:
In a first aspect, the present invention provides a self-aligned double patterning method, comprising:
a hard mask layer and an electron beam negative photoresist layer are sequentially formed on a substrate.
And exposing and developing the electron beam negative glue layer by using electron beams, and forming a plurality of sacrificial mandrels on the electron beam negative glue layer.
A photoresist layer is formed on the outer periphery of the plurality of sacrificial mandrels.
And carrying out gray scale photoetching treatment on the photoresist layer based on a preset mask plate, and forming a plurality of corresponding target sacrificial wall structures on the side wall of each sacrificial mandrel.
Etching the hard mask layer based on the plurality of target sacrificial wall structures to form a target pattern on the hard mask layer.
Compared with the prior art, in the self-aligned double patterning method provided by the invention, based on the characteristic that the electron beam negative photoresist can become similar to silicon oxide substances in an electron beam exposure area, the electron beam negative photoresist can be used for replacing CVD materials in the prior art as photoresist layers, so that a plurality of sacrificial mandrels are formed on the electron beam negative photoresist layers when electron beam lithography is used. After photoresist layers are formed on the peripheries of the sacrificial mandrels, the photoresist layers can be subjected to gray scale photoetching treatment through a preset mask plate, the photoresist layers on the top of each sacrificial mandrel and redundant photoresist layers between the side walls of every two sacrificial mandrels can be etched away, so that a plurality of corresponding target sacrificial wall structures are formed on the side walls of each sacrificial mandrel, and finally, the hard mask layer is subjected to etching treatment based on the formed target sacrificial wall structures, so that a target pattern can be formed on the hard mask layer. Based on the method, the purpose of forming the target sacrificial wall structure is achieved without back etching the photoresist layer by adopting a reactive ion etching process, so that the steps of the existing SADP process can be simplified to a certain extent, and the process cost is reduced. Meanwhile, the step of reactive ion etching is omitted, and the self-aligned double patterning method provided by the embodiment of the invention can be completed in photoetching, and the self-aligned double patterning efficiency can be improved.
In one possible implementation, the preset mask includes a first region with a first light transmittance and a second region with a second light transmittance, where the first light transmittance is less than the second light transmittance;
gray scale photoetching treatment is carried out on the photoresist layer based on a preset mask plate, a plurality of corresponding target sacrificial wall structures are formed on the side wall of each sacrificial mandrel, and the method comprises the following steps:
And carrying out gray scale photoetching treatment on the photoresist layer in the orthographic projection of the first area based on the first light transmittance, and simultaneously carrying out gray scale photoetching treatment on the photoresist layer in the orthographic projection of the second area based on the second light transmittance, so as to form a plurality of corresponding target sacrificial wall structures on the side wall of each sacrificial mandrel.
In one possible implementation, before performing the etching process on the hard mask layer based on the target sacrificial wall structure, the method further includes, before forming the target pattern on the hard mask layer: the sacrificial mandrel is removed.
In one possible implementation, forming a photoresist layer on the outer periphery of the plurality of sacrificial mandrels includes: photoresist coating is performed on the periphery of the sacrificial mandrels to form photoresist layers.
In one possible implementation, the first light transmittance is 50% and the second light transmittance is 100%.
In one possible implementation, the material of the electron beam negative glue layer comprises a hydrogen silsesquioxane polymer.
In one possible implementation, the thickness of the electron beam negative glue layer ranges from 80nm to 120nm.
In one possible implementation, the hard mask layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.
In a second aspect, the present invention further provides a semiconductor device comprising at least one patterned structure formed by the method of self-aligned double patterning described in the first aspect or any of the possible implementation manners of the first aspect.
Compared with the prior art, the beneficial effects of the semiconductor device provided by the invention are the same as those of the self-aligned double patterning method described in the technical scheme, and the description is omitted here.
In a third aspect, the present invention also provides an electronic apparatus including the semiconductor device according to the second aspect.
Compared with the prior art, the beneficial effects of the electronic equipment provided by the invention are the same as those of the self-aligned double patterning method described in the technical scheme, and the description is omitted here.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
FIGS. 1 (a) -1 (f) are process flow diagrams of self-aligned double patterning in the prior art;
FIG. 2 is a flow chart of a method for self-aligned double patterning according to an embodiment of the present invention;
FIG. 3 is a flow chart of another method for self-aligned double patterning according to an embodiment of the present invention;
Fig. 4 to 8 are process flow diagrams of self-aligned double patterning provided by the embodiment of the invention.
Reference numerals:
11-substrate, 12-existing hard mask layer,
13-Layer of sacrificial material, 14-bottom anti-reflective coating,
15-An existing photoresist layer, 16-a spacer material,
21-Substrate, 22-hard mask layer,
231-Sacrificial mandrel, 24-photoresist layer,
241-Target sacrificial wall structure, 25-preset mask,
251-First region, 252-second region.
Detailed Description
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
The self-aligned dual imaging technique (self-aligned Double Patterning, SADP) refers to the sequential use of non-lithographic process steps (thin film deposition, etching, etc.) to achieve spatial frequency doubling of the lithographic pattern after one lithographic completion.
Fig. 1 (a) to 1 (f) illustrate a conventional SADP process flow. As shown in fig. 1 (a), a layer 13 of sacrificial material (SACRIFICE LAYER), typically a chemical vapor deposition (Chemical Vapor Deposition, CVD) material, i.e., a deposited ceramic or polymer, is deposited over the existing hard mask layer 12 on the surface of the substrate 11, the sacrificial material layer 13 forming a bottom antireflective coating 14 and an existing photoresist layer 15. As shown in fig. 1 (b), the sacrificial material layer 13 is subjected to a photolithographic etching based on a mask formed of photoresist, a pattern on the mask is transferred onto the sacrificial material layer 13, and the pattern on the sacrificial material layer 13 is also called "sacrificial" or "core". As shown in fig. 1 (c), an atomic layer deposition technique (Atomic Layer Deposition, ALD) is used to deposit a thin film (referred to as "spacer 16") of relatively uniform thickness on the surface and sides of the "mangrel". As shown in fig. 1 (d), the deposited isolation material 16 is etched away using a reactive ion etching process, a step known as "etch back". Due to the geometrical effect of the "mandril" sidewall, material deposited on both sides of the pattern may remain, forming a so-called "spacer". As shown in fig. 1 (e), the "mandril" is removed using a highly selective etchant, leaving only the "space" on the surface of the substrate 11. Since the period of the "spacer" pattern is half that of the lithographic pattern, a multiplication of the spatial pattern density is achieved. Finally, as shown in FIG. 1 (f), plasma etching is used to transfer the "spacer" pattern onto the existing hard mask layer 12 in the substrate 11.
In the existing SADP process, a reactive ion etching process is also required to etch back the deposited isolation layer (Spacer) material, which results in complicated steps of the dual patterning process.
In view of this, as shown in fig. 2, an embodiment of the present invention provides a self-aligned double patterning method, which includes:
step 101: a hard mask layer 22 and an electron beam negative resist layer are sequentially formed on the substrate 21.
In the present application, the specific structure of the substrate 21 may be set according to the actual application scenario, and is not particularly limited herein. Specifically, the base 21 may be a silicon substrate, an indium phosphide (InP) substrate, a gallium arsenide (GaAs) substrate, a germanium silicon substrate, a germanium substrate, a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or the like, on which any result is not formed, or may be a base 21 on which some structure is formed. For example, the base 21 may be a common silicon substrate.
After the formation of the substrate 21, a hard mask layer 22 is formed on the surface of the substrate 21. The hard mask layer 22 is made of any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, and titanium nitride. For example, the hard mask layer 22 may be silicon oxide.
After the hard mask layer 22 is formed, an electron beam negative photoresist layer is formed on the surface of the hard mask layer 22 by spin coating. The material of the electron beam negative glue layer includes hydrogen silsesquioxane polymer (Hydrogen Silsesquioxane Polymers, HSQ), the thickness of the electron beam negative glue layer ranges from 80nm to 120nm, and the thickness of the electron beam negative glue layer can be 80nm, 82nm, 85nm, 90nm, 100nm or 120nm by way of example, and the embodiment of the invention is not limited in particular. It will be appreciated that when the thickness of the e-beam negative resist layer is less than 80nm, the use of a very thin e-beam negative resist layer may result in a problem that the e-beam negative resist layer cannot be used as a barrier layer for pattern transfer, and cannot transfer the formed pattern to the hard mask layer 22. Meanwhile, when the electron beam negative adhesive layer is thicker, the etching difficulty is also increased, so that the electron beam negative adhesive layer with proper thickness is selected, the etching difficulty in the subsequent exposure and development treatment process can be reduced, and the electron beam negative adhesive layer can be used as a barrier layer for pattern transfer.
Step 102: the electron beam negative photoresist layer is subjected to exposure development treatment by an electron beam, and a plurality of sacrificial mandrels 231 are formed on the electron beam negative photoresist layer.
It should be appreciated that when using HSQ negative photoresist as the material for the electron beam negative photoresist layer, the regions exposed by the electron beam may form a silicon oxide-like substance based on the properties of the HSQ negative photoresist, thereby forming a sacrificial plurality of sacrificial mandrels 231. In practice, the dimensions of each sacrificial mandrel 231 may be the same or different, and may be set according to the pattern to be etched, which is not particularly limited in the embodiment of the present invention.
Step 103: a photoresist layer 24 is formed on the outer circumference of the plurality of sacrificial mandrels 231.
In the present application, a photoresist coating may be performed at the outer circumference of each sacrificial mandrel 231, thereby forming a photoresist layer 24 on the hard mask layer 22.
Step 104: gray scale lithography processing is performed on the photoresist layer 24 based on the preset mask 25, and a plurality of corresponding target sacrificial wall structures 241 are formed on the side wall of each sacrificial mandrel 231.
In the present application, the preset reticle 25 includes a first region 251 having a first light transmittance and a second region 252 having a second light transmittance, and the first light transmittance is less than the second light transmittance, and exemplary, the first light transmittance may be 50% and the second light transmittance may be 100%. Because the light transmittance of different areas is different, when the photoresist layer 24 is subjected to gray scale photoetching treatment based on a preset mask plate, the photoetching etching speed of the photoresist layer 24 is also different, and based on the difference, the photoresist layer 24 can be etched into a required pattern by setting the light transmittance of different areas, so that a plurality of corresponding target sacrificial wall structures 241 are formed on the side wall of each sacrificial mandrel 231, the step of back etching the deposited isolation layer (Spacer) material by using a reactive ion etching process in the prior art is avoided, and the step of the existing SADP process is further simplified.
Step 105: the hard mask layer 22 is subjected to an etching process based on the plurality of target sacrificial wall structures 241, and a target pattern is formed on the hard mask layer 22.
In the present application, a target pattern can be formed on the hard mask layer 22 by performing an etching process on the hard mask layer 22 based on the plurality of formed target sacrificial wall structures 241. It will be appreciated that since there are two sidewalls for each sacrificial mandrel 231, the number of target sacrificial wall structures 241 formed should also be twice the number of sacrificial mandrels 231, and that when the hard mask layer 22 is etched based on the target sacrificial wall structures 241, the target pattern formed is equivalent to a multiplication of the spatial pattern density as compared to the sacrificial mandrels 231.
In summary, in the self-aligned double patterning method according to the embodiment of the present invention, based on the characteristic that the electron beam negative photoresist becomes similar to a silicon oxide material in the electron beam exposure region, the electron beam negative photoresist can be used to replace the CVD material in the prior art as the photoresist layer 24, so that a plurality of sacrificial mandrels 231 are formed on the electron beam negative photoresist layer when using electron beam lithography. After the photoresist layers 24 are formed on the peripheries of the sacrificial mandrels 231, the photoresist layers 24 on the top of each sacrificial mandrel 231 and the redundant photoresist layers 24 between the sidewalls of each sacrificial mandrel 231 can be etched through the pre-set mask 25 to form a plurality of corresponding target sacrificial wall structures 241 on the sidewalls of each sacrificial mandrel 231, and finally, the hard mask layer 22 is etched based on the plurality of formed target sacrificial wall structures 241 to form a target pattern on the hard mask layer 22. Based on this, since the embodiment of the present invention does not need to etch back the photoresist layer 24 by using a reactive ion etching process, the purpose of forming the target sacrificial wall structure 241 is achieved, and the steps of the existing SADP process can be simplified to a certain extent, and the process cost can be reduced. Meanwhile, the step of reactive ion etching is omitted, and the self-aligned double patterning method provided by the embodiment of the invention can be completed in photoetching, and the self-aligned double patterning efficiency can be improved.
Fig. 3 illustrates another self-aligned double patterning method, comprising:
Step 201: a hard mask layer 22 and an electron beam negative resist layer are sequentially formed on the substrate 21.
The specific structure of the substrate 21 may be referred to as above, and will not be described herein. The hard mask layer 22 is made of any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, and titanium nitride. For example, the hard mask layer 22 may be silicon oxide.
After the hard mask layer 22 is formed, an electron beam negative photoresist layer is formed on the surface of the hard mask layer 22 by spin coating. The material of the electron beam negative glue layer includes HSQ, and the thickness of the electron beam negative glue layer ranges from 80nm to 120nm, and exemplary, the thickness of the electron beam negative glue layer may be 80nm, 82nm, 85nm, 90nm, 100nm or 120nm, which is not particularly limited in the embodiment of the present invention. It will be appreciated that when the thickness of the e-beam negative resist layer is less than 80nm, the use of a very thin e-beam negative resist layer may result in a problem that the e-beam negative resist layer cannot be used as a barrier layer for pattern transfer, and cannot transfer the formed pattern to the hard mask layer 22. Meanwhile, when the electron beam negative adhesive layer is thicker, the etching difficulty is also increased, so that the electron beam negative adhesive layer with proper thickness is selected, the etching difficulty in the subsequent exposure and development treatment process can be reduced, and the electron beam negative adhesive layer can be used as a barrier layer for pattern transfer.
Step 202: as shown in fig. 4, the electron beam negative photoresist layer is subjected to exposure development treatment by an electron beam, and a plurality of sacrificial mandrels 231 are formed on the electron beam negative photoresist layer.
It should be appreciated that when using HSQ negative photoresist as the material for the electron beam negative photoresist layer, the regions exposed by the electron beam may form a silicon oxide-like substance based on the properties of the HSQ negative photoresist, thereby forming a sacrificial plurality of sacrificial mandrels 231. In practice, the dimensions of each sacrificial mandrel 231 may be the same or different, and may be set according to the pattern to be etched, which is not particularly limited in the embodiment of the present invention.
Step 203: as shown in fig. 5, photoresist coating is performed on the outer periphery of the plurality of sacrificial mandrels 231 to form a photoresist layer 24.
In the present application, a common photoresist may be used as the photoresist layer 24, and the photoresist layer 24 is formed on the periphery of each sacrificial mandrel 231 by spin coating, so that film growth is not required, all the process steps of self-aligned double patterning may be completed inside the photolithography, and the efficiency of self-aligned double patterning may be improved to some extent.
Step 204: as shown in fig. 6, the photoresist layer 24 in the orthographic projection of the first region 251 is subjected to gray scale lithography based on the first light transmittance, and the photoresist layer 24 in the orthographic projection of the second region 252 is subjected to gray scale lithography based on the second light transmittance, so that a plurality of corresponding target sacrificial wall structures 241 are formed on the side wall of each sacrificial mandrel 231.
In the present application, the preset reticle 25 includes a first region 251 having a first light transmittance and a second region 252 having a second light transmittance, and the first light transmittance is less than the second light transmittance, and the first light transmittance is, for example, 50% and the second light transmittance is 100%. Based on this, the etching speed and the etching degree of the photoresist layer 24 in the front projection of the first region 251 are much smaller than those of the photoresist layer 24 in the front projection of the second region 252, so that only part of the material of the photoresist layer 24 in the front projection of the first region 251 is etched away, and the photoresist layer 24 in the front projection of the second region 252 is completely etched away, thereby etching the photoresist layer 24 into a required pattern to form a plurality of corresponding target sacrificial wall structures 241 on the side wall of each sacrificial mandrel 231, eliminating the step of back etching the deposited isolation layer (Spacer) material by using the reactive ion etching process in the prior art, and further simplifying the step of the conventional SADP process.
Step 205: as shown in fig. 7, the sacrificial mandrel 231 is removed.
In this embodiment, the sacrificial mandrel 231 may be etched away by using a selective etching solution, or the sacrificial mandrel 231 may be removed by other methods, which is not limited in the embodiment of the present invention.
Step 206: as shown in fig. 8, the hard mask layer 22 is subjected to an etching process based on a plurality of target sacrificial wall structures 241, and a target pattern is formed on the hard mask layer 22.
In the present application, a target pattern can be formed on the hard mask layer 22 by performing an etching process on the hard mask layer 22 based on the plurality of formed target sacrificial wall structures 241. It will be appreciated that since there are two sidewalls for each sacrificial mandrel 231, the number of target sacrificial wall structures 241 formed should also be twice the number of sacrificial mandrels 231, and that when the hard mask layer 22 is etched based on the target sacrificial wall structures 241, the target pattern formed is equivalent to a multiplication of the spatial pattern density as compared to the sacrificial mandrels 231.
The embodiment of the invention also provides a semiconductor device, which comprises at least one patterned structure, wherein the patterned structure is manufactured and formed by adopting the self-aligned double patterning method provided by the embodiment.
Compared with the prior art, the semiconductor device provided by the embodiment of the invention has the same beneficial effects as the self-aligned double patterning method described in the above embodiment, and is not described here.
The embodiment of the invention also provides electronic equipment, which comprises the semiconductor device in the embodiment.
Compared with the prior art, the electronic device provided by the embodiment of the invention has the same beneficial effects as the self-aligned double patterning method in the above embodiment, and is not repeated here.
In the above description, technical details of patterning, etching, and the like of each layer are not described in detail. Those skilled in the art will appreciate that layers, regions, etc. of the desired shape may be formed by a variety of techniques. In addition, to form the same structure, those skilled in the art can also devise methods that are not exactly the same as those described above. In addition, although the embodiments are described above separately, this does not mean that the measures in the embodiments cannot be used advantageously in combination.
The embodiments of the present disclosure are described above. These examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be made by those skilled in the art without departing from the scope of the disclosure, and such alternatives and modifications are intended to fall within the scope of the disclosure.
Claims (10)
1. A method of self-aligned double patterning, comprising:
Sequentially forming a hard mask layer and an electron beam negative glue layer on a substrate;
Exposing and developing the electron beam negative glue layer through electron beams, and forming a plurality of sacrificial mandrels on the electron beam negative glue layer;
forming photoresist layers on the peripheries of the sacrificial mandrels;
Gray scale photoetching treatment is carried out on the photoresist layer based on a preset mask plate, and a plurality of corresponding target sacrificial wall structures are formed on the side wall of each sacrificial mandrel;
And etching the hard mask layer based on the target sacrificial wall structures to form a target pattern on the hard mask layer.
2. The method of claim 1, wherein the pre-set reticle includes a first region having a first light transmittance and a second region having a second light transmittance, the first light transmittance being less than the second light transmittance;
gray scale photoetching treatment is carried out on the photoresist layer based on a preset mask plate, a plurality of corresponding target sacrificial wall structures are formed on the side wall of each sacrificial mandrel, and the method comprises the following steps:
And carrying out gray scale photoetching treatment on the photoresist layer in the orthographic projection of the first area based on the first light transmittance, and simultaneously carrying out gray scale photoetching treatment on the photoresist layer in the orthographic projection of the second area based on the second light transmittance, so as to form a plurality of corresponding target sacrificial wall structures on the side wall of each sacrificial mandrel.
3. The method of claim 1, wherein prior to the etching the hard mask layer based on the target sacrificial wall structure, the method further comprises:
The sacrificial mandrel is removed.
4. The method of self-aligned double patterning of claim 1, wherein forming a photoresist layer on the outer periphery of a plurality of the sacrificial mandrels comprises:
And photoresist coating is carried out on the peripheries of the sacrificial mandrels, so that the photoresist layers are formed.
5. The method of self-aligned double patterning of claim 2, wherein the first light transmittance is 50% and the second light transmittance is 100%.
6. The method of claim 1, wherein the material of the e-beam negative photoresist layer comprises a hydrogen silsesquioxane polymer.
7. The method of claim 1, wherein the thickness of the electron beam negative photoresist layer is in the range of 80nm to 120nm.
8. The method of claim 1, wherein the hard mask layer comprises any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.
9. A semiconductor device comprising at least one patterned structure formed by the self-aligned double patterning method of any one of claims 1 to 8.
10. An electronic device comprising the semiconductor device according to claim 9.
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