WO2023020100A1 - 芯片测试系统 - Google Patents

芯片测试系统 Download PDF

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Publication number
WO2023020100A1
WO2023020100A1 PCT/CN2022/099455 CN2022099455W WO2023020100A1 WO 2023020100 A1 WO2023020100 A1 WO 2023020100A1 CN 2022099455 W CN2022099455 W CN 2022099455W WO 2023020100 A1 WO2023020100 A1 WO 2023020100A1
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Prior art keywords
test
fixture
interface
chip
interfaces
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PCT/CN2022/099455
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English (en)
French (fr)
Inventor
朱魏
龙华
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深圳飞骧科技股份有限公司
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Publication of WO2023020100A1 publication Critical patent/WO2023020100A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/52—Testing for short-circuits, leakage current or ground faults
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/50—Testing of electric apparatus, lines, cables or components for short-circuits, continuity, leakage current or incorrect line connections
    • G01R31/54—Testing for continuity

Definitions

  • the present application relates to the technical field of radio frequency circuit debugging, in particular to a chip testing system.
  • wireless communication technology As human beings enter the information age, wireless communication technology has developed rapidly. Mobile phones, wireless local area networks, Bluetooth, etc. have become an indispensable part of social life and development. The progress of wireless communication technology is inseparable from the development of radio frequency circuit and microwave technology.
  • a very important link in RF chip debugging is to use load pull to determine the load impedance of the chip. Impedance matching is performed according to the obtained load impedance to achieve the best performance of the radio frequency chip.
  • connection interface of the load pulling system is a standard type interface such as SMA or BNC.
  • the pins of the chip are usually not general-purpose interfaces such as SMA or BNC. Therefore, when testing the load impedance performance of the chip under test, an auxiliary fixture is needed to connect the chip under test to the load pulling system.
  • the S-parameters measured by the vector analyzer that collects the chip parameters are the overall S-parameters including the fixture, not the S-parameters of the chip.
  • To obtain the parameters of the chip that is, the de-embedding file
  • usually at least three fixtures are required to test separately, and then perform corresponding calculations.
  • this application intends to provide a chip test system, and the corresponding parameters can be obtained through the measurement of the three channels of the fixture file, and then through the operation and transmission of the single-chip microcomputer, the test parameters of the chip (that is, the de-embedding file) can be obtained, and then the actual load of the chip can be directly obtained by loading the de-embedding file into the input and output terminals of the load pulling system impedance.
  • the chip test system provided by this application includes:
  • a first biaser one end of which is connected to the signal source
  • a source tuner the input end of which is connected to the other end of the first bias device
  • a chip test fixture including three measurement paths, the input terminals of which are connected to the output terminals of the source tuner;
  • a load tuner the input end of which is connected to the output end of the chip test fixture
  • a second biaser one end of which is connected to the output end of the load tuner
  • a regulated DC power supply respectively connected to the power supply interfaces of the first biaser and the second biaser;
  • a spectrum analyzer is connected to the coupling end of the coupler.
  • the chip test fixture includes:
  • a group of test input interfaces arranged on the EVB board, constitute the input end of the female fixture
  • a group of test output interfaces arranged on the EVB board, set opposite to a group of test input interfaces, constitute the output end of the female fixture;
  • the sub-fixture is fixed in the groove of the mother fixture by bolts, and includes a set of sub-fixture test interfaces correspondingly connected with a set of test input interfaces and a set of test output interfaces of the mother fixture.
  • the sub-clamps include: single-chip micro-clamps or chip sub-clamps.
  • the set of test input interfaces includes,
  • the set of test output interfaces includes,
  • the second test interface is set opposite to the first test interface
  • the fourth test interface is set opposite to the third test interface
  • the sixth test interface is set opposite to the fifth test interface.
  • the set of test input interfaces or the set of test output interfaces includes: SMA interfaces.
  • the EVB board includes: Rogers board.
  • the female clamp also includes:
  • VCC voltage interface and GND ground interface are VCC voltage interface and GND ground interface.
  • the female fixture further includes: a data transmission interface.
  • the data transmission interface includes: a USB interface.
  • the chip testing system further includes:
  • the test software acquires test data through the data transmission interface.
  • the chip test system provided by this application only needs one chip test fixture to obtain the de-embedding file, which is more convenient than the traditional method of using three fixtures to perform parameter tests of straight-through, open circuit and short circuit.
  • the de-embedding file can be imported into the load pulling system software to get the real load impedance at both ends of the chip, which can be applied to most RF chips, and the de-embedding file can be reused only once, and the real load can also be obtained after replacing the chip impedance.
  • Fig. 1 shows a schematic diagram of the composition of a chip testing system according to an exemplary embodiment of the present application
  • Fig. 2 shows a schematic diagram of parameter acquisition of a chip testing system according to an exemplary embodiment of the present application
  • Fig. 3 shows a schematic structural diagram of a female fixture according to an exemplary embodiment of the present application
  • Fig. 4 shows a schematic structural diagram of a sub-clamp according to a first exemplary embodiment of the present application
  • Fig. 5 shows a schematic structural diagram of a sub-clamp according to a second exemplary embodiment of the present application
  • Fig. 6 shows a schematic diagram of the combined connection of the female and child clamps according to an exemplary embodiment of the present application
  • Fig. 7 shows a schematic diagram of connection of a chip test fixture according to the first exemplary embodiment of the present application
  • FIG. 8 shows a schematic diagram of connection of a chip test fixture according to a second exemplary embodiment of the present application.
  • FIG. 1 shows a schematic diagram of the composition of a chip testing system according to an exemplary embodiment of the present application.
  • the chip test system 3000 provided by the present application includes: a signal source 3100, a first bias device 3200, a source tuner 3300, a chip test fixture 2000, a load tuner 3400, a second bias device 3500, a coupling Device 3600, Power Meter 3700, Power Supply 3800, Spectrum Analyzer 3900.
  • the signal source 3100 provides signals for the load pull test of the chip.
  • One end of the first biaser 3200 is connected to the signal source 3100 , and the other end is connected to the source tuner 3300 .
  • An input terminal of the source tuner 3300 is connected to the first biaser 3200 , and an output terminal thereof is connected to the chip test fixture 2000 .
  • the input terminal of the chip test fixture 2000 is connected to the output terminal of the source tuner 3300 .
  • the input terminal of the load tuner 3400 is connected to the output terminal of the chip test fixture 2000 .
  • One end of the second biaser 3500 is connected to the output end of the load tuner 3400 , and the other end is connected to the coupling end of the coupler 3600 .
  • the through output of the coupler 3600 is connected to a power meter 3700 .
  • the power supply 3800 is connected to the power supply interfaces of the first biaser 3200 and the second biaser 3500 respectively.
  • the coupled ends of the spectrum analyzer 3900 and the coupler 3600 are connected.
  • the chip test fixture 2000 includes a mother fixture and a daughter fixture from which de-embedding files can be obtained. For example, the combination of the mother fixture and the single-chip microcomputer fixture can obtain the S parameters of de-embedding. Combining the mother fixture with the chip sub-fixture, the S-parameters of the chip without de-embedding can be obtained.
  • the chip test fixture 2000 includes three measurement paths, and the S parameters under straight-through, open-circuit and short-circuit conditions can be respectively obtained without changing the fixture.
  • Fig. 2 shows a schematic diagram of parameter acquisition of a chip testing system according to an exemplary embodiment of the present application.
  • the S-parameter tester 4000 is respectively connected to the input end of the source tuner 3300 and the output end of the load tuner 3400 .
  • Fig. 3 shows a schematic structural diagram of a female clamp according to an exemplary embodiment of the present application.
  • the female fixture 1000 provided by the present application includes an EVB board 100 , a set of test interfaces 200 , a set of power supply interfaces 300 and a data transmission interface 400 .
  • the EVB board 100 can be a rectangular Rogers board with a groove 110 in the center for placing a test sub-fixture, such as a single-chip microcomputer sub-fixture or a chip sub-fixture.
  • a set of test interfaces 200 is disposed on the EVB board 100 .
  • a group of test interfaces includes 6 test interfaces, which are respectively a first test interface 211, a second test interface 221, a third test interface 212, a fourth test interface 222, The fifth test interface 213 and the sixth test interface 223 .
  • the first test interface 211 , the third test interface 212 and the third test interface 213 are disposed on one side of the EVB board 100 .
  • the second test interface 221 , the fourth test interface 222 and the sixth test interface 223 are disposed on the other side of the EVB board 100 .
  • the second test interface 221 is opposite to the first test interface 211 .
  • the fourth test interface 222 is opposite to the third test interface 212 .
  • the sixth test interface 223 is opposite to the fifth test interface 213 .
  • a shrapnel (not shown in the figure) may be provided at each test interface for connecting the interface of the sub-fixture.
  • the set of test interfaces 200 may be SMA interfaces.
  • a set of power interfaces 300 includes a VCC voltage interface 310 and a GND ground interface 320, which are arranged on one side of the EVB board 100, and are used to supply power to the single-chip microcomputer or chip during testing.
  • the set of power interfaces 300 may be in the form of pin headers.
  • the data transmission interface 400 is set on one side of the EVB board 100 , after the parameter test is completed, the test result can be directly transmitted to the software of the test system through the data transmission interface 400 .
  • the data transmission interface may be a USB interface.
  • the sub-fixture can be a microcontroller sub-fixture or a chip sub-fixture.
  • Fig. 4 shows a schematic structural diagram of a sub-clamp according to the first exemplary embodiment of the present application.
  • the single-chip sub-clamp 500 includes a first group of interfaces: interface 511, interface 512 and interface 513, and a second group of interfaces: interface 521, interface 522 and interface 523, two groups
  • the interfaces form three test paths, which are respectively connected to the three sets of test interfaces of the female fixture, for example, connected together through the shrapnel at the interface of the female fixture.
  • the interface 511 and the interface 521 are connected to the straight-through port on the back of the microcontroller.
  • the interface 512 and the interface 522 are respectively connected to the open-circuit end of the single-chip microcomputer.
  • the interface 513 and the interface 523 are respectively connected to the grounding port inside the single-chip microcomputer.
  • the MCU sub-fixture 500 also includes a power interface 531 , a ground interface 532 and a data transmission interface 540 .
  • Fig. 5 shows a schematic structural diagram of a sub-clamp according to a second exemplary embodiment of the present application.
  • the chip sub-clamp 600 is substantially the same size as the microcontroller sub-clamp, including an interface 610 , an interface 620 , a power interface 631 , a ground interface 632 and a data transmission interface 640 .
  • the interface 610 is connected to the input terminal 710 of the chip under test 700
  • the interface 620 is connected to the output terminal 720 of the chip under test 700 .
  • the power interface 631 is connected to the power supply
  • the ground interface 632 is connected to the ground
  • the data transmission interface 640 is used to transmit test data
  • the other interfaces are left open.
  • Fig. 6 shows a schematic diagram of the combined connection of the female and child clamps according to an exemplary embodiment of the present application.
  • the sub-fixture and the mother fixture can be connected by means of metal spring sheets and metal contacts.
  • each test port of the mother fixture 1000 is provided with a metal spring piece in the middle groove area, for example, the test interface 213 is correspondingly provided with a metal spring piece 2131 .
  • Fig. 7 shows a schematic diagram of connection of a chip test fixture according to the first exemplary embodiment of the present application.
  • a set of interfaces 511 , 512 , and 513 of the single chip microcomputer sub-fixture 500 are respectively connected to the first test interface 211 , the third test interface 212 , and the third test interface 213 of the mother fixture.
  • a set of interfaces 521 , 522 , and 523 of the single chip microcomputer sub-fixture 500 are respectively connected to the second test interface 221 , the fourth test interface 222 , and the sixth test interface 223 of the mother fixture.
  • the power interface 531 and the ground interface 532 of the single chip microcomputer sub-fixture 500 are respectively connected to the VCC voltage interface 310 and the GND ground interface 320 of the mother fixture.
  • the data transmission interface 540 of the single chip microcomputer sub-fixture 500 is connected with the data transmission interface 400 of the mother fixture.
  • the interface 511 and the interface 521 of the single-chip microcomputer sub-clamp 500 are connected to the through port on the back of the single-chip microcomputer.
  • the interface 512 and the interface 522 of the single-chip sub-fixture 500 are respectively connected to the open-circuit end of the single-chip microcomputer.
  • the interface 513 and the interface 523 of the single-chip microcomputer sub-fixture 500 are respectively connected to the ground port inside the single-chip microcomputer.
  • the path connected by the first test interface 211 of the mother fixture, the interface 511 of the single-chip microcomputer sub-fixture 500 , the interface 521 of the single-chip microcomputer sub-fixture 500 and the third test interface 221 of the mother fixture is a straight path.
  • the path connected by the second test interface 212 of the mother fixture, the interface 512 of the single-chip microcomputer sub-fixture 500 , the interface 522 of the single-chip microcomputer sub-fixture 500 and the fourth test interface 222 of the mother fixture is an open circuit.
  • the path connecting the third test interface 213 of the mother fixture, the interface 513 of the single-chip microcomputer sub-fixture 500 , the interface 523 of the single-chip microcomputer sub-fixture 500 and the sixth test interface 223 of the mother fixture is a short circuit.
  • the obtained S parameter is straight-through.
  • the obtained S parameter is an open circuit.
  • the obtained S parameter is a short circuit.
  • the single-chip microcomputer When the S parameters of the three channels are tested respectively, the single-chip microcomputer will record three sets of S parameters.
  • the final de-embedded S-parameters are obtained after formula conversion with the de-embedding formula internally. According to some embodiments of the present application, the de-embedded S-parameters can be output through the data transmission port 400 .
  • FIG. 8 shows a schematic diagram of connection of a chip test fixture according to a second exemplary embodiment of the present application.
  • the single-chip microcomputer fixture can be taken out from the mother fixture, replaced with the chip sub-fixture 600, and the chip sub-fixture 600 is fixed in the center of the groove through the bolt hole on the mother fixture to form the first
  • the two-chip test fixture is shown in Figure 6.
  • the interface 610 of the chip sub-fixture 600 is connected to the second test interface 212 of the mother fixture 1000
  • the interface 620 of the chip sub-fixture 600 is connected to the fourth test interface 222 of the mother fixture, and the other test interfaces of the mother fixture are suspended.
  • the interface 610 is also connected to the input terminal of the chip to be tested
  • the interface 620 is also connected to the output terminal of the chip to be tested.
  • the power interface 631 and the ground interface 632 of the chip sub-fixture 600 are respectively connected to the VCC voltage interface 310 and the GND ground interface 320 of the mother fixture.
  • the data transmission interface 640 of the sub-chip fixture 600 is connected to the data transmission interface 400 of the mother fixture.
  • a set of chip S parameters without de-embedding can be obtained through the second chip test fixture. Similarly, the S-parameters of the chip without de-embedding can be output through the data transmission port 400 .
  • the S-parameters of de-embedding are obtained by combining the mother fixture with the single-chip microcomputer child fixture.
  • Chip S-parameters without de-embedding were obtained by combining the mother fixture with the chip daughter fixture. After calculating the de-embedded S-parameters and the chip S-parameters without de-embedding, a real chip S-parameter with only the input terminal to the output terminal of the chip can be obtained.
  • the chip test system provided by this application only needs one chip test fixture to obtain the de-embedding file, which is more convenient than the traditional method of using three fixtures to perform parameter tests of straight-through, open circuit and short circuit.
  • the de-embedding file can be imported into the load pulling system software to get the real load impedance at both ends of the chip, which can be applied to most RF chips, and the de-embedding file can be reused only once, and the real load can also be obtained after replacing the chip impedance.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

一种芯片测试系统（3000），包括：信号源（3100）；第一偏置器（3200），其一端与信号源（3100）相连；源调谐器（3300），其输入端与第一偏置器（3200）的另一端相连；芯片测试夹具（2000），包括三个测量通路，其输入端与源调谐器（3300）的输出端相连；负载调谐器（3400），其输入端与芯片测试夹具（2000）的输出端相连；第二偏置器（3500），其一端与负载调谐器（3400）的输出端相连；耦合器（3600），其耦合端与第二偏置器（3500）的另一端相连；功率计（3700），与耦合器（3600）的直通输出端相连；电源（3800），分别与第一偏置器（3200）、第二偏置器（3500）的供电接口相连；频谱仪（3900），与耦合器（3600）的耦合端相连。通过夹具的三个测量通路分别得到对应的参数文件，经过单片机运算可以得到芯片测试参数，载入到负载牵引系统中便可直接得到芯片实际负载阻抗。

Description

芯片测试系统 技术领域
本申请涉及射频电路调试技术领域，具体地涉及一种芯片测试系统。
背景技术
随着人类进入信息化时代，无线通信技术有了飞速发展。手机、无线局域网、蓝牙等已成为社会生活和发展不可或缺的一部分。无线通信技术的进步离不开射频电路和微波技术的发展。
目前射频芯片调试中一个非常重要的环节就是利用负载牵引来确定芯片的负载阻抗。根据得到的负载阻抗进行阻抗匹配来达到射频芯片的最佳性能。
通常，负载牵引系统的连接接口是SMA或者BNC等标准类型接口。而芯片的引脚通常不是SMA或者BNC等通用类型接口。因此，对被测芯片进行负载阻抗性能测试时，需要辅助夹具将被测芯片与负载牵引系统之间进行连接。这样，采集芯片参数的矢量分析仪所测得到的S参数是包含夹具的整体的S参数，并非芯片的S参数。若要得到芯片的参数(即去嵌文件)，通常需要至少三块夹具进行分别测试后，再进行相应的计算。
实用新型内容
为了在芯片的负载牵引测试过程胡总直接获得芯片的实际负载阻抗图，无需再进行去嵌，本申请拟提供一种芯片测试系统，通过夹具的三个通路的测量可以分别得到相对应的参数文件，再经过单片机的运算与传输后可以得到芯片的测试参数(即去嵌文件)，然后通过将去嵌文件载入到负载牵引系统中的输入端和输出端从而可以直接得到芯片的 实际负载阻抗。
本申请提供的芯片测试系统包括：
信号源；
第一偏置器，其一端与所述信号源相连；
源调谐器，其输入端与所述第一偏置器的另一端相连；
芯片测试夹具，包括三个测量通路，其输入端与所述源调谐器的输出端相连；
负载调谐器，其输入端与所述芯片测试夹具的输出端相连；
第二偏置器，其一端与所述负载调谐器的输出端相连；
耦合器，其耦合端与所述第二偏置其的另一端相连；
功率计，与所述耦合器的直通输出端相连；
稳压直流电源，分别与所述第一偏置器、所述第二偏置器的供电接口相连；
频谱仪，与所述耦合器的耦合端相连。
根据本申请的一些实施例，所述芯片测试夹具包括：
母夹具，包括，
EVB板，中央设置凹槽；
一组测试输入接口，设置于所述EVB板上，构成所述母夹具的输入端；
一组测试输出接口，设置于所述EVB板上，与一组测试输入接口相对设置，构成所述母夹具的输出端；
子夹具，通过螺栓固定在所述母夹具的凹槽中，包括一组子夹具测试接口与所述母夹具的一组测试输入接口和一组测试输出接口对应相连。
根据本申请的一些实施例，所述子夹具包括：单片机子夹具或芯片子夹具。
根据本申请的一些实施例，所述一组测试输入接口包括，
第一测试接口；
第三测试接口；
第五测试接口；
所述一组测试输出接口包括，
第二测试接口，与所述第一测试接口相对设置；
第四测试接口，与所述第三测试接口相对设置；
第六测试接口，与所述第五测试接口相对设置。
根据本申请的一些实施例，所述一组测试输入接口或所述一组测试输出接口包括：SMA接口。
根据本申请的一些实施例，所述EVB板包括：罗杰斯板材。
根据本申请的一些实施例，所述母夹具还包括：
VCC电压接口和GND接地接口。
根据本申请的一些实施例，所述母夹具还包括：数据传输接口。
根据本申请的一些实施例，所述数据传输接口包括：USB接口。
根据本申请的一些实施例，所述芯片测试系统，还包括：
测试软件，通过所述数据传输接口获取测试数据。
本申请提供的芯片测试系统，只需要一块芯片测试夹具即可获得去嵌文件，相比传统的分别用三块夹具来进行直通、开路、短路的参数测试而言，更便捷。去嵌文件导入到负载牵引系统软件中即可得到真实的芯片两端的负载阻抗，可以适用于大部分的射频芯片，只需一次去嵌可以重复使用去嵌文件，更换芯片后亦可得到真实负载阻抗。
本申请的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本申请的实践了解到。
附图说明
为了更清楚地说明本申请实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，还可以根据这些附图获得其他的附图，而并不超出本申请要求保护的范围。
图1示出根据本申请示例实施例的芯片测试系统组成示意图；
图2示出根据本申请示例实施例的芯片测试系统参数采集示意图；
图3示出根据本申请示例实施例的母夹具结构示意图；
图4示出根据本申请第一示例实施例的子夹具结构示意图；
图5示出根据本申请第二示例实施例的子夹具结构示意图；
图6示出根据本申请示例实施例的母子夹具组合连接示意图；
图7示出根据本申请第一示例实施例的芯片测试夹具连接示意图；
图8示出根据本申请第二示例实施例的芯片测试夹具连接示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
此外，所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施例中。在下面的描述中，提供许多具体细节从而给出对本申请的实施例的充分理解。然而，本领域技术人员将意识到，可以实践本申请的技术方案而没有特定细节中的一个或更多，或者可以采用其它的方法、组元、装置、步骤等。在其它情况下，不详细示出或描述公知方法、装置、实现或者操作以避免模糊本申请的各方面。
应理解，虽然本文中可能使用术语第一、第二等来描述各种组件，但这些组件不应受这些术语限制。这些术语乃用以区分一组件与另一组件。因此，下文论述的第一组件可称为第二组件而不偏离本申请概念的教示。如本文中所使用，术语“及/或”包括相关联的列出项目中的任一个及一或多者的所有组合。
本领域技术人员可以理解，附图只是示例实施例的示意图，可能不是按比例的。附图中的模块或流程并不一定是实施本申请所必须的，因此不能用于限制本申请的保护范围。
本发明人发现，在现有的射频芯片负载牵引性能测试中，若要获取芯片的去嵌文件，需要通过三块夹具分别进行测试获取三组参数，测试效率低且需要的夹具数量多、成本高。为此，本申请拟提供一种芯片测试系统，只需要一块芯片测试夹具即可获得三组参数从而获得去嵌文件，将去嵌文件传输到负载牵引系统中便可以直接得到芯片的实际负载阻抗图。
以下将结合附图对本申请的技术方案进行详细介绍。
图1示出根据本申请示例实施例的芯片测试系统组成示意图。
如图1所示，本申请提供的芯片测试系统3000包括：信号源3100、第一偏置器3200、源调谐器3300、芯片测试夹具2000、负载调谐器3400、第二偏置器3500、耦合器3600、功率计3700、电源3800、频谱仪3900。
其中，信号源3100为芯片的负载牵引测试提供信号。第一偏置器3200的一端与信号源3100相连，另一端与源调谐器3300相连。源调谐器3300的输入端与第一偏置器3200相连，其输出端与芯片测试夹具2000相连。芯片测试夹具2000输入端与源调谐器3300的输出端相连。负载调谐器3400的输入端与芯片测试夹具2000的输出端相连。第二偏置器3500的一端与负载调谐器3400的输出端相连，另一端与耦合器3600的耦合端相连。耦合器3600的直通输出端与功率计3700相连。 电源3800分别与第一偏置器3200、第二偏置器3500的供电接口相连。频谱仪3900耦合器3600的耦合端相连。
芯片测试夹具2000包括可获得去嵌文件的母夹具和子夹具。例如，母夹具与单片机子夹具组合，可获得去嵌的S参数。将母夹具与芯片子夹具组合，可获得没有去嵌的芯片S参数。芯片测试夹具2000包括三个测量通路，可在不更换夹具的情况下分别获得直通、开路、短路下的S参数。
图2示出根据本申请示例实施例的芯片测试系统参数采集示意图。
在进行射频芯片的参数采集时，如图2所示，S参数测试仪4000分别与源调谐器3300的输入端和负载调谐器3400的输出端相连。
图3示出根据本申请示例实施例的母夹具结构示意图。
如图3所示，本申请提供的母夹具1000包括EVB板100、一组测试接口200、一组电源接口300和数据传输接口400。
EVB板100可以是一块矩形的罗杰斯板材，其中央设置凹槽110，用于放置测试子夹具，例如单片机子夹具或者芯片子夹具。一组测试接口200设置于所述EVB板100上。根据本申请的示例实施例，如图1所示，一组测试接口包括6个测试接口，分别为第一测试接口211、第二测试接口221、第三测试接口212、第四测试接口222、第五测试接口213、第六测试接口223。第一测试接口211、第三测试接口212、第三测试接口213设置于EVB板100的一侧。第二测试接口221、第四测试接口222、第六测试接口223设置于EVB板100的另一侧。第二测试接口221与所述第一测试接口211相对设置。第四测试接口222与所述第三测试接口212相对设置。第六测试接口223与所述第五测试接口213相对设置。根据本申请的一些实施例，每个测试接口处可以设置弹片(图中未示)，用以连接子夹具的接口。根据本申请的一些实施例，所述一组测试接口200可以是SMA接口。
一组电源接口300包括VCC电压接口310和GND接地接口320，设置于所述EVB板100的一侧边上，用于在测试时为单片机或芯片供电。根据本申请的一些实施例，所述一组电源接口300的形式可以是排针。数据传输接口400设置于所述EVB板100的一个侧边上，参数测试完毕后，可以通过数据传输接口400直接将测试结果传输至测试系统的软件中。根据本申请的一些实施例，所述数据传输接口可以是USB接口。
在进行芯片测试时，本申请提供的母夹具与子夹具进行配合使用，最终获得芯片的去嵌文件。子夹具可以是单片机子夹具或者芯片子夹具。
图4示出根据本申请第一示例实施例的子夹具结构示意图。
根据本申请的示例实施例，如图4所示，单片机子夹具500包括第一组接口：接口511、接口512和接口513，以及第二组接口：接口521、接口522和接口523，两组接口组成三路测试通路，分别与母夹具的三组测试接口相连，例如通过母夹具的接口处的弹片连接在一起。接口511和接口521连接单片机背部的直通口。接口512和接口522分别连接单片机的开路端。接口513和接口523分别连接单片机内部的接地口。单片机子夹具500还包括电源接口531和接地接口532以及数据传输接口540。
图5示出根据本申请第二示例实施例的子夹具结构示意图。
根据本申请的示例实施例，如图5所示，芯片子夹具600与单片机子夹具的大小基本一致，包括接口610、接口620、电源接口631、接地接口632以及数据传输接口640。接口610连接待测芯片700的输入端710，接口620连接待测芯片700的输出端720。电源接口631连接电源，接地接口632连接地，数据传输接口640用于传输测试数据，其他接口悬空开路。芯片子夹具600与母夹具组合时，接口610、接口620分别与母夹具的一组测试接口相连。
图6示出根据本申请示例实施例的母子夹具组合连接示意图。
子夹具与母夹具可以通过金属弹簧片和金属触点的方式连接。如图6所示，以单片机子夹具500与母夹具1000的组合连接为例，母夹具1000的各个测试口在中间凹槽区域均设置金属弹簧片，例如测试接口213对应设置金属弹簧片2131。单片机子夹具500的背面均有连接用的金属触点，例如图中的5131。当单片子夹具向下按压时，金属触点5131和金属弹簧片2131就会接触在一起。每一个接口处的金属触点和弹簧片接触后，再通过螺丝固定四角后即可达到无焊接连接。
图7示出根据本申请第一示例实施例的芯片测试夹具连接示意图。
在进行芯片性能测试时，首先将单片机子夹具500通过母夹具上的螺栓孔固定在凹槽的中央，形成第一芯片测试夹具，如图7所示。单片机子夹具500的一组接口511、512、513分别与母夹具的第一测试接口211、第三测试接口212、第三测试接口213相连。单片机子夹具500的一组接口521、522、523分别与母夹具的第二测试接口221、第四测试接口222、第六测试接口223相连。单片机子夹具500的电源接口531和接地接口532分别与母夹具的VCC电压接口310和GND接地接口320相连。单片机子夹具500的数据传输接口540与母夹具的数据传输接口400相连。
此外，单片机子夹具500的接口511和接口521连接单片机背部的直通口。单片机子夹具500的接口512和接口522分别连接单片机的开路端。单片机子夹具500的接口513和接口523分别连接单片机内部的接地口。
母夹具的第一测试接口211、单片机子夹具500的接口511、单片机子夹具500的接口521和母夹具的第三测试接口221连接成的通路为直通路。母夹具的第二测试接口212、单片机子夹具500的接口512、单片机子夹具500的接口522和母夹具的第四测试接口222连接成的通路为开路。母夹具的第三测试接口213、单片机子夹具500的接口513、 单片机子夹具500的接口523和母夹具的第六测试接口223连接成的通路为短路。
当芯片测试仪的测试接口连接母夹具的第一测试接口211和第三测试接口221时，获得的S参数为直通。当芯片测试仪的测试接口连接母夹具的第二测试接口212和第四测试接口222时，获得的S参数为开路。当芯片测试仪的测试接口连接母夹具的第三测试接口213和第六测试接口223时，获得的S参数为短路。
当三路的S参数分别测试完后，单片机将记录下三组S参数。在内部用去嵌公式经过公式换算后得到最终的去嵌S参数。根据本申请的一些实施例，可以通过数据传输口400将去嵌S参数输出。
图8示出根据本申请第二示例实施例的芯片测试夹具连接示意图。
通过单片机子夹具获得去嵌S参数后，可以将单片机子夹具从母夹具中取出，更换为芯片子夹具600，将芯片子夹具600通过母夹具上的螺栓孔固定在凹槽的中央，形成第二芯片测试夹具，如图6所示。芯片子夹具600的接口610与母夹具1000的第二测试接口212相连，芯片子夹具600的接口620与母夹具的第四测试接口222相连，母夹具的其他测试接口悬空。接口610还连接待测芯片的输入端，接口620还连接待测芯片的输出端。芯片子夹具600的电源接口631和接地接口632分别母夹具的VCC电压接口310和GND接地接口320相连。芯片子夹具600的数据传输接口640与母夹具的数据传输接口400相连。
通过第二芯片测试夹具可以得到一组没有去嵌的芯片S参数。类似地，可以通过数据传输口400将没有去嵌的芯片S参数输出。
由此，通过将母夹具与单片机子夹具组合，获得了去嵌的S参数。通过将母夹具与芯片子夹具组合，获得了没有去嵌的芯片S参数。将去嵌的S参数和没有去嵌的芯片S参数进行运算后可以便可以得到个只有芯片输入端到输出端的真实的芯片S参数。
本申请提供的芯片测试系统，只需要一块芯片测试夹具即可获得去嵌文件，相比传统的分别用三块夹具来进行直通、开路、短路的参数测试而言，更便捷。去嵌文件导入到负载牵引系统软件中即可得到真实的芯片两端的负载阻抗，可以适用于大部分的射频芯片，只需一次去嵌可以重复使用去嵌文件，更换芯片后亦可得到真实负载阻抗。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明仅用于帮助理解本申请的方法及其核心思想。同时，本领域技术人员依据本申请的思想，基于本申请的具体实施方式及应用范围上做出的改变或变形之处，都属于本申请保护的范围。综上所述，本说明书内容不应理解为对本申请的限制。

Claims (10)

  1. 一种芯片测试系统，其特征在于，包括：
    信号源；
    第一偏置器，其一端与所述信号源相连；
    源调谐器，其输入端与所述第一偏置器的另一端相连；
    芯片测试夹具，包括三个测量通路，其输入端与所述源调谐器的输出端相连；
    负载调谐器，其输入端与所述芯片测试夹具的输出端相连；
    第二偏置器，其一端与所述负载调谐器的输出端相连；
    耦合器，其耦合端与所述第二偏置其的另一端相连；
    功率计，与所述耦合器的直通输出端相连；
    电源，分别与所述第一偏置器、所述第二偏置器的供电接口相连；
    频谱仪，与所述耦合器的耦合端相连。
  2. 根据权利要求1所述的芯片测试系统，其特征在于，所述芯片测试夹具包括：
    母夹具，包括，
    EVB板，中央设置凹槽；
    一组测试输入接口，设置于所述EVB板上，构成所述母夹具的输入端；
    一组测试输出接口，设置于所述EVB板上，与一组测试输入接口相对设置，构成所述母夹具的输出端；
    子夹具，通过螺栓固定在所述母夹具的凹槽中，包括一组子夹具测试接口与所述母夹具的一组测试输入接口和一组测试输出接口对应相连。
  3. 根据权利要求2所述的芯片测试系统，其特征在于，所述子夹具包括：
    单片机子夹具或芯片子夹具。
  4. 根据权利要求2所述的芯片测试系统，其特征在于，
    所述一组测试输入接口包括，
    第一测试接口；
    第三测试接口；
    第五测试接口；
    所述一组测试输出接口包括，
    第二测试接口，与所述第一测试接口相对设置；
    第四测试接口，与所述第三测试接口相对设置；
    第六测试接口，与所述第五测试接口相对设置。
  5. 根据权利要求2所述的芯片测试系统，其特征在于，所述一组测试输入接口或所述一组测试输出接口包括：SMA接口。
  6. 根据权利要求2所述的芯片测试系统，其特征在于，所述EVB板包括：罗杰斯板材。
  7. 根据权利要求2所述的芯片测试系统，其特征在于，所述母夹具还包括：
    VCC电压接口和GND接地接口。
  8. 根据权利要求2所述的芯片测试系统，其特征在于，所述母夹具还包括：数据传输接口。
  9. 根据权利要求8所述的芯片测试系统，其特征在于，所述数据传输接口包括：USB接口。
  10. 根据权利要求8所述的芯片测试系统，其特征在于，还包括：
    测试软件，通过所述数据传输接口获取测试数据。
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