WO2023019753A1 - I2c总线的通信控制方法、系统和装置 - Google Patents

I2c总线的通信控制方法、系统和装置 Download PDF

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Publication number
WO2023019753A1
WO2023019753A1 PCT/CN2021/128509 CN2021128509W WO2023019753A1 WO 2023019753 A1 WO2023019753 A1 WO 2023019753A1 CN 2021128509 W CN2021128509 W CN 2021128509W WO 2023019753 A1 WO2023019753 A1 WO 2023019753A1
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WIPO (PCT)
Prior art keywords
clock signal
state
low level
slave device
master device
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PCT/CN2021/128509
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English (en)
French (fr)
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卢亮
李进
宁健
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西安易朴通讯技术有限公司
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Publication of WO2023019753A1 publication Critical patent/WO2023019753A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4063—Device-to-bus coupling
    • G06F13/4068—Electrical coupling
    • G06F13/4086—Bus impedance matching, e.g. termination
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0016—Inter-integrated circuit (I2C)

Definitions

  • the embodiments of the present application relate to the field of communication technologies, and in particular, to a communication control method, system, and device for an I2C bus.
  • the integrated circuit bus (Inter-Integrated Circuit, I2C) is a common serial communication bus.
  • the I2C serial bus generally has two signal lines, one is a bidirectional data line, and the other is a clock line.
  • the device that controls the bus data transmission is called the master device, and the device that receives the command of the master device is called the slave device.
  • the master device can send a clock signal through the clock line output circuit, and decide when to send a control command according to the level of the clock signal.
  • the slave device usually sends or receives the signal on the data line according to the clock signal on the bus, and can also send a low-level signal to the clock line to pull down the clock signal to extend the cycle of the bus clock signal. The process of pulling down the clock signal from the device is called clock stretching.
  • the master device since the master device and the slave device are not directly connected, when the slave device initiates clock stretching, the master device cannot respond to clock stretching and suspends data transmission. If the master device still sends instructions to the slave device at this time, The slave device may not be able to respond to the command in time, resulting in communication failure.
  • the present application provides a communication control method, system, and device for an I2C bus.
  • the clock signal of the master device can be controlled according to the clock signal of the slave device, so as to avoid the delay between the master device and the slave device when the slave device triggers clock extension. Communication failure, improve the stability and effectiveness of data transmission.
  • the present application provides a communication control method of an I2C bus, the method includes: if the falling edge of the first clock signal corresponding to the master device is detected, the first clock signal and the second clock signal corresponding to the slave device Set to low level; after the first preset time period, convert the second clock signal from low level to high impedance state, and monitor the state of the second clock signal; control the first clock signal according to the state of the second clock signal status.
  • controlling the state of the first clock signal according to the state of the second clock signal includes: setting the first clock signal to a low level if it is detected that the second clock signal is at a low level.
  • the method further includes: setting the second clock signal to a high-impedance state, and continuing to monitor the state of the second clock signal until the second clock signal is at a high level .
  • controlling the state of the first clock signal according to the state of the second clock signal includes: setting the first clock signal to a high-impedance state if it is detected that the second clock signal is at a high level.
  • it also includes: acquiring the first clock signal within the fourth preset duration; determining the duty cycle and period of the first clock signal according to the first clock signal within the fourth preset duration; according to the duty cycle and Period, to determine the first preset duration.
  • monitoring the state of the second clock signal includes: monitoring the state of the second clock signal after a second preset period of time after setting the second clock signal to a high-impedance state.
  • the present application provides an I2C bus communication control system, the system includes: a master device, a control device and a slave device.
  • the control device is communicatively connected with the master device and the slave device respectively.
  • the master device is configured to send the first clock signal to the control device.
  • the slave device is used for receiving the second clock signal sent by the control device.
  • the control device is used to monitor the first clock signal. If the falling edge of the first clock signal is detected, the first clock signal and the second clock signal are set to low level, and after the first preset time period, the second clock signal is set to low level.
  • the second clock signal is converted from a low level to a high impedance state, the state of the second clock signal is monitored, and the state of the first clock signal is controlled according to the state of the second clock signal.
  • control device is specifically configured to set the first clock signal to be at low level if it is detected that the second clock signal is at low level.
  • control device is further configured to put the second clock signal into a high-impedance state, and continue to monitor the state of the second clock signal until the second clock signal is at a high level.
  • control device is specifically configured to set the first clock signal to a high-impedance state if it is detected that the second clock signal is at a high level.
  • control device is also used to acquire the first clock signal within the fourth preset time length; determine the duty cycle and period of the first clock signal according to the first clock signal within the fourth preset time length; Duty ratio and period determine the first preset duration.
  • control device is specifically configured to monitor the state of the second clock signal after a second preset time period after setting the second clock signal to the high-impedance state.
  • an I2C bus communication control device which includes:
  • the monitoring module is configured to set the first clock signal and the second clock signal corresponding to the slave device to low level if the falling edge of the first clock signal corresponding to the master device is detected.
  • the control module is configured to switch the second clock signal from a low level to a high impedance state after the first preset time period.
  • the monitoring module is also used to monitor the state of the second clock signal after the second preset time period.
  • the control module is further configured to control the first clock signal according to the state of the second clock signal.
  • control module is specifically configured to set the first clock signal to be low level if it is detected that the second clock signal is low level.
  • control module is further configured to put the second clock signal into a high-impedance state.
  • the monitoring module is further configured to continuously monitor the state of the second clock signal until the second clock signal is at a high level.
  • control module is specifically configured to set the first clock signal to a high-impedance state if it is detected that the second clock signal is at a high level.
  • control module is also used to acquire the first clock signal within the fourth preset duration; determine the duty cycle and period of the first clock signal according to the first clock signal within the fourth preset duration; Duty ratio and period determine the first preset duration.
  • the monitoring module is further configured to monitor the state of the second clock signal after a second preset period of time after the second clock signal is set to a high-impedance state.
  • the present application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by at least one processor, and the instructions are processed by at least one processor executed by a processor, so that at least one processor can execute the method of the first aspect or an optional manner of the first aspect.
  • the present application provides a computer-readable storage medium, where computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, they are used to implement the first aspect or the optional manner of the first aspect Methods.
  • the present application provides a communication control method, system and device of an I2C bus. If the method detects the falling edge of the first clock signal corresponding to the master device, the first clock signal and the second clock signal corresponding to the slave device are set to is low level, after the first preset duration, the second clock signal is converted from low level to high impedance state, and the state of the second clock signal is monitored; the state of the first clock signal is controlled according to the state of the second clock signal
  • the state can control the clock signal of the master device according to the clock signal of the slave device, avoiding the communication failure between the master device and the slave device when the slave device triggers clock stretching, and improving the stability and effectiveness of data transmission.
  • FIG. 1 is a schematic diagram of an application scenario of an I2C bus communication control method provided by the present application
  • FIG. 2 is a schematic flow diagram of a communication control method for an I2C bus provided by the present application
  • FIG. 3 is a schematic flow diagram of another I2C bus communication control method provided by the present application.
  • Fig. 4 is a timing diagram of a kind of I2C clock signal provided by the present application.
  • FIG. 5 is a schematic structural diagram of a communication control system of an I2C bus provided by the present application.
  • FIG. 6 is a schematic structural diagram of an I2C bus communication control device provided by the present application.
  • FIG. 7 is a schematic structural diagram of an electronic device provided by the present application.
  • the integrated circuit bus (Inter-Integrated Circuit, I2C) is a serial communication bus.
  • the I2C serial bus generally has two signal lines, one is a bidirectional data line, and the other is a bidirectional clock line.
  • the master device that controls the bus data transmission, on the one hand, it sends the clock signal through the clock line output circuit, and on the other hand, it detects the level of the clock signal on the bus to determine when to send the next clock pulse level.
  • As a slave device that accepts the command of the master device it sends or receives the signal on the data line according to the clock signal on the bus, and can also send a low-level signal to the clock line to extend the cycle of the bus clock signal.
  • the slave device when the slave device needs to perform other tasks, or when the speed of the slave device cannot keep up with the master device, the slave device can pull down the clock signal to suspend the data transmission with the master device until the slave device releases the clock signal, The data transfer between the master device and the slave device is resumed.
  • the process of pulling down the clock signal from the device is called clock stretching.
  • the master device since the master device and the slave device are not directly connected, when the slave device initiates clock stretching, the master device cannot respond to clock stretching and suspends data transmission. If the master device still sends instructions to the slave device at this time, The slave device may not be able to respond to the command in time, resulting in communication failure.
  • the master device can be controlled to suspend data transmission, thereby ensuring the reliability of data transmission between the master device and the slave device.
  • the present application provides a communication control method of the I2C bus, the method is applied to electronic equipment, and the electronic equipment is serially connected between the master device and the slave device, that is, the electronic device is serially connected to the I2C clock signal of the master device. Between the port and the I2C clock signal port of the slave device, it can realize I2C transparent transmission. After the device is powered on, during initialization, the port connecting the electronic device to the I2C clock signal of the master device is set to a high-impedance state to monitor the state of the clock signal of the master device.
  • the clock of the master device and the clock of the slave device are controlled, and both the clocks of the master device and the slave device are controlled to be at low level, and timing is started.
  • the clock signal is a square wave signal, with a low level for half a clock cycle and a high level for half a clock cycle. Therefore, by monitoring whether the clock signal of the slave device jumps to a high level after half a clock cycle, it can be determined whether the slave device triggers clock stretching. Based on this, after half a clock cycle, the electronic device sets the clock of the slave device to a high-impedance state, releases the control right of the clock, and monitors the state of the clock signal of the slave device.
  • the clock signal of the slave device becomes high level, it means that the slave device does not extend the clock, then the clock signal of the master device is set to a high-impedance state, and the control of the clock signal of the master device is released; if the slave device is detected If the clock signal of the slave device becomes low level, it means that the slave device has extended the clock, and the clock signal of the master device is still controlled to be low level, and continues to monitor the state of the clock signal of the slave device until the clock signal of the slave device jumps to When the high point is flat, the clock signal of the master device is set to a high-impedance state, and the control of the clock signal of the master device is released.
  • the electronic device when the electronic device transparently transmits I2C, when the slave device triggers clock extension, the electronic device can control the clock signal of the master device to keep the low level state in time, and then suspend the communication between the master device and the slave device. After the slave device completes the clock extension, it releases the control right of the clock signal of the master device, so that the master device and the slave device resume normal communication.
  • FIG. 1 is a schematic diagram of an application scenario of an I2C bus communication control method provided by the present application. As shown in FIG. 1 , the scenario includes: a master device 11 , an electronic device 12 and a slave device 13 .
  • the electronic device 12 is respectively connected to the master device 11 and the slave device 12 through an I2C bus.
  • the electronic device 13 can transparently transmit relevant data.
  • the electronic device 12 may include a programmable logic device (Field Programmable Gate Array, FPGA), a complex programmable logic device (Complex Programmable Logic Device, CPLD) and other devices with control functions.
  • a programmable logic device Field Programmable Gate Array, FPGA
  • a complex programmable logic device Complex Programmable Logic Device, CPLD
  • Fig. 2 is a schematic flow chart of a communication control method of an I2C bus provided by the present application, the method is applied to electronic equipment, as shown in Fig. 2, the method includes:
  • a master device generally refers to a device that issues a main command
  • a slave device generally refers to a device that receives a command.
  • the first clock signal is an I2C clock signal corresponding to the master device; the second clock signal is an I2C clock signal corresponding to the slave device.
  • the first preset duration may be a specific duration set by the user; it may also be determined by the electronic device according to the duty cycle and period of the first clock signal. Specifically, the first preset duration may be a corresponding duration when the clock signal is at a low level in one clock cycle.
  • the clock signal of the I2C bus is a square wave, and correspondingly, the first preset duration is half a clock cycle.
  • the user can finish in time by setting the timer inside the electronic device.
  • control the first clock signal If the second clock signal is low, control the first clock signal to be low; if the second clock signal is high, then control the first clock signal to be in a high-impedance state, and release the control right of the first clock signal , enabling the master to control the state of the first clock signal.
  • the first clock signal and the second clock signal corresponding to the slave device are set to low level, and after the first preset period of time, the The second clock signal is converted from a low level to a high-impedance state, and the state of the second clock signal is monitored; the state of the first clock signal is controlled according to the state of the second clock signal.
  • I2C transparent transmission it can be realized according to the slave device
  • the clock signal of the master device controls the clock signal of the master device, avoiding the communication failure between the master device and the slave device when the slave device triggers clock extension, and improving the stability and effectiveness of data transmission.
  • Fig. 3 is a schematic flow chart of another I2C bus communication control method provided by the present application, the method is applied to electronic equipment, as shown in Fig. 3, the method includes:
  • S301 and S201 have the same technical features, and for the specific description, refer to S201, and details are not repeated here.
  • the electronic device If the electronic device has just been powered on, before performing S301, it also includes setting the first clock signal to a high-impedance state, that is, setting the state of the port of the electronic device for receiving the first clock signal corresponding to the master device to a high-impedance state. With this setting, the port state of the electronic device will change following the change of the first clock signal corresponding to the master device, and then the first clock signal can be monitored.
  • a high-impedance state that is, setting the state of the port of the electronic device for receiving the first clock signal corresponding to the master device to a high-impedance state.
  • the falling edge of the first signal is detected, it indicates that the first clock signal will enter a low level state, so the states of the first clock signal and the second clock signal are both set to low level.
  • Figure 4 is a timing diagram of an I2C clock signal provided by the present application. As shown in Figure 4, if the falling edge of the first clock signal corresponding to the master device is detected, the first clock signal and the second clock signal corresponding to the slave device are The clock signals are all set to low level.
  • S302 and S202 have the same technical features, and for the specific description, refer to S202, which will not be repeated here.
  • the clock signal is usually a signal with high and low levels alternately, and the first preset duration is specifically the duration during which the first clock signal is at a low level within one clock cycle.
  • the clock signal is a square wave signal with a duty cycle of 50%. Based on this, the first preset duration can be set to half a clock cycle.
  • the duty cycle of the clock signal is different, and the corresponding duration of the low level state is also different.
  • the method further includes: acquiring the first clock signal within the fourth preset duration; determining the duty cycle and period of the first clock signal according to the first clock signal within the fourth preset duration; ratio and period to determine the first preset duration.
  • the fourth preset duration should be greater than the period of the first clock signal.
  • the period and duty cycle of the first clock signal can be determined, and then the corresponding first preset duration can be determined according to the period and duty cycle.
  • monitoring the state of the second clock signal includes: monitoring the state of the second clock signal after a second preset time period after setting the second clock signal to a high-impedance state.
  • a time margin can be reserved for the slave device to pull down the clock signal, so as to improve the accuracy of the monitoring results and the accuracy of the control.
  • Setting the second clock signal to a high-impedance state means that the electronic device sets the port connected to the second clock signal corresponding to the slave device to a high-impedance state, so that the state of the port can follow the change of the second clock signal. change, that is, the state of the second clock signal can be monitored.
  • the second preset duration shown in FIG. 4 is one-eighth of a clock period, that is, 1/8Tscl.
  • the electronic device monitors the state of the second clock signal after a period of 1/8Tscl after setting the second clock signal to the high impedance state.
  • the first preset duration is half a clock cycle
  • half a clock cycle that is, after 1/2Tscl
  • the second clock signal is detected to be still at a low level, it indicates that the slave device is pulled down
  • the clock signal is activated, that is, the slave device triggers clock stretching, the state of the first clock signal is not changed, and the first clock signal is still set to a low level.
  • the second clock signal transitions from a low level to a high level, it indicates that the slave device ends clock stretching.
  • the first clock signal is set to a high-impedance state, releasing the control right of the state of the first clock signal, and the master
  • the device controls the state of the first clock signal.
  • the master device can continue to communicate with the slave device.
  • the electronic device sets the first clock signal to a high-impedance state to detect the state of the first clock signal.
  • the above steps are re-executed to perform a new round of control on the first clock signal.
  • the present application is implemented on the basis of the above-mentioned embodiments, and if it is detected that the second clock signal is at a low level, then the second clock signal is set to a high-impedance state, and the state of the second clock signal is continuously detected until the second The second clock signal is at a high level, so that when the slave device triggers clock extension, it can control the clock signal of the master device at a low level, suspending the communication between the master device and the slave device; if the second clock signal is detected to be at a high level level, then set the first clock signal to a high-impedance state to release the control right to the first clock signal, so that the master device can control the state of the first clock signal, so that the master device and the slave device can continue to communicate, avoiding the In the case of transparent transmission, during the communication process between the master device and the slave device, the communication fails because the slave device triggers clock extension, which improves the stability and effectiveness of data transmission.
  • FIG. 5 is a schematic structural diagram of an I2C bus communication control system provided by the present application. As shown in FIG. 5 , the system includes: a master device 51 , a control device 52 and a slave device 53 .
  • the control device 52 is communicatively connected with the master device 51 and the slave device 53 respectively.
  • the master device 51 is configured to send the first clock signal to the control device 52 .
  • the slave device 51 is configured to receive the second clock signal sent by the control device 52 .
  • the control device 52 is used to monitor the first clock signal. If the falling edge of the first clock signal is detected, the first clock signal and the second clock signal are set to low level, and after the first preset time period, the The second clock signal is converted from a low level to a high impedance state, the state of the second clock signal is monitored, and the state of the first clock signal is controlled according to the state of the second clock signal.
  • control device 52 is specifically configured to continue setting the first clock signal to a low level if it is detected that the second clock signal is at a low level.
  • control device 52 is further configured to set the second clock signal to a high-impedance state, and continue to monitor the state of the second clock signal until the second clock signal is at a high level.
  • control device 52 is specifically configured to set the first clock signal to a high-impedance state if it is detected that the second clock signal is at a high level.
  • control device 52 is also used to acquire the first clock signal within the fourth preset time length; determine the duty cycle and period of the first clock signal according to the first clock signal within the fourth preset time length; The duty cycle and period determine the first preset duration.
  • control device 52 is specifically configured to monitor the state of the second clock signal after a second preset time period after setting the second clock signal to the high-impedance state.
  • the system can realize the above method, and its content and effect can refer to the method embodiment part, which will not be repeated here.
  • FIG. 6 is a schematic structural diagram of a communication control device for an I2C bus provided by the present application. As shown in FIG. 6, the device includes:
  • the monitoring module 61 is configured to set the first clock signal and the second clock signal corresponding to the slave device to low level if a falling edge of the first clock signal corresponding to the master device is detected.
  • the control module 62 is configured to switch the second clock signal from a low level to a high impedance state after a first preset time period.
  • the monitoring module 61 is further configured to monitor the state of the second clock signal after a second preset time period.
  • the control module 62 is further configured to control the first clock signal according to the state of the second clock signal.
  • control module 62 is specifically configured to continue setting the first clock signal to a low level if it is detected that the second clock signal is at a low level.
  • control module 62 is also configured to put the second clock signal into a high-impedance state.
  • the monitoring module 61 is further configured to continue monitoring the state of the second clock signal until the second clock signal is at a high level.
  • control module 62 is specifically configured to set the first clock signal to a high-impedance state if it is detected that the second clock signal is at a high level.
  • control module 62 is also configured to acquire the first clock signal within the fourth preset time length; determine the duty cycle and period of the first clock signal according to the first clock signal within the fourth preset time length; The duty cycle and period determine the first preset duration.
  • the monitoring module 62 is also configured to monitor the state of the second clock signal after a second preset period of time after the second clock signal is set to a high-impedance state.
  • the device can execute the above-mentioned method, and its content and effect can refer to the part of the method embodiment, which will not be repeated here.
  • FIG. 7 is a schematic structural diagram of an electronic device provided in the present application.
  • the electronic device includes: a processor 71 and a memory 72 ; the processor 71 and the memory 72 are connected in communication.
  • the memory 72 is used to store computer programs.
  • the processor 71 is configured to call a computer program stored in the memory 72 to implement the methods in the above method embodiments.
  • the electronic device further includes: a transceiver 73, configured to communicate with other devices.
  • the electronic device can execute the above method, and its content and effects can refer to the method embodiments, which will not be repeated here.
  • the present application also provides a computer-readable storage medium, wherein computer-executable instructions are stored in the computer-readable storage medium, and the computer-executable instructions are used to implement the above method when executed by a processor.

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Abstract

本申请提供一种I2C总线的通信控制方法、系统和装置，该方法包括：若监测到主设备对应的第一时钟信号的下降沿，则将第一时钟信号和从设备对应的第二时钟信号设置为低电平；在第一预设时长后，将第二时钟信号由低电平转换为高阻态，并监测第二时钟信号的状态；根据第二时钟信号的状态控制第一时钟信号的状态。通过该方法在I2C透传情况下，能够根据从设备的时钟信号控制主设备的时钟信号，避免从设备触发时钟延展时，主设备和从设备通信失败，提高数据传输的稳定性和有效性。

Description

I2C总线的通信控制方法、系统和装置
本公开要求于2021年8月20日提交中国专利局、申请号为CN202110959742.7、申请名称为“I2C总线的通信控制方法、系统和装置”的中国专利申请的优先权，其全部内容通过引用结合在本公开中。
技术领域
本申请实施例涉及通信技术领域，尤其涉及一种I2C总线的通信控制方法、系统和装置。
背景技术
集成电路总线(Inter-Integrated Circuit，I2C)是一种常见的串行通信总线。I2C串行总线一般有两根信号线，一根是双向的数据线，另一根是时钟线。控制总线数据传送的设备称为主设备，接收主设备命令的设备称为从设备。主设备能够通过时钟线输出电路发送时钟信号，并根据时钟信号的电平，决定什么时候发送控制指令。从设备通常按照总线上的时钟信号发出或接收数据线上的信号，还可以向时钟线发出低电平信号，拉低时钟信号，以延长总线时钟信号周期。从设备拉低时钟信号的过程，称为时钟延展。
然而，在I2C透传情况下，由于主设备和从设备没有直连，当从设备发起时钟延展时，主设备无法响应时钟延展，暂停数据传输，如果此时主设备仍向从设备发送指令，从设备将可能无法及时响应该指令，导致通信失败。
发明内容
本申请提供一种I2C总线的通信控制方法、系统和装置，在I2C透传情况下，能够根据从设备的时钟信号控制主设备的时钟信号，避免从设备触发时钟延展时，主设备和从设备通信失败，提高数据传输的稳定性和有 效性。
第一方面，本申请提供一种I2C总线的通信控制方法，该方法包括：若监测到主设备对应的第一时钟信号的下降沿，则将第一时钟信号和从设备对应的第二时钟信号设置为低电平；在第一预设时长后，将第二时钟信号由低电平转换为高阻态，并监测第二时钟信号的状态；根据第二时钟信号的状态控制第一时钟信号的状态。
可选地，根据第二时钟信号的状态控制第一时钟信号的状态，包括：若监测到第二时钟信号为低电平，则将第一时钟信号置为低电平。
可选地，将第一时钟信号置为低电平之后，方法还包括：将第二时钟信号置为高阻态，并继续监测第二时钟信号的状态，直至第二时钟信号为高电平。
可选地，根据第二时钟信号的状态控制第一时钟信号的状态，包括：若监测到第二时钟信号为高电平，则将第一时钟信号置为高阻态。
可选地，还包括：获取第四预设时长内的第一时钟信号；根据第四预设时长内的第一时钟信号，确定第一时钟信号的占空比和周期；根据占空比和周期，确定第一预设时长。
可选地，监测第二时钟信号的状态，包括：在将第二时钟信号设置为高阻态后的第二预设时长后，监测第二时钟信号的状态。
第二方面，本申请提供的一种I2C总线的通信控制系统，该系统包括：主设备、控制设备和从设备。
控制设备分别与主设备和从设备通信连接。
主设备，用于向控制设备发送第一时钟信号。
从设备，用于接收控制设备发送第二时钟信号。
控制设备，用于监测第一时钟信号，若监测到第一时钟信号的下降沿，则将第一时钟信号和第二时钟信号设置为低电平，并在第一预设时长后，将第二时钟信号由低电平转换为高阻态，监测第二时钟信号的状态，并根据第二时钟信号的状态控制第一时钟信号的状态。
可选地，控制设备，具体用于若监测到第二时钟信号为低电平，则将第一时钟信号置为低电平。
可选地，控制设备，还用于将第二时钟信号置为高阻态，并继续监测第二时钟信号的状态，直至第二时钟信号为高电平。
可选地，控制设备，具体用于若监测到第二时钟信号为高电平，则将第一时钟信号置为高阻态。
可选地，控制设备，还用于获取第四预设时长内的第一时钟信号；根据第四预设时长内的第一时钟信号，确定第一时钟信号的占空比和周期；根据占空比和周期，确定第一预设时长。
可选地，控制设备，具体用于在将第二时钟信号设置为高阻态后的第二预设时长后，监测第二时钟信号的状态。
第三方面，本申请提供的一种I2C总线的通信控制装置，该装置包括：
监测模块，用于若监测到主设备对应的第一时钟信的下降沿，则将第一时钟信号和从设备对应的第二时钟信号置为低电平。
控制模块，用于在第一预设时长后，将第二时钟信号由低电平转换置为高阻态。
监测模块，还用于在第二预设时长后，监测第二时钟信号的状态。
控制模块，还用于根据第二时钟信号的状态控制第一时钟信号。
可选地，控制模块，具体用于若监测到第二时钟信号为低电平，则将第一时钟信号置为低电平。
可选地，控制模块，还用于将第二时钟信号置为高阻态。
监测模块，还用于继续监测第二时钟信号的状态，直至第二时钟信号为高电平。
可选地，控制模块，具体用于若监测到第二时钟信号为高电平，则将第一时钟信号置为高阻态。
可选地，控制模块，还用于获取第四预设时长内的第一时钟信号；根据第四预设时长内的第一时钟信号，确定第一时钟信号的占空比和周期；根据占空比和周期，确定第一预设时长。
可选地，监测模块，还用于在将第二时钟信号设置为高阻态后的第二预设时长后，监测第二时钟信号的状态。
第四方面，本申请提供一种电子设备，包括：至少一个处理器；以及 与至少一个处理器通信连接的存储器；其中，存储器存储有可被至少一个处理器执行的指令，指令被至少一个处理器执行，以使至少一个处理器能够执行如第一方面或第一方面的可选方式的方法。
第五方面，本申请提供一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，计算机执行指令被处理器执行时用于实现如第一方面或第一方面的可选方式的方法。
本申请提供一种I2C总线的通信控制方法、系统和装置，该方法通过若监测到主设备对应的第一时钟信号的下降沿，则将第一时钟信号和从设备对应的第二时钟信号设置为低电平，在第一预设时长后，将第二时钟信号由低电平转换为高阻态，并监测第二时钟信号的状态；根据第二时钟信号的状态控制第一时钟信号的状态，能够实现根据从设备的时钟信号控制主设备的时钟信号，避免从设备触发时钟延展时，主设备和从设备通信失败，提高数据传输的稳定性和有效性。
附图说明
图1为本申请提供的一种I2C总线的通信控制方法的应用场景的示意图；
图2为本申请提供的一种I2C总线的通信控制方法的流程示意图；
图3为本申请提供的另一种I2C总线的通信控制方法的流程示意图；
图4为本申请提供的一种I2C时钟信号的时序图；
图5为本申请提供的一种I2C总线的通信控制系统的结构示意图；
图6为本申请提供的一种I2C总线的通信控制装置的结构示意图；
图7为本申请提供的一种电子设备的结构示意图。
通过上述附图，已示出本公开明确的实施例，后文中将有更详细的描述。这些附图和文字描述并不是为了通过任何方式限制本公开构思的范围，而是通过参考特定实施例为本领域技术人员说明本公开的概念。
具体实施方式
这里将详细地对示例性实施例进行说明，其示例表示在附图中。下面的描述涉及附图时，除非另有表示，不同附图中的相同数字表示相同或相 似的要素。以下示例性实施例中所描述的实施方式并不代表与本公开相一致的所有实施方式。相反，它们仅是与如所附权利要求书中所详述的、本公开的一些方面相一致的装置和方法的例子。
集成电路总线(Inter-Integrated Circuit，I2C)是一种串行通信总线。I2C串行总线一般有两根信号线，一根是双向的数据线，另一根是双向的时钟线。作为控制总线数据传送的主设备，一方面通过时钟线输出电路发送时钟信号，另一方面检测总线上的时钟信号的电平，以决定什么时候发送下一个时钟脉冲电平。作为接受主设备命令的从设备，按总线上的时钟信号发出或接收数据线上的信号，也可以向时钟线发出低电平信号以延长总线时钟信号周期。例如，当从设备需要执行其他任务，或者，当从设备的速率跟不上主设备时，从设备可以将时钟信号拉低，暂停与主设备之间的数据传输，直至从设备释放时钟信号，才恢复主设备和从设备之间的数据传输。从设备拉低时钟信号的过程，称为时钟延展。然而，在I2C透传情况下，由于主设备和从设备没有直连，当从设备发起时钟延展时，主设备不能响应时钟延展，暂停数据传输，如果此时主设备仍向从设备发送指令，从设备将可能无法及时响应该指令，导致通信失败。
如果，当从设备发起时钟延展时，能够对主设备的时钟加以控制，则能够控制主设备暂停数据传输，从而保障主设备和从设备之间数据传输的可靠性。
基于此，本申请提供了一种I2C总线的通信控制方法，该方法应用于电子设备，该电子设备串接在主设备和从设备之间，即该电子设备串接在主设备的I2C时钟信号端口和从设备的I2C时钟信号端口之间，其能够实现I2C透传。设备上电后，初始化时先将电子设备与主设备的I2C时钟信号连接的端口置为高阻态，以监测主设备的时钟信号的状态。当监测到主设备的时钟信号的下降沿时，则对主设备的时钟和从设备的时钟进行控制，控制主设备的时钟和从设备的时钟均为低电平，并开始计时。通常情况下，时钟信号为方波信号，半个时钟周期为低电平，半个时钟周期为高电平。因此，通过监测半个时钟周期后，从设备的时钟信号是否跳变为高点平，即可确定出从设备是否触发了时钟延展。基于此，当半个时钟周期后，电子设备将从设备的时钟设置为高阻态，释放时钟的控制权，以监测从设备 的时钟信号的状态。若监测到从设备的时钟信号变为高电平，则说明从设备没有延展时钟，则将主设备的时钟信号置为高阻态，释放主设备的时钟信号的控制权；若监测到从设备的时钟信号变为低电平，则说明从设备延展了时钟，则仍控制主设备的时钟信号为低电平，并继续监测从设备的时钟信号的状态，直至从设备的时钟信号跳变为高点平，才将主设备的时钟信号置为高阻态，释放主设备的时钟信号的控制权。通过该方法，在电子设备透传I2C的情况下，从设备触发时钟延展时，电子设备能够及时控制主设备的时钟信号保持低电平状态，进而暂停主设备和从设备之间的通信，当从设备结束时钟延展后，才释放主设备的时钟信号的控制权，使主设备和从设备恢复正常通信。
图1为本申请提供的一种I2C总线的通信控制方法的应用场景的示意图，如图1所示，该场景包括：主设备11、电子设备12和从设备13。
电子设备12分别与主设备11和从设备12通过I2C总线连接。当主设备11和从设备13通过I2C总线通信时，电子设备13可以透传相关数据。
电子设备12具体可以包括可编程逻辑器件(Field Programmable Gate Array，FPGA)、复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)等具有控制功能的器件。
图2为本申请提供的一种I2C总线的通信控制方法的流程示意图，该方法应用于电子设备，如图2所示，该方法包括：
S201、若监测到主设备对应的第一时钟信号的下降沿，则将第一时钟信号和从设备对应的第二时钟信号设置为低电平。
具体的，主设备一般指发布主要命令的设备；从设备一般指接收命令的设备。
第一时钟信号为主设备对应的I2C时钟信号；第二时钟信号为从设备对应的I2C时钟信号。
S202、在第一预设时长后，将第二时钟信号由低电平转换为高阻态，并监测第二时钟信号的状态。
第一预设时长可以是用户设置的具体时长；也可以是电子设备根据第一时钟信号的占空比和周期确定。具体的，第一预设时长可以是一个时钟 周期中，时钟信号为低电平时对应的时长。
通常情况下，I2C总线的时钟信号为方波，相应的，第一预设时长即为半个时钟周期。用户可以通过设置电子设备内部的计时器完成及时。
S203、根据第二时钟信号的状态控制第一时钟信号的状态。
若第二时钟信号为低电平，则控制第一时钟信号为低电平；若第二时钟信号为高点平，则控制第一时钟信号为高阻态，释放第一时钟信号的控制权，使主设备能够控制第一时钟信号的状态。
本申请实施例通过若监测到主设备对应的第一时钟信号的下降沿，则将第一时钟信号和从设备对应的第二时钟信号设置为低电平，在第一预设时长后，将第二时钟信号由低电平转换为高阻态，并监测第二时钟信号的状态；根据第二时钟信号的状态控制第一时钟信号的状态，在I2C透传情况下，能够实现根据从设备的时钟信号控制主设备的时钟信号，避免从设备触发时钟延展时，主设备和从设备通信失败，提高数据传输的稳定性和有效性。
图3为本申请提供的另一种I2C总线的通信控制方法的流程示意图，该方法应用于电子设备，如图3所示，该方法包括：
S301、若监测到主设备对应的第一时钟信号的下降沿，则将第一时钟信号和从设备对应的第二时钟信号设置为低电平。
S301和S201具有相同的技术特征，具体描述可参照S201，在此不做赘述。
若电子设备刚上电，那么在执行S301之前，还包括将第一时钟信号设置为高阻态，即将电子设备用于接收主设备对应的第一时钟信号的端口的状态设置为高阻态。通过这种设置，电子设备的端口状态会跟随主设备对应的第一时钟信号的变化而变化，进而可以监测第一时钟信号。
若监测到第一信号的下降沿，则表明第一时钟信号将键入低电平状态，因此，将第一时钟信号和第二时钟信号的状态均设置为低电平。
图4为本申请提供的一种I2C时钟信号的时序图，如图4所示，若监测到主设备对应的第一时钟信号的下降沿，则将第一时钟信号和从设备对应的第二时钟信号均设置为低电平。
S302、在第一预设时长后，将第二时钟信号由低电平转换为高阻态， 并监测第二时钟信号的状态。
S302和S202具有相同的技术特征，具体描述可参照S202，在此不做赘述。
时钟信号通常为高低电平交替的信号，第一预设时长具体为一个时钟周期内，第一时钟信号为低电平的时长。通常情况下，时钟信号为占空比为50％的方波信号，基于此，第一预设时长可以设置为半个时钟周期。
时钟信号的占空比不同，其对应的处于低电平状态的时长也不同。
可选地，该方法还包括：获取第四预设时长内的第一时钟信号；根据第四预设时长内的第一时钟信号，确定第一时钟信号的占空比和周期；根据占空比和周期，确定第一预设时长。
具体的，第四预设时长应大于第一时钟信号的周期。
通过该方法能够确定出第一时钟信号的周期和占空比，进而可以根据其周期和占空比确定出对应的第一预设时长。
可选地，监测第二时钟信号的状态包括：在将第二时钟信号设置为高阻态后的第二预设时长后，监测第二时钟信号的状态。
通过设置第二预设时长，能够为从设备拉低时钟信号预留时间裕量，提高监测结果的准确性，提高控制的准确性。
将第二时钟信号设置为高阻态，其实质是电子设备将其与从设备对应的第二时钟信号连接的端口设置为了高阻态，进而该端口的状态能够跟随第二时钟信号的变化而变化，即可以监测第二时钟信号的状态。
继续参见图4，图4所示第二预设时长为八分之一个时钟周期，即1/8Tscl。电子设备在将第二时钟信号设置为高阻态后的1/8Tscl时长后，监测第二时钟信号的状态。
S303、若监测到第二时钟信号为低电平，则执行S304；若监测到第二时钟信号为高电平，则执行S306。
S304、继续将第一时钟信号置为低电平。
S305、将第二时钟信号置为高阻态，并继续监测第二时钟信号的状态，直至第二时钟信号为高电平。
继续参见图4，假设第一预设时长为半个时钟周期，则在半个时钟周期后，即1/2Tscl后，若监测到第二时钟信号仍为低电平，则表明从设备 拉低了时钟信号，即从设备触发了时钟延展，则不改变第一时钟信号的状态，仍然将第一时钟信号置为低电平。当第二时钟信号由低电平跳变为高点平，则表明从设备结束时钟延展。
S306、将第一时钟信号置为高阻态。
继续参见图4，若检测到第二时钟信号为高点平，则表明从设备没有拉低时钟信号，将第一时钟信号设置为高阻态，释放第一时钟信号的状态的控制权，主设备控制第一时钟信号的状态。主设备可以和从设备继续通信。电子设备则将第一时钟信号设置为高阻态，以检测第一时钟信号的状态。当监测到下一个第一时钟信号的下降沿时，则重新执行上述步骤，对第一时钟信号进行新一轮的控制。
本申请实施在上述实施例的基础上，进一步的通过若监测到第二时钟信号为低电平，则将第二时钟信号置为高阻态，并继续检测第二时钟信号的状态，直至第二时钟信号为高电平，进而能够在从设备触发时钟延展时，控制主设备的时钟信号时钟低电平，暂停主设备和从设备之间的通信；若监测到第二时钟信号为高电平，则将第一时钟信号置为高阻态，以释放对第一时钟信号的控制权，使主设备控制第一时钟信号的状态，进而使主设备和从设备能够继续进行通信，避免了在透传情况下，主设备和从设备通信过程中，由于从设备触发时钟延展，而导致通信失败，提高了数据传输的稳定性和有效性。
图5为本申请提供的一种I2C总线的通信控制系统的结构示意图，如图5所示，该系统包括：主设备51、控制设备52和从设备53。
控制设备52分别与主设备51和从设备53通信连接。
主设备51，用于向控制设备52发送第一时钟信号。
从设备51，用于接收控制设备52发送第二时钟信号。
控制设备52，用于监测第一时钟信号，若监测到第一时钟信号的下降沿，则将第一时钟信号和第二时钟信号设置为低电平，并在第一预设时长后，将第二时钟信号由低电平转换为高阻态，监测第二时钟信号的状态，并根据第二时钟信号的状态控制第一时钟信号的状态。
可选地，控制设备52，具体用于若监测到第二时钟信号为低电平，则继续将第一时钟信号置为低电平。
可选地，控制设备52，还用于将第二时钟信号置为高阻态，并继续监测第二时钟信号的状态，直至第二时钟信号为高电平。
可选地，控制设备52，具体用于若监测到第二时钟信号为高电平，则将第一时钟信号置为高阻态。
可选地，控制设备52，还用于获取第四预设时长内的第一时钟信号；根据第四预设时长内的第一时钟信号，确定第一时钟信号的占空比和周期；根据占空比和周期，确定第一预设时长。
可选地，控制设备52，具体用于在将第二时钟信号设置为高阻态后的第二预设时长后，监测第二时钟信号的状态。
该系统可以实现上述方法，其内容和效果可参考方法实施例部分，对此不再赘述。
图6为本申请提供的一种I2C总线的通信控制装置的结构示意图，如图6所示，该装置包括：
监测模块61，用于若监测到主设备对应的第一时钟信的下降沿，则将第一时钟信号和从设备对应的第二时钟信号置为低电平。
控制模块62，用于在第一预设时长后，将第二时钟信号由低电平转换置为高阻态。
监测模块61，还用于在第二预设时长后，监测第二时钟信号的状态。
控制模块62，还用于根据第二时钟信号的状态控制第一时钟信号。
可选地，控制模块62，具体用于若监测到第二时钟信号为低电平，则继续将第一时钟信号置为低电平。
可选地，控制模块62，还用于将第二时钟信号置为高阻态。
监测模块61，还用于继续监测第二时钟信号的状态，直至第二时钟信号为高电平。
可选地，控制模块62，具体用于若监测到第二时钟信号为高电平，则将第一时钟信号置为高阻态。
可选地，控制模块62，还用于获取第四预设时长内的第一时钟信号；根据第四预设时长内的第一时钟信号，确定第一时钟信号的占空比和周期；根据占空比和周期，确定第一预设时长。
可选地，监测模块62，还用于在将第二时钟信号设置为高阻态后的第 二预设时长后，监测第二时钟信号的状态。
该装置可以执行上述方法，其内容和效果可参考方法实施例部分，对此不再赘述。
图7为本申请提供的一种电子设备的结构示意图，如图7所示，该电子设备包括：处理器71、存储器72；处理器71与存储器72通信连接。存储器72用于存储计算机程序。处理器71用于调用存储器72中存储的计算机程序，以实现上述方法实施例中的方法。
可选地，该电子设备还包括：收发器73，用于与其他设备实现通信。
该电子设备可以执行上述方法，其内容和效果可参考方法实施例部分，对此不再赘述。
本申请还提供了一种计算机可读存储介质，计算机可读存储介质中存储有计算机执行指令，计算机执行指令被处理器执行时用于实现上述方法。
该计算机可读存储介质所存储的计算机执行指令被处理器执行时能实现上述方法，其内容和效果可参考方法实施例部分，对此不再赘述。
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其它实施方案。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由下面的权利要求书指出。应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求书来限制。

Claims (10)

  1. 一种I2C总线的通信控制方法，其特征在于，包括：
    若监测到主设备对应的第一时钟信号的下降沿，则将所述第一时钟信号和从设备对应的第二时钟信号设置为低电平；
    在第一预设时长后，将所述第二时钟信号由所述低电平转换为高阻态，并监测所述第二时钟信号的状态；
    根据所述第二时钟信号的状态控制所述第一时钟信号的状态。
  2. 根据权利要求1所述的方法，其特征在于，所述根据所述第二时钟信号的状态控制所述第一时钟信号的状态，包括：
    若监测到所述第二时钟信号为低电平，则继续将所述第一时钟信号置为低电平。
  3. 根据权利要求2所述的方法，其特征在于，所述将所述第一时钟信号置为低电平之后，所述方法还包括：
    将所述第二时钟信号置为高阻态，并继续监测所述第二时钟信号的状态，直至所述第二时钟信号为高电平。
  4. 根据权利要求1所述的方法，其特征在于，所述根据所述第二时钟信号的状态控制所述第一时钟信号的状态，包括：
    若监测到所述第二时钟信号为高电平，则将所述第一时钟信号置为高阻态。
  5. 根据权利要求1-4任一项所述的方法，其特征在于，还包括：
    获取第四预设时长内的所述第一时钟信号；
    根据所述第四预设时长内的所述第一时钟信号，确定所述第一时钟信号的占空比和周期；
    根据所述占空比和所述周期，确定所述第一预设时长。
  6. 根据权利要求3所述的方法，其特征在于，所述监测所述第二时钟信号的状态，包括：
    在将所述第二时钟信号设置为高阻态后的第二预设时长后，监测所述第二时钟信号的状态。
  7. 一种I2C总线的通信控制系统，其特征在于，包括：主设备、控制设备和从设备；
    所述控制设备分别与所述主设备和所述从设备通信连接；
    所述主设备用于向所述控制设备发送第一时钟信号；
    所述从设备用于接收所述控制设备发送第二时钟信号；
    所述控制设备用于监测所述第一时钟信号，若监测到所述第一时钟信号的下降沿，则将所述第一时钟信号和所述第二时钟信号设置为低电平，并在第一预设时长后，将所述第二时钟信号由所述低电平转换为高阻态，监测所述第二时钟信号的状态，并根据所述第二时钟信号的状态控制所述第一时钟信号的状态。
  8. 一种I2C总线的通信控制装置，其特征在于，包括：
    监测模块，用于若监测到主设备对应的第一时钟信的下降沿，则将所述第一时钟信号和从设备对应的第二时钟信号置为低电平；
    控制模块，用于在第一预设时长后，将所述第二时钟信号由所述低电平转换置为高阻态，并在第二预设时长后，监测所述第二时钟信号的状态，并根据所述第二时钟信号的状态控制所述第一时钟信号的状态。
  9. 一种控制设备，其特征在于，包括：
    至少一个处理器；以及
    与所述至少一个处理器通信连接的存储器；其中，
    所述存储器存储有可被所述至少一个处理器执行的指令，所述指令被所述至少一个处理器执行，以使所述至少一个处理器能够执行如权利要求1至6中任一项所述的方法。
  10. 一种可读存储介质，其特征在于，所述可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至6中任一项所述的方法。
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