WO2023019657A1 - 半导体结构及其制造方法 - Google Patents

半导体结构及其制造方法 Download PDF

Info

Publication number
WO2023019657A1
WO2023019657A1 PCT/CN2021/116890 CN2021116890W WO2023019657A1 WO 2023019657 A1 WO2023019657 A1 WO 2023019657A1 CN 2021116890 W CN2021116890 W CN 2021116890W WO 2023019657 A1 WO2023019657 A1 WO 2023019657A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
metal
metal layer
vias
holes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/116890
Other languages
English (en)
French (fr)
Inventor
李宗翰
刘志拯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Changxin Memory Technologies Inc
Original Assignee
Changxin Memory Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Changxin Memory Technologies Inc filed Critical Changxin Memory Technologies Inc
Priority to US17/672,757 priority Critical patent/US12334415B2/en
Publication of WO2023019657A1 publication Critical patent/WO2023019657A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/49—Adaptable interconnections, e.g. fuses or antifuses
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W99/00—Subject matter not provided for in other groups of this subclass

Definitions

  • Embodiments of the present application relate to but are not limited to a semiconductor structure and a manufacturing method thereof.
  • test unit is usually formed in the manufacturing process for performing the resistance test of the through hole.
  • test unit is located on the periphery of the device, and there are no other graphics around it, which may easily cause deformation of the through hole, making it difficult for the test results to reflect the actual resistance of the through hole inside the device.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof.
  • the semiconductor structure provided by the embodiment of the present application includes:
  • an insulating layer located between the first metal layer and the second metal layer, for isolating the first metal layer and the second metal layer;
  • At least four through holes are located in the insulating layer, the at least four through holes have conductive material for connecting the first metal layer and the second metal layer.
  • an embodiment of the present application provides a method for manufacturing a semiconductor structure, including:
  • the conductive material in the at least four via holes is used to connect the first metal layer and the second metal layer.
  • FIG. 1 is a first schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 2 is a second schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram 3 of a semiconductor structure provided in an embodiment of the present application.
  • FIG. 4 is a schematic diagram 4 of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 5 is a schematic diagram of a first metal layer in a semiconductor structure provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram 5 of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 7 is a flow chart of a method for manufacturing a semiconductor structure provided in an embodiment of the present application.
  • FIG. 8A is a schematic diagram of synchronously forming multiple through holes in a method for manufacturing a semiconductor structure provided by an embodiment of the present application.
  • 8B is a schematic diagram of forming a through hole in an embodiment
  • FIG. 9 is a schematic diagram of a semiconductor structure in an embodiment
  • FIG. 10 is a sixth schematic diagram of a semiconductor structure provided by an embodiment of the present application.
  • FIG. 11 is a cross-sectional view of a dummy via hole in a semiconductor structure provided by an embodiment of the present application.
  • the semiconductor structure 100 includes:
  • the first metal layer 120 is located on the surface of the semiconductor substrate 110;
  • the second metal layer 130 is located above the surface of the first metal layer 120;
  • an insulating layer 140 located between the first metal layer 120 and the second metal layer 130, for isolating the first metal layer 120 and the second metal layer 130;
  • At least four through holes 150 are located in the insulating layer 140 , the at least four through holes 150 have conductive materials for connecting the first metal layer 120 and the second metal layer 130 .
  • the above-mentioned semiconductor structure may be a test structure located around the semiconductor device for testing, or called a test unit.
  • the semiconductor structure can be formed synchronously with the semiconductor device during the process of manufacturing various semiconductor devices (such as memories and chips) using the wafer. Since the semiconductor structure and the semiconductor device are separated from each other, the performance of the semiconductor device is not affected.
  • the semiconductor structure can be used for testing during the manufacturing process of the semiconductor device, so as to realize the process monitoring of the semiconductor device.
  • the region where the semiconductor structure is located can be cut off, and only the semiconductor device is kept and the semiconductor device is processed. Packaged separately.
  • the above semiconductor structure may also be retained and packaged together with the semiconductor device, so as to facilitate product testing.
  • first metal layer and second metal layer are metal layers formed synchronously with different metal layers in the semiconductor device, and both the first metal layer and the second metal layer may have patterns formed by etching, for example, linear or mesh shape.
  • the first metal layer and the second metal layer are isolated from each other by an insulating layer, and the insulating layer may be made of insulating materials such as silicon oxide or silicon nitride.
  • the first metal layer and the second metal layer may be connected to each other through a through hole, and the through hole penetrates through the insulating layer and is connected to the first metal layer and the second metal layer.
  • the number of through holes includes at least four, and these through holes may be spaced apart from each other and distributed in different positions, and respectively connect the first metal layer and the second metal layer.
  • the first metal layer includes: a plurality of underlying metal lines distributed in parallel along a first direction;
  • the second metal layer includes: a plurality of top-layer metal lines distributed in parallel along a second direction; wherein the second direction is perpendicular to the first direction.
  • the first metal layer may be a linear metal wire, and may include a plurality of metal wires distributed side by side. Since the first metal layer is a metal layer close to the surface of the substrate, these metal lines may be referred to as bottom metal lines.
  • the plurality of underlying metal lines can all be distributed in parallel along the first direction, and the first direction can be any direction parallel to the surface of the substrate, which can be implemented in an actual manufacturing process.
  • the second metal layer can be a plurality of metal lines distributed in parallel with a structure similar to that of the first metal layer. Compared with the first metal layer, the second metal layer is far away from the substrate surface, so it can be called the top metal layer. Wire.
  • the plurality of top-layer metal lines are parallel distributed along the second direction. The second direction can be perpendicular to the first direction, which can make the structure more stable.
  • the at least four through holes 150 are located on at least two of the underlying metal lines 121 in the first metal layer 120 and at least two of the second metal layer 130 .
  • the metal lines of the first metal layer and the second metal layer are perpendicular to each other, therefore, the bottom metal lines of the first metal layer and the top metal lines of the second metal layer respectively have overlapping positions. These overlapping positions are located on the same straight line in the direction perpendicular to the substrate surface, therefore, the above-mentioned at least four through holes can be formed at these overlapping positions, so as to realize the connection between the first metal layer and the second metal layer.
  • both the first metal layer and the second metal layer have multiple metal lines, they can have multiple overlapping positions, each overlapping position can form a through hole, and the multiple through holes can be respectively located at different overlapping positions .
  • the at least four vias include four test vias; wherein the four test vias are respectively located at four overlapping positions of two top-layer metal lines and two bottom-layer metal lines.
  • the above-mentioned semiconductor structure may include four test vias, and these test vias are used for resistance testing. Therefore, the metal lines on which these test vias are located can be connected to an external test circuit.
  • the test may also be performed in a manner that the probe directly touches the position of the through hole or the metal wire.
  • the four test vias can be located at the four overlapping positions of the two top metal lines and the two bottom metal lines, since each metal line is connected with two vias, and the two vias are connected to different other One layer of metal wires. In this way, the four test via holes can connect different combinations of the four metal wires. During the test, four sets of test data can be obtained to facilitate sufficient data processing and improve the reliability of the test.
  • the two top-layer metal lines connected to the test via holes and the two bottom-layer metal lines may not be two adjacent top-layer metal lines, that is, there may be one or more metal lines connected to the test via holes. top metal wire.
  • the at least four through holes 150 further include at least one pair of auxiliary through holes 151 and at least four test through holes 152 , wherein the at least one pair of auxiliary through holes 151 It is connected to the spaced top metal line 131 or the spaced bottom metal line 121 , and the distance between a pair of auxiliary vias 151 is greater than the distance between any two test vias 152 .
  • an auxiliary via hole may be disposed in the center of the semiconductor structure.
  • the distances between the above four through holes can be equal in pairs, so as to have a stable structure and facilitate testing.
  • auxiliary via holes can be formed on the spaced metal lines to facilitate auxiliary testing.
  • Auxiliary vias appear in pairs and are connected to the same top metal line or bottom technology line. The spacing of the auxiliary via holes may be greater than the spacing between the above-mentioned testing via holes, so as not to affect the testing via holes.
  • the two top metal lines connected to the test vias are connected through a test pad; the two bottom metal lines connected to the test vias are connected through a test pad.
  • the top-layer metal lines connected by the test vias are connected to each other through the test pads, and the bottom metal lines are also connected through the test pads (as shown in FIG. 5A, the test pad 501 is connected to two bottom-layer metal lines 502), so that The test via holes are connected to each other through metal lines.
  • resistance testing can be realized through a set of external testing channels.
  • the test vias are connected to each other, so the data obtained from the test can be calculated to obtain the average resistance value of each via.
  • the resistance value of each via hole in the semiconductor device can be estimated more accurately, so as to determine whether the device may fail.
  • the metal line connected to the auxiliary via hole is not connected to the metal line connected to the test via hole, so a separate test can be performed. In this way, auxiliary test data can be provided during the test, which is convenient for verifying the reliability of the test.
  • the semiconductor structure 100 further includes:
  • At least two dummy via holes 160, the dummy via holes 160 penetrate through the insulating layer, and connect any layer in the first metal layer 120 or the second metal layer 130; the at least two The figure surrounded by the dummy through holes 160 and the distribution positions of the at least four through holes 150 is center-symmetric or axisymmetric.
  • a dummy via is a via hole having a structure similar to that of a test via hole or an auxiliary via hole and penetrating through an insulating layer.
  • the dummy via hole may also contain conductive materials such as metal, but it does not have the function of connecting the first metal layer and the second metal layer. That is to say, the dummy via hole may only connect to the first metal layer or only connect to the second metal layer.
  • the dummy vias can be used to support the entire semiconductor structure.
  • the position distribution of the dummy vias and other vias can be centrally symmetric or axially symmetric, thereby making the semiconductor structure more stable.
  • the dummy vias, together with the test vias and auxiliary vias can constitute a structure simulating the actual vias in the semiconductor device, so that the test data of the test vias is closer to the data of the actual vias in the semiconductor device.
  • the test vias form a first axisymmetric distribution with the centerline of the semiconductor structure as an axis, and the distances from the test vias in the first axisymmetric distribution to the center of the semiconductor structure may be different.
  • the auxiliary through holes and the dummy through holes together form a second axisymmetric distribution with the centerline of the semiconductor structure as an axis, and the distances from the second axisymmetric distribution to the center of the semiconductor structure may be different.
  • the ratio of the distance between any two test vias in the first axisymmetric distribution to the distance from any test via to the center of the semiconductor structure ranges from 1.5 to 3.
  • the ratio of the distance from the via holes in the second axisymmetric distribution to the center of the semiconductor structure to the distance from the via holes in the first axisymmetric distribution to the center of the semiconductor structure is greater than 3.
  • the test vias form a first centrosymmetric distribution centered on the center of the semiconductor structure, and the test vias in the first centrosymmetric distribution are at the same distance from the center of the semiconductor structure.
  • the auxiliary through holes and the dummy through holes together form a second centrosymmetric distribution centered on the center of the semiconductor structure, and the distances from the second centrosymmetric distribution to the center of the semiconductor structure are the same.
  • the dummy via hole is filled with an insulating material.
  • the dummy through hole can play a supporting role, prevent other through holes from being deformed, and prevent the dummy through hole from causing electrical interference to the first metal layer, the second metal layer or other through holes.
  • the at least four vias are used for resistance testing by Kelvin four-wire detection.
  • Kelvin four-wire detection method is also called four-terminal detection, or four-point probe method. This method can eliminate the impedance of wiring and contact resistance by separating the electrodes of current and voltage, so as to realize accurate resistance testing.
  • the metal wires connected to the above at least four through holes can be used to connect different detection terminals respectively, so as to realize four-wire detection. Compared with the method of single-point test, the detection accuracy can be improved.
  • the embodiment of the present application also provides a method for manufacturing a semiconductor structure, including:
  • Step S101 forming a first metal layer on the surface of the semiconductor substrate
  • Step S102 covering the first metal layer with an insulating layer
  • Step S103 forming at least four via holes penetrating through the insulating layer and connecting to the first metal layer;
  • Step S104 filling the at least four through holes with conductive material
  • Step S105 forming a second metal layer on the insulating layer and the at least four through holes; the conductive material in the at least four through holes is used to connect the first metal layer and the second metal layer.
  • the manufacturing process of the semiconductor structure is carried out synchronously during the manufacturing process of the semiconductor device product.
  • the above-mentioned first metal layer, second metal layer and insulating layer are all formed synchronously with each layer in the semiconductor device.
  • the above-mentioned at least four through holes are also carried out synchronously with the process of forming the through holes in the semiconductor device.
  • FIG. 8A after the first metal layer 801 is formed and covers the insulating layer (not shown in the figure), there A plurality of via holes 802 are formed synchronously, and then related processes such as the subsequent second metal layer are performed.
  • the entire structure can be made more stable and closer to the structure of an actual semiconductor device, so that these via holes can be used to reflect the entire structure. The quality of the manufacturing process.
  • the forming the first metal layer on the surface of the semiconductor substrate includes:
  • the forming a second metal layer on the insulating layer and the at least four through holes includes:
  • a plurality of top-layer metal lines distributed in parallel along a second direction are formed on the insulating layer and the at least four through holes; wherein the second direction is perpendicular to the first direction.
  • a layer of metal layer can be formed on the surface of the semiconductor substrate first, and then a plurality of metal lines can be formed by patterned etching; a patterned mask layer can also be formed on the semiconductor substrate first, and then the mask layer The unmasked area is deposited with metal to form a plurality of metal lines, and then the area is masked to form a first metal layer with a plurality of underlying metal lines.
  • an insulating material may be deposited thereon to form an isolation layer.
  • the forming at least four via holes penetrating the insulating layer and connecting the first metal layer includes:
  • each of the bottom metal lines includes two holes distributed along the second direction.
  • Target positions, and two adjacent target positions located on the two underlying metal lines are distributed along the first direction;
  • a plurality of top-layer metal lines distributed in parallel along the second direction are formed on the insulating layer and the at least four through holes, including:
  • a top-layer metal line is formed above two target positions distributed along the first direction, and the target position is a position where two of the top-layer metal lines and two of the bottom-layer metal lines overlap.
  • the insulating layer may be drilled at the target position by means of etching to form the above four test via holes, and the depth of the via hole is the thickness of the insulating layer.
  • the surface of the insulating layer can be communicated with the underlying metal line through the through hole penetrating the insulating layer.
  • a conductive material such as metal dock, metal copper or other compound conductive materials may be filled in the through hole or covered on the inner wall of the through hole. The conductive material connects to the underlying metal lines through vias and leads to the top of the insulating layer.
  • the above-mentioned top-layer metal lines can be continuously formed on the top of the insulating layer, and the top-layer metal lines and the bottom-layer metal lines are perpendicular to each other, so there is an overlapping position between each metal line on the top layer and the bottom layer.
  • the above-mentioned test via hole can penetrate through the insulating layer at the overlapping position, so as to be able to connect the top metal layer and the bottom metal layer.
  • the forming at least four via holes penetrating through the insulating layer and connecting the first metal layer further includes:
  • One top-layer metal line between the two top-layer metal lines forms at least a pair of auxiliary via holes that penetrate through the insulating layer and respectively connect different bottom-layer metal lines, wherein the distance between the pair of auxiliary via holes is greater than any The distance between the two test vias.
  • an auxiliary via hole may also be formed at the corresponding position of a top-layer metal line between the corresponding positions of the top-layer metal line (not yet formed) where the above-mentioned test via hole is located, and connected underlying metal lines.
  • the bottom metal line of the auxiliary via connection is also located between the two bottom metal lines of the above test via connection, and the bottom metal line of the auxiliary via connection is not connected with other bottom metal lines, so the auxiliary via can be used for testing alone , to provide data to assist in judging the resistance of the via.
  • a top layer metal line can be formed on the insulating layer, and the top layer metal line can be connected to the test via hole and the auxiliary via hole respectively.
  • the method also includes:
  • the dummy vias penetrate through the insulating layer and connect any one of the first metal layer or the second metal layer; the at least two dummy vias
  • the figure surrounded by the holes and the distribution positions of the at least four through holes is centrally symmetrical or axially symmetrical.
  • a dummy via hole penetrating through the insulating layer may also be formed.
  • the location of the dummy via is not the overlapping location of the bottom metal line and the top layer metal line. That is, one end of a dummy via can be connected to a bottom metal line but the other end will not be connected to a top layer metal line, or one end of a dummy via can be connected to a top layer metal line but the other end will not be connected to a top metal line.
  • the bottom metal line is connected, therefore, the top metal line and the bottom metal line are not conducted.
  • the method also includes:
  • An insulating material is filled in the at least two dummy via holes.
  • the dummy via hole can be used to provide support, so that the entire semiconductor structure simulates the structure inside the semiconductor device, reducing the probability of deformation of the test via hole, thereby improving the test performance of the test via hole. Since the dummy via hole does not need to be electrically connected, the inside of the dummy via hole may be filled with an insulating material, and the type of the insulating material may be silicon oxide, silicon nitride, or other organic materials.
  • the dummy via is connected to the first metal layer, and the method further includes:
  • a covering layer is formed, and the covering layer is filled between the top layer metal lines and covers the dummy via holes.
  • One end of the dummy via hole may be connected to the first metal layer, that is, connected to at least one underlying metal line, and penetrate through the insulating layer.
  • the other end of the dummy via hole is exposed on the top of the insulating layer and is located between the top metal lines.
  • a covering layer may be formed after the formation of the second metal layer to cover the dummy via holes exposed on the top of the insulating layer and fill the spaces between the top metal lines of the second metal layer , so that the top-layer metal lines are isolated from each other by the covering layer.
  • the material of the covering layer is an insulating material, which may be silicon oxide, silicon nitride or other organic materials.
  • each layer of metal is connected through via holes.
  • the traditional ISOTest-key IsolationTest-key , isolation test unit
  • ISOTest-key isolation test unit
  • the test structure of the through hole includes a bottom metal line 901 , a top layer metal line 902 and a test via 903 located at the overlapping position of the two metal lines and connecting the two metal lines.
  • the through hole of this structure is easily affected by the surrounding isolation layer, resulting in unstable photolithography process, and there is no other pattern structure (pattern) around the single test through hole, and it is easy to planarize the metal layer in the subsequent process.
  • the test hole is deformed and the test cannot be performed.
  • the resistance value of a single test via hole has a high probability of error, which cannot accurately reflect the resistance value of the actual via hole in the device.
  • the first metal layer 1010 includes a plurality of bottom metal lines 1011
  • the top metal layer 1020 includes a plurality of top metal lines 1021 .
  • four test via holes 1030 are provided, and the four test via holes are connected to the bottom metal line and the top metal line.
  • the two bottom metal lines 1011 and the two top metal lines 1021 respectively connected to the four test vias 1030 are connected through the test pads 1012 and 1022 respectively, so that the four test vias can be tested synchronously by using the test pads.
  • Auxiliary vias 1040 and dummy vias 1050 are also provided outside the four test vias 1030 , wherein the auxiliary vias 1040 can communicate with two metal lines of the first metal layer 1010 and the second metal layer 1020 .
  • the auxiliary via hole 1040 can be used for auxiliary testing, and can also be used for supporting the entire semiconductor structure.
  • dummy via holes 1050 may also be provided. The dummy via hole 1050 is connected to the bottom metal layer 1020 and penetrates the insulating layer between the first metal layer 1010 and the second metal layer 1020 , but is not connected to the top layer metal line.
  • the dummy vias 1050 and other vias can be used to form a stable and symmetrical structure, reducing the possibility of deformation of the test vias. Therefore, the dummy via hole 1050 does not need to be conductive, and the dummy via hole 1050 can be filled with an insulating material, as shown in FIG. 11 .
  • the disclosed devices and methods may be implemented in other ways.
  • the device embodiments described above are only illustrative.
  • the division of the units is only a logical function division.
  • the coupling, or direct coupling, or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be electrical, mechanical or other forms of.
  • the units described above as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units; they may be located in one place or distributed to multiple network units; Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present application can be integrated into one processing unit, or each unit can be used as a single unit, or two or more units can be integrated into one unit; the above-mentioned integration
  • the unit can be realized in the form of hardware or in the form of hardware plus software functional unit.
  • Embodiments of the present application provide a semiconductor structure and a manufacturing method thereof. Through the technical solution provided by the embodiment of this application, at least four via holes are used to connect the first metal layer and the second metal layer. Hole deformation leads to inaccurate testing; on the other hand, multiple through holes are also convenient for flexible testing, making the test results closer to the actual resistance of the through holes inside the device.

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

本申请实施例公开了一种半导体结构及其制造方法。该半导体结构包括：半导体衬底；第一金属层，位于所述半导体衬底表面；第二金属层，位于所述第一金属层表面的上方；绝缘层，位于所述第一金属层和所述第二金属层之间，用于隔离所述第一金属层和第二金属层；至少四个通孔，位于所述绝缘层中，所述至少四个通孔中具有用于连接所述第一金属层和所述第二金属层的导电材料。

Description

半导体结构及其制造方法
相关申请的交叉引用
本申请基于申请号为202110935666.6、申请日为2021年8月16日、申请名称为“半导体结构及其制造方法”的中国专利申请提出，并要求该中国专利申请的优先权，该中国专利申请的全部内容在此引入本申请作为参考。
技术领域
本申请实施例涉及但不限于一种半导体结构及其制造方法。
背景技术
对于存储器、芯片等半导体器件，通常在半导体衬底上采用多层结构来实现。半导体衬底表面的各层电性连接通过金属线来实现，而不同层的金属线则通过通孔连接。通孔的阻值是影响连接性能的重要参数，因此，通常在制造过程中形成测试单元(Test-key)用于进行通孔的电阻测试。
然而测试单元位于器件外围，周围没有其他图形，容易造成通孔变形，导致测试结果难以反映器件内部通孔的实际阻值。
发明内容
本申请实施例提供一种半导体结构及其制造方法。
第一方面，本申请实施例提供的半导体结构，包括：
半导体衬底；
第一金属层，位于所述半导体衬底表面；
第二金属层，位于所述第一金属层表面的上方；
绝缘层，位于所述第一金属层和所述第二金属层之间，用于隔离所述第一金属层和第二金属层；
至少四个通孔，位于所述绝缘层中，所述至少四个通孔中具有用于连接所述第一金属层和所述第二金属层的导电材料。
第二方面，本申请实施例提供一种半导体结构的制造方法，包括：
在半导体衬底表面形成第一金属层；
在所述第一金属层上覆盖绝缘层；
形成贯穿所述绝缘层并连接所述第一金属层的至少四个通孔；
在所述至少四个通孔中填充导电材料；
在所述绝缘层和所述至少四个通孔上形成第二金属层；
所述至少四个通孔中的所述导电材料用于连接所述第一金属层和所述第二金属层。
附图说明
一个或多个实施例通过与之对应的附图中的图片进行示例性说明，除非有特别申 明，附图中的图不构成比例限制。
图1为本申请实施例提供的一种半导体结构的示意图一；
图2为本申请实施例提供的一种半导体结构的示意图二；
图3为本申请实施例提供的一种半导体结构的示意图三；
图4为本申请实施例提供的一种半导体结构的示意图四；
图5为本申请实施例提供的一种半导体结构中第一金属层的示意图；
图6为本申请实施例提供的一种半导体结构的示意图五；
图7为本申请实施例提供的一种半导体结构的制造方法的流程图；
图8A为本申请实施例提供的一种半导体结构的制造方法中同步形成多个通孔的示意图；
图8B为一实施例中形成一个通孔的示意图；
图9为一实施例中半导体结构的示意图；
图10为本申请实施例提供的一种半导体结构的示意图六；
图11为本申请实施例提供的一种半导体结构中虚置通孔位置的剖面图。
具体实施方式
为了便于理解本申请，下面将参照相关附图对本申请进行更全面的描述。附图中给出了本申请的首选实施例。但是，本申请可以以许多不同的形式来实现，并不限于本文所描述的实施例。相反地，提供这些实施例的目的是使对本申请的公开内容更加透彻全面。
除非另有定义，本文所使用的所有的技术和科学术语与属于本申请的技术领域的技术人员通常理解的含义相同。本文中在本申请的说明书中所使用的术语只是为了描述具体的实施例的目的，不是旨在于限制本申请。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本申请实施例提供一种半导体结构，如图1所示，该半导体结构100包括：
半导体衬底110；
第一金属层120，位于所述半导体衬底110表面；
第二金属层130，位于所述第一金属层120表面的上方；
绝缘层140，位于所述第一金属层120和所述第二金属层130之间，用于隔离所述第一金属层120和第二金属层130；
至少四个通孔150，位于所述绝缘层140中，所述至少四个通孔150中具有用于连接所述第一金属层120和所述第二金属层130的导电材料。
在本申请实施例中，上述半导体结构可以为位于半导体器件周围的用于进行测试的测试结构，或称为测试单元。该半导体结构可以在利用晶圆制造各种半导体器件(如存储器、芯片)等的过程中，与半导体器件同步形成。由于该半导体结构与半导体器件相互分离，因此不影响半导体器件的性能。
该半导体结构可以在半导体器件的制造过程中用于进行测试，从而实现半导体器件的制程监控，在完成半导体器件的制造时，可以切割掉上述半导体结构所在的区域，仅保留半导体器件并对半导体器件分别进行封装。当然，也可以将上述半导体结构保留， 并与半导体器件封装在一起，从而便于对产品进行测试。
上述第一金属层与第二金属层为与半导体器件中不同金属层同步形成的金属层，第一金属层与第二金属层均可以具有通过刻蚀等方式形成的图形，例如，线形或者网状。第一金属层与第二金属层之间通过绝缘层相互隔离，绝缘层可以为氧化硅或者氮化硅等绝缘材料制成。
第一金属层与第二金属层之间可以通过通孔相互连接，通孔贯穿绝缘层，并连接到第一金属层与第二金属层。通孔内可以具有金属等导电材料，通过导电材料实现第一金属层与第二金属层之间的电连接。
在本申请实施例中，通孔的数量至少包括四个，这些通孔可以相互间隔分布在不同的位置，并分别连接第一金属层与第二金属层。
由于整个半导体结构中具有多个通孔，因此，相对于如图2所示的半导体结构200中仅具有一个通孔201的测试结构，本申请实施例中的每个通孔的附近都具有其他通孔等结构的支撑。如此，一方面可以减少通孔变形导致测试不准确的情况；另一方面，多个通孔也便于进行灵活地测试，使得测试结果更加接近器件内部通孔的实际阻值。
在一些实施例中，所述第一金属层包括：沿第一方向平行分布的多条底层金属线；
所述第二金属层包括：沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
在本申请实施例中，第一金属层可以为线形的金属线，并且可以包括并排分布的多条金属线。由于第一金属层为靠近衬底表面的金属层，因此，这些金属线可以称为底层金属线。这里，多条底层金属线可以均沿第一方向平行分布，第一方向可以为平行于衬底表面的任意方向，可以以实际制造过程中便于实现的方式为准。
在本申请实施例，第二金属层可以为与第一金属层结构类似的多条平行分布的金属线，相对于第一金属层，第二金属层远离衬底表面，因此可以称为顶层金属线。多条顶层金属线沿着第二方向平行分布。第二方向可以与第一方向相互垂直，这样可以使结构更加稳定。
在一些实施例中，如图3所示，所述至少四个通孔150位于所述第一金属层120中至少两条所述底层金属线121与所述第二金属层130中的至少两条顶层金属线131的交叠位置。
上述第一金属层与第二金属层的金属线相互垂直，因此，第一金属层的各底层金属线与第二金属层的各顶层金属线分别具有交叠的位置。这些交叠的位置在垂直于衬底表面的方向上位于同一直线，因此，可以在这些交叠位置形成上述至少四个通孔，从而实现第一金属层与第二金属层的连接。
由于第一金属层与第二金属层都具有多条金属线，因此可以具有多个交叠位置，每个交叠位置可以形成一个通孔，多个通孔则可以分别位于不同的交叠位置。
在一些实施例中，所述至少四个通孔包括四个测试通孔；其中，所述四个测试通孔分别位于两条顶层金属线与两条底层金属线的四个交叠位置处。
在本申请实施例中，上述半导体结构可以包括四个测试通孔，这些测试通孔用于进行阻值的测试。因此，这些测试通孔所在的金属线可以与外部的测试电路连接。当然， 在测试时也可以采用探针直接接触通孔位置或者金属线的方式进行测试。
四个测试通孔可以位于两条顶层金属线与两条底层金属线的四个交叠位置处，由于每条金属线上连接有两个通孔，且这两个通孔连接至不同的另一层金属线，这样，四个测试通孔可以连接这四条金属线的不同组合，在测试时，从而得到四组测试数据便于进行充分的数据处理，提升测试的可靠性。
在一些实施例中，连接有所述测试通孔的两条顶层金属线之间具有一条间隔的顶层金属线；且连接有所述测试通孔的两条底层金属线之间具有一条间隔的底层金属线。
上述连接有测试通孔的两条顶层金属线以及两层底层金属线都可以不是并列相邻的两条顶层金属线，即两条连接有测试通孔的顶层金属线之间可以具有一条或多条顶层金属线。这里，连接有测试通孔的两条顶层金属线与两条底层金属线之间各有一条间隔的金属线。
如此，一方面可以具有可以使得各测试通孔之间具有一定的间距，提升整体结构的稳定性，另一方面可以减少测试时各通孔之间带来的干扰。
在一些实施例中，如图4所示，所述至少四个通孔150中还包括至少一对辅助通孔151和至少四个测试通孔152，其中，所述至少一对辅助通孔151连接在所述间隔的顶层金属线131或间隔的底层金属线121上，且一对所述辅助通孔151的间距大于任意两个所述测试通孔152的间距。
在一些实施例中，半导体结构中心可设置有辅助通孔。
上述四个通孔之间的间距可以两两相等，从而具有稳定的结构，便于进行测试。此外，各通孔所在的金属线之间还存在间隔的金属线，因此，可以在间隔的金属线上形成辅助通孔，便于进行辅助测试。辅助通孔成对出现并与同一顶层金属线或者底层技术线连接。辅助通孔的间距可以大于上述测试通孔之间的间距，从而不会对测试通孔造成影响。
在一些实施例中，连接所述测试通孔的所述两条顶层金属线之间通过测试焊盘连接；连接所述测试通孔的所述两条底层金属线之间通过测试焊盘连接。
也就是说，测试通孔连接的顶层金属线通过测试焊盘相互连接，底层金属线也通过测试焊盘连接(如图5A所示，测试焊盘501连接了两条底层金属线502)，使得测试通孔之间通过各金属线相互连通。这样，通过外部的一组测试通路就可以实现电阻的测试。各测试通孔之间相互连接，因此可以对测试得到的数据进行计算得到每个通孔平均的阻值。相比于如图5B所示的测试焊盘503仅连接一条底层金属线504的情况，能够更准确地估计半导体器件中各通孔的阻值，从而判断器件是否存在失效的可能。
需要说明的是辅助通孔所连接的金属线并未与测试通孔连接的金属线连通，因此可以进行单独测试。这样，可以在测试过程中提供辅助测试的数据，便于验证测试的可靠性。
在一些实施例中，如图6所示，所述半导体结构100还包括：
至少两个虚置通孔160，所述虚置通孔160贯穿所述绝缘层，且连接所述第一金属层120或所述第二金属层130中的任一层；所述至少两个虚置通孔160与所述至少四个通孔150的分布位置所围成图形呈中心对称或轴对称。
在本申请实施例中，虚置通孔(Dummyvia)是具有与测试通孔或者辅助通孔有类似结构，贯穿绝缘层的通孔。虚置通孔中也可以包含金属等导电材料，但其并不具有连通第一金属层和第二金属层的作用。也就是说，虚置通孔可以仅连接第一金属层或者仅连接第二金属层。
虚置通孔的可以用于支撑整个半导体结构，例如，虚置通孔与其他通孔的位置分布可以呈现中心对称或者轴对称，从而使得半导体结构更加稳定。此外，虚置通孔还可以与测试通孔以及辅助通孔等共同构成模拟半导体器件中实际通孔的结构，使得测试通孔的测试数据更加接近半导体器件中的实际通孔的数据。
在一些实施例中，测试通孔构成以半导体结构中线为轴的第一轴对称分布，第一轴对称分布的测试通孔到半导体结构中心的距离可不相同。辅助通孔和虚置通孔共同构成以半导体结构中线为轴的第二轴对称分布，第二轴对称分布的通孔到半导体结构中心的距离可不相同。第一轴对称分布中的任意两个测试通孔之间的距离，与任意测试通孔到半导体结构中心的距离，之比的范围为1.5～3。第二轴对称分布中的通孔到半导体结构中心的距离，与第一轴对称分布中的通孔到半导体结构中心的距离，之比的范围为大于3。
在一些实施例中，测试通孔构成以半导体结构中心为中心的第一中心对称分布，第一中心对称分布的测试通孔到半导体结构中心的距离相同。辅助通孔和虚置通孔共同构成以半导体结构中心为中心的第二中心对称分布，第二中心对称分布的通孔到半导体结构中心的距离相同。
在一些实施例中，所述虚置通孔中填充有绝缘材料。
这样，虚置通孔可以起到支撑作用，防止其他通孔变形，并防止虚置通孔对第一金属层、第二金属层或者其他通孔产生电性干扰。
在一些实施例中，所述至少四个通孔用于通过开尔文四线检测法进行电阻测试。
开尔文四线检测法又称为四端子检测，或者四点探针法。该方法通过分离电流和电压的电极，可以消除布线和接触电阻的阻抗，从而实现精准地电阻测试。在本申请实施例中，可以利用上述至少四个通孔所连接的金属线分别连接不同的检测端，从而实现四线检测，相比于单点测试的方法，可以提升检测的准确性。
如图7所示，本申请实施例还提供一种半导体结构的制造方法，包括：
步骤S101、在半导体衬底表面形成第一金属层；
步骤S102、在所述第一金属层上覆盖绝缘层；
步骤S103、形成贯穿所述绝缘层并连接所述第一金属层的至少四个通孔；
步骤S104、在所述至少四个通孔中填充导电材料；
步骤S105、在所述绝缘层和所述至少四个通孔上形成第二金属层；所述至少四个通孔中的所述导电材料用于连接所述第一金属层和所述第二金属层。
由于上述半导体结构可以为位于半导体器件周围的用于进行测试的测试结构，因此，该半导体结构的制造过程是在制造半导体器件产品的过程中同步进行的。上述第一金属层、第二金属层以及绝缘层均与半导体器件中的各层对应同步形成。
上述至少四个通孔也与半导体器件中形成通孔的过程同步进行，如图8A所示，在 第一金属层801形成并覆盖绝缘层(图中未示出)后，在多个目标位置同步形成多个通孔802，然后再进行后续第二金属层等的相关制程。相比于如图8B所示的，在第一金属层811上仅形成一个通孔812的方式，可以使得整个结构更加稳定，且更加接近实际半导体器件的结构，从而可以利用这些通孔反映整个制造过程的好坏。
在一些实施例中，所述在半导体衬底表面形成第一金属层，包括：
在半导体表面形成沿第一方向平行分布的多条底层金属线；
所述在所述绝缘层和所述至少四个通孔上形成第二金属层，包括：
在所述绝缘层和所述至少四个通孔上形成多条沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
这里，可以先在半导体衬底表面形成一层金属层，然后通过图形化刻蚀的方式形成多条金属线；也可以先在半导体衬底上形成图形化的掩膜层，然后在掩膜层未遮挡的区域沉积金属并形成多条金属线，然后再区域掩膜层，从而形成具有多条底层金属线的第一金属层。
形成第一金属层后，可以在上面沉积绝缘材料，形成隔离层。
在一些实施例中，所述形成贯穿所述绝缘层并连接所述第一金属层的至少四个通孔，包括：
在两条所述底层金属线的四个目标位置处，形成贯穿所述绝缘层并连接所述底层金属线的四个测试通孔；每条所述底层金属线包括沿第二方向分布两个目标位置，且位于两条所述底层金属线的相邻两个目标位置沿第一方向分布；
在所述绝缘层和所述至少四个通孔上形成多条沿第二方向平行分布的多条顶层金属线，包括：
在沿第一方向分布的两个目标位置上方形成顶层金属线，所述目标位置为两条所述顶层金属线和两条所述底层金属线交叠的位置。
在形成绝缘层之后，可以通过刻蚀等方法在目标位置处对绝缘层进行打孔，形成上述四个测试通孔，通孔的深度即绝缘层的厚度。通过贯穿绝缘层的通孔，可以使得绝缘层表面与底层金属线连通。然后，可以在通孔内填充或者在通孔内壁上覆盖导电材料，如金属坞、金属铜或者其他化合物导电材料等。导电材料通过通孔与底层金属线连接，并连通到绝缘层顶部。
在绝缘层顶部可以继续形成上述顶层金属线，顶层金属线与底层金属线相互垂直分布，因此顶层和底层的每条金属线之间都具有一个交叠的位置。上述测试通孔可以贯穿该交叠位置处的绝缘层，从而能够连接顶层金属层和底层金属层。
在一些实施例中，所述形成贯穿所述绝缘层并连接所述第一金属层的至少四个通孔，还包括：
在两条所述顶层金属线之间的一条顶层金属线形成贯穿所述绝缘层并分别连接不同的底层金属线的至少一对辅助通孔，其中，所述一对辅助通孔的间距大于任意两个所述测试通孔的间距。
在本申请实施例中，形成顶层金属线之前，还可以在上述测试通孔所在的顶层金属线(此时还未形成)对应位置之间的一条顶层金属线对应位置形成辅助通孔，并连接底 层金属线。辅助通孔连接的底层金属线也位于上述测试通孔连接的两条底层金属线之间，并且辅助通孔连接的底层金属线不与其他底层金属线连接，因此辅助通孔可用于单独进行测试，提供辅助判断通孔阻值的数据。
形成上述测试通孔以及辅助通孔后可以在绝缘层上形成顶层金属线，并且顶层金属线可以分别与测试通孔以及辅助通孔连接。
在一些实施例中，所述方法还包括：
形成至少两个虚置通孔，所述虚置通孔贯穿所述绝缘层，且连接所述第一金属层或所述第二金属层中的任一层；所述至少两个虚置通孔与所述至少四个通孔的分布位置所围成图形呈中心对称或轴对称。
在本申请实施例中，在形成绝缘层后以及形成顶层金属线之前，还可以形成贯穿绝缘层的虚置通孔。虚置通孔所在位置并非底层金属线与顶层金属线的交叠位置。也就是说，虚置通孔的一端可以与底层金属线连接，但另一端不会与顶层金属线连接，或者，虚置通孔的一端可以与顶层金属线连接，但另一端则不会与底层金属线连接，因此，不会导通顶层金属线和底层金属线。
在一些实施例中，所述方法还包括：
在所述至少两个虚置通孔中填充绝缘材料。
虚置通孔可以用于提供支撑，使得整个半导体结构模拟半导体器件内部的结构，减少测试通孔变形的概率，从而提升测试通孔的测试性能。由于虚置通孔不需要实现电连接，因此，虚置通孔内部可以填充绝缘材料，绝缘材料的类型可以为氧化硅、氮化硅等材料，也可以为其他有机物材料。
在一些实施例中，所述虚置通孔连接所述第一金属层，所述方法还包括：
形成覆盖层，所述覆盖层填充于所述顶层金属线之间，且覆盖所述虚置通孔。
上述虚置通孔的一端可以连接第一金属层，即连接至少一条底层金属线，并贯穿绝缘层。虚置通孔的另一端则暴露在绝缘层的顶部，且位于顶层金属线之间。
在本申请实施例中，可以在第二金属层形成后继续形成一层覆盖层，将裸露在绝缘层顶部的虚置通孔覆盖住，并填充第二金属层的各条顶层金属线之间，使得各条顶层金属线之间通过覆盖层相互隔离。
覆盖层的材料为绝缘材料，可以为氧化硅、氮化硅或者其他有机物材料等。
本申请实施例还提供如下示例：
对于MOS(Metal-Oxide-SemiconductorField-EffectTransistor，金属氧化物半导体场效应晶体管)器件等的后段工艺(BEOL，BackendofLine)各层金属都是通过通孔进行连接，传统的ISOTest-key(IsolationTest-key，隔离测试单元)一般测试单个通孔的阻值。
如图9所示，但通孔的测试结构包括一条底层金属线901，一条顶层金属线902和位于这两条金属线的交叠位置，并连通这两条金属线的测试通孔903。这种结构的通孔容易受到周围隔离层的影响，导致光刻工艺不稳定，并且单个的测试通孔的周围没有其他图形结构(pattern)，后续对金属层进行平坦化处理等的过程中容易造成测试通孔变形，无法进行测试。此外，单个的测试通孔的阻值出现误差的概率高，不能准确反映器件中的实际通孔的阻值。
本申请实施例中，采用“3×3加2×2”形状的通孔结构。如图10所示，第一金属层1010包括多条底层金属线1011，顶层金属层1020包括多条顶层金属线1021。在两条底层金属线与两条顶层金属线分别相交的四个交叠位置处，设置有四个测试通孔1030，这四个测试通孔的连通底层金属线和顶层金属线。此外，第一金属层1010与第二金属层1020之间具有绝缘层(图中未示出)。
分别与四个测试通孔1030连接的两条底层金属线1011和两条顶层金属线1021分别通过测试焊盘1012和1022连接，这样可以利用测试焊盘同步对四个测试通孔进行测试。
四个测试通孔1030的外部还设置有辅助通孔1040和虚置通孔1050，其中，辅助通孔1040可以连通第一金属层1010和第二金属层1020的两条金属线。辅助通孔1040可以用于进行辅助测试，也可以用于支撑整个半导体结构。此外，为了使整个半导体结构稳定，还可以设置虚置通孔1050。虚置通孔1050与底层金属层1020连接，贯穿第一金属层1010与第二金属层1020之间的绝缘层，但不与顶层金属线向连。
虚置通孔1050与其他通孔可以用于形成稳定对称的结构，减少测试通孔变形的可能。因此，虚置通孔1050无需具有导电性，虚置通孔1050中可以填充绝缘材料，如图11所示。
应理解，说明书通篇中提到的“一个实施例”或“一实施例”意味着与实施例有关的特定特征、结构或特性包括在本申请的至少一个实施例中。因此，在整个说明书各处出现的“在一个实施例中”或“在一实施例中”未必一定指相同的实施例。此外，这些特定的特征、结构或特性可以任意适合的方式结合在一个或多个实施例中。应理解，在本申请的各种实施例中，上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定，而不应对本申请实施例的实施过程构成任何限定。上述本申请实施例序号仅仅为了描述，不代表实施例的优劣。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。
在本申请所提供的几个实施例中，应该理解到，所揭露的设备和方法，可以通过其它的方式实现。以上所描述的设备实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，如：多个单元或组件可以结合，或可以集成到另一个系统，或一些特征可以忽略，或不执行。另外，所显示或讨论的各组成部分相互之间的耦合、或直接耦合、或通信连接可以是通过一些接口，设备或单元的间接耦合或通信连接，可以是电性的、机械的或其它形式的。
上述作为分离部件说明的单元可以是、或也可以不是物理上分开的，作为单元显示的部件可以是、或也可以不是物理单元；既可以位于一个地方，也可以分布到多个网络单元上；可以根据实际的需要选择其中的部分或全部单元来实现本实施例方案的目的。
另外，在本申请各实施例中的各功能单元可以全部集成在一个处理单元中，也可以 是各单元分别单独作为一个单元，也可以两个或两个以上单元集成在一个单元中；上述集成的单元既可以采用硬件的形式实现，也可以采用硬件加软件功能单元的形式实现。
以上所述，仅为本申请的实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。
工业实用性
本申请实施例提供了一种半导体结构及其制造方法。通过本申请实施例提供的技术方案，采用至少四个通孔连接第一金属层和第二金属层，一方面，每个通孔的周围都存在其他的通孔等结构的支撑，可以减少通孔变形导致测试不准确的情况；另一方面，多个通孔也便于进行灵活地测试，使得测试结果更加接近器件内部通孔的实际阻值。

Claims (17)

  1. 一种半导体结构，包括：
    半导体衬底；
    第一金属层，位于所述半导体衬底表面；
    第二金属层，位于所述第一金属层表面的上方；
    绝缘层，位于所述第一金属层和所述第二金属层之间，用于隔离所述第一金属层和第二金属层；
    至少四个通孔，位于所述绝缘层中，所述至少四个通孔中具有用于连接所述第一金属层和所述第二金属层的导电材料。
  2. 根据权利要求1所述的半导体结构，其中，所述第一金属层包括：沿第一方向平行分布的多条底层金属线；
    所述第二金属层包括：沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
  3. 根据权利要求2所述的半导体结构，其中，所述至少四个通孔位于所述第一金属层中至少两条所述底层金属线与所述第二金属层中的至少两条顶层金属线的交叠位置。
  4. 根据权利要求3所述的半导体结构，其中，所述至少四个通孔包括四个测试通孔；其中，所述四个测试通孔分别位于两条顶层金属线与两条底层金属线的四个交叠位置处。
  5. 根据权利要求4所述的半导体结构，其中，连接有所述测试通孔的两条顶层金属线之间具有一条间隔的顶层金属线；且连接有所述测试通孔的两条底层金属线之间具有一条间隔的底层金属线。
  6. 根据权利要求5所述的半导体结构，其中，所述至少四个通孔中还包括至少一对辅助通孔，其中，所述至少一对辅助通孔连接在所述间隔的顶层金属线或间隔的底层金属线上，且一对所述辅助通孔的间距大于任意两个所述测试通孔的间距。
  7. 根据权利要求4所述的半导体结构，其中，连接所述测试通孔的所述两条顶层金属线之间通过测试焊盘连接；连接所述测试通孔的所述两条底层金属线之间通过测试焊盘连接。
  8. 根据权利要求1所述的半导体结构，还包括：
    至少两个虚置通孔，所述虚置通孔贯穿所述绝缘层，且连接所述第一金属层或所述第二金属层中的任一层；所述至少两个虚置通孔与所述至少四个通孔的分布位置所围成图形呈中心对称或轴对称。
  9. 根据权利要求8所述的半导体结构，其中，所述虚置通孔中填充有绝缘材料。
  10. 根据权利要求1所述的半导体结构，其中，所述至少四个通孔用于通过开尔文四线检测法进行电阻测试。
  11. 一种半导体结构的制造方法，包括：
    在半导体衬底表面形成第一金属层；
    在所述第一金属层上覆盖绝缘层；
    形成贯穿所述绝缘层并连接所述第一金属层的至少四个通孔；
    在所述至少四个通孔中填充导电材料；
    在所述绝缘层和所述至少四个通孔上形成第二金属层；
    所述至少四个通孔中的所述导电材料用于连接所述第一金属层和所述第二金属层。
  12. 根据权利要求11所述的方法，其中，所述在半导体衬底表面形成第一金属层，包括：
    在半导体表面形成沿第一方向平行分布的多条底层金属线；
    所述在所述绝缘层和所述至少四个通孔上形成第二金属层，包括：
    在所述绝缘层和所述至少四个通孔上形成多条沿第二方向平行分布的多条顶层金属线；其中，所述第二方向垂直于所述第一方向。
  13. 根据权利要求12所述的方法，其中，所述形成贯穿所述绝缘层并连接所述第一金属层的至少四个通孔，包括：
    在两条所述底层金属线的四个目标位置处，形成贯穿所述绝缘层并连接所述底层金属线的四个测试通孔；每条所述底层金属线包括沿第二方向分布两个目标位置，且位于两条所述底层金属线的相邻两个目标位置沿第一方向分布；
    在所述绝缘层和所述至少四个通孔上形成多条沿第二方向平行分布的多条顶层金属线，包括：
    在沿第一方向分布的两个目标位置上方形成顶层金属线，所述目标位置为两条所述顶层金属线和两条所述底层金属线交叠的位置。
  14. 根据权利要求13所述的方法，其中，所述形成贯穿所述绝缘层并连接所述第一金属层的至少四个通孔，还包括：
    在两条所述顶层金属线之间的一条顶层金属线形成贯穿所述绝缘层并分别连接不同的底层金属线的至少一对辅助通孔，其中，所述一对辅助通孔的间距大于任意两个所述测试通孔的间距。
  15. 根据权利要求12所述的方法，还包括：
    形成至少两个虚置通孔，所述虚置通孔贯穿所述绝缘层，且连接所述第一金属层或所述第二金属层中的任一层；所述至少两个虚置通孔与所述至少四个通孔的分布位置所围成图形呈中心对称或轴对称。
  16. 根据权利要求15所述的方法，还包括：
    在所述至少两个虚置通孔中填充绝缘材料。
  17. 根据权利要求16所述的方法，其中，所述虚置通孔连接所述第一金属层，所述方法还包括：
    形成覆盖层，所述覆盖层填充于所述顶层金属线之间，且覆盖所述虚置通孔。
PCT/CN2021/116890 2021-08-16 2021-09-07 半导体结构及其制造方法 Ceased WO2023019657A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/672,757 US12334415B2 (en) 2021-08-16 2022-02-16 Through vias with test structure

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110935666.6 2021-08-16
CN202110935666.6A CN115706072B (zh) 2021-08-16 2021-08-16 半导体结构及其制造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US17/672,757 Continuation US12334415B2 (en) 2021-08-16 2022-02-16 Through vias with test structure

Publications (1)

Publication Number Publication Date
WO2023019657A1 true WO2023019657A1 (zh) 2023-02-23

Family

ID=85181228

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/116890 Ceased WO2023019657A1 (zh) 2021-08-16 2021-09-07 半导体结构及其制造方法

Country Status (2)

Country Link
CN (1) CN115706072B (zh)
WO (1) WO2023019657A1 (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118657109A (zh) * 2024-08-20 2024-09-17 杭州广立微电子股份有限公司 一种测试结构的版图设计方法、测试结构及可读存储介质
CN118969775A (zh) * 2024-07-31 2024-11-15 浙江创芯集成电路有限公司 测试结构及其形成方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030230810A1 (en) * 2002-06-12 2003-12-18 Nec Electronics Corporation Semiconductor device including evaluation elements
CN102064155A (zh) * 2009-11-17 2011-05-18 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105097778A (zh) * 2014-04-23 2015-11-25 中芯国际集成电路制造(上海)有限公司 用于改进斜坡电流测试检测能力的通孔阵列测试结构
CN109786359A (zh) * 2017-11-13 2019-05-21 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN110335861A (zh) * 2019-07-08 2019-10-15 上海华虹宏力半导体制造有限公司 一种半导体器件及其制作方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20100080236A (ko) * 2008-12-31 2010-07-08 주식회사 동부하이텍 반도체 제조용 모니터링 패턴 및 그 제조 방법
JP7070848B2 (ja) * 2018-07-26 2022-05-18 住友電工デバイス・イノベーション株式会社 半導体装置の製造方法
KR20200111369A (ko) * 2019-03-19 2020-09-29 삼성전자주식회사 잔여 테스트 패턴을 포함하는 반도체 장치
CN112731101B (zh) * 2020-12-18 2023-09-12 江苏物联网研究发展中心 一种集成电路连通率测试系统及其制作方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030230810A1 (en) * 2002-06-12 2003-12-18 Nec Electronics Corporation Semiconductor device including evaluation elements
CN102064155A (zh) * 2009-11-17 2011-05-18 台湾积体电路制造股份有限公司 半导体器件及其制造方法
CN105097778A (zh) * 2014-04-23 2015-11-25 中芯国际集成电路制造(上海)有限公司 用于改进斜坡电流测试检测能力的通孔阵列测试结构
CN109786359A (zh) * 2017-11-13 2019-05-21 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN110335861A (zh) * 2019-07-08 2019-10-15 上海华虹宏力半导体制造有限公司 一种半导体器件及其制作方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118969775A (zh) * 2024-07-31 2024-11-15 浙江创芯集成电路有限公司 测试结构及其形成方法
CN118657109A (zh) * 2024-08-20 2024-09-17 杭州广立微电子股份有限公司 一种测试结构的版图设计方法、测试结构及可读存储介质

Also Published As

Publication number Publication date
CN115706072B (zh) 2025-08-01
CN115706072A (zh) 2023-02-17

Similar Documents

Publication Publication Date Title
US12334415B2 (en) Through vias with test structure
US7934429B2 (en) Stress-distribution detecting semiconductor package group and detection method of stress distribution in semiconductor package using the same
TWI601222B (zh) 具有監控鏈與測試導線之積體電路測試結構
US9081050B2 (en) Semiconductor device and test method
US7939936B2 (en) Semiconductor package having semiconductor device featuring externally-accessible endless ring-shaped resistance circuit
KR20040010267A (ko) 다층 배선을 갖는 반도체 집적 회로 장치
WO2023019657A1 (zh) 半导体结构及其制造方法
CN115706073B (zh) 半导体结构及其制造方法
US20070210306A1 (en) Test pattern for measuring contact short at first metal level
CN102054809B (zh) 一种重布线机构
US20230048600A1 (en) Semiconductor structure and method for manufacturing semiconductor structure
WO2022048232A1 (zh) 半导体器件及其制作方法
US10796973B2 (en) Test structures connected with the lowest metallization levels in an interconnect structure
US7808248B2 (en) Radio frequency test key structure
US7308395B2 (en) Simulation circuit pattern evaluation method, manufacturing method of semiconductor integrated circuit, test substrate, and test substrate group
TWI919446B (zh) 半導體結構及其製造方法
CN119907611B (zh) 显示面板母板、显示面板母板的制备方法及测试方法
JPH10313033A (ja) 半導体装置及びその製造方法
TW202545344A (zh) 半導體結構及其製造方法
CN119923163A (zh) 显示装置、显示装置的制备方法及测试方法
KR20100087811A (ko) 테스트 패턴을 구비한 반도체 소자
KR20030087294A (ko) 반도체소자의 테스트 패턴
CN108573888A (zh) 用于栅极介电完整性测试的结构
KR100192578B1 (ko) 비아 저항 체크 패턴 형성 방법
CN119907574A (zh) 显示面板、显示装置、制备方法及测试方法和测试装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21953893

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21953893

Country of ref document: EP

Kind code of ref document: A1