WO2023015456A1 - 封装结构及电子装置 - Google Patents

封装结构及电子装置 Download PDF

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Publication number
WO2023015456A1
WO2023015456A1 PCT/CN2021/111866 CN2021111866W WO2023015456A1 WO 2023015456 A1 WO2023015456 A1 WO 2023015456A1 CN 2021111866 W CN2021111866 W CN 2021111866W WO 2023015456 A1 WO2023015456 A1 WO 2023015456A1
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WO
WIPO (PCT)
Prior art keywords
shape memory
memory object
wiring
temperature
packaging
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Application number
PCT/CN2021/111866
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English (en)
French (fr)
Inventor
吴鸣
向志强
丁飞
王启东
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to PCT/CN2021/111866 priority Critical patent/WO2023015456A1/zh
Priority to EP21953087.0A priority patent/EP4362069A1/en
Priority to CN202180099506.0A priority patent/CN117561590A/zh
Publication of WO2023015456A1 publication Critical patent/WO2023015456A1/zh
Priority to US18/437,428 priority patent/US20240178160A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/62—Protection against overvoltage, e.g. fuses, shunts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H85/02—Details
    • H01H85/04—Fuses, i.e. expendable parts of the protective device, e.g. cartridges
    • H01H85/041—Fuses, i.e. expendable parts of the protective device, e.g. cartridges characterised by the type
    • H01H85/046—Fuses formed as printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/49—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions wire-like arrangements or pins or rods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/562—Protection against mechanical damage
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0201—Thermal arrangements, e.g. for cooling, heating or preventing overheating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01H—ELECTRIC SWITCHES; RELAYS; SELECTORS; EMERGENCY PROTECTIVE DEVICES
    • H01H85/00—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive
    • H01H2085/0004—Protective devices in which the current flows through a part of fusible material and this current is interrupted by displacement of the fusible material when this current becomes excessive making use of shape-memory material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/63—Connectors not provided for in any of the groups H01L24/10 - H01L24/50 and subgroups; Manufacturing methods related thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0302—Properties and characteristics in general
    • H05K2201/0308—Shape memory alloy [SMA]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10265—Metallic coils or springs, e.g. as part of a connection element

Definitions

  • the present application relates to the technical field of semiconductors, in particular to a packaging structure and an electronic device.
  • SMT Surface-mount technology
  • Power semiconductor devices such as power supplies are soldered on a printed circuit board (PCB) in the form of SMT secondary packaging to supply power to the single board.
  • PCB printed circuit board
  • Overcurrent refers to the abnormal current carried by electrical components, that is, beyond the normal working current range.
  • Embodiments of the present application provide a packaging structure and an electronic device with overcurrent self-protection capability.
  • the present application provides a packaging structure, including a power semiconductor device, a wiring and a shape memory, the wiring is electrically connected to the power semiconductor device; the shape memory is in contact with the wiring, and the shape memory is used for the shape memory When the temperature is not less than the preset temperature, the deformation occurs, so that the wiring is cut off or the current in the wiring is reduced.
  • the preset temperature is the temperature at which the shape memory object starts to deform.
  • a trace break means that the current in the trace is cut off.
  • the heat formula Q I 2 R, wherein, Q represents heat, I represents current, and R represents impedance.
  • Power semiconductor devices will generate heat when there is overcurrent, causing the external temperature to rise.
  • the external temperature refers to the temperature of the environment where the shape memory object is located.
  • the heat generated when the power semiconductor device is overcurrent is conducted to the shape memory object.
  • the temperature of the shape memory material increases.
  • the shape memory object rises to a preset temperature, the shape memory object begins to deform.
  • the deformation of the shape memory object leads to the disconnection of the wiring or the reduction of the current in the wiring, which reduces the generation of heat, delays the rise of the external temperature, reduces the influence of the overcurrent of the power semiconductor device on the circuit board, and greatly reduces the circuit board being damaged.
  • the shape memory object is an over-current protection structure of the package structure, that is, the package structure has an over-current (over-temperature) self-protection capability. Even if the power semiconductor device is damaged due to overcurrent, the burned package structure can be directly removed, and the circuit board can be retained for reuse.
  • the contact between the shape memory object and the wiring includes two situations: (1) the shape memory object is in insulated contact with the wiring; (2) the shape memory object is in electrical contact with the wiring.
  • the shape memory object deforms when the temperature of the shape memory object reaches a preset temperature, so as to apply stress generated during the deformation to the wiring to break the wiring and thereby cut off the current flow.
  • the shape memory acts as part of the flow through structure of the package structure.
  • the shape memory object is used to deform when the temperature of the shape memory object reaches a preset temperature. For example, the elongation of the shape memory object will increase the impedance in the flow structure formed by the shape memory object and the wiring, thereby reducing the trace current.
  • the traces are copper wires.
  • the resistivity of the shape memory material is usually more than 20 times the resistivity of the copper wire. If the power semiconductor device is over-current, due to the high resistivity of the shape memory object, a large amount of heat will be concentrated on the shape memory object and then the shape memory object will be fused, causing the wiring to be cut off.
  • the deformation of the shape memory object can cause the wires to break due to the stress of the deformation of the shape memory object, causing the wires to break.
  • the traces are at least partially encapsulated in a shape memory object, and the stress generated when the shape memory object deforms acts on the traces, so that the traces Line breaks.
  • the traces are at least partially encapsulated in the shape memory object, that is, the shape memory object surrounds at least part of the outer wall of the traces, so as to increase the contact area between the shape memory object and the traces.
  • the shape memory object When the shape memory object is deformed, it will arch, causing the part of the wires surrounded by it to bend and break under force.
  • the shape memory substance is a polymer with a one-way shape memory effect, or Ceramics with a one-way shape memory effect.
  • the packaging structure further includes a packaging medium
  • the shape memory is A shape memory alloy with a one-way shape memory effect
  • the shape memory object is encapsulated in an encapsulation medium
  • the shape memory object is used to deform when the temperature of the shape memory object reaches a preset temperature. In this way, the wire can be interrupted or the current in the wire can be reduced.
  • the length of the shape memory object is elongated, which increases the impedance in the flow structure formed by the shape memory object and the wiring, and reduces the impedance in the wiring. current, thereby reducing the possibility of trace overcurrent.
  • the wiring includes a first extension, a second extension part and the connecting part, the first end of the connecting part is in electrical contact with the first extending part, the second end of the connecting part is in electrical contact with the second extending part, and the shape memory object is located between the first extending part and the second extending part.
  • the shape memory object and the wiring are arranged at intervals.
  • the shape memory object is wound around the outer wall of the connecting part .
  • the shape memory object is disposed in close contact with the connecting portion.
  • the shape memory object is a shape with a one-way shape memory effect
  • the memory alloy the package structure also includes a solder formation, the solder formation is fixedly connected to the wiring, the solder formation is located outside the packaging medium, the shape memory is implanted in the solder formation, one end of the shape memory is electrically connected to the wiring, the shape The other end of the memory object is used for electrical connection with the circuit board, and the shape memory object is used to elongate when the temperature of the shape memory object reaches a preset temperature, so as to increase the impedance in the flow structure of the package structure, thereby reducing the wiring in the current.
  • Implanting the shape memory substance into the solder formation means that the shape memory substance is buried in the solder formation and surrounded by the solder formation.
  • the solder formation includes solder. While the package structure realizes overcurrent protection, the internal circuit structure of the package structure does not need to be changed, which facilitates the preparation of the package structure.
  • the shape memory object is an elastic structure
  • the shape memory object The initial state is the compressed state or the natural state.
  • the initial state of the shape memory is a compressed state.
  • the shape memory object is elongated.
  • the elastic force of the shape memory object combined with the stress generated when the shape memory object deforms acts on the wiring, causing the wiring to break.
  • the wiring and the shape memory object are electrically Contact forms a flow-through structure
  • the shape-memory object is used to elongate when the temperature of the shape-memory object reaches the preset temperature, and the resistance of the flow-through structure after the deformation of the shape-memory object is greater than that of the shape-memory object
  • the impedance of the flow-through structure before the material is deformed reduces the current in the wiring, thereby reducing the possibility of overcurrent in the wiring.
  • the present application provides an electronic device, including the packaging structure and the circuit board according to the first aspect or the first to ninth possible implementations of the first aspect of the application, and the circuit board is provided with a control
  • the circuit and the packaging structure are fixed on the circuit board through solder formations, the traces of the packaging structure are electrically connected to the control circuit on the circuit board, and the control circuit is used to control the on and off of the power semiconductor device.
  • FIG. 1 is a schematic diagram of an electronic device provided in the first embodiment of the present application.
  • FIG. 2 is a schematic diagram of the package body provided in the first embodiment of the present application.
  • Figure 3a is a schematic diagram of the initial state of the shape memory object
  • Fig. 3b is a schematic diagram of a possible bending structure formed when the shape memory object is deformed
  • Figure 3c is a schematic diagram of another possible bending structure formed when the shape memory object is deformed
  • FIG. 5 is a schematic diagram of a package structure provided in a second embodiment of the present application.
  • Figure 6a is a schematic diagram of a possible structure when the wiring and the shape memory object are spaced apart and the temperature of the shape memory object is lower than the preset temperature;
  • Figure 6b is a schematic diagram of a possible structure when the wiring and the shape memory object are spaced apart and the temperature of the shape memory object is not less than a preset temperature;
  • Fig. 7a is a schematic diagram of a possible structure when the shape memory is wound around the wiring and the temperature of the shape memory is lower than the preset temperature;
  • Fig. 7b is a schematic diagram of a possible structure when the shape memory is wound around the wiring and the temperature of the shape memory is not lower than a preset temperature;
  • FIG. 8 is a schematic diagram of another possible structure when the shape memory object is wound around the wiring and the temperature of the shape memory object is not lower than a preset temperature;
  • Figure 9a is a schematic diagram of a possible structure when the shape memory object is close to the wiring and the temperature of the shape memory object is lower than the preset temperature;
  • Figure 9b is a schematic diagram of a possible structure when the shape memory object is close to the wiring and the temperature of the shape memory object is not less than a preset temperature;
  • FIG. 10 is a schematic diagram of an electronic device provided in a third embodiment of the present application.
  • the packaging structure of power semiconductor devices such as power supplies is welded on the circuit board for power supply. Other electronic components are usually arranged on the circuit board.
  • the packaging structure includes power semiconductor devices, wiring and packaging media (also known as plastic packaging). Power semiconductor devices and wiring are packaged in packaging media.
  • the trace material is usually copper.
  • the melting point of copper is approximately 1085°C.
  • a power semiconductor device is generally an integrated circuit (ie, a Si chip) disposed on a Si substrate.
  • the withstand temperature of Si can reach 1414°C.
  • the usual tolerance temperature of the circuit board is about 350°C. It can be seen that the tolerance temperature of the circuit board is the lowest.
  • the external temperature is the temperature of the environment where the package structure is located.
  • the power semiconductor device may burn, and the burning will spread to the packaging medium and the circuit board along the wiring. Since the tolerance temperature of the circuit board is low, when the external temperature exceeds the tolerance temperature of the circuit board, the high temperature may easily cause damage to the circuit board. Therefore, an overcurrent of a power semiconductor device may lead to the scrapping of an entire circuit board.
  • the present application provides a packaging structure including a power semiconductor device.
  • the power semiconductor device generates heat when the power semiconductor device is overcurrent.
  • the current in the small traces realizes the over-current (over-temperature) self-protection capability of the package structure, reduces the possibility of the circuit board being damaged, and thus improves the safety and reliability of the electronic device.
  • the packaging structure provided in this application can be applied in various electronic devices that need to use power semiconductor devices.
  • Power semiconductor devices are used for power conversion processing, including frequency conversion, voltage conversion, current conversion, power management and so on.
  • the electronic device may be an electrical energy conversion device requiring the use of power semiconductor devices.
  • the power conversion device can be mounted on the power conversion equipment to complete various power functions of the equipment.
  • the electronic device of the present application can be applied in the field of electric vehicle power system, that is, the electric energy conversion equipment can be an electric vehicle, wherein the electronic device can be a motor controller, and the packaging structure can be a power conversion unit assembled in the motor controller;
  • the device can also be an on-board charger (OBC), and the packaging structure is an energy conversion unit;
  • the electronic device can also be a low-voltage control power supply, and the packaging structure is a DC-DC conversion unit therein.
  • OBC on-board charger
  • the electronic device of the present application is not limited to the field of electric vehicles, and can also be widely used in the fields of traditional industrial control, communication, smart grid, electrical appliances, etc., for example, it can be applied to uninterruptible power supplies in data centers supply, UPS), inverters for photovoltaic power generation equipment, power supplies for servers, switching power supplies for electrical appliances (such as refrigerators), etc. It can be understood that this application does not limit electronic devices to power conversion devices, that is, this application does not limit power semiconductor devices to perform power conversion, and power semiconductor devices can also be used in electronic devices to change voltage, frequency, etc. to achieve circuit control functions.
  • UPS data centers supply
  • inverters for photovoltaic power generation equipment power supplies for servers
  • switching power supplies for electrical appliances such as refrigerators
  • this application does not limit electronic devices to power conversion devices, that is, this application does not limit power semiconductor devices to perform power conversion, and power semiconductor devices can also be used in electronic devices to change voltage, frequency, etc. to achieve circuit control functions.
  • the first embodiment of the present application provides an electronic device 100 , including a circuit board 10 and a package structure 30 soldered on the circuit board 10 .
  • the circuit board 10 may be a network single board.
  • the package structure 30 includes a package body 301 and a solder formation 303 .
  • the package body 301 is soldered on the circuit board 10 through the solder formation 303 .
  • the packaging structure 30 is an embedded component packaging (embedded component packaging, ECP), and a solder formation 303 is formed between the packaging body 301 and the circuit board 10 through a reflow process, and then the packaging body 301 is welded to the circuit plate 10.
  • ECP embedded component packaging
  • the air or nitrogen is heated to a high enough temperature and blown to the circuit board on which the components have been pasted, so that the solder on both sides of the components is melted and bonded to the circuit board.
  • the solder formation 303 is located outside the package body 301 .
  • the soldering temperature of the reflow soldering process is 260°C. It can be understood that the solder formation 303 can also be pre-assembled on the package body 301 .
  • the package body 301 includes a power semiconductor device 31 , wires 33 , package medium 35 and shape memory 37 .
  • the power semiconductor device 31 is packaged in the packaging medium 35 , and a part of the wiring 33 is packaged in the packaging medium 35 .
  • the power semiconductor device 31 is electrically connected to the wiring 33 .
  • the circuit board 10 is provided with a control circuit 11 (as shown in FIG. 1 ).
  • the control circuit 11 includes but not limited to capacitors, inductors and other electronic devices.
  • the wiring 33 is electrically connected to the control circuit 11 of the circuit board 10 .
  • the control circuit 11 is used to control the turn-on and turn-off of the power semiconductor device 31 to realize power conversion.
  • the remaining part of the wiring 33 is encapsulated in the shape memory object 37 , that is, the part of the wiring 33 is in insulated contact with the shape memory object 37 .
  • the shape memory object 37 is used for deforming when the temperature of the shape memory object 37 is not lower than a preset temperature, so as to break the wiring 33 and thereby cut off the current. It can be understood that the package body 301 may also include other components, such as capacitors.
  • the preset temperature is the temperature at which the shape memory object begins to deform (phase transition).
  • the external temperature refers to the temperature of the environment where the shape memory object 37 is located.
  • the heat generated when the power semiconductor device 31 is overcurrent is conducted to the shape memory material 37 .
  • the shape memory object 37 rises to a preset temperature, the shape memory object 37 is deformed.
  • the stress generated when the shape memory object 37 is deformed acts on the wiring 33 , so that the wiring 33 breaks, and then the wiring 33 is cut off.
  • the shape memory object 37 is an overcurrent protection structure of the package structure 30.
  • the shape memory object 37 is deformed and the wiring 33 is cut off, that is, the package structure 30 has an overcurrent self-protection structure. ability, thereby prolonging the service life of the circuit board 10 .
  • the packaging structure 30 in the circuit board assembly 100 is damaged due to overcurrent, the damaged packaging structure 30 can be removed directly, and the circuit board 10 can be retained for reuse.
  • the power semiconductor device 31 is packaged in the packaging medium 35 , which means that the packaging medium 35 wraps (or surrounds) the power semiconductor device 31 .
  • a part of the wiring 33 is encapsulated in the packaging medium 35 , which means that the packaging medium 35 wraps (or surrounds) a part of the wiring 33 .
  • the rest of the traces 33 are encapsulated in the shape memory 37 .
  • the remaining part of the trace 33 is encapsulated in the shape memory object 37 , which means that the shape memory object 37 covers at least part of the outer surface of the trace 33 .
  • the shape memory object 37 is also used as a plastic package of the package structure 30 to encapsulate the wiring 33 .
  • the wiring 33 is a copper wiring. It can be understood that the wires 33 may be wires made of other materials, for example, gold, etc., and the material of the wires 33 is not limited in this application.
  • the packaging medium 35 is an ajinomoto build-up film (ABF film). It can be understood that the packaging medium 35 is not limited to the ABF film, and it can also be a plastic package made of other materials.
  • the shape memory object 37 and the packaging medium 35 are stacked.
  • the shape memory object 37 is arranged close to the outermost layer of the packaging medium 35 and is arranged on the side of the packaging body 301 away from the circuit board 10 (as shown in FIG. 1 ), so that the shape memory object 37 is arranged on the packaging medium 35 conveniently. .
  • the shape memory material 37 is a polymer having a one-way shape memory effect.
  • the one-way shape memory effect refers to the deformation that occurs when the shape memory object 37 can return to a low temperature when heated.
  • Shape memory 37 is a smart thermosensitive polymer.
  • Smart thermosensitive polymer is a kind of polymer material that can have a predetermined response to the change of its own temperature, that is, the change of its own temperature prompts the microstructure of the polymer to undergo a predetermined response, so that the specific macroscopic properties of the polymer can be adjusted accordingly. corresponding changes occur.
  • Heat-sensitive shape memory polymer is a kind of smart material. After being deformed and fixed, this kind of polymer product can automatically return to its original shape under specific external conditions-heat stimulation. It can be understood that the shape memory object 37 can also be a ceramic having a one-way shape memory effect.
  • the shape memory object 37 will deform when the temperature of the shape memory object 37 is not lower than the preset temperature, and the stress generated when the shape memory object 37 deforms acts on the wiring 33 , causing the wiring 33 to bend and break under force.
  • the initial shape of the shape memory object 37 is flat (as shown in FIG. 3 a ).
  • the shape memory object 37 maintains the original shape.
  • heat will be released, thereby increasing the external temperature.
  • the temperature of the shape memory object 37 increases as the external temperature increases.
  • the shape memory object 37 is deformed to form a curved structure.
  • the shape memory material 37 will form an arched structure as shown in FIG. 3b or FIG. 3c.
  • the stress generated by the bending and arching of the shape memory object 37 acts on the wire 33 , and the wire 33 is bent and broken under the force, so that the wire 33 is cut off.
  • the preset temperature is greater than 260°C and not greater than 500°C, so that the shape memory object 37 can resist the high temperature when the package body 301 and the circuit board 10 are reflowed, and the shape memory object 37 can be used in the power semiconductor device.
  • the present application does not limit the range of the preset temperature, and the preset temperature can be set as required.
  • the position of the shape memory object 37 in the package body 301 is not limited, and at least part of the wiring 33 is encapsulated in the shape memory object 37.
  • the side of the body 301 close to the circuit board 10 (as shown in FIG. 4 ), or the shape memory object 37 is covered by the packaging medium 35 .
  • the shape memory 37 replaces all of the packaging medium 35 , that is, the power semiconductor device 31 is packaged in the shape memory 37 , and the wiring 33 is packaged in the shape memory 37 .
  • the difference between the package structure provided by the second embodiment of the present application and the package structure provided by the first embodiment is that the shape memory object 37 is a shape memory alloy, and the shape memory object 37 is in electrical contact with the wiring 33 .
  • the encapsulation structure 30 includes a flow-through structure, and the flow-through structure includes a wire 33 and a shape memory object 37 .
  • the shape memory object 37 is fixedly connected to the wiring 33 , and the shape memory object 37 is electrically connected to the wiring 33 .
  • the shape memory object 37 serves as a part of the flow-through structure of the encapsulation structure 30 .
  • the shape memory material 37 is a shape memory alloy.
  • Shape memory alloys SMA are functional metal materials with shape memory effect and superelasticity. For general metal materials, when the deformation exceeds the elastic limit, permanent deformation will occur, which is called plastic deformation, and it cannot be fully restored when it is heated or stress unloaded while it is in a solid state. But shape memory alloys are different. Shape memory alloys have shape memory effects and superelasticity, that is, solid materials with a certain shape undergo plastic deformation at lower temperatures or when stress is , the shape memory alloy can return to the shape before deformation.
  • the shape memory effect can be divided into three types: one-way shape memory effect, two-way shape memory effect and full-range shape memory effect.
  • the one-way shape memory effect means that the alloy can recover the deformation at low temperature when heating and heating; after special heat treatment for some alloys, it can not only recover the deformation at low temperature when heating and heating, but also can be in the process of phase transformation when the temperature is lowered. Recovering the deformation at high temperature is called the two-way shape memory effect; the shape memory alloy with the two-way shape memory effect shows the opposite shape at low temperature and high temperature, which is called the full-range shape memory effect.
  • Table 1 exemplarily shows the tensile strength, elongation, austenite transformation initiation temperature (As) and shape memory recovery strain of some titanium-based high-temperature memory alloys.
  • a titanium-based high-temperature memory alloy with an austenite transformation initiation temperature (As) greater than 260° C. and not greater than 500° C. can be selected for use in the second embodiment.
  • R ⁇ L/S, where ⁇ is the resistivity, L is the length, and S is the area.
  • ⁇ is the resistivity
  • L is the length
  • S is the area.
  • the shape memory object 37 elongates when the temperature of the shape memory object 37 is not lower than the preset temperature, thereby increasing the impedance of the flow-through structure and reducing the possibility of overcurrent in the wiring 33 .
  • the wiring 33 is a copper wire, and the resistivity of the shape memory object 37 is more than 20 times that of the wiring 33 .
  • the contact area between the shape memory object 37 and the wiring 33 is larger than that between the wiring 33 and the wiring 33.
  • the contact area is at least one hundredth smaller. According to the law of resistance, the impedance of the flow-through structure after the shape memory object 37 is deformed is more than 2000 times the original impedance of the flow-through structure when the shape memory object 37 is not deformed.
  • the shape memory material 37 can be fused to cut off the current in the wiring 33 .
  • the wiring 33 includes a first extending portion 331 , a second extending portion 333 and a connecting portion 335 .
  • the first extension portion 331 extends along a first direction (the transverse direction in FIG. 6 a ).
  • the second extension portion 333 extends along the first direction (the transverse direction in FIG. 6 a ).
  • the first extension portion 331 is electrically connected to the power semiconductor device 31 .
  • the shape memory object 37 is a shape memory alloy having a one-way shape memory effect.
  • connection portion 335 A first end of the connection portion 335 is in electrical contact with the first extension portion 331 , a second end of the connection portion 335 is in electrical contact with the second extension portion 333 , and the connection portion 335 is located between the first extension portion 331 and the second extension portion 333 .
  • the shape memory object 37 is spaced apart from the connecting portion 335 .
  • the shape memory object 37 is an elastic structure, for example, the shape memory object 37 can be coiled into a columnar spring structure. It can be understood that the shape memory object 37 can also be an elastic structure of other shapes.
  • the initial state of the shape memory object 37 includes a natural state, a compressed state and a stretched state.
  • the shape memory object 37 is in a natural state when no external force is applied.
  • the height of the shape memory object 37 in the compressed state is smaller than that in the natural state.
  • the height of the shape memory object 37 in the stretched state is greater than that in the natural state. Assume that when the temperature of the shape memory object 37 is lower than the preset temperature, the state of the shape memory object 37 is the initial state.
  • the initial state of the shape memory material 37 is a compressed state.
  • the shape memory object 37 is deformed and elongated.
  • the elastic force of the shape memory object 37 combined with the stress generated when the shape memory object 37 deforms acts on the first extension portion 331, so that the connecting portion 335 is separated from the first extension portion 331 (as shown in FIG. 6 b ), and the wiring 33 directly fracture.
  • the elastic force of the shape memory object 37 combined with the stress generated when the shape memory object 37 deforms acts on the second extension portion 333 , so that the connection portion 335 is separated from the second extension portion 333 , and the wiring 33 is broken.
  • the shape memory 37 can directly break the wiring 33 and cut off the current.
  • the connecting portion 335 is located between the two shape memory objects 37 to shorten the time for breaking the wiring 33 and improve the overcurrent protection efficiency of the package structure 30 . It can be understood that the present application does not limit the number of shape memory objects 37 .
  • the shape memory material 37 is wound (winded) on the outer wall of the trace 33 .
  • the wiring 33 includes a first extending portion 331 , a second extending portion 333 and a connecting portion 335 .
  • the first extension portion 331 extends along a first direction (transverse direction in FIG. 7a ).
  • the second extension portion 333 extends along the first direction (transverse direction in FIG. 7a ).
  • a first end of the connection portion 335 is in electrical contact with the first extension portion 331
  • a second end of the connection portion 335 is in electrical contact with the second extension portion 333
  • the connection portion 335 is located between the first extension portion 331 and the second extension portion 333 .
  • the shape memory material 37 is wound on the outer wall of the connecting portion 335 .
  • the initial state of the shape memory material 37 is a compressed state.
  • the shape memory object 37 is elongated.
  • the elastic force of the shape memory object 37 combined with the stress generated when the shape memory object 37 deforms acts on the first extension portion 331, so that the connecting portion 335 is separated from the first extension portion 331 (as shown in FIG. 7b ), and the wiring 33 directly broken.
  • the elastic force of the shape memory object 37 combined with the stress generated when the shape memory object 37 deforms acts on the second extension portion 333 , so that the connection portion 335 is separated from the second extension portion 333 , and the wiring 33 is broken.
  • the shape memory 37 when the shape memory 37 is not blown, the shape memory 37 can directly break the wiring 33 and cut off the current. It can be understood that the initial state of the shape memory object 37 can also be a natural state, since the shape memory object 37 is restricted by the first extension portion 331 and the second extension portion 333 during the elongation process, the shape memory object 37 is compressed.
  • the shape memory 37 is wound (winded) on the outer wall of the wire 33 (as shown in FIG. 7 a ), and the initial state of the shape memory 37 is a natural state.
  • the shape memory object 37 is stretched or bent. Since the shape memory object 37 is restricted by the first extension portion 331 and the second extension portion 333 during the elongation process, the shape memory object 37 bends, causing the connecting portion 335 to bend along with the shape memory object 37 (as shown in FIG. 8 ).
  • the bending deformation of the connecting portion 335 reduces the contact area between the connecting portion 335 and the first extending portion 331 until it is separated from the first extending portion 331 , and/or the connecting portion 335 is separated from the second extending portion 333 .
  • the shape memory object 37 is placed close to the connecting portion 335 (as shown in FIG. 9 a ), and the initial state of the shape memory object 37 is a natural state.
  • the temperature of the shape memory object 37 is not lower than the preset temperature, the shape memory object 37 is elongated. Since the shape memory object 37 is restricted by the first extension portion 331 and the second extension portion 333 during the elongation process, the shape memory object 37 bends, causing the connecting portion 335 to deform along with the bending of the shape memory object 37 (as shown in FIG. 9b ).
  • the bending deformation of the connecting portion 335 reduces the contact area between the connecting portion 335 and the first extending portion 331 until it is separated from the first extending portion 331 , and/or the connecting portion 335 is separated from the second extending portion 333 .
  • the electrical contact method between the shape memory object 37 and the wiring 33 is not limited to the examples in this application.
  • the shape memory object 37 deforms when the temperature of the shape memory object 37 is not less than the preset temperature.
  • the stress acts on the wiring 33, so that the wiring 33 is broken to realize the flow interruption of the wiring 33; or, the shape memory object elongates when the temperature of the shape memory object 37 is not less than the preset temperature, increasing the flow through the packaging structure
  • the impedance of the structure reduces the current in trace 33.
  • the difference between the electronic device 100 provided by the third embodiment of the present application and the electronic device provided by the first embodiment is that the shape memory 37 is arranged outside the package body 301 , and the shape memory 37 is implanted into the solder formation.
  • the shape memory object 37 is electrically connected to the circuit board 10
  • the shape memory object 37 is electrically connected to the wiring 33 .
  • the package body 301 includes a power semiconductor device 31 , wires 33 and a package medium 35 .
  • the power semiconductor device 31 is packaged in the packaging medium 35 , and a part of the wiring 33 is packaged in the packaging medium 35 .
  • the power semiconductor device 31 is electrically connected to the wiring 33 .
  • the solder formation 303 includes but is not limited to tin.
  • the solder formation 303 is located outside the package body 301 .
  • a first end of the solder formation 303 is fixedly connected to the trace 33
  • a second end of the solder formation 303 is fixedly connected to the circuit board 10 .
  • the shape memory 37 is implanted in the solder formation 303 .
  • a first end of the shape memory object 37 is in electrical contact with the wiring 33
  • a second end of the shape memory object 37 is in electrical contact with the circuit board 10 .
  • the wiring 33 and the shape memory object 37 form a flow-through structure.
  • Implanting the shape memory object 37 in the solder formation 303 means that the shape memory object 37 is buried in the solder formation 303 and surrounded by the solder formation 303 .
  • the outer surface of the package body 301 is usually provided with pads (not shown). After the package body 301 is manufactured, the shape memory object 37 is placed on the pad, and solder is poured on the shape memory object 37 to form the solder formation 303 , so that the solder formation 303 and the shape memory object 37 are integrated.
  • the solder formation 303 and the shape memory 37 can be pre-assembled on the package body 301 , or can be fabricated on site when the package structure 30 is placed on the circuit board 10 .
  • the shape memory material 37 is a shape memory alloy.
  • the shape memory object 37 is an elastic structure.
  • the initial state of the shape memory object 37 is a natural state.
  • the shape memory object 37 elongates when the temperature is not lower than the preset temperature, which reduces the contact area between the shape memory object 37 and the wiring 33 , thereby increasing the impedance of the flow-through structure. As the length of the shape memory object 37 becomes longer, the impedance of the flow-through structure will increase, and the current carried by the flow-through structure will decrease.
  • the flow-through structure Excessive current can generate a lot of heat. A large amount of heat generated by the overcurrent of the flow-through structure will concentrate on the shape memory material 37 , and the shape memory material 37 may be melted at high temperature, thereby cutting off the current between the wiring 33 and the circuit board 10 .
  • the initial state of the shape memory object 37 may be a compressed state.
  • the initial state of the shape memory object 37 may be a natural state, and when the temperature of the shape memory object 37 is not lower than a preset temperature, the shape memory object 37 will elongate. Since the shape memory object 37 is restricted by the package body 301 and the circuit board 10 during the elongation process, the shape memory object 37 bends, so that the solder formation 303 bends along with the bending of the shape memory object 37 . The bending deformation of the solder formation 303 reduces the contact area of the solder formation 303 with the package body 301 until it is separated from the package body 301 , and/or reduces the contact area of the solder formation 303 with the circuit board 10 until it is separated from the circuit board 10 .
  • the circuit structure inside the package structure 30 ie, inside the package body 301 ) remains unchanged, which facilitates the preparation of the package structure 30 .
  • the expression “and/or” includes any and all combinations of the associated listed words.
  • the expression “A and/or B” may include A, may include B, or may include both A and B.
  • expressions including ordinal numbers such as "first” and “second” may modify each element.
  • elements are not limited by the above expressions.
  • the above expressions do not limit the order and/or importance of the elements.
  • the above expressions are only used to distinguish one element from other elements.
  • the first user equipment and the second user equipment indicate different user equipments, although both the first user equipment and the second user equipment are user equipments.
  • a first element could be termed a second element
  • a second element could be termed a first element, without departing from the scope of the present application.

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Abstract

一种封装结构（30）及电子装置（100），封装结构（30）包括功率半导体器件（31）、走线（33）及形状记忆物（37），走线（33）与功率半导体器件（31）电连接；形状记忆物（37）与走线（33）接触，形状记忆物（37）用于在形状记忆物（37）的温度不小于预设温度时发生形变，使走线（33）断流或减小走线（33）中的电流。如此，降低功率半导体器件（31）过流时产生的高温对电路板（10）的影响，大大降低了电路板（10）被损坏的可能性，实现了封装结构（30）具有过流自保护的能力。

Description

封装结构及电子装置 技术领域
本申请涉及半导体技术领域，特别涉及一种封装结构及电子装置。
背景技术
表面贴装技术(surface-mount technology，SMT)是目前电子组装行业里最流行的一种技术和工艺。自70年代初推向市场以来，SMT已逐渐替代传统“人工插件”的波焊组装方式，成为现代电子组装产业的主流。SMT技术推动和促进了电子元器件向片式化、小型化、薄型化、轻量化、高可靠、多功能方向发展。
电源等功率半导体器件通过SMT二级封装的形式焊接在电路板(printed circuit board，PCB)上为单板进行供电。但是，功率半导体器件一旦过流(过电流)则会产生大量热量，容易对电路板造成损伤，严重时会“烧板”。过流是指电气元件承载的电流异常，即超出正常工作的通流范围。
发明内容
本申请实施例提供了一种具有过流自保护能力的封装结构及电子装置。
第一方面，本申请提供一种封装结构，包括功率半导体器件、走线及形状记忆物，走线与功率半导体器件电连接；形状记忆物与走线接触，形状记忆物用于在形状记忆物的温度不小于预设温度时发生形变，使走线断流或减小走线中的电流。
预设温度为形状记忆物开始形变的温度。走线断流是指走线中的电流被切断。
根据热量公式Q＝I 2R，其中，Q表示热量，I表示电流，R表示阻抗。功率半导体器件在过流时会产生热量，致使外界温度升高。外界温度是指形状记忆物所处环境的温度。功率半导体器件过流时所产生的热量传导至形状记忆物。形状记忆物的温度升高。当形状记忆物的温度升高到预设温度时，形状记忆物开始发生形变。形状记忆物的形变致使走线断流或走线中的电流减小，减少了热量的产生，延缓外界温度的升高，降低功率半导体器件过流对电路板的影响，大大降低了电路板被损毁的可能性，实现了封装结构具有过流自保护的能力。换而言之，形状记忆物为封装结构的过流保护结构，即封装结构具备过流(过温)自保护能力。即使功率半导体器件因过流损毁，可直接去除已烧毁的封装结构，电路板可保留进行重复使用。
形状记忆物与走线接触，包括两种情况：(1)形状记忆物与走线绝缘接触；(2)形状记忆物与走线电接触。
在形状记忆物与走线绝缘接触的情况中，形状记忆物在形状记忆物的温度达到预设温度时发生形变，以将形变时产生的应力作用在走线上使走线断裂进而断流。
在形状记忆物与走线电接触的一种情况中，即形状记忆物作为封装结构的通流结构一部分。形状记忆物用于在形状记忆物的温度达到预设温度时发生形变，例如，形状记忆物的长度伸长，会增大形状记忆物与走线构成的通流结构中的阻抗，进而减小走线的电流。
通常走线为铜导线。形状记忆物的电阻率通常为铜导线的电阻率的20倍以上。若功率半 导体器件过流时，由于形状记忆物的电阻率较大，大量热量会集中在形状记忆物上进而熔断形状记忆物，使得走线断流。
形状记忆物的形变，可以使走线受到形状记忆物的形变时的应力而断裂，致使走线断流。
根据第一方面，在本申请第一方面的第一种可能的实现方式中，走线至少部分封装于形状记忆物中，形状记忆物发生形变时产生的应力作用在走线上，以使走线断裂。
走线至少部分封装于形状记忆物中，即形状记忆物包围至少部分走线的外壁，以能够增大形状记忆物与走线的接触面积。形状记忆物发生形变时会发生拱起，致使其包围的部分走线受力弯折断裂。
根据第一方面或本申请第一方面的第一种可能的实现方式，在本申请第一方面的第二种可能的实现方式中，形状记忆物为具有单程形状记忆效应的高聚物，或具有单程形状记忆效应的陶瓷。
根据第一方面或本申请第一方面的第一种至第二种可能的实现方式，在本申请第一方面的第三种可能的实现方式中，封装结构还包括封装介质，形状记忆物为具有单程形状记忆效应的形状记忆合金，形状记忆物封装于封装介质中，形状记忆物用于在形状记忆物的温度达到预设温度时发生形变。如此，可以使走线断流或使所述走线中的电流减小。
一种情况中，形状记忆物发生形变时发生拱起，致使周遭封装介质及/或走线变形，走线受力弯折断裂。
一种情况中，在形状记忆物的温度达到预设温度时，形状记忆物的长度伸长，增大了形状记忆物与走线构成的通流结构中的阻抗，减小了走线中的电流，进而降低了走线过流的可能性。例如，形状记忆物的电阻率大于走线的电阻率。根据公式Q＝I 2R，若走线仍然会过流，由于形状记忆物的电阻率大于走线的电阻，热量会集中在形状记忆物上熔断形状记忆物，使得走线断流。
根据第一方面或本申请第一方面的第一种至第三种可能的实现方式，在本申请第一方面的第四种可能的实现方式中，走线包括第一延伸部、第二延伸部及连接部，连接部的第一端与第一延伸部电接触，连接部的第二端与第二延伸部电接触，形状记忆物位于第一延伸部与第二延伸部之间。
根据第一方面或本申请第一方面的第一种至第四种可能的实现方式，在本申请第一方面的第五种可能的实现方式中，形状记忆物与走线间隔设置。
根据第一方面或本申请第一方面的第一种至第五种可能的实现方式，在本申请第一方面的第六种可能的实现方式中，形状记忆物绕设于连接部的外壁上。
根据第一方面或本申请第一方面的第一种至第六种可能的实现方式，在本申请第一方面的第七种可能的实现方式中，形状记忆物紧贴连接部设置。
根据第一方面或本申请第一方面的第一种至第七种可能的实现方式，在本申请第一方面的第八种可能的实现方式中，形状记忆物为具有单程形状记忆效应的形状记忆合金，封装结构还包括焊料形成物，焊料形成物与走线固定连接，焊料形成物位于封装介质外，形状记忆物植入焊料形成物内，形状记忆物的一端与走线电连接，形状记忆物的另一端用于与电路板电连接，形状记忆物用于在形状记忆物的温度达到预设温度时伸长，以增大封装结构的通流结构中的阻抗，进而减小走线中的电流。
形状记忆物植入所述焊料形成物内，是指是指形状记忆物埋设于焊料形成物内并由焊料形成物包围。焊料形成物包括焊料。封装结构实现过流保护的同时，封装结构的内部线路结构不需作更改，方便了封装结构的制备。
根据第一方面或本申请第一方面的第一种至第八种可能的实现方式，在本申请第一方面的第九种可能的实现方式中，形状记忆物为弹性结构，形状记忆物的初始状态为压缩状态或自然状态。
形状记忆物的初始状态为压缩状态。形状记忆物的温度不小于预设温度时，形状记忆物伸长。形状记忆物的弹性作用力结合形状记忆物在发生形变时产生的应力作用在走线上，使走线断裂。
根据第一方面或本申请第一方面的第一种至第九种可能的实现方式，在本申请第一方面的第十种可能的实现方式中，所述走线与所述形状记忆物电接触形成通流结构，所述形状记忆物用于在所述形状记忆物的温度达到所述预设温度时伸长，所述形状记忆物发生形变后的通流结构的阻抗大于所述形状记忆物发生形变前的通流结构的阻抗，减小了走线中的电流，进而降低了走线过流的可能性。
第二方面，本申请提供一种电子装置，包括根据第一方面或本申请第一方面的第一种至第九种可能的实现方式所述的封装结构与电路板，电路板上设有控制电路，封装结构通过焊料形成物固定于电路板，封装结构的走线与电路板上的控制电路电连接，控制电路用于控制功率半导体器件的导通和关断。
附图说明
图1为本申请第一实施方式提供的电子装置的示意图；
图2为本申请第一实施方式提供的封装本体的示意图；
图3a为形状记忆物的初始状态的示意图；
图3b为形状记忆物形变时形成的一可能弯曲结构的示意图；
图3c为形状记忆物形变时形成的另一可能弯曲结构的示意图；
图4为封装本体的一可能结构示意图；
图5为本申请第二实施方式提供的封装结构的示意图；
图6a为走线与形状记忆物间隔设置并在形状记忆物的温度小于预设温度时的可能结构示意图；
图6b为走线与形状记忆物间隔设置并在形状记忆物的温度不小于预设温度时的可能结构示意图；
图7a为形状记忆物绕设于走线并在形状记忆物的温度小于预设温度时的可能结构示意图；
图7b为形状记忆物绕设于走线并在形状记忆物的温度不小于预设温度时的一可能结构示意图；
图8为形状记忆物绕设于走线并在形状记忆物的温度不小于预设温度时的另一可能结构示意图；
图9a为形状记忆物紧贴走线并在形状记忆物的温度小于预设温度时的可能结构示意图；
图9b为形状记忆物紧贴走线并在形状记忆物的温度不小于预设温度时的可能结构示意图；
图10为本申请第三实施方式提供的电子装置的示意图。
具体实施方式
电源等功率半导体器件封装结构焊接在电路板上以进行供电。电路板上通常亦设置其他的电子元器件。封装结构包括功率半导体器件、走线及封装介质(又称塑封体)。功率半导体器件与走线均封装于封装介质中。走线的材质通常为铜。铜的熔点大致为1085℃。功率半导体器件通常为设置在Si基底上的集成电路(即Si芯片)。Si的耐受温度可达到1414℃。电路板通常的耐受温度大致为350℃。可见，电路板的耐受温度最低。
然而，功率半导体器件一旦过流则会产生热量，导致外界温度升高。外界温度为封装结构所处环境的温度。特别是，功率半导体器件若过流则可能会发生燃烧现象，燃烧沿着走线会蔓延至封装介质及电路板。由于电路板的耐受温度较低，外界温度超过电路板的耐受温度时，高温容易导致电路板损坏。因此，一个功率半导体器件的过流可能会导致一整块电路板的报废。
基于此，本申请提供一种包括功率半导体器件的封装结构，功率半导体器件过流产生热量，形状记忆物在形状记忆物的温度不小于预设温度时能够发生形变，使走线断流或减小走线中的电流，实现封装结构具过流(过温)自保护能力，减少电路板被损坏的可能性，从而提高电子装置的安全可靠性。
本申请提供的封装结构可以应用在各种需要采用功率半导体器件的电子装置中。功率半导体器件用于进行功率变换处理，包括变频、变压、变流、功率管理等等。电子装置可以是需要采用功率半导体器件的电能转换装置。而电能转换装置又可以搭载在电能转换设备上以完成设备的各类电力功能。例如，本申请的电子装置可以应用在电动汽车动力系统领域，即电能转换设备可以为电动车，其中，电子装置可以为电机控制器，封装结构为装配在电机控制器中的动力转换单元；电子装置也可以为车载充电器(on-board charger，OBC)，封装结构为能量转换单元；电子装置还可以为低压控制电源，封装结构为其中的DC-DC转换单元等等。除此之外，本申请的电子装置也不限于电动汽车领域，也可以广泛地应用在传统工业控制、通信、智能电网、电器等领域，例如，可以应用于数据中心的不间断电源(uninterruptible power supply,UPS)、光伏发电设备的逆变器、服务器的电源、电器(例如冰箱)的开关电源等等。可以理解，本申请不限定电子装置为电能转换装置，即本申请不限定功率半导体器件进行电能转换，功率半导体器件也可以在电子装置中用于改变电压、频率等以实现电路控制功能。
下面将结合附图对本申请作进一步地详细描述。
请参阅图1，本申请第一实施方式提供一种电子装置100，包括电路板10及焊接于电路板10上的封装结构30。本实施方式中，电路板10可以为网络单板。
封装结构30包括封装本体301及焊料形成物303。封装本体301通过焊料形成物303焊接于电路板10上。本实施方式中，封装结构30为嵌入式元器件封装(embedded component packaging，ECP)，通过回流焊工艺在封装本体301与电路板10之间形成焊料形成物303，进而将封装本体301焊接于电路板10上。回流焊工艺中，是通过将空气或氮气加热到足够高的温度后吹向已经贴好元器件的电路板，让元器件两侧的焊料融化好与电路板粘接。焊料形成物303位于封装本体301外。通常回流焊工艺的焊接温度为260℃。可以理解，焊料形成物303也可以预装在封装本体301上。
请结合参阅图2，封装本体301包括功率半导体器件31、走线33、封装介质35及形状记忆物37。功率半导体器件31封装于封装介质35中，走线33的一部分封装于封装介质35中。功率半导体器件31与走线33电连接。电路板10设有控制电路11(如图1所示)。控制电路11包括但不限定电容、电感等电子器件。走线33与电路板10的控制电路11电连接。 控制电路11用于控制功率半导体器件31的导通和关断，实现功率转换。走线33的其余部分封装于形状记忆物37中，即走线33部分与形状记忆物37绝缘接触。形状记忆物37用于在形状记忆物37的温度不小于预设温度时发生形变，以使走线33断裂进而断流。可以理解，封装本体301还可以包括其他的元件，例如，电容。
预设温度为形状记忆物开始形变(相变)的温度。功率半导体器件31过流时会产生热量进而使外界温度升高。外界温度是指形状记忆物37所处环境的温度。功率半导体器件31过流时所产生的热量传导至形状记忆物37。形状记忆物37的温度升高到预设温度时，形状记忆物37发生形变。形状记忆物37发生形变时产生的应力作用在走线33上，使得走线33断裂，进而实现走线33断流。由于走线33断流，减少热量的产生，延缓外界温度的升高，降低了外界温度对电路板10的影响，降低了电路板10被损坏的可能性。换而言之，形状记忆物37为封装结构30的过流保护结构，当功率半导体器件31过流时，形状记忆物37发生形变使走线33断流，即封装结构30具备过流自保护能力，进而延长了电路板10的使用寿命。当电路板组件100中的封装结构30出现过流造成封装结构30损坏时，可直接去除已损坏的封装结构30，而电路板10可保留进行重复使用。
功率半导体器件31封装于封装介质35中，是指封装介质35包覆(或包围)功率半导体器件31。走线33的一部分封装于封装介质35，是指封装介质35包覆(或包围)走线33的一部分。走线33的其余部分封装于形状记忆物37。走线33的其余部分封装于形状记忆物37，是指形状记忆物37覆盖走线33的至少部分外表面。换而言之，形状记忆物37亦作为封装结构30的塑封体对走线33进行塑封。
本实施方式中，走线33为铜走线。可以理解，走线33可以为其他材质的走线，例如，金等，本申请对走线33的材质不作限定。
本实施方式中，封装介质35为味之素堆积膜(ajinomoto build-up film，ABF膜)。可以理解，封装介质35不限定为ABF膜，其还可以为其他材质的塑封体。
本实施方式中，形状记忆物37与封装介质35层叠设置。本实施方式中，形状记忆物37靠近封装介质35的最外层设置并设于封装本体301远离电路板10(如图1所示)的一侧，以方便形状记忆物37设置于封装介质35。
本实施方式中，形状记忆物37为具有单程形状记忆效应的高聚物。单程形状记忆效应是指加热升温时形状记忆物37能够恢复低温时发生的形变。形状记忆物37是一种智能热敏聚合物。智能热敏聚合物是一种能够对自身温度的变化发生预定响应的高分子材料,也就是说,自身温度的变化促使聚合物的微观结构发生预定的响应,从而使聚合物特定的宏观性能随之发生相应的变化。热敏形状记忆聚合物属于智能材料的一种,该类聚合物制品经过形变并固定后,在特定的外界条件-热刺激下能自动回复到初始形状。可以理解，形状记忆物37还可以为具有单程形状记忆效应的陶瓷。
形状记忆物37在形状记忆物37的温度不小于预设温度时会发生形变，形状记忆物37形变时产生的应力作用在走线33上，使走线33受力弯折断裂。例如，形状记忆物37的初始形状为平坦状(如图3a所示)。形状记忆物37的温度小于预设温度时，形状记忆物37保持初始形状。功率半导体器件31发生过流时会释放热量，进而使外界温度升高。形状记忆物37的温度随着外界温度升高而升高。当形状记忆物37的温度不小于预设温度时，形状记忆物37发生形变形成弯曲结构。例如，形状记忆物37会形成如图3b或图3c所示的拱起结构。形状记忆物37弯曲拱起产生的应力作用在走线33上，走线33受力弯折断裂，实现走线33断流。
若预设温度太低，在封装本体与电路板进行回流焊时，形状记忆物因回流焊的温度而发生形变。若预设温度太高，在功率半导体器件出现过流(例如过流短路)时，形状记忆物的温度需要较长时间才会上升至预设温度，如此，导致形状记忆物难以及时响应功率半导体器件的过流，造成损坏电路板的后果。本实施方式中，预设温度大于260℃并不大于500℃，以使形状记忆物37能够抵抗封装本体301与电路板10进行回流焊时的高温，及使形状记忆物37能够在功率半导体器件31出现过流时在较短时间内(功率半导体器件31过流早期的温度不高时)即可发生形变进行响应。
可以理解，本申请不限定预设温度的范围，预设温度可根据需要进行设定。
可以理解，形状记忆物37在封装本体301中的位置不作限定，走线33的至少部分封装于形状记忆物37内，例如，形状记忆物37靠近封装介质35的最外层设置并设于封装本体301靠近电路板10(如图4所示)的一侧，或者形状记忆物37被封装介质35包覆。
在一些实施方式中，形状记忆物37替代全部的封装介质35，即功率半导体器件31封装于形状记忆物37内，走线33封装于形状记忆物37中。
请参阅图5，本申请第二实施方式提供的封装结构与第一实施方式提供的封装结构的区别在于，形状记忆物37为形状记忆合金，形状记忆物37与走线33电接触。
较为具体地，封装结构30包括通流结构，通流结构包括走线33与形状记忆物37。形状记忆物37与走线33固定连接，形状记忆物37与走线33电连接。换而言之，形状记忆物37作为封装结构30的通流结构的一部分。
形状记忆物37为形状记忆合金。形状记忆合金(shape memory alloys，SMA)是一种具有形状记忆效应和超弹性的功能金属材料。对于一般的金属材料而言，当形变超过弹性极限时，将发生永久变形，这种变形被称为塑性变形，并且在处于固态状态时对其进行加热或应力卸载，这种变形不能完全恢复。但是形状记忆合金则不同，形状记忆合金具有形状记忆效应和超弹性，也就是说，具有一定形状的固态材料在较低温度下或增加应力时发生塑性变形，但当温度升高或应力减小时，形状记忆合金又能够恢复到变形前的形状。
根据变形和恢复方式的不同，形状记忆效应可以分为单程形状记忆效应、双程形状记忆效和全程形状记忆效应三类。单程形状记忆效应是指加热升温时合金能够恢复低温时发生的形变；对某些合金进行特殊的热处理之后，不仅能够在加热升温时恢复低温时的形变，还能够在温度降低的相变过程中恢复高温状态下的变形，称为双程形状记忆效应；具有双程形状记忆效应的形状记忆合金，在低温和高温时呈现相反的形状，称为全程形状记忆效应。
请参表1，表1示例性地展示了部分钛基高温记忆合金的抗拉强度、延伸率、奥氏体相变开始温度(As)和形状记忆回复应变。可选取奥氏体相变开始温度(As)大于260℃并不大于500℃的钛基高温记忆合金应用于第二实施方式中。
根据电阻定律公式R＝ρL/S，其中，ρ为电阻率，L为长度，S为面积。当L增大，及/或S减小时，阻抗则会增加。形状记忆物37在形状记忆物37的温度不小于预设温度时伸长，进而提高了通流结构的阻抗，降低走线33过流的可能性。本实施方式中，走线33为铜线，形状记忆物37的电阻率是走线33的电阻率的20倍以上。在形状记忆物37的温度不小于预设温度时，由于形状记忆物37形变后的长度变长，形状记忆物37和走线33之间的接触面积比走线33与走线33之间的接触面积至少小一百分之一。根据电阻定律，形状记忆物37发生形变后的通流结构的阻抗是形状记忆物37未发生形变时的通流结构的原阻抗的2000倍以上。
表1 部分钛基高温记忆合金的抗拉强度、延伸率、奥氏体相变开始温度(As)和形状记忆回复应变
Figure PCTCN2021111866-appb-000001
根据公式Q＝I 2R，其中，Q表示热量，I表示电流，R表示阻抗。功率半导体器件31发生过流时会释放热量进而使外界温度升高。外界温度升高使形状记忆物37的温度升高。形状记忆物37在形状记忆物37的温度不小于预设温度时会伸长，使通流结构的阻抗提高，减小了走线33中的电流，降低了走线33过流的可能性，减少了热量的产生，延缓形状记忆物37的温度升高。若走线33仍然过流，由于形状记忆物37发生形变后的通流结构的阻抗远大于形状记忆物37未发生形变时的通流结构的原阻抗，热量会集中在形状记忆物37上从而能够熔断形状记忆物37，实现切断走线33中的电流。
请参阅图6a，走线33包括第一延伸部331、第二延伸部333及连接部335。第一延伸部331沿第一方向(如图6a中的横向)延伸。第二延伸部333沿第一方向(如图6a中的横向)延伸。第一延伸部331与功率半导体器件31电连接。本实施方式中，形状记忆物37为具有单程形状记忆效应的形状记忆合金。
连接部335的第一端与第一延伸部331电接触，连接部335的第二端与第二延伸部333电接触，连接部335位于第一延伸部331与第二延伸部333之间。形状记忆物37与连接部335间隔设置。第二实施方式中，形状记忆物37为弹性结构，例如，形状记忆物37可以盘绕成柱状弹簧结构。可以理解，形状记忆物37也可以为其他形状的弹性结构。
形状记忆物37的初始状态包括自然状态、压缩状态及拉伸状态。形状记忆物37未受外力时为自然状态。形状记忆物37处于压缩状态时的高度要小于处于自然状态时的高度。形状记忆物37处于拉伸状态时的高度要大于处于自然状态时的高度。设形状记忆物37的温度小于预设温度时，形状记忆物37的状态为初始状态。
形状记忆物37的初始状态为压缩状态。形状记忆物37的温度不小于预设温度时，形状记忆物37发生形变并伸长。形状记忆物37的弹性作用力结合形状记忆物37发生形变时产生的应力作用在第一延伸部331上，使得连接部335脱离第一延伸部331(如图6b所示)，走线33直接断裂。及/或，形状记忆物37的弹性作用力结合形状记忆物37在发生形变时产生的应力作用在第二延伸部333上，使连接部335脱离第二延伸部333，走线33断裂。如此，在形状记忆物37未熔断的情况下，形状记忆物37可使走线33直接断裂而断流。形状记忆物37的数量为两个，连接部335位于两个形状记忆物37之间，以缩短折断走线33的时长，提高封装结构30的过流保护效率。可以理解，本申请对形状记忆物37的数量不作限定。
在一些实施方式中，形状记忆物37缠绕(绕设)于走线33的外壁上。如图7a所示，走线33包括第一延伸部331、第二延伸部333与连接部335。第一延伸部331沿第一方向(图7a中的横向)延伸。第二延伸部333沿第一方向(图7a中的横向)延伸。连接部335的第一端与第一延伸部331电接触，连接部335的第二端与第二延伸部333电接触，连接部335位于第一延伸部331与第二延伸部333之间。形状记忆物37缠绕于连接部335的外壁上。形状记忆物37的初始状态为压缩状态。形状记忆物37的温度不小于预设温度时，形状记忆物37伸长。形状记忆物37的弹性作用力结合形状记忆物37在发生形变时产生的应力作用在第一延伸部331上，使得连接部335脱离第一延伸部331(如图7b所示)，走线33直接断裂。及/或，形状记忆物37的弹性作用力结合形状记忆物37在发生形变时产生的应力作用在第二延伸部333上，使连接部335脱离第二延伸部333，走线33断裂。如此，在形状记忆物37未熔断的情况下，形状记忆物37可使走线33直接断裂而断流。可以理解，形状记忆物37的初始状态也可为自然状态，由于形状记忆物37在伸长的过程中受到第一延伸部331与第二延伸部333的限制，形状记忆物37被压缩。
在一些实施方式中，形状记忆物37缠绕(绕设)于走线33的外壁上(如图7a所示)，形状记忆物37的初始状态为自然状态。形状记忆物37的温度不小于预设温度时，形状记忆物37伸长或弯曲。由于形状记忆物37在伸长的过程中受到第一延伸部331与第二延伸部333的限制，形状记忆物37弯曲，致使连接部335随同形状记忆物37弯曲而弯曲(如图8所示)。连接部335的弯曲变形，使连接部335减少与第一延伸部331的接触面积直至脱离第一延伸部331，及/或，连接部335脱离第二延伸部333。
在一些实施方式中，形状记忆物37紧贴连接部335(如图9a所示)设置，形状记忆物37的初始状态为自然状态。形状记忆物37的温度不小于预设温度时，形状记忆物37伸长。由于形状记忆物37在伸长的过程中受到第一延伸部331与第二延伸部333的限制，形状记忆物37弯曲，致使连接部335随同形状记忆物37弯曲而变形(如图9b所示)。连接部335的弯曲变形，使连接部335减少与第一延伸部331的接触面积直至脱离第一延伸部331，及/或，连接部335脱离第二延伸部333。
可以理解，形状记忆物37与走线33的电接触方式不限定于本申请所示例，形状记忆物37在形状记忆物37的温度不小于预设温度时发生形变，形状记忆物37形变时产生的应力作用在走线33上，使走线33断裂实现走线33断流；或者，形状记忆物在形状记忆物37的温度不小于预设温度时伸长，增大封装结构中的通流结构的阻抗，减小走线33中的电流。
请参阅图10，本申请第三实施方式提供的电子装置100与第一实施方式提供的电子装置的区别在于，形状记忆物37设置于封装本体301的外部，形状记忆物37植入焊料形成物303内，形状记忆物37与电路板10电连接，形状记忆物37与走线33电连接。
具体地，封装本体301包括功率半导体器件31、走线33与封装介质35。功率半导体器件31封装于封装介质35中，走线33的一部分封装于封装介质35中。功率半导体器件31与走线33电连接。
焊料形成物303包括但不限定为锡料。焊料形成物303位于封装本体301外。焊料形成物303的第一端与走线33固定连接，焊料形成物303的第二端与电路板10固定连接。形状记忆物37植入于焊料形成物303内。形状记忆物37的第一端与走线33电接触，形状记忆物37的第二端与电路板10电接触。走线33与形状记忆物37形成通流结构。
形状记忆物37植入于焊料形成物303内，是指形状记忆物37埋设于焊料形成物303内 并由焊料形成物303包围。封装本体301的外表面通常设有焊盘(图未示)。制作封装本体301后，将形状记忆物37放置在焊盘处，将焊料浇筑在形状记忆物37上形成焊料形成物303，如此，使焊料形成物303与形状记忆物37形成一体。焊料形成物303与形状记忆物37可以预装在封装本体301上，也可以在将封装结构30设置于电路板10上时现场制成。
形状记忆物37为形状记忆合金。本实施方式中，形状记忆物37为弹性结构。形状记忆物37的初始状态为自然状态。形状记忆物37在温度不小于预设温度时伸长，减少了形状记忆物37与走线33之间的接触面积，进而提高了通流结构的阻抗。由于形状记忆物37的长度变长，通流结构的阻抗会增大，通流结构承载的电流减小。若走线33仍然过流，由于形状记忆物37发生形变后的通流结构的阻抗远大于形状记忆物37未发生形变的通流结构的原阻抗，根据公式Q＝I 2R，通流结构过流会产生大量热量。通流结构过流产生的大量热量会集中在形状记忆物37上，高温可熔断形状记忆物37，从而切断走线33与电路板10之间的电流。
可以理解，形状记忆物37的初始状态可以为压缩状态。
可以理解，形状记忆物37的初始状态可以为自然状态，形状记忆物37的温度不小于预设温度时，形状记忆物37伸长。由于形状记忆物37在伸长的过程中受到封装本体301与电路板10的限制，形状记忆物37弯曲，致使焊料形成物303随同形状记忆物37弯曲而弯曲。焊料形成物303的弯曲变形，使焊料形成物303减少与封装本体301的接触面积直至脱离封装本体301，及/或，使焊料形成物303减少与电路板10的接触面积直至脱离电路板10。
封装结构30实现过流保护的同时，封装结构30的内部(即封装本体301内)的线路结构不作更改，方便了封装结构30的制备。
应当理解的是，可以在本申请中使用的诸如“包括”以及“可以包括”之类的表述表示所公开的功能、操作或构成要素的存在性，并且并不限制一个或多个附加功能、操作和构成要素。在本申请中，诸如“包括”及/或“具有”之类的术语可解释为表示特定特性、数目、操作、构成要素、组件或它们的组合，但是不可解释为将一个或多个其它特性、数目、操作、构成要素、组件或它们的组合的存在性或添加可能性排除在外。
此外，在本申请中，表述“及/或”包括关联列出的词语中的任意和所有组合。例如，表述“A及/或B”可以包括A，可以包括B，或者可以包括A和B这二者。
在本申请中，包含诸如“第一”和“第二”等的序数在内的表述可以修饰各要素。然而，这种要素不被上述表述限制。例如，上述表述并不限制要素的顺序及/或重要性。上述表述仅用于将一个要素与其它要素进行区分。例如，第一用户设备和第二用户设备指示不同的用户设备，尽管第一用户设备和第二用户设备都是用户设备。类似地，在不脱离本申请的范围的情况下，第一要素可以被称为第二要素，类似地，第二要素也可以被称为第一要素。
当组件被称作“连接”或“接入”其他组件时，应当理解的是：该组件不仅直接连接到或接入到其他组件，而且在该组件和其它组件之间还可以存在另一组件。另一方面，当组件被称作“直接连接”或“直接接入”其他组件的情况下，应该理解它们之间不存在组件。
以上所述，仅为本申请的具体实施方式，但本申请的保护范围并不局限于此，任何熟悉本技术领域的技术人员在本申请揭露的技术范围内，可轻易想到变化或替换，都应涵盖在本申请的保护范围之内。因此，本申请的保护范围应以所述权利要求的保护范围为准。

Claims (13)

  1. 一种封装结构，其特征在于，包括功率半导体器件、走线及形状记忆物，所述走线与所述功率半导体器件电连接；所述形状记忆物与所述走线接触，所述形状记忆物用于在所述形状记忆物的温度达到预设温度时发生形变，使所述走线断流或使所述走线中的电流减小。
  2. 根据权利要求1所述的封装结构，其特征在于，所述形状记忆物与所述走线绝缘接触，所述走线至少部分封装于所述形状记忆物中，所述形状记忆物发生形变时产生的应力作用在所述走线上，以使所述走线断流。
  3. 根据权利要求2所述的封装结构，其特征在于，所述形状记忆物为具有单程形状记忆效应的高聚物，或具有单程形状记忆效应的陶瓷。
  4. 根据权利要求2所述的封装结构，其特征在于，所述封装结构还包括封装介质，所述功率半导体器件封装于所述封装介质中，所述走线的一部分封装于所述封装介质中，所述走线的其余部分封装于所述形状记忆物中。
  5. 根据权利要求1所述的封装结构，其特征在于，所述封装结构还包括封装介质，所述形状记忆物为具有单程形状记忆效应的形状记忆合金，所述形状记忆物封装于所述封装介质中，所述形状记忆物用于在所述形状记忆物的温度达到所述预设温度时发生形变，使所述走线断流或使所述走线中的电流减小。
  6. 根据权利要求5所述的封装结构，其特征在于，所述走线包括第一延伸部、第二延伸部及连接部，所述连接部的第一端与所述第一延伸部电接触，所述连接部的第二端与所述第二延伸部电接触，所述形状记忆物位于所述第一延伸部与所述第二延伸部之间。
  7. 根据权利要求6所述的封装结构，其特征在于，所述形状记忆物与所述走线间隔设置。
  8. 根据权利要求6所述的封装结构，其特征在于，所述形状记忆物绕设于所述连接部的外壁上。
  9. 根据权利要求6所述的封装结构，其特征在于，所述形状记忆物紧贴所述连接部设置。
  10. 根据权利要求1所述的封装结构，其特征在于，所述形状记忆物为具有单程形状记忆效应的形状记忆合金，所述封装结构还包括焊料形成物，所述焊料形成物与所述走线固定连接，所述焊料形成物位于所述封装介质外，所述形状记忆物植入所述焊料形成物内，所述形状记忆物的一端与所述走线电连接，所述形状记忆物用于在所述形状记忆物的温度达到预设温度时伸长。
  11. 根据权利要求5-10任意一项所述的封装结构，其特征在于，所述形状记忆物为弹性结构，所述形状记忆物的初始状态为压缩状态或自然状态。
  12. 根据权利要求5-11任意一项所述的封装结构，其特征在于，所述走线与所述形状记忆物电接触形成通流结构，所述形状记忆物用于在所述形状记忆物的温度达到所述预设温度时伸长，所述形状记忆物发生形变后的通流结构的阻抗大于所述形状记忆物发生形变前的通流结构的阻抗。
  13. 一种电子装置，其特征在于，包括根据权利要求1-12任意一项所述的封装结构与电路板，所述封装结构通过焊料形成物固定于所述电路板，所述电路板上设有控制电路，所述封装结构的走线与所述电路板上的控制电路电连接，所述控制电路用于控制所述功率半导体器件的导通和关断。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878611A (ja) * 1994-08-31 1996-03-22 Nec Corp 半導体装置
US20020140540A1 (en) * 2001-03-28 2002-10-03 Protectronics Technology Corporation Surface mountable laminated circuit protection device and method of making the same
CN101595546A (zh) * 2005-06-02 2009-12-02 力特保险丝有限公司 过热保护装置、应用和电路
CN103098165A (zh) * 2010-08-06 2013-05-08 凤凰通讯两合有限公司 过热保护装置
CN112687646A (zh) * 2020-12-28 2021-04-20 华进半导体封装先导技术研发中心有限公司 自防损功率sip模块封装结构及其封装方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0878611A (ja) * 1994-08-31 1996-03-22 Nec Corp 半導体装置
US20020140540A1 (en) * 2001-03-28 2002-10-03 Protectronics Technology Corporation Surface mountable laminated circuit protection device and method of making the same
CN101595546A (zh) * 2005-06-02 2009-12-02 力特保险丝有限公司 过热保护装置、应用和电路
CN103098165A (zh) * 2010-08-06 2013-05-08 凤凰通讯两合有限公司 过热保护装置
CN112687646A (zh) * 2020-12-28 2021-04-20 华进半导体封装先导技术研发中心有限公司 自防损功率sip模块封装结构及其封装方法

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