WO2023004694A1 - 一种参考信号到达时间估计方法、装置及芯片 - Google Patents

一种参考信号到达时间估计方法、装置及芯片 Download PDF

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Publication number
WO2023004694A1
WO2023004694A1 PCT/CN2021/109309 CN2021109309W WO2023004694A1 WO 2023004694 A1 WO2023004694 A1 WO 2023004694A1 CN 2021109309 W CN2021109309 W CN 2021109309W WO 2023004694 A1 WO2023004694 A1 WO 2023004694A1
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signal
phase
reference signal
frequency
locked loop
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PCT/CN2021/109309
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English (en)
French (fr)
Inventor
雷镇东
王淑惠
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华为技术有限公司
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Priority to CN202180006489.1A priority Critical patent/CN115885560A/zh
Priority to PCT/CN2021/109309 priority patent/WO2023004694A1/zh
Publication of WO2023004694A1 publication Critical patent/WO2023004694A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W64/00—Locating users or terminals or network equipment for network management purposes, e.g. mobility management
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04W—WIRELESS COMMUNICATION NETWORKS
    • H04W72/00—Local resource management
    • H04W72/04—Wireless resource allocation

Definitions

  • the present application relates to the field of communication technology, and in particular to a reference signal arrival time estimation method, device and chip.
  • Signal arrival time estimation technology is one of the key technologies of cellular positioning.
  • the first wireless communication device may send reference signals to multiple other second wireless communication devices, so that the multiple second wireless communication devices measure the arrival time of the received reference signals, so that the first wireless communication device may
  • the reference signal arrival time is usually determined based on time of arrival (TOA) technology.
  • TOA time of arrival
  • the estimation accuracy of the reference signal arrival time determines the positioning accuracy of the first wireless communication device, and the estimation accuracy of the reference signal arrival time is limited by the effective bandwidth of the reference signal. The wider the bandwidth of the reference signal sent by the first wireless communication device, the second The positioning accuracy of a wireless communication device is higher.
  • the present application provides a method, device and chip for estimating the time of arrival of a reference signal, which are used to improve the positioning accuracy of a wireless communication device that supports a small bandwidth.
  • the wireless communication device may be a wireless communication device, or may be a part of the wireless communication device, such as an integrated circuit product such as a system chip or a communication chip.
  • a wireless communication device may be a computer device supporting a wireless communication function.
  • the wireless communication device may be a terminal such as a smart phone, or a wireless access network device such as a base station.
  • a system chip can also be called a system on chip (system on chip, SoC), or simply a SoC chip.
  • Communication chips may include baseband processing chips and radio frequency processing chips. Baseband processing chips are also sometimes referred to as modems or baseband chips.
  • RF processing chips are sometimes also referred to as RF transceivers or RF chips.
  • part or all of the chips in the communication chip can be integrated inside the SoC chip.
  • the baseband processing chip is integrated in the SoC chip, and the radio frequency processing chip is not integrated with the SoC chip.
  • the present application provides a method for estimating a time of arrival of a reference signal, and the method can be executed by a first wireless communication device.
  • the method includes: the first wireless communication device sends a first reference signal in a first frequency band, and sends a second reference signal in a second frequency band.
  • the sending time of the first reference signal is different from the sending time of the second reference signal
  • the center frequency point of the first frequency band is different from the center frequency point of the second frequency band
  • the phases of the first reference signal and the second reference signal are substantially synchronized , the first reference signal and the second reference signal can be used to jointly estimate the arrival time of the reference signal.
  • the reference signal arrival time is jointly estimated based on the first reference signal and the second reference signal, compared with the scheme of estimating the reference signal arrival time only using the first reference signal in the first frequency band, the reference signal used for estimating the reference signal arrival time in this application
  • the frequency domain range occupied by the signal is larger, so that the estimation accuracy of the arrival time of the reference signal can be improved.
  • the third frequency band includes the first frequency band and the second frequency band, and when there is a spaced frequency band between the first frequency band and the second frequency band, the third frequency band also includes the first frequency band and the second frequency band.
  • the frequency band spaced between the second frequency bands is a scheme for estimating the time of arrival of the reference signal.
  • the estimation accuracy of the time of arrival of the reference signal is equivalent to it, but this application can make the radio frequency channel of the wireless communication device only have the ability to support sending the first frequency band
  • the ability to transmit signals in the second frequency band is enough, and it is not required to support the transmission of signals in the third frequency band. It can be seen that this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.
  • the present application provides a method for estimating a time of arrival of a reference signal, and the method can be executed by a first wireless communication device.
  • the method includes: the first wireless communication device sequentially transmits a first reference signal and a second reference signal in a frequency hopping manner, wherein the frequency ranges of the first reference signal and the second reference signal are different but the phases are substantially synchronous, and the first reference signal and the second reference signal are substantially synchronized.
  • the second reference signal can be used to jointly estimate the reference signal arrival time.
  • the reference signal arrival time is jointly estimated based on the first reference signal and the second reference signal, compared with the scheme of estimating the reference signal arrival time only using the first reference signal in the first frequency band, the reference signal used for estimating the reference signal arrival time in this application
  • the frequency domain range occupied by the signal is larger, so that the estimation accuracy of the arrival time of the reference signal can be improved.
  • the third frequency band includes the first frequency band and the second frequency band, and when there is a spaced frequency band between the first frequency band and the second frequency band, the third frequency band also includes the first frequency band and the second frequency band.
  • the frequency band spaced between the second frequency bands is a scheme for estimating the time of arrival of the reference signal.
  • the estimation accuracy of the time of arrival of the reference signal is equivalent to it, but this application can make the radio frequency channel of the wireless communication device only have the ability to support sending the first frequency band
  • the ability to transmit signals in the second frequency band is enough, and it is not required to support the transmission of signals in the third frequency band. It can be seen that this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.
  • the time of arrival of the reference signal can be used to estimate the position of the wireless communication device.
  • the estimation accuracy of the reference time of arrival is improved, the accuracy of the position of the wireless communication device estimated based on the reference time of arrival is also improved.
  • the present application can reduce the amount of signals sent by the wireless communication device, thereby The power consumption of the wireless communication device can be reduced.
  • the first wireless communication device may also generate the first local oscillator signal through the first phase-locked loop, and the center frequency of the first local oscillator signal is the same as the first reference The center frequencies of the signals are the same.
  • the first wireless communication device may also generate a second local oscillator signal through the second phase-locked loop, and the center frequency of the second local oscillator signal is the same as the center frequency of the second reference signal.
  • the process of generating two local oscillator signals through two phase-locked loops does not need to involve the process of losing lock and re-locking of the phase-locked loop, so that Phase jitter introduced by relocking after the phase-locked loop loses lock is avoided, thereby laying a foundation for substantial synchronization of the phases of the first reference signal and the second reference signal.
  • the first wireless communication device sending the first reference signal in the first frequency band includes: sending the first reference signal in the first frequency band according to the first local oscillator signal .
  • Sending the second reference signal in the second frequency band by the first wireless communication device includes: sending the second reference signal in the second frequency band according to the second local oscillator signal.
  • the reference signal can be sent in a required frequency band by modulating the reference signal to a local oscillator signal of a different frequency.
  • the input terminal of the mixer of the first wireless communication device is selectively connected to the first phase-locked loop, and the input terminal of the mixer is connected to the second phase-locked loop.
  • Phase rings are selectively connected.
  • the reference clock signal used by the first phase-locked loop and the second phase-locked loop is the same.
  • the phase adjustment of the local oscillator signals output by the two phase-locked loops can be performed based on the same reference clock signal, thereby laying the foundation for the substantial synchronization of the phases of the first local oscillator signal and the second local oscillator signal, and then for the first reference signal A foundation is laid for substantially synchronizing with the phase of the second reference signal.
  • the first wireless communication device may further output the first synchronization signal to the first phase-locked loop and the second phase-locked loop respectively.
  • the phase difference between the first local oscillator signal output by the first phase-locked loop and the reference clock signal is adjusted according to the first synchronization signal.
  • the phase difference between the second local oscillator signal output by the second phase-locked loop and the reference clock signal is adjusted according to the first synchronization signal.
  • phase difference between the two phase-locked loops and the reference clock signal is adjusted according to the same first synchronization signal, the phase difference between the initial phases of the first local oscillator signal and the second local oscillator signal can be adjusted to 0, thereby A foundation is laid for the phase synchronization of the first local oscillator signal and the second local oscillator signal, and then a foundation is laid for the phase synchronization of the first reference signal and the second reference signal.
  • the frequency divider may be located outside the loop of the phase-locked loop, or may be located inside the loop of the phase-locked loop.
  • the first phase locked loop comprises a first oscillator, a first frequency divider and a first feedback frequency divider.
  • the output terminals of the first oscillator are respectively connected to the first frequency divider and the first feedback frequency divider.
  • the second phase-locked loop includes a second oscillator, a second frequency divider and a second feedback frequency divider.
  • the output terminals of the second oscillator are respectively connected to the second frequency divider and the second feedback frequency divider.
  • the first phase-locked loop includes a first frequency divider and a first feedback frequency divider; the input end of the first feedback frequency divider is connected to the first frequency divider output terminal.
  • the second phase-locked loop includes a second frequency divider and a second feedback frequency divider; the input end of the second feedback frequency divider is connected to the output end of the second frequency divider.
  • the first feedback frequency divider divides the frequency of the signal output by the first frequency divider and then feeds it back to the first phase-locked loop to adjust the phase difference between the first local oscillator signal and the reference clock signal.
  • the second feedback frequency divider divides the signal output by the second frequency divider and feeds it back to the second phase-locked loop to adjust the phase difference between the second local oscillator signal and the reference clock signal. Therefore, the second frequency divider can be reduced.
  • the phase jitter caused by the randomness of the starting clock edge of the first frequency divider and the second frequency divider.
  • the first wireless communication device adjusts the phase difference between the first local oscillator signal output by the first phase-locked loop and the reference clock signal according to the first synchronization signal, including: Determine the first valid edge of the reference clock signal according to the first synchronization signal, and adjust the phase difference between the first local oscillator signal and the reference clock signal based on the first valid edge.
  • the first wireless communication device adjusts the phase difference between the second local oscillator signal output by the second phase-locked loop and the reference clock signal according to the first synchronization signal, including: determining the first effective edge according to the first synchronization signal, and using the first effective edge Using the edge as a reference, adjust the phase difference between the second local oscillator signal and the reference clock signal.
  • the phase difference between the initial phases of the first local oscillator signal and the second local oscillator signal can be adjusted is 0, thereby laying a foundation for the phase synchronization of the first local oscillator signal and the second local oscillator signal, and then laying a foundation for the phase synchronization of the first reference signal and the second reference signal.
  • the first wireless communication device adjusts the phase difference between the first local oscillator signal output by the first phase-locked loop and the reference clock signal according to the first synchronization signal, including: According to the first synchronization signal, determine the first effective edge of the reference clock signal, and take the first effective edge as a reference, according to the first feedback frequency divider of the first phase-locked loop to the first frequency divider of the first phase-locked loop The frequency-divided signal of the first local oscillator signal is output, and the phase difference between the first local oscillator signal and the reference clock signal is adjusted.
  • the first wireless communication device adjusts the phase difference between the second local oscillator signal output by the second phase-locked loop and the reference clock signal according to the first synchronization signal, including: determining the first effective edge according to the first synchronization signal, and using the first effective edge edge as a reference, adjust the second local oscillator signal and The phase difference of the reference clock signal.
  • the first feedback frequency divider divides the frequency of the signal output by the first frequency divider and then feeds it back to the first phase-locked loop to adjust the phase difference between the first local oscillator signal and the reference clock signal.
  • the second feedback frequency divider divides the signal output by the second frequency divider and feeds it back to the second phase-locked loop to adjust the phase difference between the second local oscillator signal and the reference clock signal. Therefore, the second frequency divider can be reduced.
  • the phase jitter caused by the randomness of the starting clock edge of the first frequency divider and the second frequency divider.
  • the phase difference between the first local oscillator signal and the reference clock signal is equal to the phase difference between the second local oscillator signal and the reference clock.
  • the phase difference between the first local oscillator signal and the reference clock signal can be 0 or a preset value. In this way, a foundation can be laid for substantially synchronizing the phases of the first local oscillation signal and the second local oscillation signal, and then laying a foundation for substantially synchronizing the phases of the first reference signal and the second reference signal.
  • the first wireless communication device may further send the second synchronization signal to the first phase-locked loop and the second phase-locked loop respectively. Perform frequency division processing on the signal input by the first frequency divider of the first phase-locked loop according to the second synchronization signal. Perform frequency division processing on the signal input by the second frequency divider of the second phase-locked loop according to the second synchronization signal.
  • the frequency dividers of the two phase-locked loops all perform frequency division processing according to the same second synchronous signal, the first reference signal and the second synchronization signal caused by the randomness of the starting clock edges of the two frequency dividers can be alleviated. Phase jitter between two reference signals.
  • frequency division ratios of the first frequency divider and the second frequency divider are the same.
  • a foundation can be laid for substantially synchronizing the phases of the first local oscillation signal and the second local oscillation signal, and then laying a foundation for substantially synchronizing the phases of the first reference signal and the second reference signal.
  • the first wireless communication device may further send the second synchronization signal to the first frequency divider and the second frequency divider respectively.
  • the second synchronization signal it is determined that the first rising edge of the signal output by the first oscillator is the starting clock edge for frequency division.
  • the second synchronization signal it is determined that the second rising edge of the signal output by the second oscillator is the starting clock edge for frequency division.
  • the phase difference between the first rising edge and the second rising edge is equal to: the phase difference between the signal output by the first oscillator and the signal output by the second oscillator.
  • the phase jitter caused by the randomness of the initial clock edges of the first frequency divider and the second frequency divider can be alleviated, and then can be
  • the phase synchronization of the first local oscillation signal and the second local oscillation signal lays a foundation for substantially synchronizing the phases of the first reference signal and the second reference signal.
  • the difference between the phase difference between the first local oscillator signal and the reference clock signal and the phase difference between the second local oscillator signal and the reference clock signal less than the preset phase difference threshold. In this way, the phases of the first reference signal and the second reference signal can be approximately synchronized.
  • the difference between the phase difference between the first local oscillator signal and the reference clock signal and the phase difference between the second local oscillator signal and the reference clock signal Equal to: the phase difference between the signal output by the first oscillator of the first phase-locked loop and the signal output by the second oscillator of the second phase-locked loop.
  • the phases of the first reference signal and the second reference signal can be approximately synchronized, and the phase difference between the two is relatively small, which can be within the error range, and can meet the requirements of the first reference signal and the second reference signal for jointly estimating the reference signal. Arrival time required.
  • the first wireless communication device may further output the third synchronization signal to the third phase-locked loop.
  • Generate a third local oscillator signal adjust the phase difference between the third local oscillator signal and the reference clock signal according to the third synchronization signal; the center frequency of the third local oscillator signal is the same as the center frequency of the first reference signal.
  • the fourth local oscillator signal is generated, and the phase difference between the fourth local oscillator signal and the reference clock signal is adjusted according to the third synchronization signal; the center frequency of the fourth local oscillator signal is the same as the center frequency of the second reference signal.
  • the frequency of the third synchronization signal is a common divisor of the frequency of the center frequency point of the third local oscillation signal and the frequency of the center frequency point of the fourth local oscillation signal.
  • phase difference between the third local oscillator signal and the reference signal is adjusted based on the third synchronization signal, when the third phase-locked loop loses lock and then relocks, adjust the phase difference between the fourth local oscillator signal and the reference signal based on the third synchronization signal
  • the phase difference can reduce the phase jitter introduced by the relock after the third phase locked loop loses lock.
  • the first wireless communication device may also use the third synchronization signal, and the third feedback frequency divider of the third phase-locked loop on the third phase-locked loop
  • the frequency-divided third local oscillator signal output by the third frequency divider is used to adjust the phase difference between the third local oscillator signal and the reference clock signal.
  • Adjust the fourth local oscillator according to the third synchronous signal and the signal obtained by frequency-dividing the fourth local oscillator signal output by the third frequency divider of the third phase-locked loop by the third feedback frequency divider of the third phase-locked loop The phase difference between the signal and the reference clock signal.
  • the third feedback frequency divider divides the signal output by the third frequency divider and then feeds it back to the third phase-locked loop to adjust the output signal (the third local oscillator signal and the fourth local oscillator signal) and the reference The phase difference of the clock signal. Therefore, the phase jitter caused by the randomness of the starting clock edge during the two locking processes of the third frequency divider before and after the phase locked loop can be alleviated.
  • the phase-adjusted third local oscillator signal is in phase synchronization with the reference clock signal
  • the phase-adjusted fourth local oscillator signal is in phase synchronization with the reference clock signal . Therefore, a foundation is laid for the phase synchronization of the first local oscillator signal and the second local oscillator signal, and then a foundation is laid for the phase synchronization of the first reference signal and the second reference signal.
  • the phase difference between the phase-adjusted third local oscillator signal and the third synchronization signal is the same as the phase difference between the phase-adjusted fourth local oscillator signal and Phase differences between the third synchronization signals are equal. Therefore, a foundation is laid for the phase synchronization of the first local oscillator signal and the second local oscillator signal, and then a foundation is laid for the phase synchronization of the first reference signal and the second reference signal.
  • the phase of the third synchronization signal is synchronized with the reference clock signal.
  • the phase-adjusted third local oscillator signal is in phase synchronization with the third synchronization signal.
  • the phase-adjusted fourth local oscillator signal is in phase synchronization with the third synchronization signal. Therefore, the phases of the first local oscillator signal and the second local oscillator signal can be substantially synchronized, and the phases of the first reference signal and the second reference signal can be substantially synchronized.
  • the first wireless communication device may also input a third synchronization signal to the third phase-locked loop in a locked state of the third phase-locked loop.
  • the third phase-locked loop is in an unlocked state, stop inputting the third synchronization signal to the third phase-locked loop. In this way, the third synchronization signal input to the third phase-locked loop can be reduced, thereby saving the power consumption of the wireless communication device.
  • the third phase-locked loop includes a third frequency divider and a third feedback frequency divider, and the input terminal of the third feedback frequency divider is connected to the third frequency divider the output terminal of the device. Because the third feedback frequency divider divides the signal output by the third frequency divider and then feeds it back to the third phase-locked loop to adjust the output signal (the third local oscillator signal and the fourth local oscillator signal) and the reference The phase difference of the clock signal. Therefore, the phase jitter caused by the randomness of the starting clock edge during the two locking processes of the third frequency divider before and after the phase locked loop can be alleviated.
  • the first wireless communication apparatus sends the first reference signal in the first frequency band, and before sending the second reference signal in the second frequency band, the method further includes: entering sleep.
  • the wake-up time arrives, perform a wake-up.
  • the first reference signal and the second reference signal are sent during wake-up. And then go to sleep again. In this way, the power consumption of the wireless communication device can be saved.
  • the first wireless communication device sends the first reference signal in the first frequency band, and before sending the second reference signal in the second frequency band, further includes: receiving configuration information,
  • the configuration information includes information about time-domain resources for sending signals in an idle state/inactive state. Receive an RRC connection release message. go to sleep. According to the resource information in the time domain, when the wake-up time arrives, the wake-up is performed. In this way, the wake-up time can be determined according to the time-domain resource information configured for the first wireless communication device.
  • the present application provides a method for estimating a time of arrival of a reference signal, and the method can be executed by a second wireless communication device.
  • the method includes: the second wireless communication device receives a first reference signal, where the first reference signal is a signal of a first frequency band. receiving a second reference signal; the second reference signal is a signal of a second frequency band; wherein, the sending time of the first reference signal is different from the sending time of the second reference signal, and the center frequency point of the first frequency band is different from the center frequency point of the second frequency band point is different; wherein, the phases of the first reference signal and the second reference signal are substantially synchronous.
  • the time of arrival of the reference signal is jointly estimated according to the first reference signal and the second reference signal.
  • the third frequency band includes the first frequency band and the second frequency band, and when there is a spaced frequency band between the first frequency band and the second frequency band, the third frequency band also includes the first frequency band and the second frequency band.
  • the frequency band spaced between the second frequency bands is a scheme for estimating the time of arrival of the reference signal.
  • the estimation accuracy of the time of arrival of the reference signal is equivalent to it, but this application can make the radio frequency channel of the wireless communication device only have the ability to support sending the first frequency band
  • the ability to transmit signals in the second frequency band is enough, and it is not required to support the transmission of signals in the third frequency band. It can be seen that this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.
  • the present application provides a method for estimating a time of arrival of a reference signal, and the method may be executed by a second wireless communication device.
  • the method includes: the second wireless communication device receives a first reference signal, where the first reference signal is a signal of a first frequency band;
  • the second reference signal is a signal in a second frequency band; wherein, the first reference signal and the second reference signal are sent by frequency hopping, wherein the frequency ranges of the first reference signal and the second reference signal are different but The phase is substantially synchronized;
  • the time of arrival of the reference signal is jointly estimated according to the first reference signal and the second reference signal.
  • the third frequency band includes the first frequency band and the second frequency band, and when there is a spaced frequency band between the first frequency band and the second frequency band, the third frequency band also includes the first frequency band and the second frequency band.
  • the frequency band spaced between the second frequency bands is a scheme for estimating the time of arrival of the reference signal.
  • the estimation accuracy of the time of arrival of the reference signal is equivalent to it, but this application can make the radio frequency channel of the wireless communication device only have the ability to support sending the first frequency band
  • the ability to transmit signals in the second frequency band is enough, and it is not required to support the transmission of signals in the third frequency band. It can be seen that this application can improve the positioning accuracy of wireless communication devices with weak transmission capabilities.
  • the reference signal arrival time can be used to estimate the position of the wireless communication device. As the estimation accuracy of the reference time of arrival is improved, the accuracy of the position of the wireless communication device estimated based on the reference time of arrival is also improved.
  • the second wireless communication device may superimpose the first reference signal and the second reference signal in the time domain direction to obtain the third reference signal.
  • the reference signal arrival time is estimated based on the third reference signal. In this way, a solution for jointly estimating the arrival time of the reference signal according to the first reference signal and the second reference signal can be provided.
  • the second wireless communication device may sample the received signal corresponding to the first reference signal according to the sampling rate corresponding to the bandwidth of the third frequency band to obtain the first a reference signal. According to the sampling rate corresponding to the bandwidth of the third frequency band, the received signal corresponding to the second reference signal is sampled to obtain the second reference signal.
  • the third frequency band includes the first frequency band, the second frequency band, and a frequency band spaced between the first frequency band and the second frequency band.
  • the corresponding sampling rate can be higher, so the first reference signal and the second reference signal can be obtained based on the higher sampling rate, and then the estimation accuracy of the arrival time of the reference signal can be improved.
  • a wireless communication device including a communication unit and a processing unit, so as to implement the above first aspect. Any one of the second aspect, the third aspect and the fourth aspect or any implementation mode of any aspect.
  • the communication unit is used to perform functions related to transmission and reception.
  • the communication unit includes a receiving unit and a sending unit.
  • the wireless communication device is a communication chip
  • the processing unit may be one or more processors or processor cores
  • the communication unit may be an input/output circuit or port of the communication chip.
  • the communication unit may be a transmitter and a receiver, or the communication unit may be a transmitter and a receiver.
  • the wireless communication device further includes various modules that can be used to implement any implementation manner of any communication method in the first aspect above.
  • a wireless communication device including a processor and a memory.
  • a transceiver is also included, the memory is used to store computer programs or instructions, the processor is used to call and run the computer programs or instructions from the memory, and when the processor executes the computer programs or instructions in the memory, the The wireless communication device implements any one of the first aspect, the second aspect, the third aspect, and the fourth aspect or any implementation manner of any aspect.
  • processors there are one or more processors, and one or more memories.
  • the memory may be integrated with the processor, or the memory may be separated from the processor.
  • the transceiver may include a transmitter (transmitter) and a receiver (receiver).
  • a wireless communication device including a processor.
  • the processor is coupled with the memory, and can be used to execute any one of the first aspect, the second aspect, the third aspect and the fourth aspect or any implementation manner of any aspect.
  • the wireless communication device further includes a memory.
  • the wireless communication device further includes a communication interface, and the processor is coupled to the communication interface.
  • the communication interface may be a transceiver, or an input/output interface.
  • the transceiver may be a transceiver circuit.
  • the input/output interface may be an input/output circuit.
  • the communication interface may be an input/output interface, interface circuit, output circuit, input circuit, pin or related circuit on the chip or chip system wait.
  • a processor may also be embodied as processing circuitry or logic circuitry.
  • a system in an eighth aspect, includes the above wireless communication device and a second wireless communication device.
  • a computer program product includes: a computer program (also referred to as code, or instruction), which, when the computer program is run, causes the computer to perform the above-mentioned first aspect, second aspect, and first aspect. Any one or any implementation of any aspect of the third aspect and the fourth aspect.
  • a computer-readable storage medium stores a computer program (also referred to as code, or instruction) which, when running on a computer, enables the computer to execute the above-mentioned first aspect and second aspect.
  • a computer program also referred to as code, or instruction
  • a chip system may include a processor.
  • the processor is coupled with the memory, and may be used to execute any one of the first aspect, the second aspect, the third aspect, and the fourth aspect or any implementation manner of any aspect.
  • the chip system further includes a memory.
  • Memory used to store computer programs (also called code, or instructions).
  • the processor is configured to call and run a computer program from the memory, so that the device installed with the system-on-a-chip executes any one of the first aspect, the second aspect, the third aspect and the fourth aspect or any implementation manner of any aspect.
  • a processing device including: an interface circuit and a processing circuit.
  • Interface circuitry may include input circuitry and output circuitry.
  • the processing circuit is used to receive signals through the input circuit and transmit signals through the output circuit, so that any one of the first aspect, the second aspect, the third aspect and the fourth aspect or any implementation manner of any aspect is realized.
  • the above-mentioned processing device may be a chip
  • the input circuit may be an input pin
  • the output circuit may be an output pin
  • the processing circuit may be a transistor, a gate circuit, a flip-flop, and various logic circuits.
  • the input signal received by the input circuit may be received and input by, for example but not limited to, the receiver
  • the output signal of the output circuit may be, for example but not limited to, output to the transmitter and transmitted by the transmitter
  • the circuit may be the same circuit, which is used as an input circuit and an output circuit respectively at different times.
  • the present application does not limit the specific implementation manners of the processor and various circuits.
  • the first wireless communication device when the wireless communication device is a first wireless communication device, the first wireless communication device may be a terminal such as a smart phone, or may be a radio access network device such as a base station.
  • the interface circuit may be a radio frequency processing chip in the first wireless communication device, and the processing circuit may be a baseband processing chip in the first wireless communication device.
  • the wireless communication device may be a part of the first wireless communication device, such as an integrated circuit product such as a system chip or a communication chip.
  • the interface circuit may be an input/output interface, interface circuit, output circuit, input circuit, pin or related circuit on the chip or chip system.
  • the processing circuitry may be logic circuitry on the chip.
  • FIG. 1 is a schematic structural diagram of a wireless communication system provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a wireless communication device provided by an embodiment of the present application.
  • FIG. 3a is a schematic diagram of a method for estimating a location of a wireless communication device provided in an embodiment of the present application
  • FIG. 3b is a schematic diagram of a 10MHz and 20MHz clock signal phase synchronization provided by the embodiment of the present application.
  • FIG. 3c is a schematic diagram of a 20MHz and 30MHz clock signal phase synchronization provided by the embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for estimating the time of arrival of a reference signal according to an embodiment of the present application
  • FIG. 5 is a schematic flowchart of a method for sending a first reference signal and a second reference signal by the first wireless communication device in S401 in FIG. 4;
  • FIG. 6 is a schematic diagram of an example in which a first wireless communication device sends a first reference signal and a second reference signal according to an embodiment of the present application;
  • FIG. 7 is a schematic structural diagram of a first wireless communication device provided by an embodiment of the present application.
  • FIG. 8a is a schematic structural diagram of a phase-locked loop 75 and a phase-locked loop 76 in FIG. 7 provided by an embodiment of the present application;
  • FIG. 8b is a schematic diagram of the reference clock signal, the locking signal and the first synchronization signal in FIG. 8a;
  • Figure 8c is a schematic diagram of the frequency of the signal output by the phase-locked loop 75 in Figure 8a, the phase difference detected by the phase detector 751, and the synchronization signal output by the first synchronization module;
  • FIG. 9a is a schematic structural diagram of a phase-locked loop 75 and a phase-locked loop 76 in FIG. 7 provided by an embodiment of the present application;
  • Figure 9b is a reference clock signal, a locking signal and a second synchronization signal, the signal output by the oscillator 754, the signal output by the oscillator 764, the signal output by the frequency divider 756, and the signal output by the frequency divider 766 in Figure 9a schematic diagram;
  • FIG. 10 is a schematic structural diagram of a phase-locked loop 75 and a phase-locked loop 76 in FIG. 7 provided by an embodiment of the present application;
  • FIG. 11 is a schematic structural diagram of another first wireless communication device provided by an embodiment of the present application.
  • Fig. 12a is a schematic structural diagram of the phase-locked loop 81 in Fig. 11;
  • Fig. 12b is a schematic diagram of the reference clock signal, the locking signal of the phase-locked loop 81, the signal output by the third synchronization module and the signal output by the phase-locked loop 81 in Fig. 12a;
  • FIG. 13 is a schematic diagram of another structure of the phase-locked loop 81 in FIG. 11;
  • FIG. 14 is a possible implementation of S402 in FIG. 4;
  • FIG. 15 is a schematic diagram of a simulation environment provided by an embodiment of the present application.
  • FIG. 16 is a schematic structural diagram of another wireless communication device provided by an embodiment of the present application.
  • FIG. 17 is a schematic structural diagram of another wireless communication device provided by an embodiment of the present application.
  • FIG. 18 is a schematic structural diagram of another wireless communication device provided by an embodiment of the present application.
  • the technical solutions provided in the embodiments of the present application are mainly applicable to wireless communication systems.
  • the wireless communication system may comply with the wireless communication standard of the third generation partnership project (3GPP).
  • 3GPP third generation partnership project
  • the solution provided in the embodiment of the present application can be applied to a fourth generation (4th generation, 4G) communication system, such as a long term evolution (long term evolution, LTE) communication system, and can also be applied to a fifth generation (5th generation, 5G) A communication system, such as a 5G new radio (new radio, NR) communication system, or various communication systems applied in the future, such as a sixth generation (6th generation, 6G) communication system.
  • 4G fourth generation
  • LTE long term evolution
  • 5th generation, 5G 5th generation
  • a communication system such as a 5G new radio (new radio, NR) communication system
  • 6G sixth generation
  • the technical solutions provided in the embodiments of the present application may also comply with other wireless communication standards, such as the 802 series (such as 802.11, 802.15, or 802.20) wireless communication standards of the Institute of Electrical and Electronics Engineers (IEEE).
  • the method provided in the embodiment of the present application can also be applied to a Bluetooth system, a WiFi system, a LoRa system or a vehicle networking system.
  • the method provided in the embodiment of the present application may also be applied to a satellite communication system, where the satellite communication system may be integrated with the above-mentioned communication system.
  • the devices in the communication system to which the embodiments of the present application are applicable can be divided into: devices providing wireless network services and devices using wireless network services.
  • a network device includes an access network (access network, AN) device, such as a base station (for example, an access point), which may refer to a device in an access network that communicates with a wireless terminal device through one or more cells through an air interface.
  • AN access network
  • the base station can be used to convert received over-the-air frames to and from Internet Protocol (IP) packets and act as a router between the terminal device and the rest of the access network, which can include an IP network.
  • IP Internet Protocol
  • the RSU can be a fixed infrastructure entity supporting V2X applications, and can exchange messages with other entities supporting V2X applications.
  • the network device can also coordinate the attribute management of the air interface.
  • the network equipment may include an evolved base station (NodeB or eNB or e-NodeB, evolutional Node B) in the LTE system or long term evolution-advanced (LTE-A), or may also include a fifth generation mobile
  • the next generation node B (next generation node B, gNB) in the communication technology (the 5 th generation, 5G) new radio (new radio, NR) system may also include the cloud access network (cloud radio access network, Cloud RAN)
  • the embodiment of the present application does not limit the centralized unit (centralized unit, CU) and distributed unit (distributed unit, DU) in the system.
  • a device using a wireless network service may be referred to as a terminal device (terminal) or a terminal device for short.
  • Terminal devices include devices that provide voice and/or data connectivity to a user, and may include, for example, handheld devices with wireless connectivity, or processing devices connected to a wireless modem.
  • the terminal device can communicate with the core network via a radio access network (radio access network, RAN), and exchange voice and/or data with the RAN.
  • radio access network radio access network
  • the terminal device may include user equipment (user equipment, UE), wireless terminal device, mobile terminal device, device-to-device communication (device-to-device, D2D) terminal device, V2X terminal device, machine-to-machine/machine-type communication ( machine-to-machine/machine-type communications, M2M/MTC) terminal equipment, internet of things (IoT) terminal equipment, subscriber unit, subscriber station, mobile station , remote station (remote station), access point (access point, AP), remote terminal equipment (remote terminal), access terminal equipment (access terminal), user terminal equipment (user terminal), user agent (user agent), Or user equipment (user device), etc.
  • IoT internet of things
  • it may include mobile phones (or “cellular” phones), computers with mobile terminal equipment, portable, pocket, hand-held, computer built-in mobile devices, and the like.
  • PCS personal communication service
  • cordless telephone cordless telephone
  • session initiation protocol session initiation protocol
  • WLL wireless local loop
  • PDA personal digital assistant
  • constrained devices such as devices with low power consumption, or devices with limited storage capabilities, or devices with limited computing capabilities, etc.
  • it includes barcodes, radio frequency identification (radio frequency identification, RFID), sensors, global positioning system (global positioning system, GPS), laser scanners and other information sensing devices.
  • FIG. 1 is a schematic structural diagram of a wireless communication system provided by an embodiment of the present application.
  • a wireless communication system includes a terminal device and a base station. According to different transmission directions, a transmission link from a terminal device to a base station is marked as an uplink (uplink, UL), and a transmission link from a base station to a terminal device is marked as a downlink (downlink, DL).
  • uplink uplink
  • downlink downlink
  • data transmission in the uplink may be abbreviated as uplink data transmission or uplink transmission
  • data transmission in the downlink may be abbreviated as downlink data transmission or downlink transmission.
  • the base station can provide communication coverage for a specific geographical area through an integrated or external antenna device.
  • One or more terminal devices within the communication coverage of the base station can access the base station.
  • One base station can manage one or more cells. Each cell has an identification (identification), which is also called a cell identity (cell ID). From the perspective of radio resources, a cell is a combination of downlink radio resources and its paired uplink radio resources (not necessary).
  • Terminal equipment and base stations should know the predefined configuration of the wireless communication system, including the radio access technology (radio access technology, RAT) supported by the system and the wireless resource configuration specified by the system, such as the basic configuration of the radio frequency band and carrier.
  • the carrier is a frequency range that complies with system regulations. This frequency range can be jointly determined by the center frequency of the carrier (referred to as the carrier frequency) and the bandwidth of the carrier.
  • the predefined configurations of these systems can be used as part of the standard protocol of the wireless communication system, or determined through the interaction between the terminal equipment and the base station.
  • the content of relevant standard protocols may be pre-stored in the memory of terminal equipment and base stations, or embodied as hardware circuits or software codes of terminal equipment and base stations.
  • the terminal equipment and the base station support one or more of the same RAT, such as 5G NR, 4G LTE, or the RAT of the future evolution system.
  • the terminal device and the base station use the same air interface parameters, coding scheme, modulation scheme, etc., and communicate with each other based on the wireless resources specified by the system.
  • FIG. 2 is a schematic structural diagram of a wireless communication device provided by an embodiment of the present application.
  • the wireless communication apparatus may be the terminal device in the embodiment of the present application, for example, the terminal device in FIG. 1 .
  • the wireless communication device may also be the network device in the embodiment of the present application, such as the base station in FIG. 1 .
  • the wireless communication device may include a processing circuit and an interface circuit.
  • Interface circuitry may include input circuitry and output circuitry.
  • the processing circuit is adapted to receive signals through the input circuit and transmit signals through the output circuit, so that the related methods of FIGS. 4 and 5 described below are implemented.
  • the processing circuit may execute the following S401, S503, S504, and S506 through the control interface circuit.
  • the processing circuit may execute the following S402, S502, and S505 through the control interface circuit.
  • the first synchronization module, the second synchronization module, and the third synchronization module mentioned later in the embodiments of the present application may all be modules in the processing circuit.
  • the interface circuit may also be a radio frequency processing chip in the wireless communication device, and the processing circuit may be a baseband processing chip in the wireless communication device.
  • the wireless communication device may be a part of a wireless communication device, such as an integrated circuit product such as a system chip or a communication chip.
  • the interface circuit may be an input/output interface, interface circuit, output circuit, input circuit, pin or related circuit on the chip or chip system.
  • the processing circuitry may be logic circuitry on the chip.
  • the processing circuit in the embodiment of the present application may also be a processor or a part of modules or units in the processor, and the interface circuit may also be a radio frequency channel or a part of devices in the radio frequency channel.
  • the processor is used to control the radio frequency channel, so that the related methods in Fig. 4 and Fig. 5 described below are implemented.
  • the wireless communication device may include multiple components, for example: application subsystem, memory (memory), mass storage (massive storage), baseband subsystem, radio frequency integrated circuit (radio frequency integrated circuit, RFIC) , RF front end (radio frequency front end, RFFE) device, and antenna (antenna, ANT). These components can be coupled by various interconnecting buses or other electrical connections.
  • application subsystem memory (memory), mass storage (massive storage), baseband subsystem, radio frequency integrated circuit (radio frequency integrated circuit, RFIC) , RF front end (radio frequency front end, RFFE) device, and antenna (antenna, ANT).
  • RFIC radio frequency integrated circuit
  • RFFE radio frequency front end
  • antenna antenna
  • the application subsystem in FIG. 2 may be the processor 110 in FIG. 2 , or a module in the processor 110 .
  • ANT_1 represents the first antenna
  • ANT_N represents the Nth antenna
  • N is a positive integer greater than 1.
  • Tx represents the sending path
  • Rx represents the receiving path
  • different numbers represent different paths.
  • Each path can represent a signal processing channel.
  • FBRx represents a feedback receiving path
  • PRx represents a main receiving path
  • DRx represents a diversity receiving path.
  • HB means high frequency
  • LB means low frequency, both refer to the relative high and low frequencies.
  • BB means baseband.
  • the application subsystem can be used as the main control system or the main computing system of the communication device, used to run the main operating system and application programs, manage the software and hardware resources of the entire communication device, and provide the user with a user interface.
  • the application subsystem may also include driver software related to other subsystems (eg, baseband subsystem).
  • An application subsystem may include one or more processors.
  • the multiple processors may be multiple processors of the same type, or may include a combination of multiple types of processors.
  • the processor may be a general-purpose processor or a processor designed for a specific field.
  • the processor may be a central processing unit (center processing unit, CPU), a digital signal processor (digital signal processor, DSP), or a microcontroller (micro control unit, MCU).
  • the processor can also be a graphics processing unit (graphics processing unit, GPU), an image signal processor (image signal processing, ISP), an audio signal processor (audio signal processor, ASP), and an artificial intelligence (artificial intelligence, AI) Apply a specially designed AI processor.
  • AI processors include but are not limited to neural network processing unit (NPU), tensor processing unit (TPU) and processors called AI engines.
  • radio frequency integrated circuits including RFIC 1, and one or more optional RFIC 2 and radio frequency front-end devices can together form a radio frequency subsystem.
  • the RF subsystem can also be divided into RF receive path (RF receive path) and RF transmit path (RF transmit path).
  • the radio frequency receiving channel can receive the radio frequency signal through the antenna, process the radio frequency signal (such as amplifying, filtering and down-converting) to obtain the baseband signal, and transmit it to the baseband subsystem.
  • the radio frequency transmission channel can receive the baseband signal from the baseband subsystem, process the baseband signal (such as up-converting, amplifying and filtering) to obtain a radio frequency signal, and finally radiate the radio frequency signal into space through the antenna.
  • Radio frequency integrated circuits may be referred to as radio frequency processing chips or radio frequency chips.
  • the radio frequency subsystem may include an antenna switch, an antenna tuner, a low noise amplifier (low noise amplifier, LNA), a power amplifier (power amplifier, PA), a mixer (mixer), a local oscillator (local oscillator, LO ), filters and other electronic devices, these electronic devices can be integrated into one or more chips as required.
  • Radio frequency integrated circuits may be referred to as radio frequency processing chips or radio frequency chips.
  • the RF front-end device can also be a stand-alone chip. RF chips are sometimes called receivers, transmitters, transceivers or transceivers. With the evolution of technology, the antenna can sometimes be considered as a part of the radio frequency subsystem and can be integrated into the chip of the radio frequency subsystem.
  • radio frequency subsystem can also use different devices or different integration methods based on power consumption and performance requirements. For example, if some devices belonging to the radio frequency front end are integrated into the radio frequency chip, even the antenna and the radio frequency front end devices are integrated into the radio frequency chip, the radio frequency chip may also be called a radio frequency antenna module or an antenna module.
  • the baseband subsystem mainly completes the processing of baseband signals.
  • the baseband subsystem can extract useful information or data bits from baseband signals, or convert information or data bits into baseband signals to be transmitted. These information or data bits may be data representing user data such as voice, text, video, or control information.
  • the baseband subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding.
  • signal processing operations are not exactly the same.
  • the radio frequency signal is usually an analog signal
  • the signal processed by the baseband subsystem is mainly a digital signal
  • an analog-to-digital conversion device is also required in the communication device.
  • the analog-to-digital conversion device may be set in the baseband subsystem, or may be set in the radio frequency subsystem.
  • Analog to digital conversion devices include an analog to digital converter (analog to digital converter, ADC) that converts an analog signal into a digital signal, and a digital to analog converter (digital to analog converter, DAC) that converts a digital signal to an analog signal.
  • the baseband subsystem may also include one or more processors.
  • the baseband subsystem may also include one or more hardware accelerators (hardware accelerator, HAC).
  • Hardware accelerators can be used to specifically complete some sub-functions with high processing overhead, such as assembly and analysis of data packets, encryption and decryption of data packets, etc. These sub-functions can also be implemented by using a general-purpose processor, but due to performance or cost considerations, it may be more appropriate to use a hardware accelerator.
  • the hardware accelerator is mainly realized by an application specified integrated circuit (ASIC).
  • ASIC application specified integrated circuit
  • one or more relatively simple processors, such as MCUs may also be included in the hardware accelerator.
  • the baseband subsystem and the radio frequency subsystem together form a communication subsystem, which provides a wireless communication function for a communication device.
  • the baseband subsystem is responsible for managing the hardware and software resources of the communication subsystem, and can configure the working parameters of the radio frequency subsystem.
  • the processor of the baseband subsystem can run a subsystem operating system of the communication subsystem, which is often an embedded operating system or a real time operating system (real time operating system), such as the VxWorks operating system or the QuRT system of Qualcomm.
  • the baseband subsystem can be integrated into one or more chips, which can be called baseband processing chips or baseband chips.
  • the baseband subsystem can be used as an independent chip, and the chip can be called a modem (modem) or a modem chip.
  • the baseband subsystem can be manufactured and sold in units of modem chips. Modem chips are sometimes called baseband processors or mobile processors.
  • the baseband subsystem can also be further integrated into a larger chip, and manufactured and sold in units of a larger chip. This larger chip can be called a system-on-a-chip, system-on-a-chip, or system-on-a-chip (SoC), or simply an SoC chip.
  • SoC system-on-a-chip
  • the software components of the baseband subsystem can be built into the hardware components of the chip before the chip leaves the factory, or can be imported into the hardware components of the chip from other non-volatile memories after the chip leaves the factory, or can be downloaded online through the network and update these software components.
  • the communication device also includes memory, such as memory and mass storage in FIG. 2 .
  • the application subsystem and the baseband subsystem may also include one or more buffers respectively.
  • the memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory, NVM).
  • Volatile memory refers to memory in which data stored inside will be lost when the power supply is interrupted.
  • volatile memory is mainly random access memory (random access memory, RAM), including static random access memory (static RAM, SRAM) and dynamic random access memory (dynamic RAM, DRAM).
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • Non-volatile memory refers to memory in which the data stored inside will not be lost even if the power supply is interrupted.
  • Non-volatile memories include read only memory (ROM), optical discs, magnetic disks, and various memories based on flash memory (flash memory) technology.
  • volatile memory can be used for memory and cache
  • non-volatile memory such as flash memory, can be used for large-capacity storage.
  • the solution provided by the embodiment of the present application is applicable to the positioning of the first wireless communication device.
  • the first wireless communication device may be a terminal device or a network device.
  • the first wireless communication device for positioning is used as the terminal equipment as an example.
  • 5G NR defines a variety of positioning methods based on TOA estimation, such as observed time difference of arrival (OTDOA), multiple round trip time (round trip time, Multi-RTT), downlink time difference of arrival (downlink time difference of arrival, DL-TDOA), uplink time difference of arrival (uplink time difference of arrival, UL-TDOA).
  • OTDOA observed time difference of arrival
  • Multi-RTT round trip time
  • downlink time difference of arrival downlink time difference of arrival
  • DL-TDOA downlink time difference of arrival
  • uplink time difference of arrival uplink time difference of arrival
  • Fig. 3a exemplarily shows a schematic diagram of a positioning method provided by an embodiment of the present application.
  • a terminal device can send uplink Reference signal, different network devices measure the TOA of the uplink reference signal.
  • the network device reports the TOA to the positioning server.
  • the positioning server can calculate the time difference of arrival (time difference of arrival, OTDOA) according to the TOA information between multiple network devices and the terminal device, and obtain the location information of the terminal device according to the known location information of the network devices.
  • OTDOA time difference of arrival
  • the positioning server knows the location information of base station 301, base station 302, and base station 303, and knows the TOA information between each network device and terminal device, then the terminal can be obtained by solving the hyperbolic equation in Figure 3a.
  • Device location information In yet another possible implementation manner, the terminal device may also have a positioning capability, for example, the terminal device may request location information and locate its own location information by itself.
  • the terminal device requests location information from the network device, and multiple network devices respectively send downlink positioning reference signals (positioning reference signals, PRS) to the terminal device, and the terminal device respectively measures the TOA of multiple network devices based on the downlink PRS, and the terminal device According to the known positions of each network device, the position information of the terminal device can be determined, or the terminal device reports the TOA information of each network device to the positioning server.
  • the positioning server calculates the TDOA according to TOA information between multiple network devices and the terminal device, and obtains the location information of the terminal device according to the known location information of the network devices.
  • the location server may be, for example, a location management function (location management function, LMF) in the NR system.
  • LMF location management function
  • the Access and Mobility Management Function (AMF) receives service requests about terminal equipment initiated by other network elements in the network, and AMF sends information about the terminal equipment to the LMF.
  • AMF Access and Mobility Management Function
  • the LMF receives the positioning request from the AMF, initiates the positioning of the terminal device, and determines the positioning information of the terminal device.
  • the positioning method provided by the implementation of this application can be applied to various industries and businesses, so as to locate people and objects, so as to obtain the location information of personnel and materials, and further application development can be carried out based on the location information.
  • the positioning method provided by the embodiment of the present application can be applied to industrial application scenarios, such as intelligent manufacturing, storage physics, electric energy, public security and judicial departments, etc., for example, to realize the positioning of objects.
  • the terminal device that needs to be positioned may be a material and/or device that is fixed or integrated with a positioning tag.
  • the positioning method provided by the embodiment of the present application can be applied to consumer application scenarios, such as museum exhibitions, smart supermarkets, transportation hubs, etc., for example, can be used to realize the positioning of people, so as to provide services such as indoor navigation and tour services .
  • the terminal device that needs to be positioned may be a mobile phone or other device.
  • Fig. 3 b exemplarily shows a schematic diagram of a 10 megahertz (mega hertz, MHz) and 20 MHz signal phase synchronization provided by the embodiment of the present application. As shown in Fig. 3 b, the rising edge of the 20 MHz signal is aligned to the 10 MHz frequency on the rising edge of the signal.
  • the phase synchronization of the two signals means that the rising edges of the clocks of the two signals are aligned to the rising edges of the signal of the greatest common divisor frequency
  • the signal at the greatest common divisor frequency is a signal independent of the two signals.
  • Figure 3c exemplarily shows a schematic diagram of a 20MHz, 30MHz and 40MHz signal phase synchronization provided by the embodiment of the present application.
  • the greatest common divisor of 20MHz, 30MHz and 40MHz is 10MHz, then 20MHz, 30MHz and the rising edge of the 40MHz signal are aligned to the rising edge of the 10MHz frequency signal.
  • the greatest common divisor of 12.288MHz and 30.72MHz is 6.144MHz, then the rising edges of the 12.288MHz and 30.72MHz signals are aligned with the rising edges of the 6.144MHz frequency signal.
  • the two signals may also be referred to as two clock signals.
  • the phase synchronization of the two signals may also be referred to as the continuous phase of the two signals.
  • FIG. 4 exemplarily shows a flowchart of a method for estimating the time of arrival of a reference signal according to an embodiment of the present application.
  • the solution provided in FIG. 4 can be used to determine the time of arrival of the reference signal mentioned above.
  • the method may be executed by the first wireless communication device and the second wireless communication device.
  • the first wireless communication device is a wireless communication device at a sending end
  • the second wireless communication device is a wireless communication device at a receiving end.
  • the first wireless communication device may be a terminal device or a network device
  • the second wireless communication device may be a terminal device or a network device.
  • the second wireless communication device may be a network device.
  • the second wireless communication device may be a terminal device.
  • the method includes:
  • the first wireless communication apparatus sends a first reference signal in a first frequency band through a first radio frequency channel, and sends a second reference signal in a second frequency band.
  • the phases of the first reference signal and the second reference signal are substantially synchronized, and the first reference signal and the second reference signal can be used to jointly estimate the arrival time of the reference signal.
  • the second wireless communication device receives the first reference signal, and the second wireless communication device receives the second reference signal.
  • the sending time of the first reference signal is different from the sending time of the second reference signal.
  • the center frequency point of the first frequency band is different from the center frequency point of the second frequency band.
  • the difference between the center frequency point of the first frequency band and the center frequency point of the second frequency band may be understood as: the frequency ranges of the first reference signal and the second reference signal are different.
  • the frequency ranges of the first reference signal and the second reference signal may partially overlap or may not overlap at all, and there is an interval frequency band between the frequency range of the first reference signal and the frequency range of the second reference signal.
  • S401 may be replaced by: the first wireless communication apparatus sequentially sends the first reference signal and the second reference signal in a frequency hopping manner.
  • Frequency hopping may mean that the carrier frequency hops within a certain frequency band.
  • the first reference signal and the second reference signal sent by frequency hopping may have the following characteristics: the sending time of the first reference signal is different from the sending time of the second reference signal, and the frequency ranges of the first reference signal and the second reference signal are different.
  • the substance in that the phases of the first reference signal and the second reference signal are substantially synchronized may be understood as substantially.
  • the phase synchronization of the first reference signal and the second reference signal may include two situations:
  • the phases of the first reference signal and the second reference signal are synchronized.
  • the phases of the first reference signal and the second reference signal are approximately synchronous, that is, there is a small phase difference between the first reference signal and the second reference signal, which can also be understood as the phase difference is smaller than the phase difference threshold .
  • the phase difference between the first reference signal and the second reference signal is the phase difference between the signals output by the oscillators of the two phase-locked loops.
  • the first reference signal and the second reference signal may be reference signals used for positioning, for example, they may be downlink PRS, or uplink sounding reference signals (sounding reference signal, SRS).
  • they may be downlink PRS, or uplink sounding reference signals (sounding reference signal, SRS).
  • the second wireless communication apparatus jointly estimates a reference signal arrival time according to the first reference signal and the second reference signal.
  • joint estimation can also be understood as “joint estimation”, etc., which refers to jointly determining the arrival time of the reference signal by combining the first reference signal and the second reference signal.
  • the reference signal time of arrival can be used to estimate the position of the first wireless communication device.
  • the specific solution is as shown in FIG. 3a above.
  • the positioning server may estimate the position of the first wireless communication device by combining the arrival time of the reference signal sent by the first wireless communication device estimated by the multiple wireless communication devices.
  • each wireless communication device may jointly estimate the arrival time of the reference signal according to the first reference signal and the second reference signal.
  • the first wireless communication device may also send multiple signals to the second wireless communication device on multiple frequency bands, and the multiple frequency bands may correspond to the multiple signals one-to-one.
  • the second wireless communication device may receive multiple signals, and superimpose the multiple received signals in a time domain direction, so as to determine a third reference signal.
  • a plurality of signals may refer to two or more signals.
  • the multiple frequency bands are three frequency bands, including a first frequency band, a second frequency band and a fourth frequency band.
  • the sending end sends the first reference signal on the first frequency band, sends the second reference signal on the second frequency band, and sends the third reference signal on the fourth frequency band.
  • the receiving end receives the first reference signal on the first frequency band, receives the second reference signal on the second frequency band, receives the third reference signal on the fourth frequency band, and compares the first reference signal, the second reference signal and the third reference signal
  • the signals are superimposed in the time domain direction to obtain a third reference signal.
  • the multiple signals sent by the first wireless communication device to the second wireless communication device include the first reference signal and the second reference signal as an example for introduction.
  • the reference signal arrival time is jointly estimated based on the first reference signal and the second reference signal, compared with the scheme of estimating the reference signal arrival time only using the first reference signal in the first frequency band, the reference signal used for estimating the reference signal arrival time in this application
  • the frequency domain range occupied by the signal is larger, so that the estimation accuracy of the arrival time of the reference signal can be improved.
  • the third frequency band includes the first frequency band and the second frequency band, and when there is a spaced frequency band between the first frequency band and the second frequency band, the third frequency band also includes the first frequency band and the second frequency band.
  • the frequency band spaced between the second frequency bands is a scheme for estimating the time of arrival of the reference signal.
  • the estimation accuracy of the time of arrival of the reference signal is equivalent to it, but this application can make the radio frequency channel of the wireless communication device only have the ability to support sending the first frequency band
  • the ability to send signals in the second frequency band is sufficient, and it is not required to support the ability to send signals in the third frequency band. It can be seen that this application can improve the positioning accuracy of terminal devices with weaker sending capabilities.
  • the present application can reduce the amount of signals sent by the wireless communication device, thereby The power consumption of the wireless communication device can be reduced.
  • an interval frequency band may be provided between the first frequency band and the second frequency band. Since there is a positive correlation between the estimation accuracy of the reference signal arrival time between the first wireless communication device and the second wireless communication device and the interval frequency band between the first frequency band and the second frequency band, the first frequency band and the second frequency band The wider the interval between the frequency bands, the higher the estimation accuracy of the time of arrival of the reference signal, and thus the more accurate the positioning of the first wireless communication device.
  • overlapping frequency domain resources may also exist between the first frequency band and the second frequency band, or the first frequency band and the second frequency band may be a continuous frequency band.
  • the following takes the first wireless communication device as a terminal device and the second wireless communication device as a network device as an example, and uses FIG. 5 to exemplarily show the first wireless communication in S401 in FIG. 4
  • the terminal device accesses the network device.
  • a terminal device When a terminal device accesses a network device for the first time, it can go to the authentication server to perform authentication and open an account, so as to complete the two-way authentication between the terminal device and the network device, as well as complete encryption and integrity protection. Both the terminal device and the network device can generate non- The access layer (non-access stratum, NAS) encryption key and integrity protection key, the signal used for positioning later (the positioning signal may include the above-mentioned first reference signal and second reference signal, for example) can be encrypted by NAS transmission.
  • NAS non-access stratum
  • the network device sends configuration information to the terminal device, the configuration information includes information on the time domain resources allocated by the network device for the terminal device to send signals in the idle state (Idle)/inactive state (Inactive), and sends an RRC connection to the terminal device release message.
  • the time-domain resource information in the configuration information may also be the time-domain resource information allocated by the network device for the terminal device to send the positioning signal in the idle state (Idle)/inactive state (Inactive), and the positioning signal may include the above-mentioned first reference signal and a second reference signal.
  • the time domain resource may define a wake-up cycle after the terminal device goes to sleep, that is, how often it wakes up, for example, wakes up every 6 seconds.
  • the network device can release the RRC connection of the terminal device through the RRC connection release message.
  • the terminal device enters deep sleep, and the terminal device enters a low power consumption state in deep sleep, so as to save power of the terminal device.
  • the terminal device wakes up when the wake-up time corresponding to a wake-up period arrives according to the time domain resources configured by the network device.
  • the terminal device receives a synchronization signal block (Synchronization Signal Block, SSB) from the network device.
  • SSB Synchronization Signal Block
  • the wake-up terminal device can perform time synchronization with the network device through S505, so as to eliminate the clock drift of the terminal device during sleep.
  • the terminal device sends the first reference signal, and the terminal device sends the second reference signal.
  • the terminal device after performing time synchronization may send the first reference signal and the second reference signal through S506, and may execute the above S503 after sending, so as to re-enter sleep to save power consumption.
  • FIG. 6 exemplarily shows a specific example of a solution for a first wireless communication device to send a first reference signal and a second reference signal according to an embodiment of the present application, as shown in FIG. 6 :
  • the first wireless communication device generates an SRS signal with a length corresponding to a bandwidth of 100 MHz. It may also be understood that the first wireless communication device generates an SRS signal with a bandwidth of 100 MHz in a time domain direction.
  • the first wireless communication device divides the SRS signal into 5 segments, wherein each segment of the SRS signal corresponds to a bandwidth of 20 MHz.
  • the first wireless communication device selects the first reference signal and the second reference signal from the 5-segment SRS signals. For example, the first wireless communication device may select the first segment of the SRS signal in the 5 segments as the first reference signal, and select The last segment of the SRS signal in the 5 segments is used as the second reference signal.
  • the first wireless communication device sends the first reference signal centering on the carrier frequency point f1, and the first reference signal successively reaches three or more adjacent second wireless communication devices after being transmitted through the air interface.
  • One beam of the first wireless communication device (such as the Sub6G frequency band) can cover multiple nearby second wireless communication devices, so once the first wireless communication device transmits, three or more adjacent second wireless communication devices can receive SRS signals.
  • the first wireless communication device After sending the first reference signal, the first wireless communication device frequency hops to (f1+80MHz) at the second moment, and sends the second reference signal centered on the frequency-hopped carrier, and after the second reference signal is transmitted through the air interface, It also successively arrives at three or more adjacent second wireless communication devices.
  • One or more time-domain symbol periods may be separated between the first moment and the second moment.
  • the interval between the first reference signal and the second reference signal can be as short as possible, for example, the first moment when the first reference signal is sent and the second time when the second reference signal is sent There may be one time-domain symbol period between the two instants.
  • the first wireless communication device can generate a higher bandwidth SRS signal once, such as (2+N)*20MHz (such as 400MHz), and divide it into multiple times (such as twice) Sending, the frequency domain interval between two frequency hopping in multiple frequency hopping can be n*20MHz (n can be flexibly configured according to the actual positioning accuracy requirements), and the frequency domain can be non-overlapping, so that small
  • the reference signal with a wide bandwidth is used for the purpose of constructing a (2+N)*20MHz large bandwidth reference signal.
  • the second wireless communication device calculates the The higher the accuracy of the estimated TOA, the more accurate the determined transmission delay, and the more accurate the positioning of the first wireless communication device.
  • phase synchronization between the first reference signal and the second reference signal refers to the phase synchronization between the first reference signal and the second reference signal (the phase difference is 0) or the phase approximate synchronization (the phase difference is less than the preset phase difference threshold), the following content will illustrate the specific form of the phase difference between the first reference signal and the second reference signal.
  • FIG. 7 exemplarily shows a schematic structural diagram of the first wireless communication device provided by the embodiment of the present application.
  • the solution in FIG. 7 can realize phase synchronization between the first reference signal and the second reference signal.
  • the first wireless communication device may include other radio frequency channels besides the first radio frequency channel, such as a radio frequency receiving channel, or other radio frequency transmitting channels, etc., which are not limited in this embodiment of the present application.
  • the first radio frequency channel is connected to the antenna 70, and is used to process the baseband signal from the baseband subsystem 71 (such as up-conversion, amplification and filtering) to obtain a radio frequency signal, and finally radiate the radio frequency signal into space through the antenna .
  • the baseband subsystem 71 such as up-conversion, amplification and filtering
  • the first radio frequency channel may include a DAC72, a low pass filter (low pass filter, LPF) 73, a mixer 74 (the mixer 74 may also be called an uplink mixer), a variable gain amplifier 77. PA78. Band pass filter (BPF)79.
  • LPF low pass filter
  • BPF Band pass filter
  • the first radio frequency channel shown in FIG. 7 may also include a phase locked loop (phase locked loop, PLL) 75 and a phase locked loop 76.
  • the phase-locked loop 75 may be referred to as a first phase-locked loop.
  • the phase locked loop 75 can be selectively connected with the mixer 74 .
  • the phase-locked loop 75 can be used to generate the first local oscillator signal, and the center frequency of the first local oscillator signal is the same as the center frequency of the first reference signal.
  • Phase locked loop 76 may be referred to as a second phase locked loop.
  • a phase locked loop 76 may be selectively connected to the mixer 74 .
  • the phase-locked loop 76 can be used to generate a second local oscillator signal, and the center frequency of the second local oscillator signal is the same as the center frequency of the second reference signal.
  • the first wireless communication device can connect the phase-locked loop 75 to the mixer 74 when it is necessary to send the first reference signal, and the phase-locked loop 76 and the mixer The mixer 74 is disconnected, so that the mixer 74 can receive the first local oscillator signal from the phase-locked loop 75, and then the first wireless communication device can send the first reference signal in the first frequency band according to the first local oscillator signal.
  • the first wireless communication device may connect the phase-locked loop 76 to the mixer 74 when it is necessary to send the second reference signal, and the phase-locked loop 75 and the mixer The mixer 74 is disconnected, so that the mixer 74 can receive the second local oscillator signal from the phase-locked loop 76, and then the first wireless communication device can send the second reference signal in the second frequency band according to the second local oscillator signal.
  • the first radio frequency channel may have the ability to work in multiple frequency bands.
  • one or more working parameters of the radio frequency sending channel need to be adjusted so as to change the working frequency band of the first radio frequency channel.
  • the parameters of at least one of the DAC72, the low-pass filter 73, the band-pass filter 79, etc. can be adjusted. , so as to achieve the purpose of adjusting the working frequency band of the first radio frequency channel.
  • the devices included in the first radio frequency channel shown in FIG. More devices can be added to the first radio frequency receiving channel, or one or more devices shown in the figure can be deleted.
  • the phase-locked loop 76 in Figure 7 can use the phase-locked loop of the first radio frequency channel
  • the phase-locked loop 75 can use the phase-locked loop of other radio frequency channels, such as the radio frequency receiving channel can be used
  • a phase-locked loop, the phase-locked loop can be time-division multiplexed, used for the data receiving process in the receiving data time slot, and used for the data sending process in the sending data time slot.
  • phase-locked loop 75 and the phase-locked loop 76 in FIG. 7 share the same reference clock signal.
  • this synchronization signal may be referred to as a first synchronization signal.
  • the phase-locked loop 75 and the phase-locked loop 76 can both adjust the phase difference between the signal output by them and the reference clock signal based on the first synchronization signal, so that the phases of the signals output by the phase-locked loop 75 and the phase-locked loop 76 can be synchronized respectively, It can also be understood that the phase-locked loop 75 and the phase-locked loop 76 can determine the same valid edge (which can be a rising edge or a falling edge) of the reference clock signal as the first valid edge based on the first synchronization signal, and the phase-locked loop 75 and the The phase-locked loops 76 all adjust the phase difference between the respective output signals and the reference signal based on the first valid edge.
  • phase-locked loop 75 can be used to adjust the phase difference between the first local oscillator signal and the reference clock signal to a preset first phase difference, and the preset first phase difference can be 0 or a preset value.
  • the phase-locked loop 76 can be used to adjust the phase difference between the second local oscillator signal and the reference clock signal to a preset first phase difference.
  • Figure 8a exemplarily shows a schematic structural diagram of a phase-locked loop 75 and a phase-locked loop 76 in Figure 7 provided by the embodiment of the present application.
  • the phase-locked loop 75 and the phase-locked loop 76 share the same
  • the reference clock signal may also share the same first synchronization module.
  • the phase-locked loop 75 is used to generate a first local oscillator signal whose center frequency is the first frequency.
  • the phase-locked loop 76 is used to generate a second local oscillator signal whose center frequency is the second frequency.
  • the first center frequency point is the center frequency point of the first frequency band
  • the second center frequency point is the center frequency point of the second frequency band.
  • the phase locked loop 75 includes a phase detector 751 , a charge pump 752 , a low pass filter 753 , an oscillator 754 and a frequency divider 756 connected in sequence.
  • a frequency divider 755 is also included.
  • the phase detector 751 is used to receive the reference clock signal and the signal output by the frequency divider 755, and detect the phase relationship between the two to generate an output signal, which indicates the phase of the reference clock signal and the signal output by the frequency divider 755 Difference.
  • the charge pump 752 is used to convert the phase difference output by the phase detector 751 into a level, which is processed by a low-pass filter and then input to the oscillator 754 to control the frequency of the oscillation signal output by the oscillator 754 .
  • the low-pass filter 753 may also be called a digital loop filter (Digital Loop Filter, DLF), and is used for filtering the received signal, so as to output a frequency control signal for controlling the oscillator 754 .
  • DLF Digital Loop Filter
  • the oscillator 754 may be a voltage-controlled oscillator (Voltage-controlled oscillator, VCO), configured to receive a frequency control signal from the low-pass filter 753, and output an oscillating signal under the control of the signal.
  • VCO Voltage-controlled oscillator
  • the frequency divider 756 is configured to receive the oscillating signal from the oscillator 754 and perform frequency division on the oscillating signal, so as to obtain the first local oscillator signal.
  • the frequency divider 756 can be selectively connected to the frequency mixer 74 in FIG. 7 , and when the frequency divider 756 is connected to the frequency mixer 74 , the frequency divider 74 can receive the first local oscillator signal from the frequency divider 756 . When the frequency divider 756 and the mixer 74 are disconnected, the mixer 74 cannot receive the first local oscillator signal from the frequency divider 756 .
  • the frequency divider 756 may also be referred to as a first frequency divider.
  • the frequency divider 755 is configured to receive the first local oscillator signal output by the frequency divider 756 , perform frequency division processing on the first local oscillator signal, and input the frequency divided signal to the input terminal of the phase detector 751 . Since the frequency divider 755 is located on the feedback loop, the frequency divider 755 may also be referred to as a feedback frequency divider. The frequency divider 755 may also be referred to as a first feedback frequency divider.
  • the phase control module 757 is configured to adjust the frequency division ratio of the frequency divider 755 .
  • the phase control module 757 of this application can achieve the purpose of adjusting the phase difference between the first local oscillator signal and the reference clock signal by adjusting the frequency division ratio of the frequency divider 755 .
  • the input terminal of the phase control module 757 is used to receive the signal from the first synchronization module in addition to receiving the reference clock signal and the output signal of the phase detector 751 , combine the three signals to adjust the frequency division ratio of the frequency divider 755 .
  • the frequency divider 756 and the frequency divider 766 are both located inside the loop of the phase-locked loop, so it is not necessary to require that the frequency division ratio of the two be the same or different; when the frequency division ratio of the two is the same
  • the phase adjustment time of the phase-locked loop 75 and the phase-locked loop 76 can be shortened.
  • the phase locked loop 76 includes a phase detector 761 , a charge pump 762 , a low pass filter 763 , an oscillator 764 and a frequency divider 766 connected in sequence.
  • a frequency divider 765 is also included.
  • the phase detector 761 is used to receive the reference clock signal and the signal output by the frequency divider 765, and detect the phase relationship between the two to generate an output signal, which indicates the phase of the reference clock signal and the signal output by the frequency divider 765 Difference.
  • the charge pump 762 is used to convert the phase difference output by the phase detector 761 into a level, which is processed by a low-pass filter and then input to the oscillator 764 to control the frequency of the oscillating signal output by the oscillator 764 .
  • the low-pass filter 763 may also be called a digital loop filter (Digital Loop Filter, DLF), and is used to filter the received signal so as to output a frequency control signal for controlling the oscillator 764.
  • DLF Digital Loop Filter
  • the oscillator 764 may be a voltage-controlled oscillator (Voltage-controlled oscillator, VCO), used to receive the frequency control signal from the low-pass filter 763, and output an oscillating signal under the control of the signal.
  • VCO Voltage-controlled oscillator
  • the frequency divider 766 is configured to receive the oscillating signal from the oscillator 764 and perform frequency division on the oscillating signal to obtain a second local oscillator signal.
  • the frequency divider 766 can be selectively connected to the frequency mixer 74 in FIG. 7 , and when the frequency divider 766 is connected to the frequency mixer 74 , the frequency mixer 74 can receive the second local oscillator signal from the frequency divider 766 . When the frequency divider 766 is disconnected from the frequency mixer 74 , the frequency mixer 74 cannot receive the second local oscillator signal from the frequency divider 766 .
  • the frequency divider 756 and the frequency divider 766 can be connected to the mixer 74 in FIG. 7 through a switch.
  • the frequency divider 766 may also be referred to as a second frequency divider.
  • the frequency divider 765 is configured to receive the second local oscillator signal output by the frequency divider 766 , perform frequency division processing on the second local oscillator signal, and input the frequency divided signal to the input terminal of the phase detector 761 . Since the frequency divider 765 is located on the feedback loop, the frequency divider 765 may also be referred to as a feedback frequency divider. The frequency divider 765 may also be referred to as a second feedback frequency divider.
  • the phase control module 767 is configured to adjust the frequency division ratio of the frequency divider 765 .
  • the phase control module 767 of this application can achieve the purpose of adjusting the phase difference between the second local oscillator signal and the reference clock signal by adjusting the frequency division ratio of the frequency divider 765 .
  • the input terminal of the phase control module 767 is used to receive the signal from the first synchronization module in addition to the reference clock signal and the output signal of the phase detector 761 , to adjust the frequency division ratio of the frequency divider 765 by combining the three signals.
  • the first synchronization module may be connected to the phase control module 757 and the phase control module 767 respectively.
  • the first synchronization module may be configured to send a first synchronization signal to the first phase control module and the second phase control module respectively.
  • the phase-locked loop 75 when the phase-locked loop 75 is locked, it will output a signal for indicating that the phase-locked loop 75 is locked to the first synchronization module.
  • the phase-locked loop 76 after the phase-locked loop 76 is locked, it will output a signal to the first synchronization module.
  • the first synchronization module may send a first synchronization signal after the first phase-locked loop and the second phase-locked loop are locked.
  • the locking of the PLL refers to the frequency synchronization between the local oscillator signal output by the PLL and the input reference clock signal, and a relatively fixed phase difference can be maintained between the two.
  • the locking of the phase-locked loop 75 refers to maintaining a relatively fixed phase difference between the first local oscillator signal output by the phase-locked loop 75 and the reference clock signal (for example, it can be expressed as ).
  • the locking of the phase-locked loop 76 refers to maintaining a fixed phase difference between the second local oscillator signal output by the phase-locked loop 76 and the reference clock signal (for example, it can be expressed as ). and They may be the same or different, which is not limited in this embodiment of the application.
  • phase between the local oscillator signal output by the two phase-locked loops and the reference clock signal is adjusted again, so that the first local oscillator signal and the reference clock signal The phase of the second local oscillator signal is synchronized.
  • FIG. 8b exemplarily shows a schematic diagram of the reference clock signal, the locking signal and the first synchronization signal in FIG. 8a.
  • the first synchronization module receives the reference clock signal.
  • the synchronization module receives the lock signal of the phase-locked loop 75 and the lock signal of the phase-locked loop 76, it can select the falling edge of the next reference clock signal as the rising edge of the first synchronization signal.
  • the first synchronization module after the first synchronization module receives the lock signal of the phase-locked loop 75 and the lock signal of the phase-locked loop 76, it can delay several cycles of the reference clock signal and then select a falling edge of the reference clock signal as the first The rising edge of a synchronous signal, since the phase difference between the signal output by the phase-locked loop and the reference clock signal tends to be stable after the phase-locked loop is locked, if a few periods of the reference clock signal are delayed, the signal output by the phase-locked loop The phase difference with the reference clock signal is further stabilized.
  • the phase control module 757 and the phase control module 767 take the rising edge of the received signal output by the first synchronization module as a reference, Both select the rising edge of the first (or preset second, third, etc.) reference clock signal after the rising edge as the first valid edge.
  • the phase-locked loop 75 starts to adjust the phase of the first local oscillator signal and the reference clock signal based on the selected first active edge until the phase between the first local oscillator signal and the reference clock signal is adjusted to a preset value. the first phase difference.
  • phase control module 757 collects the rising edge of the signal output by the first synchronization module, according to the phase difference detected by the phase detector 751, by controlling the frequency division ratio of the frequency divider 755 within several cycles of the reference clock signal , so as to change the output frequency of the oscillator 754 within several cycles of the reference clock signal, and then achieve the purpose of changing the output integration phase and adjusting the phase difference, and then achieve the purpose of phase synchronization between the first local oscillator signal and the second local oscillator signal. This process can be repeated every time the PLL is powered on.
  • the phase-locked loop 76 starts to adjust the phase of the second local oscillator signal and the reference clock signal based on the selected first active edge until the phase between the second local oscillator signal and the reference clock signal is adjusted to the preset value.
  • the preset first phase difference can be 0 or a preset value.
  • the process of the phase control module 767 adjusting the frequency division ratio of the frequency divider 765 in the phase locked loop 76 according to the signal output by the first synchronization module can refer to the above content of the phase control module 757 and will not be repeated here.
  • phase-locked loop 75 and the phase-locked loop 76 are locked, they all select the first active edge of the reference clock signal as the reference for phase adjustment according to the first synchronous signal;
  • the phase difference between the local oscillator signal and the reference clock signal is the preset first phase difference, and the phase difference between the second local oscillator signal and the reference clock signal is also the preset first phase difference, so the first local oscillator signal and the second The phases of the two local oscillator signals are synchronized.
  • FIG 8c exemplarily shows the frequency of the signal output by the phase-locked loop 75 in Figure 8a, the phase difference detected by the phase detector 751, and the schematic diagram of the synchronous signal output by the first synchronization module, as shown in Figure 8c, the phase-locked loop
  • the frequency of the signal output by 75 increases gradually, tending to the frequency of the first center frequency point of the first local oscillator signal.
  • the phase difference between the first local oscillator signal output by the PLL and the reference clock signal tends to be stable, when the phase difference between the first local oscillator signal and the reference clock signal tends to be stable, it can be called locked
  • the phase loop 75 is in a locked state, or called the phase locked loop 75 is locked.
  • the phase-locked loop 75 starts to adjust the first local oscillator signal and The phase difference of the reference clock signal.
  • the frequency divider 756 is located inside the phase-locked loop 75 , that is, the input terminal of the frequency divider 755 is connected to the output terminal of the frequency divider 756 .
  • the frequency divider 766 is located inside the loop of the phase-locked loop 76 , that is, the input end of the frequency divider 765 is connected to the output end of the frequency divider 766 . Therefore, when the phases of the phase-locked loops are adjusted by the phase control module 757 and the phase control module 767, the random phase jitter between the frequency divider 756 and the frequency divider 766 can be eliminated.
  • the process of switching the first radio frequency channel from receiving the first local vibration signal to receiving the second local vibration signal can be shortened, for example, the process can be shortened to one
  • the symbol period can further shorten the interval between the sending moment of the first reference signal and the sending moment of the second reference signal, so that the accuracy of positioning can be further improved, and because the time of sending the first reference signal and sending the second reference signal
  • the time interval is shortened, so the working time of the wireless communication device can be reduced, and the sleeping time can be increased, thereby reducing power consumption.
  • N represents the frequency division factor (also can be referred to as frequency division ratio) of the frequency divider (such as frequency divider 755 and frequency divider 765) of the loop of phase-locked loop ;
  • int represents the integer part of the frequency division coefficient of the frequency divider
  • T refclk represents a cycle duration
  • the MOD can determine the minimum phase difference between the signal output by the phase locked loop and the reference clock signal.
  • the reference clock signal is 38.4MHz
  • the signal output by the frequency divider 755 is related to the denominator MOD of the decimal.
  • the phase of the signal output by the frequency divider 755 can cover one cycle, and the phase The step is (duration of one cycle/MOD).
  • the phase deviation between two signals can be marked by an angle
  • the phase deviation of two clock signals can also be represented by the interval between rising edges of two signals (for example, two clock signals). Therefore, in the above formula (2), it can also be said that the phase of the signal output by the frequency divider 755 can cover 360°, and the phase step is (360°/MOD).
  • the allowed minimum phase difference between the signal output by the PLL 75 and the reference clock signal is 0.005 ps.
  • MOD takes a value greater than 2604, by controlling the phase difference between the first local oscillator signal output by the phase-locked loop 75 and the reference clock signal, and by controlling the second local oscillator signal and the reference clock signal through the phase-locked loop 76
  • the phase difference between the first local oscillator signal and the second local oscillator signal can be controlled within 10 picoseconds (ps). In order to achieve a smaller phase deviation, it can be realized by increasing the MOD value through the configuration register.
  • the bandwidth of N41, N77, N78, and N79 is greater than 100MHz, which can be suitable for high-precision positioning (high bandwidth).
  • Table 1 exemplifies several possible simulation results schematic diagrams. The following is an example of the first row of Table 1.
  • the bandwidth of the positioning signal (the bandwidth of the positioning signal includes the total bandwidth of the first frequency band and the second frequency band, and the first frequency band and the total bandwidth of the second frequency band.
  • the bandwidth of the frequency band spaced between the second frequency bands) is 100M
  • the maximum phase difference (also called phase jitter) allowed between the first reference signal and the second reference signal is 277.7ps.
  • FIG. 9a exemplarily shows a schematic structural diagram of the phase-locked loop 75 and the phase-locked loop 76 in FIG. 7 provided by the embodiment of the present application.
  • the phases of the first reference signal and the second reference signal are approximately synchronous, and the phase difference between the first reference signal and the second reference signal is equal to that between the signal output by the oscillator 754 and the signal output by the oscillator 764 phase difference.
  • the phase difference between the first reference signal and the second reference signal can also be understood as the phase difference between the first local oscillator signal and the second local oscillator signal.
  • FIG. 9a and FIG. 8a is that the frequency divider 756 in FIG.
  • Fig. 9a removes the first synchronization module.
  • Added a second synchronization module For other components in FIG. 9a, reference may be made to the related description in FIG. 8a, which will not be repeated here. It should be added that a second synchronization module can also be added in Figure 8a, and the function and function of the second synchronization module are the same as those of the second synchronization module in Figure 9a below.
  • a frequency divider with a frequency division ratio of N can be understood as a counter in essence.
  • the counter accumulates the rising edges (number of cycles) of the input clock signal. When the counter reaches N-1, it outputs the first clock signal after frequency division. rising edge.
  • the first clock edge of a frequency divider to start counting is uncertain. It may start counting with the first rising edge of the received clock signal, or it may start with the second rising edge of the received clock signal. count. Based on this, the frequency divider 756 may start counting on the first rising edge of the received signal, and the frequency divider 766 may start counting on the second or third rising edge of the received signal. This uncertainty results in a random phase error between the first local oscillator signal and the second local oscillator signal.
  • the frequency divider 7546 and the frequency divider 766 perform frequency division based on the same second synchronization signal.
  • the frequency division ratio of the frequency divider 756 and the frequency divider 766 can be the same, so that the phase difference between the first local oscillator signal and the second local oscillator signal can be equal to the phase difference between the signal output by the oscillator 754 and the signal output by the oscillator 764 Phase difference.
  • phase-locked loop 76 When the signal output by the oscillator 764 and the reference clock signal When a relatively fixed phase difference is maintained between the signals, it can be understood that the phase-locked loop 76 is in a locked state. When both the phase-locked loop 75 and the phase-locked loop 76 are in the locked state, there will be a phase difference between the signals output by the oscillator 754 and the oscillator 764, and this phase difference may be called an initial phase difference.
  • phase difference between the oscillator 754 and the oscillator 764 is less than a minimum clock cycle in the signals output by the oscillator 754 and the oscillator 764, therefore, when the phase difference between the first local oscillator signal and the second local oscillator signal is
  • the phase difference between the oscillator 754 and the oscillator 764 can meet the phase change requirements of bandwidths such as 100M/200M/300M/400M.
  • FIG. 9b exemplarily shows a reference clock signal, a locking signal and a second synchronization signal, a signal output by the oscillator 754, a signal output by the oscillator 764, and a frequency divider 756 in FIG. 9a.
  • the second synchronization module after the second synchronization module receives the lock signal of the phase-locked loop 75 and the lock signal of the phase-locked loop 76, it can delay several cycles of the reference clock signal and select a falling edge of the reference clock signal as the second synchronization module.
  • the rising edge of the synchronous signal because after the phase-locked loop is locked, the phase difference between the signal output by the phase-locked loop and the reference clock signal tends to be stable, if a few cycles of the reference clock signal are delayed, the signal output by the phase-locked loop The phase difference between the reference clock signals is further stabilized.
  • the frequency divider 756 uses the received rising edge of the signal output by the second synchronization module as a reference to select The first rising edge of the signal output by the oscillator 754 after the rising edges of the two synchronization signals is used as the initial rising edge for frequency division.
  • the frequency divider 766 is based on the rising edge of the received signal output by the second synchronization module, and selects the first rising edge in the signal output by the oscillator 764 after receiving the rising edge of the second synchronization signal As the starting rising edge for frequency division.
  • phase difference between the initial rising edges selected by the frequency divider 756 and the frequency divider 766 is the phase difference between the oscillator 754 and the oscillator 764 (the initial phase difference shown in FIG. 9b ) .
  • both the frequency divider 756 and the frequency divider 766 use the first rising edge in the received signal as the initial rising edge after receiving the second synchronous signal, and the frequency divider 756 and the frequency divider can also be After receiving the second synchronization signal, the device 766 uses the second (or third, fourth, etc.) rising edge of the received signal as the initial rising edge, as long as the frequency divider 756 and the frequency divider It is sufficient that no new phase deviation between the first local oscillator signal and the second local oscillator signal is introduced between the frequency converter 766 because of selecting the position of the initial rising edge.
  • Table 2 and Table 3 show the simulation results of the scheme in FIG. 9a below.
  • Table 2 exemplarily shows the simulation results of the maximum phase difference between the first local oscillator signal and the second local oscillator signal in FIG. -2690MHz, the total bandwidth is 194MHz, taking the phase-locked loop 75 as an example, assuming that the frequency divider 756 is a frequency divider with a frequency division of 4 (currently a common frequency division ratio in the Sub6G frequency band), and the center frequency of the oscillator 754 is the first 4 times the center frequency of the local oscillator signal, the center frequency of the first local oscillator signal is 2593MHz (the center frequency of 2496MHz-2690MHz), the center frequency of the oscillator 754 is 10.372GHz (the center of the first local oscillator signal 4 times the frequency point) the maximum phase difference between the first local oscillator signal and the second local oscillator signal is 96.4 ps for one cycle of the clock signal output by the oscillator 754 .
  • Table 2 is a schematic diagram of the simulation results of the maximum phase difference between the first local oscillator signal and the second local oscillator signal in Figure 9a
  • Table 3 exemplifies several possible simulation results schematic diagrams.
  • the positioning signal bandwidth (the positioning signal bandwidth includes the total bandwidth of the first frequency band and the second frequency band, and the first frequency band and the total bandwidth of the second frequency band.
  • the bandwidth of the frequency band spaced between the second frequency bands) is 100M
  • the maximum allowed phase difference between the first reference signal and the second reference signal is 277.7ps
  • N41, N77, N78, and N79 all meet the requirements.
  • the frequency hopping bandwidth can be reduced under the N78 frequency band, which can provide more guarantees to meet the phase requirements.
  • FIG. 10 exemplarily shows a schematic structural diagram of a phase-locked loop 75 and a phase-locked loop 76 in FIG. 7 provided by an embodiment of the present application.
  • the scheme provided in FIG. 10 can synchronize the phases between the first reference signal and the second reference signal. It should be noted that the difference between FIG. 10 and FIG. 9a is that a first synchronization module is added, and the first synchronization module is connected to the phase control module 757 and the phase control module 767 .
  • the function of the first synchronization module in FIG. 10 is the same as that of the first synchronization module in FIG. 8a , and will not be repeated here.
  • the difference is that the phase control module 757 changes the phase difference between the signal output by the oscillator 754 and the reference clock signal by adjusting the frequency division ratio of the frequency divider 755, while the phase control module 767 changes the phase difference between the signal output by the oscillator 754 and the reference clock signal by adjusting the frequency division ratio of the frequency divider 765.
  • What the frequency division ratio changes is the phase difference between the signal output by the oscillator 764 and the reference clock signal.
  • phase control module 757 and the phase control module 767 receive the first synchronous signal from the first synchronous module, they select the first (or preset 2nd, 3rd, etc.)
  • the rising edge of the reference clock signal is used as the initial phase.
  • the phase-locked loop 75 starts to adjust the phase of the signal output by the oscillator 754 and the reference clock signal based on the selected initial phase until the phase between the signal output by the oscillator 754 and the reference clock signal is adjusted to the preset the first phase difference.
  • phase-locked loop 76 starts to adjust the phase of the signal output by the oscillator 764 and the reference clock signal based on the selected initial phase, until the phase between the signal output by the oscillator 764 and the reference clock signal is adjusted to a predetermined value. Set the first phase difference.
  • both the phase control module 757 and the phase control module 767 select the same position of the reference clock signal as the initial phase according to the first synchronous signal, and because after phase adjustment, the phase difference between the signal output by the oscillator 754 and the reference clock signal is predetermined
  • the first phase difference is set, and the phase difference between the signal output by the oscillator 764 and the reference clock signal is also the preset first phase difference, so the signal output by the oscillator 754 and the signal output by the oscillator 764 are in phase synchronization.
  • the synchronous signal is frequency-divided, so that the phase difference between the first local oscillator signal and the second local oscillator signal is the phase difference between the oscillator 754 and the oscillator 764, and the signal output by the oscillator 754 and the signal output by the oscillator 764 On the basis of phase synchronization, the first local oscillator signal and the second local oscillator signal are phase synchronized.
  • Fig. 11 exemplarily shows a schematic structural diagram of another first wireless communication device provided by the embodiment of the present application.
  • the scheme provided in FIG. 11 can synchronize the phases between the first reference signal and the second reference signal.
  • the difference between FIG. 11 and FIG. 7 is that only one PLL 81 is included in FIG. 11 .
  • the phase-locked loop 81 can be called the third phase-locked loop, and the phase-locked loop 81 is coupled with the mixer 74, and is used for generating the third local oscillator signal in the process of sending the first reference signal, and in the process of sending the second reference signal Generate a fourth local oscillator signal.
  • the center frequency of the third local oscillator signal is the same as that of the first reference signal; the center frequency of the fourth local oscillator signal is the same as that of the second reference signal. That is to say, the phase-locked loop 81 first outputs the third local oscillator signal, then performs frequency point switching, and outputs the fourth local oscillator signal. It can also be understood that the phase-locked loop 81 locks first, and then outputs the third local oscillator signal, and then Lost lock, lock again, and output the fourth local oscillator signal after relock. In order to synchronize the phases of the first reference signal and the second reference signal, in this embodiment of the present application, the phases of the third local oscillator signal and the fourth local oscillator signal may be synchronized.
  • Fig. 12a exemplarily shows a structural diagram of a phase-locked loop 81 in Fig. 11.
  • the phase-locked loop 81 includes a phase detector 811, a charge pump 812, a low-pass filter 813, an oscillator device 814 and frequency divider 816.
  • a frequency divider 815 is also included.
  • Frequency divider 816 may be referred to as a third frequency divider, and frequency divider 815 may be referred to as a third feedback frequency divider.
  • the schematic structural diagram of the first wireless communication device shown in FIG. 12a further includes a third synchronization signal module.
  • the output end of the third synchronization signal module is connected to the third phase control module for the third synchronization signal.
  • the third synchronization signal may be output periodically.
  • the third phase control module determines the second valid edge of the reference signal according to the received third synchronization signal, And taking the second valid edge as a reference, the phase difference between the third local oscillator signal output by the third phase-locked loop and the reference clock signal is adjusted to a preset second phase difference.
  • the third phase control module determines the third valid edge according to the received third synchronization signal, and uses the first The three effective edges are used as a reference, and the phase difference between the fourth local oscillator signal output by the third phase-locked loop and the reference clock signal is adjusted to a preset second phase difference.
  • Fig. 12b exemplarily shows a schematic diagram of the reference clock signal in Fig. 12a, the locking signal of the phase-locked loop 81, the signal output by the third synchronization module and the signal output by the phase-lock loop 81, as shown in Fig. 12b, the third synchronization module
  • the third synchronization signal is output periodically.
  • the frequency of the third synchronization signal is a common divisor of the frequency of the center frequency point of the third local oscillation signal and the frequency of the center frequency point of the fourth local oscillation signal.
  • the frequency of the third synchronization signal may be a common divisor of the frequency of the reference clock signal, the frequency of the center frequency of the third local oscillator signal, and the frequency of the center frequency of the fourth local oscillator signal.
  • the rising edge of the first reference clock signal received after the phase control module 817 receives the first third synchronization signal is determined as the second valid edge, and then the second active edge Using the effective edge as a reference, the phase difference between the third local oscillator signal output by the phase-locked loop 81 and the reference clock signal is adjusted to a preset second phase difference.
  • the second phase difference can be 0 or a preset value. When the second phase difference is 0, it can be said that the phase-locked loop 81 adjusts the third local oscillator signal and the reference clock signal output by the phase-locked loop 81 based on the second active edge. The phase difference between them is adjusted to 0 to achieve phase synchronization between the third local oscillator signal and the reference clock signal.
  • the phase-locked loop After the first wireless communication device sends the first reference signal through the first radio frequency channel, the phase-locked loop is in an out-of-lock state and locks for the second time. After the phase-locked loop 81 locks for the second time, the phase-locked loop 817 receives The rising edge of the first reference clock signal received after the first third synchronizing signal is determined as the third valid edge, and then the fourth local oscillator signal output by the phase-locked loop 81 is adjusted to match the third valid edge based on the third valid edge. The phase difference between the reference clock signals is adjusted to a preset second phase difference. The second phase difference may be 0 or a preset value, and it is illustrated in FIG. 12 b that the second phase difference is 0.
  • the phase-locked loop 81 adjusts the phase difference between the fourth local oscillator signal output by the phase-locked loop 81 and the reference clock signal, and adjusts it to 0 based on the third active edge.
  • the phase control module 817 adjusts the phase difference between the signal output by the phase-locked loop 81 and the reference clock signal, refer to the relevant description of the phase control module 757 in FIG. 8 a , which will not be repeated here.
  • the duration of the phase-locked loop 81 locking for the first time may include a period of the reference clock signal, or may include multiple periods of the third synchronization signal.
  • One cycle of the third synchronization signal may include multiple cycles of the reference clock signal.
  • the third synchronizing module periodically provides the third synchronizing signal to the phase control module 817, although the third local oscillation signal and the fourth local oscillation signal are the signals output by the phase-locked loop 81 after being locked twice before and after, but in the two After locking, the PLL 81 performs phase synchronization between the third local oscillator signal and the reference clock signal, and phase synchronization between the fourth local oscillator signal and the reference clock signal according to the third synchronization signal.
  • the frequency of the third synchronization signal is the common divisor of the frequency of the center frequency point of the third local oscillation signal and the frequency of the center frequency point of the fourth local oscillation signal, and because the foregoing content has explained that two signals can be synchronized to the two A signal at the frequency of the greatest common divisor of the frequencies of the two signals, based on this, the third local oscillator signal and the fourth local oscillator signal are phase-synchronized.
  • the phase difference between the phase-adjusted third local oscillator signal and the third synchronization signal is the same as the phase difference between the phase-adjusted fourth local oscillator signal and the third synchronization signal The difference is equal.
  • the third synchronization signal is phase-synchronized with the reference clock signal.
  • the frequency of the third synchronization signal is the common divisor of the frequency of the center frequency point of the third local oscillation signal and the frequency of the center frequency point of the fourth local oscillation signal, and because the foregoing content has explained that two signals can be synchronized to the two A signal at the frequency of the greatest common divisor of the frequencies of the two signals.
  • the phase-adjusted third local oscillator signal can be phase-synchronized with the third synchronization signal.
  • the phase-adjusted fourth local oscillator signal is in phase synchronization with the third synchronization signal.
  • Fig. 13 exemplarily shows another structural diagram of the phase-locked loop 81 in Fig. 11, the difference compared with Fig. 12a is that in Fig. Four synchronization modules, the fourth synchronization signal module transmits the received third synchronization signal from the third synchronization signal module to the third phase control module after detecting that the third phase-locked loop is locked. After the fourth synchronization signal module detects that the third phase-locked loop is out of lock, it stops transmitting the received third synchronization signal from the third synchronization signal module to the third phase control module. In this way, power consumption can be saved.
  • the frequency divider 816 is located inside the loop of the PLL 81 , that is, the input end of the frequency divider 815 is connected to the output end of the frequency divider 816 . Therefore, when the phase of the phase-locked loop 81 is adjusted based on the periodically sent third synchronization signal after two phase locks by the phase control module 817, the random phase jitter caused by the frequency divider 816 during the two phase locks can be eliminated. .
  • FIG. 14 exemplarily shows a possible implementation of S402 in FIG. 4 .
  • the second wireless communication device synthesizes the two received signals in the time domain direction to obtain a third reference signal.
  • the first wireless communication device sends a first reference signal at a first moment, and the first reference signal occupies a 20 MHz bandwidth.
  • the second wireless communication device samples the received signal at a sampling rate corresponding to a bandwidth of 100MHz, and obtains y1(t) at the third moment (wherein, y1(t) can be understood as the first reference received by the second wireless communication device Signal).
  • the first wireless communication device sends a second reference signal at a second moment, and the second reference signal occupies a bandwidth of 20 MHz.
  • the second wireless communication device samples the received signal at a sampling rate corresponding to a bandwidth of 100MHz, and obtains y2(t) at the fourth moment (wherein, y2(t) can be understood as the second reference received by the second wireless communication device Signal).
  • the second wireless communication device locally generates an SRS sequence x(t) with a bandwidth of 100MHz, and may only retain SRS signals in the first 20MHz and the last 20MHz of the SRS sequence x(t), and set 0 in the middle 60MHz. That is, the SRS signals of the first frequency band and the second frequency band in the SRS sequence x(t) are reserved, and the rest can be set to 0.
  • the second wireless communication device performs a cross-correlation operation through the following formula (3):
  • y(t) represents the superimposed signal of y1(t) and y2(t) in the time domain direction
  • x(t) represents that the second wireless communication device locally generates a 100MHz bandwidth SRS sequence x(t ), wherein, the signals of other frequency bands in the SRS sequence x(t) except the SRS signals of the first frequency band and the second frequency band may be set to 0.
  • x(t+ ⁇ ) represents the sequence after the cyclic shift of x(t) by ⁇ points, and * represents the conjugate.
  • the SRS sequence adopts the ZC sequence, which has good autocorrelation and low cross-correlation, a peak will appear when the two sequences are aligned, and the time of arrival (TOA) of the received signal is obtained by searching the time corresponding to the peak.
  • TOA time of arrival
  • the frequency domain bandwidth of the signal used for positioning is larger, the time domain pulse is narrower; at the same time, the signal bandwidth used for positioning is relatively high, so the second wireless communication device can use a higher sampling rate to sample the received signal.
  • the second wireless communication device performs sequence correlation detection, the easier it is to detect the first path of the SRS, the more accurate the obtained TOA is, and the higher the positioning accuracy of the first wireless communication device is.
  • the positioning accuracy of the first wireless communication device obtained by only sending the first reference signal and the second reference signal can be compared with that of sending the full bandwidth signal (including the first frequency band, the second frequency band and the first frequency band and the second frequency band).
  • the positioning accuracy obtained by the spaced frequency bands between the frequency bands is comparable.
  • the MUSIC algorithm may be further used in the frequency domain to perform fine delay estimation, so as to obtain a high-precision TOA.
  • the solutions provided in the embodiments of the present application may also be applied to positioning of carrier aggregation (Carrier Aggregation, CA).
  • the phase substantial synchronization technology provided by the embodiment of the present application can also be applied to the phase substantial synchronization of two carriers in 5G CA high-precision positioning.
  • a threshold may be set, and the delay corresponding to the first peak point greater than the threshold is determined as the path delay between the first wireless communication device and the second wireless communication device.
  • TOA cor arg(
  • R( ⁇ ) peak represents the peak point of the correlation sequence R( ⁇ ) in formula (3)
  • TOA cor represents the path delay between the first wireless communication device and the second wireless communication device
  • threshold indicates the set threshold
  • R max represents the highest peak point of the correlation sequence R( ⁇ ) in formula (3)
  • arg represents a function that seeks parameters for a function
  • the factory has high requirements for positioning accuracy, and at the same time, the greater the distance between the base stations (the base stations can be the aforementioned second wireless communication devices), the lower the positioning accuracy. Therefore, the InF-SH (indoor factory, sparse station spacing, 50m station spacing) scenario is used to simulate the positioning accuracy of the solution provided by the embodiment of the present application.
  • InF-SH indoor factory, sparse station spacing, 50m station spacing
  • FIG. 15 exemplarily shows a schematic diagram of a simulation environment provided by an embodiment of the present application
  • Table 4 exemplarily shows a schematic diagram of system parameters.
  • the simulation parameters are introduced below in conjunction with Figure 15 and Table 4:
  • Factory size 300 meters long, 150 meters wide, 10 meters high;
  • Base station height 8 meters
  • UE height 1.5 meters
  • Base station antenna configuration (4, 4, 2, 1, 1);
  • UE antenna configuration (1, 2, 2, 1, 1).
  • simulation scenario 3 constructs a 400MHz bandwidth positioning accuracy of 0.035m CEP 90%@LOS through two frequency hopping transmissions, and simulation scenario 6 transmits a complete 400MHz bandwidth signal.
  • the positioning accuracy (0.018m) is comparable, both reaching centimeter-level positioning accuracy, but in the embodiment of the present application, the first wireless communication device only needs to send two narrow-bandwidth signals, so that the positioning accuracy of low-performance wireless communication devices can be improved. And the power consumption of the wireless communication device can be reduced.
  • the first wireless communication device and the second wireless communication device include hardware structures and/or software modules corresponding to each function.
  • the present application can be implemented in the form of hardware or a combination of hardware and computer software with reference to the units and method steps of the examples described in the embodiments disclosed in the present application. Whether a certain function is executed by hardware or computer software drives the hardware depends on the specific application scenario and design constraints of the technical solution.
  • FIG. 16 , FIG. 17 and FIG. 18 are schematic structural diagrams of possible communication devices provided by embodiments of the present application. These communication devices can be used to implement the functions of the first wireless communication device or the second wireless communication device in the above method embodiments, and therefore can also achieve the beneficial effects of the above method embodiments.
  • the communication device may be the first wireless communication device as shown in Figure 1, or the second wireless communication device as shown in Figure 1, or it may be a wireless communication device applied to the first wireless communication device Or a module (such as a chip) of the second wireless communication device.
  • a communication device 1300 includes a processing unit 1310 and a transceiver unit 1320 .
  • the communication device 1300 is configured to implement the functions of the first wireless communication device or the second wireless communication device in the method embodiment shown in FIG. 4 or FIG. 5 above.
  • the processing unit 1310 is used to perform through the transceiver unit 1320: send the first reference signal in the first frequency band, The second frequency band sends the second reference signal.
  • the sending time of the first reference signal is different from the sending time of the second reference signal
  • the center frequency point of the first frequency band is different from the center frequency point of the second frequency band
  • the phases of the first reference signal and the second reference signal are substantially synchronized , the first reference signal and the second reference signal can be used to jointly estimate the arrival time of the reference signal.
  • the processing unit 1310 is used to execute through the transceiver unit 1320: receive the first reference signal, the first reference signal is The signal of the first frequency band. A second reference signal is received; the second reference signal is a signal of a second frequency band.
  • the sending time of the first reference signal is different from the sending time of the second reference signal, and the center frequency point of the first frequency band is different from the center frequency point of the second frequency band; wherein, the phases of the first reference signal and the second reference signal are substantially synchronized .
  • the time of arrival of the reference signal is jointly estimated according to the first reference signal and the second reference signal.
  • processing unit 1310 and the transceiver unit 1320 can be directly obtained by referring to related descriptions in the method embodiment shown in FIG. 4 , and details are not repeated here.
  • the communication device 1400 includes a processing circuit 1410 and an interface circuit 1420 .
  • the processing circuit 1410 and the interface circuit 1420 are coupled to each other.
  • the interface circuit 1420 may be a transceiver or an input-output interface.
  • the communication device 1400 may further include a memory for storing instructions executed by the processing circuit, or storing input data required by the processing circuit 1410 to execute the instructions, or storing data generated after the processing circuit 1410 executes the instructions.
  • the processing circuit 1410 is used to implement the functions of the processing unit 1310
  • the interface circuit 1420 is used to implement the functions of the transceiver unit 1320 .
  • a communication device 1500 includes a processor 1510 and a communication interface 1520 .
  • the processor 1510 and the communication interface 1520 are coupled to each other.
  • the communication interface 1520 may be a transceiver or an input and output interface.
  • the communication device 1500 may further include a memory 1530 for storing instructions executed by the processor 1510 or storing input data required by the processor 1510 to execute the instructions or storing data generated by the processor 1510 after executing the instructions.
  • the processor 1510 is used to implement the functions of the processing unit 1310
  • the communication interface 1520 is used to implement the functions of the transceiver unit 1320 .
  • the processor 1510 is used to execute through the communication interface 1520: sending the first reference signal in the first frequency band, The second frequency band sends the second reference signal.
  • the sending time of the first reference signal is different from the sending time of the second reference signal
  • the center frequency point of the first frequency band is different from the center frequency point of the second frequency band
  • the phases of the first reference signal and the second reference signal are substantially synchronized , the first reference signal and the second reference signal can be used to jointly estimate the arrival time of the reference signal.
  • the processor 1510 is used to execute through the communication interface 1520: receiving a first reference signal, the first reference signal is A signal in the first frequency band; receiving a second reference signal; the second reference signal is a signal in the second frequency band; wherein, the sending time of the first reference signal is different from the sending time of the second reference signal, and the center frequency point of the first frequency band is the same as that of the second reference signal The center frequency points of the second frequency band are different; wherein, the phases of the first reference signal and the second reference signal are substantially synchronized; and the arrival time of the reference signal is jointly estimated according to the first reference signal and the second reference signal.
  • the chip of the first wireless communication device implements the functions of the first wireless communication device in the above method embodiment.
  • the first wireless communication device chip receives information from other modules (such as radio frequency modules or antennas) in the first wireless communication device, and the information is sent to the first wireless communication device by the second wireless communication device; or, the first wireless communication device
  • the chip of the communication device sends information to other modules (such as a radio frequency module or an antenna) in the first wireless communication device, and the information is sent by the first wireless communication device to the second wireless communication device.
  • the module of the second wireless communication device implements the functions of the second wireless communication device in the above method embodiment.
  • the second wireless communication device module receives information from other modules (such as radio frequency modules or antennas) in the second wireless communication device, and the information is sent to the second wireless communication device by the first wireless communication device; or, the second wireless communication device
  • the communication device module sends information to other modules (such as a radio frequency module or an antenna) in the second wireless communication device, and the information is sent by the second wireless communication device to the first wireless communication device.
  • the second wireless communication device module here can be the baseband chip of the second wireless communication device, or it can be a DU or other modules, and the DU here can be an open radio access network (open radio access network, O-RAN) architecture.
  • O-RAN open radio access network
  • the processor in the embodiments of the present application can be a central processing unit (Central Processing Unit, CPU), and can also be other general-purpose processors, digital signal processors (Digital Signal Processor, DSP), application-specific integrated circuits (Application Specific Integrated Circuit, ASIC), Field Programmable Gate Array (Field Programmable Gate Array, FPGA) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof.
  • a general-purpose processor can be a microprocessor, or any conventional processor.
  • the present application also provides a computer program product, the computer program product including: computer program code or instruction, when the computer program code or instruction is run on the computer, the computer is made to execute the and the method of any one of the embodiments shown in FIG. 5 .
  • the present application also provides a computer-readable storage medium, the computer-readable medium stores program code, and when the program code is run on the computer, the computer is made to execute the steps shown in Figure 4 and Figure 5.
  • the computer-readable medium stores program code, and when the program code is run on the computer, the computer is made to execute the steps shown in Figure 4 and Figure 5.
  • the present application further provides a chip system, where the chip system may include a processor.
  • the processor is coupled with the memory, and may be used to execute the method in any one of the embodiments shown in FIG. 4 and FIG. 5 .
  • the chip system further includes a memory. Memory, used to store computer programs (also called code, or instructions).
  • the processor is configured to call and run a computer program from the memory, so that the device installed with the system-on-a-chip executes the method in any one of the embodiments shown in FIG. 4 and FIG. 5 .
  • the present application further provides a system, which includes the aforementioned first wireless communication device and one or more second wireless communication devices.
  • the method steps in the embodiments of the present application may be implemented by means of hardware, or may be implemented by means of a processor executing software instructions.
  • Software instructions can be composed of corresponding software modules, and software modules can be stored in random access memory, flash memory, read-only memory, programmable read-only memory, erasable programmable read-only memory, electrically erasable programmable read-only Memory, registers, hard disk, removable hard disk, CD-ROM or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may also be a component of the processor.
  • the processor and storage medium can be located in the ASIC. Additionally, the ASIC may be located in the first wireless communication device or the second wireless communication device. Of course, the processor and the storage medium may also exist in the first wireless communication device or the second wireless communication device as discrete components.
  • all or part of them may be implemented by software, hardware, firmware or any combination thereof.
  • software When implemented using software, it may be implemented in whole or in part in the form of a computer program product.
  • a computer program product consists of one or more computer programs or instructions. When the computer programs or instructions are loaded and executed on the computer, the processes or functions of the embodiments of the present application are executed in whole or in part.
  • the computer can be a general purpose computer, special purpose computer, computer network, network equipment, user equipment, or other programmable apparatus.
  • Computer programs or instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, computer programs or instructions may be Wired or wireless transmission to another website site, computer, server or data center.
  • a computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center integrating one or more available media. Available media may be magnetic media, such as floppy disks, hard disks, and magnetic tapes; optical media, such as digital video discs; or semiconductor media, such as solid-state hard disks.
  • the computer readable storage medium may be a volatile or a nonvolatile storage medium, or may include both volatile and nonvolatile types of storage media.
  • “plurality” means two or more.
  • “And/or” describes the association relationship of associated objects, indicating that there can be three types of relationships, for example, A and/or B, which can mean: A exists alone, A and B exist at the same time, and B exists alone, where A, B can be singular or plural.
  • the character “/” generally indicates that the contextual objects are an “or” relationship; in the formulas of this application, the character “/” indicates that the contextual objects are a “division” Relationship.
  • “Including at least one of A, B and C” may mean: including A; including B; including C; including A and B; including A and C; including B and C; including A, B and C.

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Abstract

一种参考信号到达时间估计方法、装置及芯片，用于提高所支持带宽较小的无线通信装置的定位精度。本申请中第一无线通信装置在第一频段发送第一参考信号，在第二频段发送第二参考信号。其中，第一参考信号的发送时间与第二参考信号的发送时间不同。第一频段的中心频点与第二频段的中心频点不同。第一参考信号和第二参考信号相位实质同步，第一参考信号和第二参考信号能被用于共同估计参考信号到达时间。本申请要求无线通信装置的射频通道仅具备支持发送第一频段和第二频段的信号的能力即可，且参考信号到达时间的估计精度较高，从而可以提高所支持带宽较小的无线通信装置的定位精度。

Description

一种参考信号到达时间估计方法、装置及芯片 技术领域
本申请涉及通信技术领域，特别涉及一种参考信号到达时间估计方法、装置及芯片。
背景技术
信号到达时间估计技术是蜂窝定位的关键技术之一。比如，第一无线通信装置可以向多个其他的第二无线通信装置发送参考信号，以便该多个第二无线通信装置测量接收到的参考信号的到达时间，从而可以实现对第一无线通信装置的位置定位，实际应用中通常基于到达时间(time of arrival，TOA)技术确定参考信号到达时间。
参考信号到达时间的估计精度决定了第一无线通信装置的定位精度，而参考信号到达时间的估计精度受限于参考信号的有效带宽，第一无线通信装置发送的参考信号的带宽越宽，第一无线通信装置的定位精度越高。
基于此，针对所支持带宽较小的无线通信装置，如何提高其定位精度成为亟需解决的问题。
发明内容
本申请提供一种参考信号到达时间估计方法、装置及芯片，用于提高所支持带宽较小的无线通信装置的定位精度。
应理解，本申请提供的方案中，无线通信装置可以是无线通信设备，也可以是无线通信设备中的部分器件，如系统芯片或通信芯片等集成电路产品。无线通信设备可以是支持无线通信功能的计算机设备。
具体地，无线通信设备可以是诸如智能手机这样的终端，也可以是诸如基站这样的无线接入网设备。系统芯片也可称为片上系统(system on chip，SoC)，或简称为SoC芯片。通信芯片可包括基带处理芯片和射频处理芯片。基带处理芯片有时也被称为调制解调器(modem)或基带芯片。射频处理芯片有时也被称为射频收发机(transceiver)或射频芯片。在物理实现中，通信芯片中的部分芯片或者全部芯片可集成在SoC芯片内部。例如，基带处理芯片集成在SoC芯片中，射频处理芯片不与SoC芯片集成。
第一方面，本申请提供一种参考信号到达时间估计方法，该方法可以由第一无线通信装置执行。该方法包括：第一无线通信装置在第一频段发送第一参考信号，在第二频段发送第二参考信号。其中，第一参考信号的发送时间与第二参考信号的发送时间不同，第一频段的中心频点与第二频段的中心频点不同；其中，第一参考信号和第二参考信号相位实质同步，第一参考信号和第二参考信号能被用于共同估计参考信号到达时间。
由于根据第一参考信号和第二参考信号共同估计参考信号到达时间，相比仅使用第一频段的第一参考信号估计参考信号到达时间的方案，本申请中用于估计参考信号到达时间的参考信号占据的频域范围更大，从而可以提高参考信号到达时间的估计精度。
相比通过发送占据第三频段的参考信号(第三频段包括第一频段和第二频段，且当第一频段和第二频段之间具有间隔的频段时，第三频段还包括第一频段和第二频段之间间隔的频段)进行参考信号到达时间估计的方案，本申请中参考信号到达时间的估计精度与之 相当，但本申请可以使无线通信装置的射频通道仅具备支持发送第一频段和第二频段的信号的能力即可，无需要求其必须支持发送第三频段的信号，可见，本申请可以提高发送能力较弱的无线通信装置的定位精度。
第二方面，本申请提供一种参考信号到达时间估计方法，该方法可以由第一无线通信装置执行。该方法包括：第一无线通信装置以跳频方式依次发送第一参考信号和第二参考信号，其中，第一参考信号和第二参考信号的频率范围不同但相位实质同步，第一参考信号和第二参考信号能被用于联合估计参考信号到达时间。
由于根据第一参考信号和第二参考信号共同估计参考信号到达时间，相比仅使用第一频段的第一参考信号估计参考信号到达时间的方案，本申请中用于估计参考信号到达时间的参考信号占据的频域范围更大，从而可以提高参考信号到达时间的估计精度。
相比通过发送占据第三频段的参考信号(第三频段包括第一频段和第二频段，且当第一频段和第二频段之间具有间隔的频段时，第三频段还包括第一频段和第二频段之间间隔的频段)进行参考信号到达时间估计的方案，本申请中参考信号到达时间的估计精度与之相当，但本申请可以使无线通信装置的射频通道仅具备支持发送第一频段和第二频段的信号的能力即可，无需要求其必须支持发送第三频段的信号，可见，本申请可以提高发送能力较弱的无线通信装置的定位精度。
在第一方面或第二方面的一种可能的实施方式中，参考信号到达时间能被用于估计无线通信设备的位置。由于参考到达时间的估计精度得到提高，因此基于该参考到达时间估计的无线通信设备的位置的精度也得到提高。
在第一方面或第二方面的一种可能的实施方式中，第一频段和第二频点之间具有间隔频段。且当第一频段和第二频段之间具有间隔的频段时，相比通过发送一个第三频段的参考信号进行参考信号到达时间估计的方案，本申请可以减少无线通信装置发送的信号量，从而可以降低无线通信装置的功耗。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置还可以通过第一锁相环产生第一本振信号，第一本振信号的中心频点与第一参考信号的中心频点相同。第一无线通信装置还可以通过第二锁相环产生第二本振信号，第二本振信号的中心频点与第二参考信号的中心频点相同。相比仅通过一个锁相环产生两个本振信号的方案，通过两个锁相环产生两个本振信号的过程中不需要涉及锁相环的失锁和再次重锁的过程，从而可以避免由于锁相环失锁后再次重锁引入的相位抖动，进而为第一参考信号和第二参考信号的相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置在第一频段发送第一参考信号，包括：根据第一本振信号，在第一频段发送第一参考信号。第一无线通信装置在第二频段发送第二参考信号，包括：根据第二本振信号，在第二频段发送第二参考信号。如此，可以通过将参考信号调制到不同频率的本振信号的方式，在需要的频段上发送参考信号。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置的混频器的输入端与第一锁相环选择性连接，且混频器的输入端与第二锁相环选择性连接。如此，可以在需要发送第一参考信号时，将混频器与第一锁相环连接，继而为第一射频通道提供第一本 振信号。在需要发送第二参考信号时，将混频器与第二锁相环连接，继而为第一射频通道提供第二本振信号。
在第一方面或第二方面的一种可能的实施方式中，第一锁相环和第二锁相环使用的参考时钟信号相同。如此，可以基于相同的参考时钟信号对两个锁相环输出的本振信号进行相位调整，从而为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置还可以向第一锁相环和第二锁相环分别输出第一同步信号。根据第一同步信号调整第一锁相环输出的第一本振信号和参考时钟信号的相位差。根据第一同步信号调整第二锁相环输出的第二本振信号和参考时钟信号的相位差。由于根据同一个第一同步信号调整两个锁相环与参考时钟信号之间的相位差，因此可以使第一本振信号和第二本振信号的初始相位的相位差被调整为0，从而为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
为了提供方案灵活性，在第一方面或第二方面的一种可能的实施方式中，分频器可以位于锁相环的环路外部，也可以位于锁相环的环路内部。分频器可以位于锁相环的环路外部的情况下，第一锁相环包括第一振荡器、第一分频器和第一反馈分频器。第一振荡器的输出端分别连接第一分频器和第一反馈分频器。第二锁相环包括第二振荡器、第二分频器和第二反馈分频器。第二振荡器的输出端分别连接第二分频器和第二反馈分频器。
分频器可以位于锁相环的环路内部的情况下，第一锁相环包括第一分频器和第一反馈分频器；第一反馈分频器的输入端连接第一分频器的输出端。第二锁相环包括第二分频器和第二反馈分频器；第二反馈分频器的输入端连接第二分频器的输出端。
由于第一反馈分频器是将第一分频器输出的信号进行分频后反馈给第一锁相环，使其调整第一本振信号和参考时钟信号的相位差。且第二反馈分频器是将第二分频器输出的信号进行分频后反馈给第二锁相环，使其调整第二本振信号和参考时钟信号的相位差，因此，可以减轻第一分频器和第二分频器的起始时钟沿的随机性带来的相位抖动。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置根据第一同步信号调整第一锁相环输出的第一本振信号和参考时钟信号的相位差，包括：根据第一同步信号，确定参考时钟信号的第一有效沿，并以第一有效沿为基准，调整第一本振信号和参考时钟信号的相位差。第一无线通信装置根据第一同步信号调整第二锁相环输出的第二本振信号和参考时钟信号的相位差，包括：根据第一同步信号，确定第一有效沿，并以第一有效沿为基准，调整第二本振信号和参考时钟信号的相位差。
由于根据第一同步信号指定参考信号的同一个第一有效沿作为两个锁相环进行相位调整的基准，因此可以使第一本振信号和第二本振信号的初始相位的相位差被调整为0，从而为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置根据第一同步信号调整第一锁相环输出的第一本振信号和参考时钟信号的相位差，包括：根据第一同步信号，确定参考时钟信号的第一有效沿，并以第一有效沿为基准，根据第一锁相环的第一反馈分频器对第一锁相环的第一分频器输出的第一本振信号进行分频后的信号，调整第一本振信号和参考时钟信号的相位差。第一无线通信装置根据第一同步信号调整第二锁相环输 出的第二本振信号和参考时钟信号的相位差，包括：根据第一同步信号，确定第一有效沿，并以第一有效沿为基准，根据第二锁相环的第二反馈分频器对第二锁相环的第二分频器输出的第二本振信号进行分频后的信号，调整第二本振信号和参考时钟信号的相位差。
由于第一反馈分频器是将第一分频器输出的信号进行分频后反馈给第一锁相环，使其调整第一本振信号和参考时钟信号的相位差。且第二反馈分频器是将第二分频器输出的信号进行分频后反馈给第二锁相环，使其调整第二本振信号和参考时钟信号的相位差，因此，可以减轻第一分频器和第二分频器的起始时钟沿的随机性带来的相位抖动。
在第一方面或第二方面的一种可能的实施方式中，第一本振信号与参考时钟信号之间的相位差，与第二本振信号与参考时钟之间的相位差相等。第一本振信号与参考时钟信号之间的相位差可以为0，也可以为预设值。如此，可以为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置还可以向第一锁相环和第二锁相环分别发送第二同步信号。根据第二同步信号对第一锁相环的第一分频器输入的信号进行分频处理。根据第二同步信号对第二锁相环的第二分频器输入的信号进行分频处理。
由于两个锁相环的分频器均是根据同一个第二同步信号进行分频处理，因此可以减轻由于两个分频器的起始时钟沿的随机性带来的第一参考信号和第二参考信号之间的相位抖动。
在第一方面或第二方面的一种可能的实施方式中，第一分频器和第二分频器的分频比相同。如此，可以为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置还可以向第一分频器和第二分频器分别发送第二同步信号。根据第二同步信号，确定第一振荡器输出的信号的第一上升沿为进行分频的起始时钟沿。根据第二同步信号，确定第二振荡器输出的信号的第二上升沿为进行分频的起始时钟沿。其中，第一上升沿和第二上升沿之间的相位差等于：第一振荡器输出的信号与第二振荡器输出的信号的相位差。
由于根据第二同步信号确定两个分频器的起始时钟沿，因此，可以减轻第一分频器和第二分频器的起始时钟沿的随机性带来的相位抖动，继而可以为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，第一本振信号和参考时钟信号之间的相位差，与第二本振信号和参考时钟信号之间的相位差的差值小于预设的相位差阈值。如此，第一参考信号和第二参考信号的相位可以近似同步。
在第一方面或第二方面的一种可能的实施方式中，第一本振信号和参考时钟信号之间的相位差，与第二本振信号和参考时钟信号之间的相位差的差值等于：第一锁相环的第一振荡器输出的信号与第二锁相环的第二振荡器输出的信号的相位差。如此，第一参考信号和第二参考信号的相位可以近似同步，且二者的相位差比较小，可以在误差范围之内，可以满足第一参考信号和第二参考信号用于联合估计参考信号到达时间的要求。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置，还可以向第三锁相环输出第三同步信号。生成第三本振信号，根据第三同步信号，调整第三本振信号与 参考时钟信号之间的相位差；第三本振信号的中心频点与第一参考信号的中心频点相同。生成第四本振信号，根据第三同步信号，调整第四本振信号与参考时钟信号之间的相位差；第四本振信号的中心频点与第二参考信号的中心频点相同。其中，第三同步信号的频率为第三本振信号的中心频点的频率和第四本振信号的中心频点的频率的公约数。
由于基于第三同步信号调整第三本振信号与参考信号的相位差，因此，当第三锁相环失锁后再重锁后，基于第三同步信号调整第四本振信号与参考信号的相位差，可以减轻第三锁相环失锁后再重锁引入的相位抖动。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置还可以根据第三同步信号，以及第三锁相环的第三反馈分频器对第三锁相环的第三分频器输出的第三本振信号进行分频后的信号，调整第三本振信号与参考时钟信号之间的相位差。根据第三同步信号，以及第三锁相环的第三反馈分频器对第三锁相环的第三分频器输出的第四本振信号进行分频后的信号，调整第四本振信号与参考时钟信号之间的相位差。
由于第三反馈分频器是将第三分频器输出的信号进行分频后反馈给第三锁相环，使其调整输出的信号(第三本振信号以及第四本振信号)和参考时钟信号的相位差。因此，可以减轻第三分频器在锁相环前后两次锁定过程中起始时钟沿的随机性带来的相位抖动。
在第一方面或第二方面的一种可能的实施方式中，进行相位调整后的第三本振信号与参考时钟信号相位同步，进行相位调整后的第四本振信号与参考时钟信号相位同步。从而为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，进行相位调整后的第三本振信号与第三同步信号之间的相位差，与进行相位调整后的第四本振信号与第三同步信号之间的相位差相等。从而为第一本振信号和第二本振信号的相位实质同步奠定基础，继而为第一参考信号和第二参考信号相位实质同步奠定基础。
在第一方面或第二方面的一种可能的实施方式中，第三同步信号与参考时钟信号相位同步。进行相位调整后的第三本振信号与第三同步信号相位同步。进行相位调整后的第四本振信号与第三同步信号相位同步。从而可以使第一本振信号和第二本振信号的相位实质同步，第一参考信号和第二参考信号相位实质同步。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置还可以在第三锁相环锁定状态下，向第三锁相环输入第三同步信号。在第三锁相环处于非锁定状态下，停止向第三锁相环输入第三同步信号。如此，可以减少向第三锁相环输入的第三同步信号，从而节省无线通信装置的功耗。
在第一方面或第二方面的一种可能的实施方式中，第三锁相环包括第三分频器和第三反馈分频器，第三反馈分频器的输入端连接第三分频器的输出端。由于第三反馈分频器是将第三分频器输出的信号进行分频后反馈给第三锁相环，使其调整输出的信号(第三本振信号以及第四本振信号)和参考时钟信号的相位差。因此，可以减轻第三分频器在锁相环前后两次锁定过程中起始时钟沿的随机性带来的相位抖动。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置在第一频段发送第一参考信号，在第二频段发送第二参考信号之前，还包括：进入睡眠。在唤醒时间到达时，进行唤醒。在唤醒期间发送第一参考信号和第二参考信号。且之后再次进入睡眠。如此，可以节省无线通信装置的功耗。
在第一方面或第二方面的一种可能的实施方式中，第一无线通信装置在第一频段发送第一参考信号，在第二频段发送第二参考信号之前，还包括：接收配置信息，配置信息包括空闲态/非激活态下发送信号的时域资源的信息。接收RRC连接释放消息。进入睡眠。根据时域资源信息，在唤醒时间到达时，进行唤醒。如此，可以根据为第一无线通信装置配置的时域资源信息确定唤醒时间。
第三方面，本申请提供一种参考信号到达时间估计方法，该方法可以由第二无线通信装置执行。该方法包括：第二无线通信装置接收第一参考信号，第一参考信号为第一频段的信号。接收第二参考信号；第二参考信号为第二频段的信号；其中，第一参考信号的发送时间与第二参考信号的发送时间不同，第一频段的中心频点与第二频段的中心频点不同；其中，第一参考信号和第二参考信号相位实质同步。根据第一参考信号和第二参考信号共同估计参考信号到达时间。
相比通过发送占据第三频段的参考信号(第三频段包括第一频段和第二频段，且当第一频段和第二频段之间具有间隔的频段时，第三频段还包括第一频段和第二频段之间间隔的频段)进行参考信号到达时间估计的方案，本申请中参考信号到达时间的估计精度与之相当，但本申请可以使无线通信装置的射频通道仅具备支持发送第一频段和第二频段的信号的能力即可，无需要求其必须支持发送第三频段的信号，可见，本申请可以提高发送能力较弱的无线通信装置的定位精度。
第四方面，本申请提供一种参考信号到达时间估计方法，该方法可以由第二无线通信装置执行。该方法包括：第二无线通信装置接收第一参考信号，第一参考信号为第一频段的信号；
接收第二参考信号；第二参考信号为第二频段的信号；其中，第一参考信号和第二参考信号是跳频发送的，其中，第一参考信号和第二参考信号的频率范围不同但相位实质同步；
根据第一参考信号和第二参考信号联合估计参考信号到达时间。
相比通过发送占据第三频段的参考信号(第三频段包括第一频段和第二频段，且当第一频段和第二频段之间具有间隔的频段时，第三频段还包括第一频段和第二频段之间间隔的频段)进行参考信号到达时间估计的方案，本申请中参考信号到达时间的估计精度与之相当，但本申请可以使无线通信装置的射频通道仅具备支持发送第一频段和第二频段的信号的能力即可，无需要求其必须支持发送第三频段的信号，可见，本申请可以提高发送能力较弱的无线通信装置的定位精度。
在第三方面或第四方面的一种可能的实施方式中，参考信号到达时间能被用于估计无线通信设备的位置。由于参考到达时间的估计精度得到提高，因此基于该参考到达时间估计的无线通信设备的位置的精度也得到提高。
在第三方面或第四方面的一种可能的实施方式中，第二无线通信装置可以将第一参考信号和第二参考信号在时域方向叠加，得到第三参考信号。根据第三参考信号估计参考信号到达时间。如此，可以提供一种根据第一参考信号和第二参考信号联合估计参考信号到达时间的方案。
在第三方面或第四方面的一种可能的实施方式中，第二无线通信装置可以根据第三频段的带宽对应的采样率，对接收到的第一参考信号对应的信号进行采样，得到第一参考信号。根据第三频段的带宽对应的采样率，对接收到的第二参考信号对应的信号进行采样，得到第二参考信号。其中，第三频段包括第一频段、第二频段，以及第一频段和第二频段之间间隔的频段。
由于频段越宽，对应的采样率可以越高，因此可以基于较高的采样率得到第一参考信号和第二参考信号，继而可以提高参考信号到达时间的估计精度。
第五方面，提供了一种无线通信装置，包括通信单元和处理单元，以执行上述第一方面。第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式。通信单元用于执行与发送和接收相关的功能。可选地，通信单元包括接收单元和发送单元。在一种设计中，无线通信装置为通信芯片，处理单元可以时一个或多个处理器或处理器核心，通信单元可以为通信芯片的输入输出电路或者端口。
在另一种设计中，通信单元可以为发射器和接收器，或者通信单元为发射机和接收机。
可选的，无线通信装置还包括可用于执行上述第一方面任一种通信方法中的任一种实施方式的各个模块。
第六方面，提供了一种无线通信装置，包括处理器和存储器。可选的，还包括收发器，该存储器用于存储计算机程序或指令，该处理器用于从存储器中调用并运行该计算机程序或指令，当处理器执行存储器中的计算机程序或指令时，使得该无线通信装置执行上述第一方面、第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式。
可选的，处理器为一个或多个，存储器为一个或多个。
可选的，存储器可以与处理器集成在一起，或者存储器与处理器分离设置。
可选的，收发器中可以包括，发射机(发射器)和接收机(接收器)。
第七方面，提供了一种无线通信装置，包括处理器。该处理器与存储器耦合，可用于执行第一方面、第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式。可选地，该无线通信装置还包括存储器。可选地，该无线通信装置还包括通信接口，处理器与通信接口耦合。
在一种实现方式中，该无线通信装置为第一无线通信装置时，通信接口可以是收发器，或，输入/输出接口。可选地，收发器可以为收发电路。可选地，输入/输出接口可以为输入/输出电路。
在又一种实现方式中，当该无线通信装置为芯片或芯片系统时，通信接口可以是该芯片或芯片系统上的输入/输出接口、接口电路、输出电路、输入电路、管脚或相关电路等。处理器也可以体现为处理电路或逻辑电路。
第八方面，提供了一种系统，系统包括上述无线通信装置和第二无线通信装置。
第九方面，提供了一种计算机程序产品，计算机程序产品包括：计算机程序(也可以称为代码，或指令)，当计算机程序被运行时，使得计算机执行上述第一方面、第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式。
第十方面，提供了一种计算机可读存储介质，计算机可读介质存储有计算机程序(也可以称为代码，或指令)当其在计算机上运行时，使得计算机执行上述第一方面、第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式。
第十一方面，提供了一种芯片系统，该芯片系统可以包括处理器。该处理器与存储器耦合，可用于执行上述第一方面、第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式。可选地，该芯片系统还包括存储器。存储器，用于存储计算机程序(也可以称为代码，或指令)。处理器，用于从存储器调用并运行计算机程序，使得安装有芯片系统的设备执行第一方面、第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式。
第十二方面，提供了一种处理装置，包括：接口电路和处理电路。接口电路可以包括输入电路和输出电路。处理电路用于通过输入电路接收信号，并通过输出电路发射信号，使得第一方面、第二方面、第三方面和第四方面任一方面或任一方面的任一种实施方式被实现。
在具体实现过程中，上述处理装置可以为芯片，输入电路可以为输入管脚，输出电路可以为输出管脚，处理电路可以为晶体管、门电路、触发器和各种逻辑电路等。输入电路所接收的输入的信号可以是由例如但不限于接收器接收并输入的，输出电路所输出的信号可以是例如但不限于输出给发射器并由发射器发射的，且输入电路和输出电路可以是同一电路，该电路在不同的时刻分别用作输入电路和输出电路。本申请对处理器及各种电路的具体实现方式不做限定。
在一种实现方式中，当无线通信装置是第一无线通信装置，其中，第一无线通信装置可以是诸如智能手机这样的终端，也可以是诸如基站这样的无线接入网设备。接口电路可以为第一无线通信装置中的射频处理芯片，处理电路可以为第一无线通信装置中的基带处理芯片。
在又一种实现方式中，无线通信装置可以是第一无线通信装置中的部分器件，如系统芯片或通信芯片等集成电路产品。接口电路可以为该芯片或芯片系统上的输入/输出接口、接口电路、输出电路、输入电路、管脚或相关电路等。处理电路可以为该芯片上的逻辑电路。
附图说明
图1为本申请实施例提供的一种无线通信系统的结构示意图；
图2为本申请实施例提供的一种无线通信装置的结构示意图；
图3a为本申请实施例提供的一种无线通信装置的位置估计方法的示意图；
图3b为本申请实施例提供的一种10MHz和20MHz的时钟信号相位同步的示意图；
图3c为本申请实施例提供的一种20MHz和30MHz的时钟信号相位同步的示意图；
图4为本申请实施例提供一种用于估计参考信号到达时间的方法流程示意图；
图5为上述图4中S401中第一无线通信装置发送第一参考信号和第二参考信号的方法流程示意图；
图6为本申请实施例提供一种第一无线通信装置发送第一参考信号和第二参考信号的示例的示意图；
图7为本申请实施例提供的第一无线通信装置的结构示意图；
图8a为本申请实施例提供的一种图7中的锁相环75和锁相环76的结构示意图；
图8b为图8a中参考时钟信号、锁定信号和第一同步信号的示意图；
图8c为图8a中锁相环75输出的信号的频率、相位检测器751检测到的相位差、第一同步模块输出的同步信号的示意图；
图9a为本申请实施例提供的一种图7中的锁相环75和锁相环76的结构示意图；
图9b为图9a中一种参考时钟信号、锁定信号和第二同步信号、振荡器754输出的信号、振荡器764输出的信号、分频器756输出的信号、分频器766输出的信号的示意图；
图10为本申请实施例提供的一种图7中的锁相环75和锁相环76的结构示意图；
图11为本申请实施例提供的另一种第一无线通信装置的结构示意图；
图12a为一种图11中锁相环81的结构示意图；
图12b为图12a中参考时钟信号、锁相环81的锁定信号、第三同步模块输出的信号和锁相环81输出的信号的示意图；
图13为一种图11中锁相环81的另一种结构示意图；
图14为图4中S402的一种可能的实现方式；
图15为本申请实施例提供的一种仿真环境的示意图；
图16为本申请实施例提供的另一种无线通信装置的结构示意图；
图17为本申请实施例提供的另一种无线通信装置的结构示意图；
图18为本申请实施例提供的另一种无线通信装置的结构示意图。
具体实施方式
下面将结合附图对本申请实施例作进一步地详细描述。
本申请实施例提供的技术方案主要适用于无线通信系统。该无线通信系统可以遵从第三代合作伙伴计划(third generation partnership project，3GPP)的无线通信标准。比如，本申请实施例提供的方案可以应用于第四代(4th generation，4G)通信系统，例如长期演进(long term evolution，LTE)通信系统，也可以应用于第五代(5th generation，5G)通信系统，例如5G新空口(new radio，NR)通信系统，或应用于未来的各种通信系统，例如第六代(6th generation，6G)通信系统。本申请实施例提供的技术方案也可以遵从其他无线通信标准，例如电气电子工程师学会(Institute of Electrical and Electronics Engineers，IEEE)的802系列(如802.11，802.15，或者802.20)的无线通信标准。本申请实施例提供的方法还可以应用于蓝牙系统、WiFi系统、LoRa系统或车联网系统中。本申请实施例提供的方法还可以应用于卫星通信系统其中，卫星通信系统可以与上述通信系统相融合。
本申请实施例适用的通信系统中的设备可以分为：提供无线网络服务的设备和使用无线网络服务的设备。
提供无线网络服务的设备是指那些组成无线通信网络的设备，可简称为网络设备(network equipment)，或网络单元(network element)。网络设备通常归属于运营商或基础设施提供商，并由这些厂商负责运营或维护。网络设备，例如包括接入网(access network，AN)设备，例如基站(例如，接入点)，可以是指接入网中在空口通过一个或多个小区与无线终端设备通信的设备。基站可用于将收到的空中帧与网际协议(IP)分组进行相互转换，作为终端设备与接入网的其余部分之间的路由器，其中接入网的其余部分可包括IP网络。RSU可以是支持V2X应用的固定基础设施实体，可以与支持V2X应用的其他实体 交换消息。网络设备还可协调对空口的属性管理。例如，网络设备可以包括LTE系统或高级长期演进(long term evolution-advanced，LTE-A)中的演进型基站(NodeB或eNB或e-NodeB，evolutional Node B)，或者也可以包括第五代移动通信技术(the 5 th generation，5G)新无线(new radio，NR)系统中的下一代节点B(next generation node B，gNB)或者也可以包括云接入网(cloud radio access network，Cloud RAN)系统中的集中式单元(centralized unit，CU)和分布式单元(distributed unit，DU)，本申请实施例并不限定。
使用无线网络服务的设备，可简称为终端设备(terminal)或终端设备。终端设备包括向用户提供语音和/或数据连通性的设备，例如可以包括具有无线连接功能的手持式设备、或连接到无线调制解调器的处理设备。该终端设备可以经无线接入网(radio access network，RAN)与核心网进行通信，与RAN交换语音和/或数据。该终端设备可以包括用户设备(user equipment，UE)、无线终端设备、移动终端设备、设备到设备通信(device-to-device，D2D)终端设备、V2X终端设备、机器到机器/机器类通信(machine-to-machine/machine-type communications，M2M/MTC)终端设备、物联网(internet of things，IoT)终端设备、订户单元(subscriber unit)、订户站(subscriber station)，移动站(mobile station)、远程站(remote station)、接入点(access point，AP)、远程终端设备(remote terminal)、接入终端设备(access terminal)、用户终端设备(user terminal)、用户代理(user agent)、或用户装备(user device)等。例如，可以包括移动电话(或称为“蜂窝”电话)，具有移动终端设备的计算机，便携式、袖珍式、手持式、计算机内置的移动装置等。例如，个人通信业务(personal communication service，PCS)电话、无绳电话、会话发起协议(session initiation protocol，SIP)话机、无线本地环路(wireless local loop，WLL)站、个人数字助理(personal digital assistant，PDA)、等设备。还包括受限设备，例如功耗较低的设备，或存储能力有限的设备，或计算能力有限的设备等。例如包括条码、射频识别(radio frequency identification，RFID)、传感器、全球定位系统(global positioning system，GPS)、激光扫描器等信息传感设备。
下面以提供无线网络服务的设备为基站，使用无线网络服务的设备为终端设备进行介绍。图1为本申请实施例提供的一种无线通信系统的结构示意图。如图1所示，无线通信系统包括终端设备和基站。按照传输方向的不同，从终端设备到基站的传输链路记为上行链路(uplink，UL)，从基站到终端设备的传输链路记为下行链路(downlink，DL)。相类似地，上行链路中的数据传输可简记为上行数据传输或上行传输，下行链路中的数据传输可简记为下行数据传输或下行传输。
该无线通信系统中，基站可通过集成或外接的天线设备，为特定地理区域提供通信覆盖。位于基站的通信覆盖范围内的一个或多个终端设备，均可以接入基站。一个基站可以管理一个或多个小区(cell)。每个小区具有一个身份证明(identification)，该身份证明也被称为小区标识(cell identity，cell ID)。从无线资源的角度看，一个小区是下行无线资源，以及与其配对的上行无线资源(非必需)的组合。
终端设备和基站应知晓该无线通信系统预定义的配置，包括系统支持的无线电接入技术(radio access technology，RAT)以及系统规定的无线资源配置等，比如无线电的频段和载波的基本配置。载波是符合系统规定的一段频率范围。这段频率范围可由载波的中心频率(记为载频)和载波的带宽共同确定。这些系统预定义的配置可作为无线通信系统的标准协议的一部分,或者通过终端设备和基站间的交互确定。相关标准协议的内容，可能会预先存储在终端设备和基站的存储器中，或者体现为终端设备和基站的硬件电路或软件代 码。
该无线通信系统中，终端设备和基站支持一种或多种相同的RAT，例如5G NR，4G LTE，或未来演进系统的RAT。具体地，终端设备和基站采用相同的空口参数、编码方案和调制方案等，并基于系统规定的无线资源相互通信。
基于上述内容，图2为本申请实施例提供的一种无线通信装置的结构示意图。该无线通信装置可以是本申请实施例中的终端设备，比如可以图1中的终端设备。该无线通信装置还可以是本申请实施例中的网络设备，比如可以图1中的基站。
一种可能的实施方式中，该无线通信装置可以包括处理电路和接口电路。接口电路可以包括输入电路和输出电路。处理电路用于通过输入电路接收信号，并通过输出电路发射信号，使得下述图4和图5的相关方法被实现。比如当该无线通信装置为终端设备，则处理电路可以通过控制接口电路执行下述S401、S503、S504和S506等。再比如当该无线通信装置为网络设备，则处理电路可以通过控制接口电路执行下述S402、S502和S505等。本申请实施例中后续提到的第一同步模块、第二同步模块和第三同步模块都可以为处理电路中的模块。
在一种实现方式中，接口电路还可以为无线通信装置中的射频处理芯片，处理电路可以为无线通信装置中的基带处理芯片。
在又一种实现方式中，无线通信装置可以是无线通信设备中的部分器件，如系统芯片或通信芯片等集成电路产品。接口电路可以为该芯片或芯片系统上的输入/输出接口、接口电路、输出电路、输入电路、管脚或相关电路等。处理电路可以为该芯片上的逻辑电路。
在又一种实现方式中，本申请实施例中的处理电路还可以为处理器或处理器中的部分模块或单元，接口电路还可以为射频通道或射频通道中的部分器件。处理器用于控制射频通道，使得下述图4和图5的相关方法被实现。
如图2所示，该无线通信装置可包括多个组件，例如：应用子系统，内存(memory)，大容量存储器(massive storage)，基带子系统，射频集成电路(radio frequency integrated circuit，RFIC)，射频前端(radio frequency front end，RFFE)器件，以及天线(antenna，ANT)。这些组件可以通过各种互联总线或其他电连接方式耦合。
图2中的应用子系统可以为设置于图2的处理器110，或者为处理器110中的一个模块。
图2中，ANT_1表示第一天线，ANT_N表示第N天线，N为大于1的正整数。Tx表示发送路径，Rx表示接收路径，不同的数字表示不同的路径。每条路径均可以表示一个信号处理通道。其中，FBRx表示反馈接收路径，PRx表示主接收路径，DRx表示分集接收路径。HB表示高频，LB表示低频，两者是指频率的相对高低。BB表示基带。应理解，图2中的标记和组件仅为示意目的，仅作为一种可能的实现方式，本申请实施例还包括其他的实现方式。例如，通信装置可以包括更多或更少的路径，包括更多或更少的组件。
其中，应用子系统可作为通信装置的主控制系统或主计算系统，用于运行主操作系统和应用程序，管理整个通信装置的软硬件资源，并可为用户提供用户操作界面。此外，应用子系统中也可包括与其他子系统(例如基带子系统)相关的驱动软件。
应用子系统可包括一个或多个处理器。多个处理器可以多个相同类型的处理器，也可以包括多种类型的处理器组合。本申请中，处理器可以是通用用途的处理器，也可以是为 特定领域设计的处理器。例如，处理器可以是中央处理单元(center processing unit，CPU)，数字信号处理器(digital signal processor，DSP)，或微控制器(micro control unit，MCU)。处理器也可以是图形处理器(graphics processing unit，GPU)、图像信号处理器(image signal processing，ISP)，音频信号处理器(audio signal processor，ASP)，以及为人工智能(artificial intelligence，AI)应用专门设计的AI处理器。AI处理器包括但不限于神经网络处理器(neural network processing unit，NPU)，张量处理器(tensor processing unit，TPU)以及被称为AI引擎的处理器。
图2中，射频集成电路(包括RFIC 1，以及一个或多个可选的RFIC 2)和射频前端器件可以共同组成射频子系统。根据信号的接收或发送路径的不同，射频子系统也可以分为射频接收通道(RF receive path)和射频发射通道(RF transmit path)。其中，射频接收通道可通过天线接收射频信号，对该射频信号进行处理(如放大、滤波和下变频)以得到基带信号，并传递给基带子系统。射频发送通道可接收来自基带子系统的基带信号，对基带信号进行处理(如上变频、放大和滤波)以得到射频信号，并最终通过天线将该射频信号辐射到空间中。射频集成电路可以被称为射频处理芯片或射频芯片。
具体地，射频子系统可包括天线开关，天线调谐器，低噪声放大器(low noise amplifier，LNA)，功率放大器(power amplifier，PA)，混频器(mixer)，本地振荡器(local oscillator，LO)、滤波器(filter)等电子器件，这些电子器件可以根据需要集成到一个或多个芯片中。射频集成电路可以被称为射频处理芯片或射频芯片。射频前端器件也可以是独立的芯片。射频芯片有时也被称为接收机(receiver)、发射机(transmitter)、收发机(transceiver)或收发信机。随着技术的演进，天线有时也可以认为是射频子系统的一部分，并可集成到射频子系统的芯片中。天线、射频前端器件和射频芯片都可以单独制造和销售。当然，射频子系统也可以基于功耗和性能的需求，采用不同的器件或者不同的集成方式。例如，将属于射频前端的部分器件集成在射频芯片中，甚至将天线和射频前端器件都集成射频芯片中，该射频芯片也可以称为射频天线模组或天线模组。
与射频子系统主要完成射频信号处理类似，顾名思义，基带子系统主要完成对基带信号的处理。基带子系统可以从基带信号中提取有用的信息或数据比特，或者将信息或数据比特转换为待发送的基带信号。这些信息或数据比特可以是表示语音、文本、视频等用户数据或控制信息的数据。例如，基带子系统可以实现诸如调制和解调，编码和解码等信号处理操作。对于不同的无线接入技术，例如5G NR和4G LTE，基带信号处理操作也不完全相同。
此外，由于射频信号通常是模拟信号，基带子系统处理的信号主要是数字信号，通信装置中还需要有模数转换器件。本申请实施例中，模数转换器件可以设置在基带子系统中，也可以设置在射频子系统中。模数转换器件包括将模拟信号转换为数字信号的模数转换器(analog to digital converter，ADC)，以及将数字信号转换为模拟信号的数模转换器(digital to analog converter，DAC)。
与应用子系统类似，基带子系统也可包括一个或多个处理器。此外，基带子系统还可以包括一种或多种硬件加速器(hardware accelerator，HAC)。硬件加速器可用于专门完成一些处理开销较大的子功能，如数据包(data packet)的组装和解析，数据包的加解密等。这些子功能采用通用功能的处理器也可以实现，但是因为性能或成本的考量，采用硬件加速器可能更加合适。在具体的实现中，硬件加速器主要是用专用集成电路(application  specified integrated circuit，ASIC)来实现。当然，硬件加速器中也可以包括一个或多个相对简单的处理器，如MCU。
本申请实施例中，基带子系统和射频子系统共同组成通信子系统，为通信装置提供无线通信功能。通常，基带子系统负责管理通信子系统的软硬件资源，并且可配置射频子系统的工作参数。基带子系统的处理器中可以运行通信子系统的子操作系统，该子操作系统往往是嵌入式操作系统或实时操作系统(real time operating system)，例如VxWorks操作系统或高通公司的QuRT系统。
基带子系统可以集成为一个或多个芯片，该芯片可称为基带处理芯片或基带芯片。基带子系统可以作为独立的芯片，该芯片可被称调制解调器(modem)或modem芯片。基带子系统可以按照modem芯片为单位来制造和销售。modem芯片有时也被称为基带处理器或移动处理器。此外，基带子系统也可以进一步集成在更大的芯片中，以更大的芯片为单位来制造和销售。这个更大的芯片可以称为系统芯片，芯片系统或片上系统(system on a chip，SoC)，或简称为SoC芯片。基带子系统的软件组件可以在芯片出厂前内置在芯片的硬件组件中，也可以在芯片出厂后从其他非易失性存储器中导入到芯片的硬件组件中，或者还可以通过网络以在线方式下载和更新这些软件组件。
此外，该通信装置中还包括存储器，例如图2中的内存和大容量存储器。此外，在应用子系统和基带子系统中，还可以分别包括一个或多个缓存。具体实现中，存储器可分为易失性存储器(volatile memory)和非易失性存储器(non-volatile memory，NVM)。易失性存储器是指当电源供应中断后，内部存放的数据便会丢失的存储器。目前，易失性存储器主要是随机存取存储器(random access memory，RAM)，包括静态随机存取存储器(static RAM，SRAM)和动态随机存取存储器(dynamic RAM，DRAM)。非易失性存储器是指即使电源供应中断，内部存放的数据也不会因此丢失的存储器。常见的非易失性存储器包括只读存储器(read only memory，ROM)、光盘、磁盘以及基于闪存(flash memory)技术的各种存储器0等。通常来说，内存和缓存可以选用易失性存储器，大容量存储器可以选用非易失性存储器，例如闪存。
在介绍本申请实施提供的方案之前，先对本申请实施例涉及到的名词和术语进行介绍。
(1)基于TOA的定位方法。
本申请实施例提供的方案适用于对第一无线通信装置的定位，第一无线通信装置可以为终端设备，也可以为网络设备，本申请实施例中以进行定位的第一无线通信装置为终端设备为例进行介绍。
5G NR定义了多种基于TOA估计的定位方法，例如观测到达时间差(observed time difference of arrival，OTDOA)，多重往返时间(round trip time，Multi-RTT)，下行到达时间差(downlink time difference of arrival，DL-TDOA)，上行到达时间差(uplink time difference of arrival，UL-TDOA)。基于TOA估计的定位方法是通过TOA估计的值进行定位。
图3a示例性示出了本申请实施例提供的一种定位方法的示意图，如图3a所示，终端设备可以向不同网络设备(如图3a中的基站301、基站302和基站303)发送上行参考信号，不同网络设备测量上行参考信号的TOA。网络设备将TOA上报给定位服务器。定位服务器可以根据多个网络设备与终端设备之间的TOA信息，计算到达时间差(time difference of arrival，OTDOA)，并根据已知的网络设备的位置信息，得到终端设备的位置 信息。比如图3a所示，定位服务器已知基站301、基站302和基站303的位置信息，且已知各个网络设备与终端设备之间的TOA信息，则通过解图3a中的双曲线方程可以得到终端设备的位置信息。又一种可能的实现方式中，终端设备也可以具备定位的能力，比如终端设备可以请求位置信息并自己来定位自身的位置信息。具体地，终端设备向网络设备请求位置信息，多个网络设备分别向终端设备发送下行定位参考信号(positioning reference signal，PRS)，终端设备基于下行PRS，分别测量多个网络设备的TOA，终端设备根据已知的各个网络设备的位置，即可确定出该终端设备的位置信息，或者终端设备将各个网络设备的TOA信息上报给定位服务器。定位服务器根据多个网络设备与终端设备之间的TOA信息，计算TDOA，并根据已知的网络设备的位置信息，得到终端设备的位置信息。
本申请实施例中，定位服务器例如可以是NR系统中的定位管理功能(location management function，LMF)。例如，一种可能的定位架构下，接入和移动性管理功能(Access and Mobility Management Function，AMF)接收网络中其它网元发起的关于终端设备的服务请求，AMF向LMF发送关于该终端设备的定位请求，LMF接收来自AMF的定位请求，发起对终端设备的定位，确定该终端设备的定位信息。
本申请实施提供的定位方法可以应用于多种行业和业务中，以便对人和对物进行定位，以获取人员和物资的位置信息，进而可以基于位置信息开展进一步的应用开发。比如本申请实施例提供的定位方法可以应用于行业应用场景，比如智能制造、仓储物理、电力能源、公检法司等场景，比如用于实现对物的定位。在此类场景下，需进行定位的终端设备可以为固定有或集成有定位标签的物资和/或设备上。
再比如本申请实施例提供的定位方法可以应用于消费者应用场景，比如博物展览、智慧商超、交通枢纽等，比如可以用于实现对人的定位，以便提供室内导航、导览业务等服务。在此类场景下，需进行定位的终端设备可以为手机等设备。
(2)相位同步。
当两个信号的频率不同，且该两个频率之间为整数倍关系，则该两个信号相位同步是指：该两个信号的上升沿对齐到最小频率的信号的上升沿。图3b中示例性示出了本申请实施例提供的一种10兆赫兹(mega hertz，MHz)和20MHz的信号相位同步的示意图，如图3b所示，20MHz的信号的上升沿对齐到10MHz的频率的信号的上升沿。
当两个信号的频率不同，且该两个频率之间并非整数倍关系，则该两个信号相位同步是指：该两个信号的时钟上升沿对齐到最大公约数频率的信号的上升沿，最大公约数频率的信号是独立于该两个信号之外的一个信号。图3c中示例性示出了本申请实施例提供的一种20MHz、30MHz和40MHz的信号相位同步的示意图，如图3c所示，20MHz、30MHz和40MHz的最大公约数为10MHz，则20MHz、30MHz和40MHz的信号的上升沿均对齐到10MHz的频率的信号的上升沿。再举个例子，12.288MHz和30.72MHz的最大公约数为6.144MHz，则12.288MHz和30.72MHz的信号的上升沿均对齐到6.144MHz的频率的信号的上升沿。
本申请实施例中两个信号也可以称为两个时钟信号。本申请实施例中两个信号相位同步也可以称为该两个信号相位连续。
基于上述内容，图4示例性示出了本申请实施例提供一种用于估计参考信号到达时间的方法流程示意图，图4提供的方案可以用于确定前述内容提到的参考信号到达时间。如 下，该方法的执行主体可以为第一无线通信装置和第二无线通信装置。第一无线通信装置为发送端的无线通信装置，第二无线通信装置为接收端的无线通信装置。其中，第一无线通信装置可以是终端设备也可以是网络设备，第二无线通信装置可以是终端设备也可以是网络设备。当第一无线通信装置为终端设备时，第二无线通信装置可以为网络设备。当第一无线通信装置为网络设备时，第二无线通信装置可以为终端设备。
为了介绍方便，后续内容以第一无线通信装置为终端设备，第二通信设备为网络设备为例进行介绍。如图4所示，该方法包括：
S401，第一无线通信装置通过第一射频通道在第一频段发送第一参考信号，在第二频段发送第二参考信号。其中，第一参考信号和第二参考信号相位实质同步，第一参考信号和第二参考信号能被用于共同估计参考信号到达时间。
相对应地，第二无线通信装置接收第一参考信号，第二无线通信装置接收第二参考信号。
在S401中，第一参考信号的发送时间与第二参考信号的发送时间不同。第一频段的中心频点与第二频段的中心频点不同。一种可能的实施方式中，第一频段的中心频点与第二频段的中心频点不同可以理解为：第一参考信号和第二参考信号的频率范围不同。第一参考信号和第二参考信号的频率范围可能有部分重叠；也可能完全无重叠，第一参考信号的频率范围和第二参考信号的频率范围之间具有间隔频段。
一种可能的实施方式中，S401可以替换为：第一无线通信装置以跳频方式依次发送第一参考信号和第二参考信号。跳频可以是指载波频率在一定的频带范围内进行跳变。跳频发送的第一参考信号和第二参考信号可以具有如下特点：第一参考信号的发送时间与第二参考信号的发送时间不同，第一参考信号和第二参考信号的频率范围不同。
本申请实施例中，第一参考信号和第二参考信号相位实质同步中的实质可以理解为substantially。第一参考信号和第二参考信号相位实质同步可以包括两种情况：
第一种情况下，第一参考信号和第二参考信号相位同步。
第二种情况下，第一参考信号和第二参考信号相位近似同步，即第一参考信号和第二参考信号之间存在一个较小的相位差，也可以理解为该相位差小于相位差阈值。在后续内容中介绍了一种可能的实施方式，该实施方式中，第一参考信号和第二参考信号之间的相位差为两个锁相环的振荡器输出的信号之间的相位差。
关于上述两种情况后续内容将详细介绍，在此处先不做阐述。
本申请实施例中，第一参考信号和第二参考信号可以是用于定位的参考信号，例如可以是下行的PRS，也可以是上行的探测参考信号(sounding reference signal，SRS)。
S402，第二无线通信装置根据第一参考信号和第二参考信号共同估计参考信号到达时间。
本申请实施例中，“共同估计”也可以理解为“联合估计”等，是指结合第一参考信号和第二参考信号共同确定出参考信号到达时间。
参考信号到达时间能被用于估计第一无线通信设备的位置。具体方案如前图3a所示，定位服务器可以结合多个无线通信装置估计的第一无线通信设备发送的参考信号到达时间，估计第一无线通信装置的位置。其中，每个无线通信装置可以根据第一参考信号和第二参考信号联合估计该参考信号到达时间。
在S401中，第一无线通信装置还可以在多个频段上向第二无线通信装置发送多个信 号，且该多个频段可以与多个信号一一对应。相对应的，S402中，第二无线通信装置可以接收多个信号，并对该接收到的多个信号在时域方向上叠加，从而确定出第三参考信号。多个信号可以是指两个或两个以上的信号。例如，多个频段为三个频段，包括第一频段、第二频段和第四频段。发送端在第一频段上发送第一参考信号，在第二频段上发送第二参考信号，在第四频段上发送第三参考信号。接收端在第一频段上接收第一参考信号，在第二频段上接收第二参考信号，在第四频段上接收第三参考信号，并对第一参考信号、第二参考信号和第三参考信号在时域方向叠加，得到第三参考信号。本申请实施例中为了介绍方便，以第一无线通信装置向第二无线通信装置发送的多个信号包括第一参考信号和第二参考信号为例进行介绍。
由于根据第一参考信号和第二参考信号共同估计参考信号到达时间，相比仅使用第一频段的第一参考信号估计参考信号到达时间的方案，本申请中用于估计参考信号到达时间的参考信号占据的频域范围更大，从而可以提高参考信号到达时间的估计精度。
相比通过发送占据第三频段的参考信号(第三频段包括第一频段和第二频段，且当第一频段和第二频段之间具有间隔的频段时，第三频段还包括第一频段和第二频段之间间隔的频段)进行参考信号到达时间估计的方案，本申请中参考信号到达时间的估计精度与之相当，但本申请可以使无线通信装置的射频通道仅具备支持发送第一频段和第二频段的信号的能力即可，无需要求其必须支持具有发送第三频段的信号的能力，可见，本申请可以提高发送能力较弱的终端设备的定位精度。
且当第一频段和第二频段之间具有间隔的频段时，相比通过发送一个第三频段的参考信号进行参考信号到达时间估计的方案，本申请可以减少无线通信装置发送的信号量，从而可以降低无线通信装置的功耗。
为了进一步提高对第一无线通信装置的定位精度，可以使第一频段和第二频段之间具有间隔频段。由于第一无线通信装置和第二无线通信装置之间的参考信号到达时间的估计精度与第一频段和第二频段之间的间隔频段之间具有正相关关系，因此第一频段和第二频段之间的间隔频段越宽，则参考信号到达时间的估计精度越高，进而对第一无线通信装置的定位也越准确。当然，第一频段和第二频段之间也可以具有重叠的频域资源，或者第一频段和第二频段可以为连续的一个频段。
为了节省第一无线通信装置的功耗，下面以第一无线通信装置为终端设备，第二无线通信装置为网络设备为例，通过图5示例性示出上述图4中S401中第一无线通信装置发送第一参考信号和第二参考信号的方法流程示意图，如图5所示，该方法包括：
S501，终端设备接入网络设备。
当终端设备首次接入网络设备时，可以到鉴权服务器进行鉴权开户，以便完成终端设备和网络设备的双向鉴权，还可以完成加密和完整性保护，终端设备和网络设备均可以生成非接入层(non-access stratum，NAS)加密密钥和完整性保护密钥，后期用于进行定位的信号(定位的信号比如可以包括上述第一参考信号和第二参考信号)可以采用NAS加密传输。
S502，网络设备向终端设备发送配置信息，配置信息包括网络设备为终端设备分配的空闲态(Idle)/非激活态(Inactive)下发送信号的时域资源的信息，并向终端设备发送RRC连接释放消息。
配置信息中的时域资源信息还可以为网络设备为终端设备分配的空闲态(Idle)/非激活态(Inactive)下发送定位信号的时域资源的信息，定位信号可以包括上述第一参考信号和第二参考信号。
其中，时域资源可以定义终端设备进入睡眠后的唤醒周期，即每隔多长时间醒来一次，比如每隔6秒醒来一次。网络设备配置该消息后可以通过RRC连接释放消息释放终端设备的RRC连接。
S503，终端设备进入睡眠。
在S503中也可以说终端设备进入深度睡眠，在深度睡眠下终端设备进入低功耗状态，以便节省终端设备的电量。
S504，终端设备根据网络设备配置的时域资源，在一个唤醒周期对应的唤醒时间到达时，进行唤醒。
S505，终端设备接收来自网络设备的同步信号块(Synchronzation Signal Block，SSB)。
唤醒后的终端设备可以通过S505终端设备可以与网络设备进行时间同步，以消除睡眠期间终端设备的时钟漂移。
S506，终端设备发送第一参考信号，终端设备发送第二参考信号。
进行时间同步后的终端设备可以通过S506发送第一参考信号和第二参考信号，发送之后可以执行上述S503，以便重新进入睡眠，以节省功耗。
针对前述S401和S506，图6示例性示出了本申请实施例提供一种第一无线通信装置发送第一参考信号和第二参考信号的方案的具体示例，如图6所示：
首先，第一无线通信装置生成100MHz带宽对应的长度的SRS信号，也可以理解为，第一无线通信装置在时域方向上生成100MHz带宽的SRS信号。
其次，第一无线通信装置将该SRS信号分为5段，其中令每段SRS信号对应20MHz带宽。
第三，第一无线通信装置从该5段SRS信号中选取第一参考信号和第二参考信号，比如第一无线通信装置可以选取5段中的第一段SRS信号作为第一参考信号，选取5段中的最后一段SRS信号作为第二参考信号。
上述内容仅仅是个示例，也可以分别生成两个20MHz带宽的SRS信号。
第四，第一无线通信装置在第一时刻，以载波频点f1为中心，发送第一参考信号，第一参考信号经过空口传输后，陆续到达临近的3个及以上第二无线通信装置。第一无线通信装置一个波束(比如Sub6G频段)可以覆盖附近多个第二无线通信装置，因而第一无线通信装置一次发送，临近的3个及以上第二无线通信装置可以收到SRS信号。
第一无线通信装置在发送第一参考信号之后，在第二时刻，跳频到(f1+80MHz)，以跳频后的载波为中心发送第二参考信号，第二参考信号经过空口传输后，也陆续到达临近的3个及以上第二无线通信装置。
第一时刻和第二时刻之间可以相隔一个或多个时域符号周期。为了进一步提高对第一无线通信装置的定位精度，第一参考信号和第二参考信号之间间隔的时间可以尽量短一些，比如发送第一参考信号的第一时刻与发送第二参考信号的第二时刻之间可以相隔一个时域符号周期。
通过该示例可以发现，为获得更高的定位精度，第一无线通信装置可一次生成更高带 宽的SRS信号，如(2+N)*20MHz(比如400MHz)，分成多次(比如两次)发送，多次跳频中的两次跳频间的频域间隔可以为n*20MHz(n可以根据实际定位精度需求灵活配置)，且频域可以无交叠，从而可以实现通过多次发送小带宽得参考信号，以构造(2+N)*20MHz大带宽参考信号的目的。由于TOA估计精度与参考信号带宽存在正相关的关系，因此，构造的信号的带宽越宽，第二无线通信装置根据接收到的来自第一无线通信装置的第一参考信号和第二参考信号所估计出的TOA精度越高，进而确定出的传输时延越准确，进而使对第一无线通信装置的定位越准确。
一种可能的实施方式中，本申请实施例中第一参考信号和第二参考信号的相位实质同步。本申请实施例中第一参考信号和第二参考信号的相位实质同步是指第一参考信号和第二参考信号之间的相位同步(相位差为0)或者相位近似同步(相位差小于预设的相位差阈值)，后续内容将对第一参考信号和第二参考信号之间的相位差的具体形式进行举例说明。
为了使第一无线通信装置通过第一射频通道发送的第一参考信号和第二参考信号的相位实质同步，图7中示例性示出了本申请实施例提供的第一无线通信装置的结构示意图，图7的方案可以实现第一参考信号和第二参考信号相位同步。本申请实施例中第一无线通信装置除了第一射频通道之外还可以包括有其他射频通道，比如射频接收通道，或者其他的射频发送通道等等，本申请实施例中不做限制。
图7中第一射频通道与天线70连接，用于将来自基带子系统71的基带信号进行处理(如上变频、放大和滤波)以得到射频信号，并最终通过天线将该射频信号辐射到空间中。
如图7所示，第一射频通道可以包括DAC72、低通滤波器(low pass filter，LPF)73、混频器74(混频器74也可以称为上行混频器)、可变增益放大器77、PA78、带通滤波器(band pass filter，BPF)79。
需要注意的是，图7所示的第一射频通道还可以包括有锁相环(phase locked loop，PLL)75和锁相环76。其中，锁相环75可以称为第一锁相环。其中，锁相环75可以与混频器74选择性连接。锁相环75可以用于产生第一本振信号，第一本振信号的中心频点与第一参考信号的中心频点相同。
锁相环76可以称为第二锁相环。锁相环76可以与混频器74选择性连接。锁相环76可以用于产生第二本振信号，第二本振信号的中心频点与第二参考信号的中心频点相同。
在上述S401中，第一无线通信装置或S506中，第一无线通信装置可以在需要发送第一参考信号的情况下，将锁相环75与混频器74连接，锁相环76与混频器74断开连接，如此，混频器74可以接收来自锁相环75的第一本振信号，进而第一无线通信装置可以根据第一本振信号，在第一频段发送第一参考信号。
在上述S401中，第一无线通信装置或S506中，第一无线通信装置可以在需要发送第二参考信号的情况下，将锁相环76与混频器74连接，锁相环75与混频器74断开连接，如此，混频器74可以接收来自锁相环76的第二本振信号，进而第一无线通信装置可以根据第二本振信号，在第二频段发送第二参考信号。
如图7所示，本申请实施例中，第一射频通道可以具有工作于多个频段的能力。当第一射频通道的工作频段发生变动时，需要对射频发送通道的一个或多个工作参数进行调整，以便使该第一射频通道所工作的频段发生更改。比如，第一射频通道的工作频段在第一频 段和第二频段之间发送变动时，可以对DAC72、低通滤波器73、带通滤波器79等中的至少一项的器件的参数进行调整，以使达到调整第一射频通道的工作频段的目的。
需要说明的是，图7中示出的第一射频通道中包括的器件仅仅是举例，除了第一射频通道包括的混频器74、锁相环76和锁相环75之外，实际应用中可以在第一射频接收通道中添加更多的器件，或者将图中所示一个或多个器件删除。需要说明的是，本申请实施例中图7中锁相环76可以使用第一射频通道的锁相环，而锁相环75可以使用其他射频通道的锁相环，比如可以使用射频接收通道的锁相环，该锁相环可以分时复用，在接收数据时隙用于数据的接收过程，在发送数据时隙用于数据的发送过程。
本申请实施例中，图7中的锁相环75和锁相环76共用同一个参考时钟信号。本申请实施例中，图7中的锁相环75和锁相环76还可以共用同一个第一同步模块，第一同步模块可以向锁相环75和锁相环76分别提供同一个同步信号，为了与其他同步信号区分，可以将该同步信号称为第一同步信号。锁相环75和锁相环76可以均基于第一同步信号调整各自输出的信号与参考时钟信号之间的相位差，从而可以使锁相环75和锁相环76各自输出的信号相位同步，也可以理解为锁相环75和锁相环76可以基于第一同步信号将参考时钟信号的同一个有效沿(可以为上升沿或下降沿)确定为第一有效沿，且锁相环75和锁相环76均基于第一有效沿调整各自输出的信号与参考信号之间的相位差。另外，锁相环75可以用于将第一本振信号和参考时钟信号的相位差调整为预设的第一相位差，预设的第一相位差可以为0或者一个预设的值。而锁相环76可以用于将第二本振信号和参考时钟信号的相位差调整为预设的第一相位差。
图8a示例性示出了本申请实施例提供的一种图7中的锁相环75和锁相环76的结构示意图，如图8a所示，锁相环75和锁相环76共用同一个参考时钟信号，还可以共用同一个第一同步模块。锁相环75用于生成中心频点为第一频点的第一本振信号。锁相环76用于生成中心频点为第二频点的第二本振信号。其中，第一中心频点为第一频段的中心频点，第二中心频点为第二频段的中心频点。
如图8a所示，锁相环75包括依次连接的相位检测器751、电荷泵752、低通滤波器753、振荡器754和分频器756。还包括分频器755。
相位检测器751，用于接收参考时钟信号和分频器755输出的信号，并检测二者的相位关系，生成输出信号，该输出信号指示出参考时钟信号和分频器755输出的信号的相位差。
电荷泵752，用于将相位检测器751输出的相位差转换为电平，经低通滤波器处理后输入至振荡器754，以控制振荡器754输出的振荡信号的频率。
低通滤波器753也可以称为数字环路滤波器(Digital Loop Filter，DLF)，用于对接收到的信号进行滤波，以便输出用于控制震荡器754的频率控制信号。
振荡器754可以为压控振荡器(Voltage-controlled oscillator，VCO)，用于接收来自低通滤波器753的频率控制信号，在该信号的控制下输出振荡信号。
分频器756，用于接收来自震荡器754的震荡信号，并对该振荡信号进行分频，从而得到第一本振信号。分频器756可以与图7中混频器74选择性连接，当分频器756与混频器74处于连接状态时，混频器74可以接收来自分频器756的第一本振信号。当分频器756与混频器74处于断开状态时，混频器74无法接收来自分频器756的第一本振信号。 分频器756也可以称为第一分频器。
分频器755，用于接收分频器756输出的第一本振信号，并对第一本振信号进行分频处理，将分频处理后的信号输入至相位检测器751的输入端。由于分频器755位于反馈环路上，因此分频器755也可以称为反馈分频器。分频器755也可以称为第一反馈分频器。
相位控制模块757，用于调整分频器755的分频比。本申请相位控制模块757可以通过调整分频器755的分频比的方式达到调整第一本振信号和参考时钟信号之间的相位差的目的。
需注意的是，在图8a所示的方案中，相位控制模块757的输入端除了用于接收参考时钟信号以及相位检测器751的输出信号之外，还用于接收来自第一同步模块的信号，结合该三个信号去调整分频器755的分频比。另外，需要补充一下，分频器756和分频器766均位于锁相环的环路内部，因此可以不必要求二者的分频比相同，也可以不同；当二者分频比相同的情况下，可以缩短锁相环75和锁相环76各自的相位调整时间。
如图8a所示，锁相环76包括依次连接的相位检测器761、电荷泵762、低通滤波器763、振荡器764和分频器766。还包括分频器765。
相位检测器761，用于接收参考时钟信号和分频器765输出的信号，并检测二者的相位关系，生成输出信号，该输出信号指示出参考时钟信号和分频器765输出的信号的相位差。
电荷泵762，用于将相位检测器761输出的相位差转换为电平，经低通滤波器处理后输入至振荡器764，以控制振荡器764输出的振荡信号的频率。
低通滤波器763也可以称为数字环路滤波器(Digital Loop Filter，DLF)，用于对接收到的信号进行滤波，以便输出用于控制震荡器764的频率控制信号。
振荡器764可以为压控振荡器(Voltage-controlled oscillator，VCO)，用于接收来自低通滤波器763的频率控制信号，在该信号的控制下输出振荡信号。
分频器766，用于接收来自震荡器764的震荡信号，并对该振荡信号进行分频，从而得到第二本振信号。分频器766可以与图7中混频器74选择性连接，当分频器766与混频器74处于连接状态时，混频器74可以接收来自分频器766的第二本振信号。当分频器766与混频器74处于断开状态时，混频器74无法接收来自分频器766的第二本振信号。分频器756和分频器766可以通过一个开关实现与图7中的混频器74的连接。分频器766也可以称为第二分频器。
分频器765，用于接收分频器766输出的第二本振信号，并对第二本振信号进行分频处理，将分频处理后的信号输入至相位检测器761的输入端。由于分频器765位于反馈环路上，因此分频器765也可以称为反馈分频器。分频器765也可以称为第二反馈分频器。
相位控制模块767，用于调整分频器765的分频比。本申请相位控制模块767可以通过调整分频器765的分频比的方式达到调整第二本振信号和参考时钟信号之间的相位差的目的。
需注意的是，在图8a所示的方案中，相位控制模块767的输入端除了用于接收参考时钟信号以及相位检测器761的输出信号之外，还用于接收来自第一同步模块的信号，结合该三个信号去调整分频器765的分频比。
如图8a所示，第一同步模块可以分别连接相位控制模块757和相位控制模块767。第一同步模块可以用于向第一相位控制模块和第二相位控制模块分别发送第一同步信号。一种可能的实施方式中，当锁相环75锁定后会向第一同步模块输出用于指示锁相环75锁定的信号，类似的，锁相环76锁定后会向第一同步模块输出用于指示锁相环76锁定的信号，第一同步模块可以在第一锁相环和第二锁相环锁定后，发送第一同步信号。
需要说明的是，本申请实施例中锁相环锁定是指锁相环输出的本振信号与输入的参考时钟信号之间频率同步，且二者之间可以维持一个较为固定的相位差。比如，锁相环75锁定是指锁相环75输出的第一本振信号和参考时钟信号之间维持一个较为固定的相位差(比如可以表示为
Figure PCTCN2021109309-appb-000001
)。锁相环76锁定是指锁相环76输出的第二本振信号和参考时钟信号之间维持一个固定的相位差(比如可以表示为
Figure PCTCN2021109309-appb-000002
)。
Figure PCTCN2021109309-appb-000003
和
Figure PCTCN2021109309-appb-000004
可能相同，也可能不同，本申请实施例不做限制。本申请实施例中在锁相环75和锁相环76均锁定之后，再次对两个锁相环输出的本振信号与参考时钟信号之间的相位进行调整，以使第一本振信号和第二本振信号相位同步。
下面结合图8b进行详细介绍，图8b示例性示出了图8a中参考时钟信号、锁定信号和第一同步信号的示意图，如图8b所示，第一同步模块接收参考时钟信号，当第一同步模块在接收到锁相环75的锁定信号和锁相环76的锁定信号之后，可以选择接下来的一个参考时钟信号的下降沿作为第一同步信号的上升沿。需要说明的是，第一同步模块可以在接收到锁相环75的锁定信号和锁相环76的锁定信号之后，可以延迟几个参考时钟信号的周期再选择一个参考时钟信号的下降沿作为第一同步信号的上升沿，由于锁相环锁定之后，锁相环输出的信号与参考时钟信号之间的相位差趋于稳定，若延迟几个参考时钟信号的周期可以使锁相环输出的信号与参考时钟信号之间的相位差进一步趋于稳定。
进一步，第一同步模块选择参考时钟信号的一个下降沿作为第一同步信号的上升沿之后，相位控制模块757和相位控制模块767以接收到的第一同步模块输出的信号的上升沿为基准，均选择该上升沿之后的第一个(或预设的第2个、第3个等等)参考时钟信号的上升沿作为第一有效沿。之后，锁相环75开始以选择的第一有效沿为基准，进行第一本振信号和参考时钟信号的相位调整，直至将第一本振信号和参考时钟信号之间的相位调整为预设的第一相位差。
具体来说，相位控制模块757采集到第一同步模块输出的信号的上升沿后，根据相位检测器751检测到相位差，通过控制参考时钟信号若干个周期内的分频器755的分频比，从而达到改变参考时钟信号若干个周期内的振荡器754的输出频率，进而达到改变输出积分相位，调整相位差的目的，进而达到第一本振信号和第二本振信号相位同步的目的。该过程每次锁相环上电后可以重复执行。
同样的，锁相环76开始以选择的第一有效沿为基准，进行第二本振信号和参考时钟信号的相位调整，直至将第二本振信号和参考时钟信号之间的相位调整为预设的第一相位差。预设的第一相位差可以为0或预设的值。相位控制模块767根据第一同步模块输出的信号调整锁相环76中的分频器765的分频比的过程可以参见上述相位控制模块757的内容，不再赘述。
通过图8b可以看出，当锁相环75和锁相环76锁定之后，均根据第一同步信号选择参考时钟信号的第一有效沿为基准进行相位调整；又由于进行相位调整后，第一本振信号与参考时钟信号的相位差为预设的第一相位差，且第二本振信号与参考时钟信号的相位差 也为预设的第一相位差，因此第一本振信号和第二本振信号相位同步。
图8c示例性示出了图8a中锁相环75输出的信号的频率、相位检测器751检测到的相位差、第一同步模块输出的同步信号的示意图，如图8c所示，锁相环75输出的信号的频率慢慢提高，趋于第一本振信号的第一中心频点的频率。如图8c所示，锁相环输出的第一本振信号和参考时钟信号之间的相位差趋于稳定，当第一本振信号和参考时钟信号之间的相位差趋于稳定可以称锁相环75处于锁定状态，或者称锁相环75锁定。当锁相环接收到来自第一同步模块输出的第一同步信号，则锁相环75开始以基于第一同步信号确定的参考时钟信号的第一有效沿为基准，调整第一本振信号和参考时钟信号的相位差。
需要注意的是，在图8a提供的方案中，分频器756位于锁相环75的环路内部，即分频器755的输入端连接分频器756的输出端。分频器766位于锁相环76的环路内部，即分频器765的输入端连接分频器766的输出端。因此当通过相位控制模块757和相位控制模块767调整各自锁相环的相位时，可以消除分频器756和分频器766之间的随机相位抖动。
相比仅采用一个锁相环先后为混频器提供第一本振信号和第二本振信号的方案，当仅使用一个锁相环时，由于锁相环需要在第一中心频点和第二中心频点之间切换，锁相环会经历锁定、失锁再重锁的过程，而单个锁相环前后两次锁定会引入不确定的相位抖动。而图7和图8a提供的方案中是通过两个锁相环分别提供两个本振信号，可以避免锁相环重锁的过程，从而可以消除锁相环重锁引入的不确定的相位抖动。
又一方面，由于通过两个锁相环的切换即可实现第一射频通道接收到的本振信号的中心频点的切换，相比仅采用一个锁相环先后为混频器提供第一本振信号和第二本振信号的方案，图7和图8a中可以将第一射频通道接收第一本振信号切换至接收第二本振信号的过程缩短，比如可以将该过程缩短至1个符号周期，进而可以缩短第一参考信号的发送时刻和第二参考信号的发送时刻之间间隔的时长，从而可以进一步提高定位的准确性，且由于发送第一参考信号和发送第二参考信号的时间间隔缩短，因此可以减少无线通信装置工作时长，增加其睡眠时长，进而可以减少功耗。
为了说明图7和图8a所提供的方案的有益效果，下面通过一个仿真示例进行展示。可以结合下述公式(1)和公式(2)来看：
Figure PCTCN2021109309-appb-000005
Figure PCTCN2021109309-appb-000006
在上述公式(1)和公式(2)中，N表示锁相环的环路的分频器(比如分频器755和分频器765)的分频系数(也可以称为分频比)；
int表示该分频器的分频系数中的整数部分；
Figure PCTCN2021109309-appb-000007
表示该分频器的分频系数中的分数部分；其中，frac为分子，MOD为分母；
T refclk表示一个周期时长。
通过上述公式(1)和公式(2)可以看出，MOD可以决定锁相环输出的信号与参考时钟信号之间的最小的相位差。以图8a的锁相环75为例进行展示，比如参考时钟信号为38.4MHz，分频器755输出的信号与小数的分母MOD相关，分频器755输出的信号的相位可以覆盖一个周期，相位步进为(一个周期的时长/MOD)。需要说明的是，两个信号之间的相位偏差可以用角度来标识，也可以用两个信号(比如两个时钟信号)的上升沿的间 隔时长来表示两个时钟信号的相位偏差。因此上述公式(2)中也可以说分频器755输出的信号的相位可以覆盖360°，相位步进为(360°/MOD)。
以锁相环75中的MOD占据的比特数量为24bit为例，被允许的锁相环75输出的信号与参考时钟信号之间的最小的相位差为0.005ps。举个例子，MOD取大于2604的值，通过控制锁相环75输出的第一本振信号与参考时钟信号之间的相位差，且通过锁相环76控制第二本振信号与参考时钟信号之间的相位差，则可以达到将第一本振信号和第二本振信号的相位差控制在10皮秒(ps)以内。为了实现更小的相位偏差，可通过配置寄存器增大MOD值来实现。
在实际应用中，1.5G低于6GHz的频段中，N41、N77、N78、N79的带宽是大于100MHz，可以适合用于高精度定位(高带宽)。表1示例性示出了几种可能的仿真结果示意图，下面以表1的第一行数值举例，定位信号带宽(定位信号带宽包括第一频段和第二频段的总带宽，以及第一频段和第二频段之间间隔的频段的带宽)为100M，第一参考信号和第二参考信号被允许的最大相位差(也可以称为相位抖动)为277.7ps，从表1可以看出N41、N77、N78、N79均满足要求。100MHz定位的相位差277.7ps需求是通过如下公式计算的：(一个周期的时长)*10°/360°＝(1/100MHz)*10/360＝277.7ps。
表1 仿真结果示意表
Figure PCTCN2021109309-appb-000008
从表1的几种示例的仿真结果可以看出，当第一参考信号和第二参考信号的相位差小于10度，接近相干。当MOD>2604，将第一参考信号和第二参考信号的相位差控制在4ps以内，可满足小于100MHz带宽定位的相位偏差需求(100MHz带宽定位的相位偏差需求为277.7ps)。其它定位信号带宽内容与之类似，不再赘述。
图9a示例性示出了本申请实施例提供的一种图7中的锁相环75和锁相环76的结构示意图。图9a提供的方案中第一参考信号和第二参考信号的相位近似同步，第一参考信号和第二参考信号之间的相位差等于振荡器754输出的信号与振荡器764输出的信号之间的相位差。第一参考信号和第二参考信号之间的相位差也可以理解为第一本振信号和第二本振信号之间的相位差。需要注意，图9a与图8a不同之处在于：图9a中分频器756位于锁相环75的环路之外，即图9a中分频器755的输入端连接的振荡器754的输出端，并非分频器756的输出端。分频器766位于锁相环76的环路之外，即图9a中分频器765的输入端连接的振荡器764的输出端，并非分频器766的输出端。且图9a去掉了第一同步模块。增加了第二同步模块。图9a中其他各个部件可以参见图8a中的相关描述，在此不再赘述。需要补充说明的是，在图8a中也可以增加第二同步模块，第二同步模块的功能于下述图 9a中的第二同步模块的功能和作用相同。
需要注意的是，图9a中锁相环75和锁相环76仍共用同一个参考时钟信号。但是由于分频器756和分频器766会带来随机相位误差，具体理由如下：
分频比为N的分频器本质上可以理解为一个计数器，计数器累计输入的时钟信号的上升沿(周期数)，当计数器达到N-1时，输出分频后的时钟信号的第一个上升沿。而一个分频器开始计数的第一时钟沿具有不确定性，可能是以接收到的时钟信号的第一个上升沿开始计数，也有可能是以接收到的时钟信号的第二个上升沿开始计数。基于此，分频器756可能以接收到的信号的第一个上升沿开始计数，分频器766可能以接收到的信号的第二个或第三个上升沿开始计数。这种不确定性导致第一本振信号和第二本振信号之间的随机相位误差。
为了解决该分频器756和分频器766带来的随机相位误差，图9a中，可以为分频器756和分频器766提供了一个第二同步模块，用于为二者提供第二同步信号，以使分频器7546和分频器766基于同一个第二同步信号进行分频。分频器756和分频器766的分频比可以相同，从而可以使第一本振信号和第二本振信号的相位差等于振荡器754输出的信号和振荡器764输出的信号之间的相位差。
图9a提供的方案中，通过相位控制模块757调整分频器755的分频比，可以使振荡器754输出的信号与参考时钟信号之间维持一个较为固定的相位差，当振荡器754输出的信号与参考时钟信号之间维持一个较为固定的相位差时可以理解为锁相环75处于锁定状态。同样的，通过相位控制模块767调整分频器765的分频比，可以使振荡器764输出的信号与参考时钟信号之间维持一个较为固定的相位差，当振荡器764输出的信号与参考时钟信号之间维持一个较为固定的相位差时可以理解为锁相环76处于锁定状态。当锁相环75和锁相环76均处于锁定状态后，振荡器754和振荡器764输出的信号之间会存在一个相位差，该相位差可以称为初始相位差。
又由于振荡器754和振荡器764之间的相位差小于振荡器754和振荡器764输出的信号中的一个最小时钟周期，因此，当第一本振信号和第二本振信号的相位差为振荡器754和振荡器764之间的相位差，可以满足100M/200M/300M/400M等带宽对相位变化的需求。
下面结合图9b进行详细介绍，图9b示例性示出了图9a中一种参考时钟信号、锁定信号和第二同步信号、振荡器754输出的信号、振荡器764输出的信号、分频器756输出的信号、分频器766输出的信号的示意图，如图9b所示，第二同步模块接收参考时钟信号，当第二同步模块在接收到锁相环75的锁定信号和锁相环76的锁定信号之后，可以选择接下来的一个参考时钟信号的下降沿作为第二同步信号的上升沿。需要说明的是，第二同步模块可以在接收到锁相环75的锁定信号和锁相环76的锁定信号之后，延迟几个参考时钟信号的周期再选择一个参考时钟信号的下降沿作为第二同步信号的上升沿，由于锁相环锁定之后，锁相环输出的信号与参考时钟信号之间的相位差趋于稳定，若延迟几个参考时钟信号的周期可以使锁相环输出的信号与参考时钟信号之间的相位差进一步趋于稳定。
进一步，第二同步模块选择参考时钟信号的一个下降沿作为第二同步信号的上升沿之后，分频器756以接收到的第二同步模块输出的信号的上升沿为基准，选择在接收到第二同步信号的上升沿之后的振荡器754输出的信号中的第一个上升沿作为进行分频的起始上升沿。
同样的，分频器766以接收到的第二同步模块输出的信号的上升沿为基准，选择在接收到第二同步信号的上升沿之后的振荡器764输出的信号中的第一个上升沿作为进行分频的起始上升沿。
如此，可以保证分频器756和分频器766所选择的起始上升沿之间的相位差为振荡器754和振荡器764之间的相位差(如图9b中所示的初始相位差)。图9b中以分频器756和分频器766均以接收到第二同步信号后以接收到的信号中的第一个上升沿作为起始上升沿，也可以使分频器756和分频器766均以接收到第二同步信号后以接收到的信号中的第二个(也可以是第三个、第四个等等)上升沿作为起始上升沿，只要分频器756和分频器766之间不再因为选择起始上升沿的位置引入第一本振信号和第二本振信号之间的新的相位偏差即可。
下面通过表2和表3展示图9a的方案的仿真结果。表2示例性示出了图9a中关于第一本振信号和第二本振信号之间的最大相位差仿真结果示意表，以第一行数值为例进行展示，频段N41的频段带宽为2496MHz-2690MHz，总带宽为194MHz，以锁相环75为例，假设分频器756为4分频(目前Sub6G频段常见的分频比)的分频器，振荡器754的中心频点为第一本振信号的中心频点的4倍，第一本振信号的中心频点为2593MHz(2496MHz-2690MHz的中心频点)，振荡器754的中心频点为10.372GHz(第一本振信号的中心频点的4倍)第一本振信号和第二本振信号之间的最大相位差为振荡器754输出的时钟信号的一个周期96.4ps。其他行的内容与之类似，在此不再赘述。
表2为图9a中关于第一本振信号和第二本振信号之间的最大相位差仿真结果示意表
Figure PCTCN2021109309-appb-000009
表3示例性示出了几种可能的仿真结果示意图，下面以表3的第一行数值举例，定位信号带宽(定位信号带宽包括第一频段和第二频段的总带宽，以及第一频段和第二频段之间间隔的频段的带宽)为100M，第一参考信号和第二参考信号被允许的最大相位差为277.7ps，N41、N77、N78、N79均满足要求。需要注意的是，400M带宽下，N78频段下可以减低跳频带宽，可以为满足相位需要提供更多保障。
表3 仿真结果示意表
Figure PCTCN2021109309-appb-000010
Figure PCTCN2021109309-appb-000011
图10示例性示出了本申请实施例提供的一种图7中的锁相环75和锁相环76的结构示意图。图10提供的方案可以使第一参考信号和第二参考信号之间相位同步。需要注意，图10与图9a不同之处在于：增加了第一同步模块，第一同步模块连接相位控制模块757和相位控制模块767。
其中，图10第一同步模块与图8a中的第一同步模块功能相同，在此不再赘述。有区别的地方在于相位控制模块757通过调整分频器755的分频比改变的是振荡器754输出的信号与参考时钟信号之间的相位差，而相位控制模块767通过调整分频器765的分频比改变的是振荡器764输出的信号与参考时钟信号之间的相位差。
如图10所示，相位控制模块757和相位控制模块767接收到来自第一同步模块的第一同步信号以后，以该信号为基准，均选择该上升沿之后的第一个(或预设的第2个、第3个等等)参考时钟信号的上升沿作为初始相位。之后，锁相环75开始以选择的初始相位为基准，进行振荡器754输出的信号和参考时钟信号的相位调整，直至将振荡器754输出的信号和参考时钟信号之间的相位调整为预设的第一相位差。
同样的，锁相环76开始以选择的初始相位为基准，进行振荡器764输出的信号和参考时钟信号的相位调整，直至将振荡器764输出的信号和参考时钟信号之间的相位调整为预设的第一相位差。
由于相位控制模块757和相位控制模块767均根据第一同步信号选择参考时钟信号的同一个位置作为初始相位，又由于进行相位调整后，振荡器754输出的信号与参考时钟信号的相位差为预设的第一相位差，且振荡器764输出的信号与参考时钟信号的相位差也为预设的第一相位差，因此振荡器754输出的信号和振荡器764输出的信号相位同步。
又由于图10中为分频器756和分频器766提供了一个第二同步模块，用于为二者提供第二同步信号，以使分频器7546和分频器766基于同一个第二同步信号进行分频，从而使第一本振信号和第二本振信号的相位差为振荡器754和振荡器764之间的相位差，在振荡器754输出的信号和振荡器764输出的信号相位同步的基础上，第一本振信号和第二本振信号相位同步。
图11示例性示出了本申请实施例提供的另外一种第一无线通信装置的结构示意图。图11提供的方案可以使第一参考信号和第二参考信号之间相位同步。图11与图7的不同之处在于，图11中仅包括一个锁相环81。锁相环81可以称为第三锁相环，锁相环81与混频器74耦合，用于在发送第一参考信号的过程中产生第三本振信号，在发送第二参考信号的过程中产生第四本振信号。第三本振信号的中心频点与第一参考信号的中心频点相同；第四本振信号的中心频点与第二参考信号的中心频点相同。也就是说，锁相环81先输出第三本振信号，之后进行频点切换，输出第四本振信号，也可以理解为锁相环81先锁定，锁定后输出第三本振信号，之后失锁，再次锁定，重新锁定后输出第四本振信号。为了使第一参考信号和第二参考信号相位同步，本申请实施例中可以使第三本振信号和第四本振信号相位同步。
图12a示例性示出了一种图11中锁相环81的结构示意图，如图12a所示，锁相环81 包括依次连接的相位检测器811、电荷泵812、低通滤波器813、振荡器814和分频器816。还包括分频器815。分频器816可以称为第三分频器，分频815可以称为第三反馈分频器。相关器件的作用可以参见前述图8a的相关内容，在此不再赘述。
图12a所示的第一无线通信装置的结构示意图中还包括第三同步信号模块。第三同步信号模块的输出端与第三相位控制模块连接，用于第三同步信号。第三同步信号可以是周期性输出的。在第三锁相环用于输出第三本振信号的过程中：在第三锁相环锁定后，第三相位控制模块根据接收到的第三同步信号，确定参考信号的第二有效沿，并以第二有效沿为基准，将第三锁相环输出的第三本振信号与参考时钟信号之间的相位差调整为预设的第二相位差。
在第三锁相环用于输出第四本振信号的过程中：在第三锁相环锁定后，第三相位控制模块根据接收到的第三同步信号，确定第三有效沿，并以第三有效沿为基准，将第三锁相环输出的第四本振信号与参考时钟信号之间的相位差调整为预设的第二相位差。
图12b示例性示出了图12a中参考时钟信号、锁相环81的锁定信号、第三同步模块输出的信号和锁相环81输出的信号的示意图，如图12b所示，第三同步模块周期性输出第三同步信号。第三同步信号的频率为第三本振信号的中心频点的频率和第四本振信号的中心频点的频率的公约数。又一种可能的实施方式中，第三同步信号的频率可以为参考时钟信号的频率、第三本振信号的中心频点的频率和第四本振信号的中心频点的频率的公约数。
在锁相环81第一次锁定后，在相位控制模块817接收到第一个第三同步信号之后所接收到的第一个参考时钟信号的上升沿确定为第二有效沿，之后以第二有效沿为基准，调整锁相环81输出的第三本振信号与参考时钟信号之间的相位差，将其调整为预设的第二相位差。第二相位差可以为0或预设值，当第二相位差为0，可以说锁相环81以第二有效沿为基准，调整锁相环81输出的第三本振信号与参考时钟信号之间的相位差，将其调整为0，以到达第三本振信号与参考时钟信号相位同步的目的。
第一无线通信装置通过第一射频通道发送完毕第一参考信号之后，锁相环处于失锁状态，并第二次锁定，在锁相环81第二次锁定后，在相位控制模块817接收到第一个第三同步信号之后所接收到的第一个参考时钟信号的上升沿确定为第三有效沿，之后以第三有效沿为基准，调整锁相环81输出的第四本振信号与参考时钟信号之间的相位差，将其调整为预设的第二相位差。第二相位差可以为0或预设值，图12b中以第二相位差为0进行示意。当第二相位差为0，可以说锁相环81以第三有效沿为基准，调整锁相环81输出的第四本振信号与参考时钟信号之间的相位差，将其调整为0，以到达第四本振信号与参考时钟信号相位同步的目的。关于相位控制模块817调整锁相环81输出的信号与参考时钟信号之间的相位差的方式可以参见前述图8a中相位控制模块757的相关描述，在此不再赘述。
需要说明的是，图12b仅仅是为了示意，在实际应用中，锁相环81第一次锁定的时长可能包括参考时钟信号的周期，也可能包括第三同步信号的多个周期。第三同步信号的一个周期可能包括参考时钟信号的多个周期。
由于基于第三同步模块周期性向相位控制模块817提供第三同步信号，因此虽然第三本振信号和第四本振信号是前后两次分别锁定后锁相环81输出的信号，但在两次锁定后，锁相环81均是根据第三同步信号进行第三本振信号与参考时钟信号的相位同步，以及第 四本振信号与参考时钟信号的相位同步。又由于第三同步信号的频率为第三本振信号的中心频点的频率和第四本振信号的中心频点的频率的公约数，且由于前述内容已经说明两个信号可以同步到该两个信号的频率的最大公约数的频率的信号，基于此，第三本振信号和第四本振信号相位同步。
又一种可能的实施方式中，进行相位调整后的第三本振信号与第三同步信号之间的相位差，与进行相位调整后的第四本振信号与第三同步信号之间的相位差相等。第三同步信号与参考时钟信号相位同步。又由于第三同步信号的频率为第三本振信号的中心频点的频率和第四本振信号的中心频点的频率的公约数，且由于前述内容已经说明两个信号可以同步到该两个信号的频率的最大公约数的频率的信号，基于此，进行相位调整后的第三本振信号可以与第三同步信号相位同步。进行相位调整后的第四本振信号与第三同步信号相位同步。
图13示例性示出了一种图11中锁相环81的另一种结构示意图，相比图12a的不同之处在于，图13中在第三同步模块和相位控制模块之间增加了第四同步模块，第四同步信号模块在检测到第三锁相环锁定后，将接收到的来自第三同步信号模块的第三同步信号传输至第三相位控制模块。第四同步信号模块在检测到第三锁相环失锁后，停止将接收到的来自第三同步信号模块的第三同步信号传输至第三相位控制模块。如此，可以节省功耗。
需要注意的是，在图12a和图13提供的方案中，分频器816位于锁相环81的环路内部，即分频器815的输入端连接分频器816的输出端。因此当通过相位控制模块817在前后两次相位锁定后基于周期性发送的第三同步信号调整锁相环81的相位时，可以消除分频器816前后两次锁定过程中带来的随机相位抖动。
图14示例性示出了前述图4中S402的一种可能的实现方式，如图14所示，第二无线通信装置将接收到的两个信号在时域方向合成，得到第三参考信号。
下面结合图14对第二无线通信装置侧的方案进行介绍，如图14所示：
第一无线通信装置在第一时刻发送第一参考信号，第一参考信号占用20MHz带宽。第二无线通信装置以100MHz带宽对应的采样率对接收到的信号进行采样，在第三时刻得到y1(t)(其中，y1(t)可以理解为第二无线通信装置接收到的第一参考信号)。
第一无线通信装置在第二时刻发送第二参考信号，第二参考信号占用20MHz带宽。第二无线通信装置以100MHz带宽对应的采样率对接收到的信号进行采样，在第四时刻得到y2(t)(其中，y2(t)可以理解为第二无线通信装置接收到的第二参考信号)。
第二无线通信装置将两次采用得到的信号y1(t)和y2(t)在时域方向叠加，得到第三参考信号y(t)，可以写为：y(t)＝y1(t)+y2(t)。
第二无线通信装置本地生成一个100MHz带宽的SRS序列x(t)，可以只保留该SRS序列x(t)中前20MHz和后20MHz有SRS信号，中间60MHz置0。即保留该SRS序列x(t)中第一频段和第二频段的SRS信号，其余可以置0。
进一步，第二无线通信装置通过以下公式(3)进行互相关运算：
R(τ)＝∑ ky(t)x(t+τ) *……公式(3)
在公式(3)中，y(t)表示y1(t)和y2(t)在时域方向叠加的信号，x(t)表示第二无线通信装置本地生成一个100MHz带宽的SRS序列x(t)，其中，该SRS序列x(t)中除第一频段和 第二频段的SRS信号之外的其余频段的信号可以置0。x(t+τ)表示x(t)的循环移位τ个点之后的序列，*表示取共轭。
由于SRS序列采用ZC序列，有较好的自相关性和低互相关性，当两个序列对齐时会出现尖峰，通过搜索尖峰对应的时刻获得接收信号的到达时间(TOA)。由于用于定位的信号的频域带宽越大，时域脉冲越窄；同时用于定位的信号带宽较高，则第二无线通信装置可以采用较高的采样率对接收到的信号进行采样，进而第二无线通信装置在做序列相关检测时，越容易检测到SRS的首径，得到的TOA越精确，进而对第一无线通信装置的定位精度越高。本申请实施例中可以使仅发送第一参考信号和第二参考信号得到的对第一无线通信装置的定位精度与发送全带宽信号(包括第一频段、第二频段以及第一频段和第二频段之间具有的间隔频段)得到的定位精度相当。本申请实施例中，为进一步提升定位精度，可以在频域中进一步采用MUSIC算法进行精时延估计，以得到高精度的TOA。本申请实施例提供的方案也可以应用于载波聚合(Carrier Aggregation，CA)的定位。本申请实施例提供的相位实质同步技术也可应用到5G CA高精度定位中两个载波的相位实质同步中。
在对第三参考信号进行TOA估计的过程中，比如可以设置阈值，将大于该阈值的第一个峰值点对应时延确定为第一无线通信装置和第二无线通信装置的路径时延。
TOA cor＝arg(|R(τ) peak| first>threshold×R max)……公式(4)
在公式(4)中，R(τ) peak表示公式(3)中的相关序列R(τ)的峰值点；
TOA cor表示第一无线通信装置和第二无线通信装置的路径时延；
|R(τ) peak| first表示公式(3)中的相关序列R(τ)的第一个峰值点；
threshold表示设置的阈值；
R max表示公式(3)中的相关序列R(τ)的最高峰值点；
arg表示对函数求参数的函数；
公式(4)表示即第一个大于阈值的峰值点对应的时延即为第一无线通信装置到第二无线通信装置的路径时延，TOA cor＝τ Cor。
为了进一步展示本申请实施的有益效果，下面提供一个仿真场景进行展示，考虑到工厂对定位精度要求高，同时基站(基站可以为前述第二无线通信装置)的间距越大，定位精度越低，因此InF-SH(室内工厂，站间距疏，50m站间距)场景用于仿真本申请实施例提供的方案的定位精度。
图15示例性示出了本申请实施例提供的一种仿真环境的示意图，表4中示例性示出了一种系统参数的示意表。下面结合图15和表4对仿真参数进行介绍：
基站个数：18个(选择其中7个参与定位)；
工厂尺寸：长300米，宽150米，高10米；
基站高度：8米；
UE高度：1.5米；
基站天线配置：(4，4，2，1，1)；
UE天线配置：(1，2，2，1，1)。
表4 中示例性示出了一种系统参数的示意表。
Figure PCTCN2021109309-appb-000012
表5 仿真结果示意表
Figure PCTCN2021109309-appb-000013
Figure PCTCN2021109309-appb-000014
比如表5中仿真场景3和仿真场景6中，仿真场景3通过两次跳频发送构造400MHz带宽的定位精度达到0.035m CEP 90％@LOS,与仿真场景6通过发送完整的400MHz带宽的信号的定位精度(0.018m)相当，都达到了厘米级定位精度，但本申请实施例中第一无线通信装置仅发送两个窄带宽信号即可，从而可以提高低性能的无线通信装置的定位精度，且可以降低无线通信装置的功耗。
可以理解的是，为了实现上述实施例中功能，第一无线通信装置和第二无线通信装置包括了执行各个功能相应的硬件结构和/或软件模块。本领域技术人员应该很容易意识到，结合本申请中所公开的实施例描述的各示例的单元及方法步骤，本申请能够以硬件或硬件和计算机软件相结合的形式来实现。某个功能究竟以硬件还是计算机软件驱动硬件的方式来执行，取决于技术方案的特定应用场景和设计约束条件。
图16、图17和图18为本申请的实施例提供的可能的通信装置的结构示意图。这些通信装置可以用于实现上述方法实施例中第一无线通信装置或第二无线通信装置的功能，因此也能实现上述方法实施例所具备的有益效果。在本申请的实施例中，该通信装置可以是如图1所示的第一无线通信装置，也可以是如图1所示的第二无线通信装置，还可以是应用于第一无线通信装置或第二无线通信装置的模块(如芯片)。
如图16所示，通信装置1300包括处理单元1310和收发单元1320。通信装置1300用于实现上述图4或图5中所示的方法实施例中第一无线通信装置或第二无线通信装置的功能。
当通信装置1300用于实现图4或图5所示的方法实施例中第一无线通信装置的功能时：处理单元1310用于通过收发单元1320执行：在第一频段发送第一参考信号，在第二频段发送第二参考信号。其中，第一参考信号的发送时间与第二参考信号的发送时间不同，第一频段的中心频点与第二频段的中心频点不同；其中，第一参考信号和第二参考信号相位实质同步，第一参考信号和第二参考信号能被用于共同估计参考信号到达时间。
当通信装置1300用于实现图4或图5所示的方法实施例中第二无线通信装置的功能时：处理单元1310用于通过收发单元1320执行：接收第一参考信号，第一参考信号为第一频段的信号。接收第二参考信号；第二参考信号为第二频段的信号。其中，第一参考信号的发送时间与第二参考信号的发送时间不同，第一频段的中心频点与第二频段的中心频点不同；其中，第一参考信号和第二参考信号相位实质同步。根据第一参考信号和第二参考信号共同估计参考信号到达时间。
有关上述处理单元1310和收发单元1320更详细的描述可以直接参考图4所示的方法实施例中相关描述直接得到，这里不加赘述。
如图17所示，通信装置1400包括处理电路1410和接口电路1420。处理电路1410和接口电路1420之间相互耦合。可以理解的是，接口电路1420可以为收发器或输入输出接口。可选的，通信装置1400还可以包括存储器，用于存储处理电路执行的指令或存储处理电路1410运行指令所需要的输入数据或存储处理电路1410运行指令后产生的数据。
当通信装置1400用于实现图4或图5所示的方法时，处理电路1410用于实现上述处理单元1310的功能，接口电路1420用于实现上述收发单元1320的功能。
如图18所示，通信装置1500包括处理器1510和通信接口1520。处理器1510和通信接口1520之间相互耦合。可以理解的是，通信接口1520可以为收发器或输入输出接口。可选的，通信装置1500还可以包括存储器1530，用于存储处理器1510执行的指令或存储处理器1510运行指令所需要的输入数据或存储处理器1510运行指令后产生的数据。
当通信装置1500用于实现图4或图5所示的方法时，处理器1510用于实现上述处理单元1310的功能，通信接口1520用于实现上述收发单元1320的功能。
当通信装置1500用于实现图4或图5所示的方法实施例中第一无线通信装置的功能时：处理器1510用于通过通信接口1520执行：在第一频段发送第一参考信号，在第二频段发送第二参考信号。其中，第一参考信号的发送时间与第二参考信号的发送时间不同，第一频段的中心频点与第二频段的中心频点不同；其中，第一参考信号和第二参考信号相位实质同步，第一参考信号和第二参考信号能被用于共同估计参考信号到达时间。
当通信装置1500用于实现图4或图5所示的方法实施例中第二无线通信装置的功能时：处理器1510用于通过通信接口1520执行：接收第一参考信号，第一参考信号为第一频段的信号；接收第二参考信号；第二参考信号为第二频段的信号；其中，第一参考信号的发送时间与第二参考信号的发送时间不同，第一频段的中心频点与第二频段的中心频点不同；其中，第一参考信号和第二参考信号相位实质同步；根据第一参考信号和第二参考信号共同估计参考信号到达时间。
当上述通信装置为应用于第一无线通信装置的芯片时，该第一无线通信装置芯片实现上述方法实施例中第一无线通信装置的功能。该第一无线通信装置芯片从第一无线通信装置中的其它模块(如射频模块或天线)接收信息，该信息是第二无线通信装置发送给第一无线通信装置的；或者，该第一无线通信装置芯片向第一无线通信装置中的其它模块(如射频模块或天线)发送信息，该信息是第一无线通信装置发送给第二无线通信装置的。
当上述通信装置为应用于第二无线通信装置的模块时，该第二无线通信装置模块实现上述方法实施例中第二无线通信装置的功能。该第二无线通信装置模块从第二无线通信装置中的其它模块(如射频模块或天线)接收信息，该信息是第一无线通信装置发送给第二无线通信装置的；或者，该第二无线通信装置模块向第二无线通信装置中的其它模块(如射频模块或天线)发送信息，该信息是第二无线通信装置发送给第一无线通信装置的。这里的第二无线通信装置模块可以是第二无线通信装置的基带芯片，也可以是DU或其他模块，这里的DU可以是开放式无线接入网(open radio access network，O-RAN)架构下的DU。
可以理解的是，本申请的实施例中的处理器可以是中央处理单元(Central Processing Unit，CPU)，还可以是其它通用处理器、数字信号处理器(Digital Signal Processor，DSP)、专用集成电路(Application Specific Integrated Circuit，ASIC)、现场可编程门阵列(Field Programmable Gate Array，FPGA)或者其它可编程逻辑器件、晶体管逻辑器件，硬件部件或者其任意组合。通用处理器可以是微处理器，也可以是任何常规的处理器。
根据本申请实施例提供的方法，本申请还提供一种计算机程序产品，该计算机程序产品包括：计算机程序代码或指令，当该计算机程序代码或指令在计算机上运行时，使得该计算机执行图4和图5所示实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种计算机可读存储介质，该计算机可读介质存储有程序代码，当该程序代码在计算机上运行时，使得该计算机执行图4和图5 所示实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种芯片系统，该芯片系统可以包括处理器。该处理器与存储器耦合，可用于执行图4和图5所示实施例中任意一个实施例的方法。可选地，该芯片系统还包括存储器。存储器，用于存储计算机程序(也可以称为代码，或指令)。处理器，用于从存储器调用并运行计算机程序，使得安装有芯片系统的设备执行图4和图5所示实施例中任意一个实施例的方法。
根据本申请实施例提供的方法，本申请还提供一种系统，其包括前述的第一无线通信装置和一个或多个第二无线通信装置。
本申请的实施例中的方法步骤可以通过硬件的方式来实现，也可以由处理器执行软件指令的方式来实现。软件指令可以由相应的软件模块组成，软件模块可以被存放于随机存取存储器、闪存、只读存储器、可编程只读存储器、可擦除可编程只读存储器、电可擦除可编程只读存储器、寄存器、硬盘、移动硬盘、CD-ROM或者本领域熟知的任何其它形式的存储介质中。一种示例性的存储介质耦合至处理器，从而使处理器能够从该存储介质读取信息，且可向该存储介质写入信息。当然，存储介质也可以是处理器的组成部分。处理器和存储介质可以位于ASIC中。另外，该ASIC可以位于第一无线通信装置或第二无线通信装置中。当然，处理器和存储介质也可以作为分立组件存在于第一无线通信装置或第二无线通信装置中。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机程序或指令。在计算机上加载和执行计算机程序或指令时，全部或部分地执行本申请实施例的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、网络设备、用户设备或者其它可编程装置。计算机程序或指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机程序或指令可以从一个网站站点、计算机、服务器或数据中心通过有线或无线方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是集成一个或多个可用介质的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，例如，软盘、硬盘、磁带；也可以是光介质，例如，数字视频光盘；还可以是半导体介质，例如，固态硬盘。该计算机可读存储介质可以是易失性或非易失性存储介质，或可包括易失性和非易失性两种类型的存储介质。
需要指出的是，本专利申请文件的一部分包含受著作权保护的内容。除了对专利局的专利文件或记录的专利文档内容制作副本以外，著作权人保留著作权。
在本申请的各个实施例中，如果没有特殊说明以及逻辑冲突，不同的实施例之间的术语和/或描述具有一致性、且可以相互引用，不同的实施例中的技术特征根据其内在的逻辑关系可以组合形成新的实施例。
本申请中，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A,B可以是单数或者复数。在本申请的文字描述中，字符“/”，一般表示前后关联对象是一种“或”的关系；在本申请的公式中，字符“/”，表示前后关联对象是一种“相除”的关系。“包括A，B和C中的至少一个”可以表示：包括A；包括B；包括C；包括A和B；包括A和C；包括B和C；包括A、B和C。
可以理解的是，在本申请的实施例中涉及的各种数字编号仅为描述方便进行的区分，并不用来限制本申请的实施例的范围。上述各过程的序号的大小并不意味着执行顺序的先后，各过程的执行顺序应以其功能和内在逻辑确定。

Claims (29)

  1. 一种无线通信装置，其特征在于，包括处理电路，以及与所述处理电路耦合的接口电路，其中，所述处理电路用于通过所述接口电路：
    在第一频段发送第一参考信号，在第二频段发送第二参考信号；
    其中，所述第一参考信号的发送时间与所述第二参考信号的发送时间不同，所述第一频段的中心频点与所述第二频段的中心频点不同；其中，所述第一参考信号和所述第二参考信号相位实质同步，所述第一参考信号和所述第二参考信号能被用于共同估计参考信号到达时间。
  2. 如权利要求1所述的无线通信装置，其特征在于，还包括第一锁相环和第二锁相环；
    所述第一锁相环用于产生第一本振信号，所述第一本振信号的中心频点与所述第一参考信号的中心频点相同；
    所述第二锁相环用于产生第二本振信号，所述第二本振信号的中心频点与所述第二参考信号的中心频点相同。
  3. 如权利要求1或2所述的无线通信装置，其特征在于，所述第一锁相环和所述第二锁相环使用的参考时钟信号相同。
  4. 如权利要求2或3所述的无线通信装置，其特征在于，所述处理电路，还用于通过所述接口电路：向所述第一锁相环和所述第二锁相环分别输出第一同步信号；
    所述第一锁相环，还用于：根据所述第一同步信号调整所述第一本振信号和参考时钟信号的相位差；
    所述第二锁相环，还用于：根据所述第一同步信号调整所述第二本振信号和所述参考时钟信号的相位差。
  5. 如权利要求4所述的无线通信装置，其特征在于，所述第一锁相环，具体用于：
    根据所述第一同步信号，确定所述参考时钟信号的第一有效沿，并以所述第一有效沿为基准，调整所述第一本振信号和所述参考时钟信号的相位差；
    所述第二锁相环，具体用于：
    根据所述第一同步信号，确定所述第一有效沿，并以所述第一有效沿为基准，调整所述第二本振信号和所述参考时钟信号的相位差。
  6. 如权利要求5所述的无线通信装置，其特征在于，所述第一锁相环，具体用于：
    根据所述第一同步信号，确定所述参考时钟信号的第一有效沿，并以所述第一有效沿为基准，根据所述第一锁相环的第一反馈分频器对第一锁相环的第一分频器输出的所述第一本振信号进行分频后的信号，调整所述第一本振信号和所述参考时钟信号的相位差；
    所述第二锁相环，具体用于：
    根据所述第一同步信号，确定所述第一有效沿，并以所述第一有效沿为基准，根据所述第二锁相环的第二反馈分频器对第二锁相环的第二分频器输出的所述第二本振信号进行分频后的信号，调整所述第二本振信号和所述参考时钟信号的相位差。
  7. 如权利要求2-6任一项所述的无线通信装置，其特征在于，所述第一本振信号与所述参考时钟信号之间的相位差，与所述第二本振信号与所述参考时钟之间的相位差相等。
  8. 如权利要求2-7任一项所述的无线通信装置，其特征在于，所述第一锁相环包括第一分频器和第一反馈分频器；所述第一反馈分频器的输入端连接所述第一分频器的输出端；
    所述第二锁相环包括第二分频器和第二反馈分频器；所述第二反馈分频器的输入端连接所述第二分频器的输出端。
  9. 如权利要求2-8任一项所述的无线通信装置，其特征在于，所述处理电路，还用于通过所述接口电路：向所述第一锁相环和所述第二锁相环分别发送第二同步信号；
    所述第一锁相环，还用于根据所述第二同步信号进行信号的分频处理；
    所述第二锁相环，还用于根据所述第二同步信号进行信号的分频处理。
  10. 如权利要求1所述的无线通信装置，其特征在于，还包括第三锁相环；
    所述处理电路，还用于通过所述接口电路：向所述第三锁相环输出第三同步信号；
    所述第三锁相环，用于：
    生成第三本振信号，根据所述第三同步信号，调整所述第三本振信号与参考时钟信号之间的相位差；所述第三本振信号的中心频点与所述第一参考信号的中心频点相同；
    生成第四本振信号，根据所述第三同步信号，调整所述第四本振信号与所述参考时钟信号之间的相位差；所述第四本振信号的中心频点与所述第二参考信号的中心频点相同；
    其中，所述第三同步信号的频率为所述第三本振信号的中心频点的频率和所述第四本振信号的中心频点的频率的公约数。
  11. 如权利要求1-10任一项所述的无线通信装置，其特征在于，所述处理电路，具体用于通过所述接口电路：
    进入睡眠；
    在唤醒时间到达时，进行唤醒；
    在第一频段发送第一参考信号，在第二频段发送第二参考信号；
    再次进入睡眠。
  12. 一种无线通信装置，其特征在于，包括处理电路，以及与所述处理电路耦合的接口电路，其中，所述处理电路用于通过所述接口电路：
    接收第一参考信号，所述第一参考信号为第一频段的信号；
    接收第二参考信号；所述第二参考信号为第二频段的信号；其中，所述第一参考信号的发送时间与所述第二参考信号的发送时间不同，所述第一频段的中心频点与所述第二频段的中心频点不同；其中，所述第一参考信号和所述第二参考信号相位实质同步；
    根据所述第一参考信号和所述第二参考信号共同估计参考信号到达时间。
  13. 如权利要求12所述的无线通信装置，其特征在于，所述处理电路，具体用于：
    将所述第一参考信号和所述第二参考信号在时域方向叠加，得到第三参考信号；
    根据所述第三参考信号估计参考信号到达时间。
  14. 一种参考信号到达时间估计方法，其特征在于，包括：
    在第一频段发送第一参考信号，在第二频段发送第二参考信号；
    其中，所述第一参考信号的发送时间与所述第二参考信号的发送时间不同，所述第一频段的中心频点与所述第二频段的中心频点不同；其中，所述第一参考信号和所述第二参考信号相位实质同步，所述第一参考信号和所述第二参考信号能被用于共同估计参考信号到达时间。
  15. 如权利要求14所述的方法，其特征在于，所述方法还包括：
    通过第一锁相环产生第一本振信号，所述第一本振信号的中心频点与所述第一参考信号的中心频点相同；
    通过第二锁相环产生第二本振信号，所述第二本振信号的中心频点与所述第二参考信号的中心频点相同。
  16. 如权利要求15所述的方法，其特征在于，所述第一锁相环和所述第二锁相环使用的参考时钟信号相同。
  17. 如权利要求15或16所述的方法，其特征在于，所述方法，还包括：
    向所述第一锁相环和所述第二锁相环分别输出第一同步信号；
    根据所述第一同步信号调整所述第一锁相环输出的所述第一本振信号和参考时钟信号的相位差；
    根据所述第一同步信号调整所述第二锁相环输出的所述第二本振信号和所述参考时钟信号的相位差。
  18. 如权利要求17所述的方法，其特征在于，所述根据所述第一同步信号调整所述第一锁相环输出的所述第一本振信号和参考时钟信号的相位差，包括：
    根据所述第一同步信号，确定所述参考时钟信号的第一有效沿，并以所述第一有效沿为基准，调整所述第一本振信号和所述参考时钟信号的相位差；
    所述根据所述第一同步信号调整所述第二锁相环输出的所述第二本振信号和所述参考时钟信号的相位差，包括：
    根据所述第一同步信号，确定所述第一有效沿，并以所述第一有效沿为基准，调整所述第二本振信号和所述参考时钟信号的相位差。
  19. 如权利要求18所述的方法，其特征在于，所述根据所述第一同步信号调整所述第一锁相环输出的所述第一本振信号和参考时钟信号的相位差，包括：
    根据所述第一同步信号，确定所述参考时钟信号的第一有效沿，并以所述第一有效沿为基准，根据所述第一锁相环的第一反馈分频器对第一锁相环的第一分频器输出的所述第一本振信号进行分频后的信号，调整所述第一本振信号和所述参考时钟信号的相位差；
    所述根据所述第一同步信号调整所述第二锁相环输出的所述第二本振信号和所述参考时钟信号的相位差，包括：
    根据所述第一同步信号，确定所述第一有效沿，并以所述第一有效沿为基准，根据所述第二锁相环的第二反馈分频器对第二锁相环的第二分频器输出的所述第二本振信号进行分频后的信号，调整所述第二本振信号和所述参考时钟信号的相位差。
  20. 如权利要求15-19任一项所述的方法，其特征在于，所述第一本振信号与所述参考时钟信号之间的相位差，与所述第二本振信号与所述参考时钟之间的相位差相等。
  21. 如权利要求15-20任一项所述的方法，其特征在于，所述方法，还包括：
    向所述第一锁相环和所述第二锁相环分别发送第二同步信号；
    根据所述第二同步信号对所述第一锁相环的第一分频器输入的信号进行分频处理；
    根据所述第二同步信号对所述第二锁相环的第二分频器输入的信号进行分频处理。
  22. 如权利要求14所述的方法，其特征在于，所述方法，还包括：
    向第三锁相环输出第三同步信号；
    生成第三本振信号，根据所述第三同步信号，调整所述第三本振信号与参考时钟信号之间的相位差；所述第三本振信号的中心频点与所述第一参考信号的中心频点相同；
    生成第四本振信号，根据所述第三同步信号，调整所述第四本振信号与所述参考时钟信号之间的相位差；所述第四本振信号的中心频点与所述第二参考信号的中心频点相同；
    其中，所述第三同步信号的频率为所述第三本振信号的中心频点的频率和所述第四本振信号的中心频点的频率的公约数。
  23. 如权利要求14-22任一项所述的方法，其特征在于，所述在第一频段发送第一参考信号，在第二频段发送第二参考信号之前，还包括：
    进入睡眠；
    在唤醒时间到达时，进行唤醒；
    所述在第一频段发送第一参考信号，在第二频段发送第二参考信号之后，还包括：
    再次进入睡眠。
  24. 一种参考信号到达时间估计方法，其特征在于，包括：
    接收第一参考信号，所述第一参考信号为第一频段的信号；
    接收第二参考信号；所述第二参考信号为第二频段的信号；其中，所述第一参考信号的发送时间与所述第二参考信号的发送时间不同，所述第一频段的中心频点与所述第二频段的中心频点不同；其中，所述第一参考信号和所述第二参考信号相位实质同步；
    根据所述第一参考信号和所述第二参考信号共同估计参考信号到达时间。
  25. 如权利要求24所述的方法，其特征在于，所述根据所述第一参考信号和所述第二参考信号共同估计参考信号到达时间，包括：
    将所述第一参考信号和所述第二参考信号在时域方向叠加，得到第三参考信号；
    根据所述第三参考信号估计参考信号到达时间。
  26. 一种通信装置，其特征在于，所述装置包括处理器和存储器，
    所述存储器，用于存储可执行程序；
    所述处理器，用于执行存储器中的计算机可执行程序，使得权利要求14-25中任一项所述的方法被执行。
  27. 一种通信装置，其特征在于，所述装置包括处理器和通信接口，
    所述通信接口，用于输入和/或输出信息；
    所述处理器，用于执行计算机可执行程序，使得权利要求14-25中任一项所述的方法被执行。
  28. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机可执行程序，所述计算机可执行程序在被计算机调用时，使所述计算机执行如权利要求14-25任一项所述的方法。
  29. 一种芯片系统，其特征在于，包括：
    所述通信接口，用于输入和/或输出信息；
    处理器，用于执行计算机可执行程序，使得安装有所述芯片系统的设备执行如权利要求14-25任一项所述的方法。
PCT/CN2021/109309 2021-07-29 2021-07-29 一种参考信号到达时间估计方法、装置及芯片 WO2023004694A1 (zh)

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CN109842934A (zh) * 2017-11-24 2019-06-04 北京三星通信技术研究有限公司 用户设备ue的定位方法、定位装置及用户设备
US20210132177A1 (en) * 2019-11-04 2021-05-06 Arizona Board Of Regents On Behalf Of Arizona State University Position information estimation in a distributed radio frequency (rf) communications system

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Publication number Priority date Publication date Assignee Title
US20080186231A1 (en) * 2007-02-05 2008-08-07 Daniel Aljadeff Dual bandwidth time difference of arrival (tdoa) system
CN106922219A (zh) * 2014-08-01 2017-07-04 波尔特公司 针对使用rf的位置寻找的部分同步多边测量/三边测量方法和系统
CN109842934A (zh) * 2017-11-24 2019-06-04 北京三星通信技术研究有限公司 用户设备ue的定位方法、定位装置及用户设备
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