WO2023000832A1

WO2023000832A1 - Display module and display apparatus

Info

Publication number: WO2023000832A1
Application number: PCT/CN2022/096188
Authority: WO
Inventors: 刘长瑜
Original assignee: Oppo广东移动通信有限公司
Priority date: 2021-07-19
Filing date: 2022-05-31
Publication date: 2023-01-26
Also published as: CN113506539A; CN113506539B; CN115273744A

Abstract

A display module, comprising: a pixel circuit array (100) comprising a first sub-array (110), the first sub-array (110) comprising a plurality of first pixel sub-circuits and a plurality of first isolation sub-structures; a plurality of driving wires; and a light-emitting device array (200) comprising a plurality of light-emitting devices, the plurality of light-emitting devices being respectively electrically connected to the plurality of driving wires in one-to-one correspondence, the plurality of driving wires being respectively electrically connected to the plurality of the first pixel sub-circuits in one-to-one correspondence, such that the plurality of the light-emitting devices are electrically conductive with the plurality of the first pixel sub-circuits in one-to-one correspondence, the size of the light-emitting device array (200) in a first direction being greater than the size of the pixel circuit array (100) in the first direction, and the first direction being perpendicular to the thickness direction of the display module, wherein each of the first isolation sub-structures is respectively located between two adjacent first pixel sub-circuits in the first direction, so that the length difference between the driving wires corresponding to the light-emitting devices of the same color is within a first preset range.

Description

Display modules and display devices

Cross References to Related Applications

This application claims the priority of the Chinese patent application with the application number 2021108133711 and the title of the invention "Display Module and Display Device" filed with the China Patent Office on July 19, 2021, the entire contents of which are incorporated herein by reference.

technical field

The present application relates to the field of display technology, in particular to a display module and a display device.

Background technique

The statements herein merely provide background information related to the present application and do not necessarily constitute exemplary techniques.

With the continuous development of science and technology, people have higher and higher requirements for the appearance of display devices. Full screens have been popularized in the market. It is particularly important to reduce the frame of the display screen and increase the screen ratio. The display area of the display screen is composed of a pixel driving circuit and a display light-emitting device. When realizing a display device with a narrow frame, it is usually necessary to adjust the arrangement of at least one of the pixel drive circuit and the display light-emitting device, but the above-mentioned adjustment will greatly The display uniformity of the display device is affected, and the display quality is reduced.

Contents of the invention

According to various embodiments of the present application, a display module and a display device are provided.

A display module, comprising:

A pixel circuit array comprising a first sub-array comprising a plurality of first pixel sub-circuits and a plurality of first isolation sub-structures;

Multiple drive traces; and

The array of light-emitting devices includes a plurality of light-emitting devices, and the plurality of light-emitting devices are electrically connected to the plurality of driving wires in one-to-one correspondence, and the plurality of driving wires are respectively connected to the plurality of first pixel sub-circuits. One-to-one electrical connection, so that the plurality of light-emitting devices and the plurality of first pixel sub-circuits are electrically connected in one-to-one correspondence, and the size of the light-emitting device array in the first direction is larger than that of the pixels. The size of the circuit array in the first direction, the first direction is perpendicular to the thickness direction of the display module;

Wherein, each of the first isolation substructures is located between two adjacent first pixel subcircuits in the first direction, so that the length difference of the driving wires corresponding to the light emitting devices of the same color is between within the first preset range.

A display device, comprising: the above-mentioned display module.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects and advantages of the present application will be apparent from the description, drawings and claims.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments or exemplary technologies of the present application, the following will briefly introduce the accompanying drawings that need to be used in the descriptions of the embodiments or exemplary technologies. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present application. Those skilled in the art can also obtain the drawings of other embodiments according to these drawings without creative work.

FIG. 1 is one of the structural schematic diagrams of a display module of an embodiment;

FIG. 2 is one of the structural schematic diagrams of a pixel circuit array according to an embodiment;

Fig. 3 is a schematic structural diagram of a light emitting device array according to an embodiment;

4 is a schematic structural diagram of a display module without a first isolation structure;

FIG. 5 is the second structural schematic diagram of a pixel circuit array in an embodiment;

FIG. 6 is a second structural schematic diagram of a display module of an embodiment;

Fig. 7 is a schematic structural diagram of a first repeating unit and a corresponding light-emitting device in an embodiment;

FIG. 8 is one of the circuit diagrams of the first pixel sub-circuit of an embodiment;

FIG. 9 is a schematic diagram of the position of the gate drive circuit of an embodiment;

FIG. 10 is a third structural schematic diagram of a display module of an embodiment;

FIG. 11 is a schematic top view of the positions of the first grid sub-circuit and the second grid sub-circuit according to an embodiment;

Fig. 12 is a schematic cross-sectional view of the positions of the first gate sub-circuit and the second gate sub-circuit according to an embodiment;

FIG. 13 is a schematic cross-sectional view of a driving circuit of an LTPS structure according to an embodiment;

FIG. 14 is a schematic cross-sectional view of a driving circuit of an LTPO structure according to an embodiment;

FIG. 15 is the second circuit diagram of the first pixel sub-circuit in an embodiment;

FIG. 16 is a fourth structural schematic diagram of a display module of an embodiment;

FIG. 17 is a third schematic structural diagram of a pixel circuit array in an embodiment;

FIG. 18 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 17;

FIG. 19 is a fourth structural schematic diagram of a pixel circuit array in an embodiment;

FIG. 20 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 19;

FIG. 21 is a fifth structural schematic diagram of a pixel circuit array in an embodiment;

FIG. 22 is a schematic structural diagram of a display module formed based on the pixel circuit array of the embodiment in FIG. 21;

Fig. 23 is a schematic diagram of the position of the light emitting device and the gate driving circuit in the display module of an embodiment;

Fig. 24 is a partial schematic diagram of the connection relationship between the light emitting device and the first pixel sub-circuit in the embodiment of Fig. 23;

25 is a schematic cross-sectional view of a display module according to an embodiment;

FIG. 26 is a schematic top view of the position of the fan-out wiring group according to an embodiment;

Fig. 27 is a schematic diagram of the position of a light emitting device array according to an embodiment.

Component label description:

Pixel circuit array: 100; first sub-array: 110; first pixel circuit: 111; first gate: 1101; first source: 1102; first drain: 1103; source contact structure: 1104; drain Contact structure: 1105; anode: 1107; second active layer: 1108; second gate insulating layer: 1109; second gate: 1110; light-shielding layer: 1111; substrate layer: 1112; first buffer layer: 1113; A gate insulating layer: 1114; an interlayer insulating layer: 1115; a planarization layer: 1116; a first isolation structure: 101; a second pixel circuit: 112; a first repeating unit: 113; a second sub-array: 120; Subarray: 130; third pixel circuit: 131; fourth subarray: 140; fourth pixel circuit: 141; anode reset unit: 1511; gate reset unit: 1512; data writing unit: 1513; threshold compensation unit: 1514; light emitting control unit: 1515; light emitting device array: 200; light emitting repeating unit: 210; repeating subunit: 2101; virtual quadrilateral: 2102; light emitting device: 201; gate driving circuit: 300; The first gate sub-circuit: 311; the second gate sub-circuit: 312; the second driving unit: 320; the gate line: 400; the fan-out wiring group: 500; the virtual plane: 600.

detailed description

In order to facilitate understanding of the embodiments of the present application, the following will describe the embodiments of the present application more comprehensively with reference to related drawings. A preferred embodiment of the embodiments of the application is given in the accompanying drawings. However, the embodiments of the present application can be implemented in many different forms, and are not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the embodiments of the present application more thorough and comprehensive.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field of the embodiments of this application. The terms used herein in the description of the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

In the description of the embodiments of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper", "lower", "vertical", "horizontal", "inner" and "outer" are based on the drawings The method or positional relationship shown is only for the convenience of describing the embodiment of the present application and simplifying the description, and does not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as Limitations on the embodiments of this application.

It can be understood that the terms "first", "second" and the like used in this application may be used to describe various elements herein, but these elements are not limited by these terms. These terms are only used to distinguish one element from another element. For example, a first direction could be termed a second direction, and, similarly, a second direction could be termed a first direction, without departing from the scope of the present application. Both the first direction and the second direction are directions, but they are not the same direction.

In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be interpreted as indicating or implying relative importance or implicitly specifying the quantity of indicated technical features. Thus, the features defined as "first" and "second" may explicitly or implicitly include at least one of these features. In the description of the present application, "plurality" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present application, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

FIG. 1 is one of the structural schematic diagrams of a display module according to an embodiment. The display module according to the embodiment of the present application is applied to a display device with a narrow frame. The display device may be a smart phone, a tablet computer, a game device, an augmented reality (Augmented Reality, AR) device, a notebook, a desktop computing device, a wearable device, and the like. For the convenience of understanding, the following uses the mobile phone as an example for illustration. Referring to FIG. 1 , the display module of the present embodiment includes a pixel circuit array, a light emitting device array and a plurality of driving wires L. Referring to FIG. Specifically, FIG. 2 is one of the schematic structural diagrams of a pixel circuit array 100 according to an embodiment, and FIG. 3 is a schematic structural diagram of a light emitting device array 200 according to an embodiment. The pixel circuit array 100 and the light emitting device array 200 are stacked in the thickness direction. to form a display module. Wherein, the size of the light emitting device array 200 in the first direction is larger than the size of the pixel circuit array 100 in the first direction.

Referring to FIG. 2, the pixel circuit array 100 includes a first sub-array 110, and the first sub-array 110 includes a plurality of first pixel sub-circuits and a plurality of first isolation sub-structures, and each of the first isolation sub-structures is respectively located at Between two adjacent first pixel sub-circuits in the first direction. Among them, part of the first isolation substructure is provided between two adjacent first pixel sub-circuits in the first direction, and the remaining part is not provided between two adjacent first pixel sub-circuits in the first direction. There is a first isolation substructure, which can be specifically set according to needs. It can be understood that, although in the embodiment of FIG. 2 , a first isolation substructure is provided every four first pixel subcircuits in the first direction, that is, the first isolation substructures are evenly arranged on the first sub-circuits. array 110 , but the first isolation substructures may also be unevenly arranged in the first subarray 110 . For example, a first isolation substructure may be provided at intervals of four first pixel sub-circuits in one region, and a first isolation substructure may be provided at intervals of five first pixel sub-circuits in another region. The embodiment does not limit this. Wherein, the plurality of first isolating substructures may also be arranged in a non-aligned manner in the first direction, that is, the plurality of first isolating substructures may not be arranged in a row, for example, may be arranged in a misplaced position, which is not limited in this embodiment.

Referring to FIG. 1 to FIG. 3 , the light emitting device array 200 includes a plurality of light emitting devices, and the plurality of light emitting devices are respectively connected to the plurality of first pixel sub-circuits through a plurality of driving wires L in a one-to-one correspondence. Specifically, the circular structure located at the lower part of each first pixel sub-circuit in FIG. 2 is the node for connecting the light-emitting device 201 to the first pixel sub-circuit. That is, it is used to connect the anode of the first pixel sub-circuit. It can be understood that the circular structures in the embodiments shown in FIG. 2 and FIG. 3 are only for illustrative purposes, and are not used to limit the scope of protection of the present application, and the positions can be adjusted accordingly according to the design of circuit traces. Wherein, the relative positions of the plurality of first isolation substructures and the plurality of first pixel subcircuits are such that the length difference of the driving wiring L corresponding to each of the light emitting devices of the same color is within a first preset range. . The so-called length difference refers to the difference between the length of the longest driving trace L and the length of the shortest driving trace L.

Wherein, the first preset range may be, for example, 0 um to 200 um. It can be understood that the first preset range may be jointly determined according to the type and resolution of the display device. For example, the types may include mobile phone, tablet computer and television, and the first preset range of the tablet computer may be larger than the first preset range of the mobile phone and smaller than the first preset range of the TV. In this embodiment, by controlling the length difference of the driving wires L corresponding to the light emitting devices of the same color within the first preset range, the brightness difference of the light emitting devices caused by the length difference of the driving wires L can be reduced. , thereby improving the display uniformity of the display module.

Continuing to refer to FIG. 2, in one embodiment, the display module includes a plurality of first pixel circuits 111 and a plurality of first isolation structures 101, and each of the first pixel circuits 111 includes a plurality of first Pixel sub-circuits, each of the first isolation structures 101 includes a plurality of first isolation sub-structures, and each of the first isolation structures 101 is located between two adjacent first pixel circuits 111 in the first direction , the first direction is perpendicular to the thickness direction of the display module.

Continuing to refer to FIG. 3 , in one embodiment, the light-emitting device array 200 is divided into a plurality of light-emitting repeating units 210 , and each of the light-emitting repeating units 210 includes a plurality of light-emitting devices 201 . The light emitting repeating unit 210 includes a plurality of repeating subunits 2101. The light emitting repeating unit 210 includes 4n red light emitting devices, 8n green light emitting devices and 4n blue light emitting devices, where n is an integer greater than or equal to 1. Wherein, two adjacent pixels can share the red light-emitting device or the blue light-emitting device, thereby improving the resolution of the display module, suppressing the color fringing problem of the display module, and further improving the display quality. It can be understood that this embodiment does not specifically limit the arrangement of the red light-emitting devices, green light-emitting devices and blue light-emitting devices, as long as the above-mentioned technical solutions for improving the resolution of the display module can be realized, they all belong to this embodiment. protected range.

In one of the embodiments, continuing to refer to FIG. 3 , each of the repeating subunits 2101 includes one of the red light emitting devices, two of the green light emitting devices and one of the blue light emitting devices that are separated from each other, wherein the One of the green light-emitting devices and one of the red light-emitting devices in the repeating subunit 2101 respectively have the centers of the two first vertices of the virtual quadrilateral 2102, and the two first vertices are located on one side of the virtual quadrilateral 2102. on the diagonal. The other green light-emitting device and one blue light-emitting device in the repeating subunit 2101 respectively have the centers of two second vertices located in the virtual quadrilateral 2102, and the two second vertices are located in the virtual quadrilateral 2102 on the other diagonal.

It should be noted that each light-emitting device in this embodiment may be, but not limited to, organic light-emitting diodes (Organic light-emitting diodes, OLEDs), quantum dot light-emitting diodes (Quantum Dot Light Emitting Diodes, QLEDs), and micron-scale light-emitting diodes ( Micro LED), etc. Each embodiment of the present application is described by taking the light-emitting device as an organic light-emitting diode as an example. Wherein, each light-emitting device can be an organic light-emitting diode of a different color, such as a red OLED, a green OLED, and a blue OLED. The display of different colors makes the display device realize full-color display.

Exemplarily, if the display module needs to achieve richer colors or a larger color gamut, a larger number of light-emitting devices may be provided, for example, light-emitting devices including four different colors. In this embodiment, it is described that the display module includes light emitting devices of three different colors as an example, and the three colors may be red (R), green (G) and blue (B) respectively. It can be understood that the above numbers are only used for exemplary description, and are not used to limit the protection scope of this embodiment. FIG. 4 is a schematic structural diagram of a display module without a first isolation structure. Referring to FIG. 4 , in the upper left and lower right corners of FIG. 4 , the driving lines corresponding to two green light-emitting devices are boldly shown respectively. Wherein, the light emitting device on the left side in FIG. 4 can be understood as the light emitting device near the center of the display module, and the light emitting device on the right side in FIG. 4 can be understood as the light emitting device near the frame of the display module. Obviously, the length difference between the two circuit traces is large, which will lead to differences in the performance of the light emitting device such as response speed or luminous brightness, resulting in uneven display of the display module in the first direction. Moreover, more critically, in FIG. 4 , the length of the driving trace changes gradually, that is, the closer to the frame, the longer the length of the driving trace. Therefore, there is no region in FIG. 4 where the lengths of the driving traces are set in the same manner.

Referring to FIG. 1 for comparison, two first pixel sub-circuits filled in a grid shape are shown, and each first pixel sub-circuit is connected to a corresponding blue light-emitting device via a driving wire. Referring to FIG. 4, two pixel sub-circuits filled in a grid shape are also shown, and each pixel sub-circuit is respectively connected to the corresponding blue light-emitting device through a driving wire, and the two connected blue light-emitting devices The positional relationship corresponds to the positional relationship of the two blue light emitting devices shown in the embodiment of FIG. 1 .

Referring to the connection relationship of the driving wires in FIG. 1 and FIG. 4, it can be found that the driving wires connected between the two first pixel sub-circuits filled in a grid pattern and the corresponding blue light-emitting devices shown in FIG. The lengths of the lines are the same, but the lengths of the driving lines connected between the two first pixel sub-circuits filled in a grid pattern and the corresponding blue light-emitting devices shown in FIG. 4 are different, specifically, the one on the right The driving wire connected to the first pixel sub-circuit is longer than the driving wire connected to the first pixel sub-circuit on the left. As described above, the length of the driving wires will affect the performance of the light emitting device such as response speed or luminous brightness. Therefore, for the two first pixel sub-circuits in the embodiment of FIG. , the correspondingly connected two blue light-emitting devices have very similar performances such as response speed or luminous brightness, that is, the display uniformity is better. However, for the two first pixel sub-circuits in FIG. 4 , due to the different lengths of the connected driving wires, there may be certain differences in performances such as response speed and luminous brightness of the two correspondingly connected blue light-emitting devices. , that is, the uniformity of the display is not as good as that of the Figure 1 embodiment.

It can be understood that FIG. 4 only shows a part of the structure of the display module, and the above differences will become more obvious as the size and number of pixels of the display module increase. For example, assume that the size of the pixel circuit array 100 in the first direction is 99.5% of the size of the light emitting device array 200 in the first direction, that is, 0.5% of the width is reserved for setting other peripheral circuits. Then, the distance between the light emitting device located in the center of the light emitting device array 200 and its corresponding driving circuit is the shortest, and the length of the driving wiring can be understood to be approximately equal to 0 cm. For the light-emitting device located at the outermost side of the light-emitting device array 200, its corresponding driving circuit is located at the outermost side of the pixel circuit array 100, and due to the inherent difference in size between the pixel circuit array 100 and the light-emitting device array 200, the light-emitting device will The length of the driving wire is approximately equal to 0.5% of the size of the light emitting device array 200 in the first direction. If the size of the display module in the first direction is 6 cm, the length of the driving wire is approximately equal to 0.3 mm. It can be seen that, if the first isolation structure is not provided, the uniformity of the wiring length needs to be greatly sacrificed when realizing a display device with a narrow frame.

In this embodiment, by making the size of the pixel circuit array in the first direction smaller than the size of the light-emitting device in the first direction, the peripheral circuits can be placed under the light-emitting device, that is, more space is provided for setting other peripheral circuits. circuit, and arrange the light emitting device array part above other peripheral circuits, thereby narrowing the width of the left and right borders of the display module without affecting the light emitting area of the display module. At the same time, by adding the first isolating substructure, and the relative positions of the multiple first isolating substructures and the multiple first pixel circuits, the length relationship of the driving wires can be effectively adjusted, that is, multiple pixels of the same color The lengths of the driving wires corresponding to the light-emitting devices are similar, which avoids the excessive difference in length between the driving wires corresponding to the light-emitting devices of the same color, thereby affecting the response speed or luminous brightness of the light-emitting devices, thereby improving The display uniformity of the display module.

Wherein, as shown in FIG. 1 , a first isolation structure 101 may be provided between every two adjacent first pixel circuits 111 to make the arrangement of the first pixel circuits 111 more uniform. At the same time, the length of the driving wires in each first pixel circuit 111 can be set in the same way, so as to further improve the uniformity of the length of the driving wires. In other embodiments, the first isolation structure may also be provided between only part of the two adjacent first pixel circuits, and the first isolation structure may not be provided between the remaining part of the adjacent two first pixel circuits. , which is not limited in this embodiment.

FIG. 5 is the second structural schematic diagram of the pixel circuit array 100 of an embodiment, and FIG. 6 is a structural schematic diagram of a display module obtained based on the pixel circuit array 100 of the embodiment of FIG. 5 and the light emitting device array 200 of the embodiment of FIG. 3 . Referring to FIG. 2 and FIG. 5 together, in this embodiment, the first isolation structure may be the second pixel circuit 112, that is, the first sub-array 110 includes a plurality of first pixel circuits 111 and a plurality of second pixel circuits 112 , two first pixel circuits 111 and one second pixel circuit 112 are shown in the embodiment in FIG. 5 . One second pixel circuit 112 is provided between any two adjacent first pixel circuits 111 in the first direction, the first direction is perpendicular to the thickness direction of the display module, that is, the second A pixel circuit 111 and a second pixel circuit 112 are arranged at intervals in the first direction. Exemplarily, the first direction may be the width direction of the display module.

Optionally, a plurality of first pixel sub-circuits in each first pixel circuit 111 may be arranged in an array, for example, arranged in an array of 4 rows×4 columns as shown in the embodiment of FIG. 5 . It should be noted that the number and arrangement of the first pixel sub-circuits of the first pixel circuit 111 in FIG. 5 are only for illustrative purposes, and are not intended to limit the scope of protection of this embodiment. Wherein, the first isolation substructure may be a second pixel subcircuit, and the plurality of second pixel subcircuits are not connected to the light emitting device, that is, the second pixel circuit 112 may include a plurality of second pixel subcircuits. Wherein, the plurality of second pixel sub-circuits may be arranged along the second direction, or may be arranged in an array. Further, the size of the first pixel sub-circuit may be the same as that of the second pixel sub-circuit, and the structure of the second pixel sub-circuit may be the same as that of the first pixel sub-circuit, so as to reduce the pixel circuit array 100 It can also reduce the differential influence of various optical effects on the size structure during the exposure preparation process, thereby improving the preparation yield of the pixel circuit array.

The second pixel subcircuit can be understood as a dummy pixel subcircuit (dummy pixel), that is, as shown in FIG. 6 , the second pixel subcircuit is not connected to the light emitting device, but is only used to optimize the size and arrangement of the pixel circuit array. Specifically, by relatively reducing the size of the pixel circuit array 100 in the first direction, a larger space can be provided for arranging other peripheral circuits, that is, other peripheral circuits and the pixel circuit array 100 are arranged in the same layer, and the light emitting device The array 200 is partly arranged on other peripheral circuits, so that the width of the left and right borders of the display module can be narrowed by moving the positions of other peripheral circuits on the basis of keeping the light emitting area of the display module unchanged. At the same time, after reducing the size of each first pixel sub-circuit, it is still necessary to make the first pixel sub-circuit correspond to the position of the corresponding light-emitting device, so as to prevent the drive line between the two from being too long, which will affect the response speed of the light-emitting device or Luminous brightness. Therefore, the second pixel sub-circuit can fill the gap between the first pixel sub-circuits caused by size reduction, so as to achieve the above-mentioned purpose of position correspondence, improve the arrangement uniformity of the first pixel sub-circuit, thereby improving the display uniformity of the display module. sex. At the same time, by setting the second pixel sub-circuit (dummy pixel) identical to the first pixel sub-circuit, it can be ensured that the structure, size and spacing of each pixel sub-circuit inside the pixel circuit array 100 are consistent, avoiding the problem caused by the inconsistency of circuit wiring density. The problem of the screen Mura. Moreover, the consistent structure of the pixel sub-circuits is also conducive to the stability of the manufacturing process, ensuring the electrical consistency of the thin film transistors and ensuring the uniformity of the display.

Wherein, the first pixel circuit 111 can be aligned with the second pixel circuit 112 in the second direction. Specifically, the first pixel circuit 111 may have a first side edge and a third side edge extending along the second direction, the first side edge may also be understood as a left edge, and the third side edge may also be understood as a right edge. The first pixel circuit 111 may also have a second side edge and a fourth side edge extending along the first direction, the second side edge may also be understood as an upper edge, and the fourth side edge may also be understood as a lower edge. One side edge of the second pixel circuit 112 is aligned with the second side edge of the first pixel circuit 111 in the second direction, thereby simplifying the design of the pixel circuit array 100 .

Fig. 7 is a schematic structural diagram of the first repeating unit 113 and the corresponding light emitting device in an embodiment. Referring to Fig. 7, in one embodiment, one adjacent first pixel circuit 111 and one second pixel circuit 111 are defined. The pixel circuits 112 together form a first repeating unit 113 . It should be noted that this embodiment takes the first pixel circuit 111 on the left and the second pixel circuit 112 on the right as an example to divide to form the first repeating unit 113. In other embodiments, it can also be The first pixel circuit 111 on the right and the second pixel circuit 112 on the left are divided as an example.

Referring to FIG. 3 and FIG. 7 together, the plurality of light-emitting repeating units 210 are in one-to-one correspondence with the plurality of first pixel circuits 111 . The difference between the size of the light-emitting repeating unit 210 in the first direction and the size of the first repeating unit 113 in the first direction is within a third preset range, that is, it can be understood that the light-emitting repeating unit 210 The size in the first direction is similar to the size of the first repeating unit 113 in the first direction. Wherein, the third preset range may be, for example, 0um to 5um. In this embodiment, by setting the size relationship between the light-emitting repeating unit 210 and the first repeating unit 113, the correspondence between the positions of the light-emitting repeating unit 210 and the first repeating unit 113 can be realized, thereby setting a shorter driving line, To improve the stability and reliability of the driving current.

Fig. 8 is one of the circuit diagrams of the first pixel sub-circuit of an embodiment. Referring to Fig. 8, in this embodiment, the first pixel sub-circuit includes a drive transistor T1, an anode reset unit 1511, a gate reset unit 1512, a data write Input unit 1513, threshold compensation unit 1514 and light emission control unit 1515.

Specifically, the driving transistor T1 is used to generate a driving current. Wherein, the gate of the driving transistor T1 is connected to the gate reset unit 1512 , the first pole of the driving transistor T1 is used to receive the data signal Data, and the second pole of the driving transistor T1 can output the driving current correspondingly. Wherein, the current value of the driving current is determined by the data signal Data, and directly affects the light-emitting brightness of the light-emitting device.

The control terminal of the anode reset unit 1511 is used to receive the second scan signal Scan(n), the input terminal of the anode reset unit 1511 is used to receive the reset voltage signal Vinit, and the output terminal of the anode reset unit 1511 is connected to the anode of the light emitting device.

The anode reset unit 1511 is used to receive the reset voltage Vinit through the input terminal after the gate of the driving transistor T1 is reset, and pull down the anode of the light emitting device connected thereto to the reset voltage Vinit, so as to reset the anode of the light emitting device. Wherein, the reset voltage Vinit can be understood as the initial charging voltage of the anode of the light emitting device. By resetting the anode of the light-emitting device, the driving current used to drive the light-emitting device can be changed to flow to the anode of the light-emitting device to drive the light-emitting device to emit light. At the same time, the driving current will not be affected, thereby ensuring the light-emitting device Reliability of luminous brightness.

The control terminal of the gate reset unit 1512 is connected to the gate control terminal for receiving the first scan signal Scan(n-1); the input terminal of the gate reset unit 1512 is connected to the second reset terminal for receiving the reset voltage Vinit ; The output terminal of the gate reset unit 1512 is connected to the gate of the driving transistor T1. Specifically, the gate reset unit 1512 can pull down the gate voltage of the driving transistor T1 to the reset voltage Vinit according to the first scanning signal Scan(n-1) received by the control terminal, so as to reset the gate of the driving transistor T1 .

The data writing unit 1513 includes a data writing transistor T2, the gate of the data writing transistor T2 is connected to the second scanning signal line Scan(n), the first pole of the data writing transistor T2 is connected to the data signal line, and the data writing transistor T2 is connected to the data signal line. The second pole of the transistor T2 is connected to the first pole of the driving transistor T1, and the data writing transistor T2 is used to control the signal between the second scanning signal line and the first pole of the driving transistor T1 according to the second scanning signal Scan(n). On and off of the transmission path. Specifically, taking the data writing transistor T2 as a P-type transistor as an example, when the second scanning signal Scan(n) is at a low level, the data writing transistor T2 is turned on, and transmits the data signal Data to the first transistor of the driving transistor T1. One pole; when the second scan signal Scan(n) is at low level, the data writing transistor T2 is turned off. It can be understood that the data writing unit 1513 is not limited to the data writing transistor T2 of this embodiment, and may also be other circuit structures capable of realizing the signal transmission function according to the enable control signal.

The threshold compensation unit 1514 is connected to the gate and the second electrode of the driving transistor T1 respectively, and is used for controlling the on-off of the signal transmission path between the gate and the second electrode of the driving transistor T1 according to the second scan signal Scan(n). Specifically, by setting the threshold compensation unit 1514, the threshold voltage of the driving transistor T1 can be compensated, so as to prevent the threshold voltage of the driving transistor T1 from affecting the brightness of the light emitting device.

Wherein, the threshold compensation unit 1514 includes a threshold compensation transistor T3 and a storage capacitor C1. The storage capacitor C1 is connected to the second power supply voltage terminal VDD and the gate of the driving transistor T1 respectively. The gate of the threshold compensation transistor T3 is connected to the first scanning signal line, the first electrode of the threshold compensation transistor T3 is connected to the second electrode of the driving transistor T1, and the second electrode of the threshold compensation transistor T3 is connected to the gate of the driving transistor T1. The threshold compensation transistor T3 is used for controlling the on-off of the signal transmission path between the gate and the second electrode of the driving transistor T1 according to the second scan signal Scan(n). Specifically, taking the threshold compensation transistor T3 as a P-type transistor as an example, when the second scan signal Scan(n) is at a low level, threshold compensation is performed and the storage capacitor C1 is charged, so that the compensation result is stored in the storage capacitor C1 .

Optionally, the threshold compensation transistor T3 may be a double-gate transistor. In this embodiment, the threshold compensation transistor T3 with a double-gate transistor structure can effectively improve the reliability of the threshold compensation, thereby improving the display quality of the display device. It can be understood that other transistors in the first pixel sub-circuit may also be double-gate transistors to further improve display quality.

The light emission control unit 1515 includes a first control transistor T5 and a second control transistor T6. Wherein, the gate of the first control transistor T5 is used to receive the light-emitting control signal, the first pole of the first control transistor T5 is connected to the second power supply voltage terminal, and the second pole of the first control transistor T5 is connected to the first terminal of the driving transistor T1. The first control transistor T5 is used to control the on-off of the signal transmission path between the second power supply voltage terminal and the first pole of the driving transistor T1 according to the light emission control signal EM. The gate of the second control transistor T6 is used to receive the light emission control signal EM, the first pole of the second control transistor T6 is connected to the second pole of the driving transistor T1, and the second pole of the second control transistor T6 is connected to the anode of the light emitting device, The second control transistor T6 is used for controlling the on-off of the signal transmission path between the second pole of the driving transistor T1 and the anode of the light-emitting device according to the light-emitting control signal EM. Exemplarily, the first control transistor T5 and the second control transistor T6 are P-type transistors as an example for illustration, when the light emission control signal EM is at a low level, the first control transistor T5 and the second control transistor T6 are turned on, The voltage of the first pole of the driving transistor T1 is pulled up to the second power supply voltage VDD, and the gate-source voltage difference of the first driving transistor T1 changes to generate a driving current and output the driving current to the light emitting device, thereby controlling the light emitting device to emit light.

It should be noted that various transistors in this embodiment are not limited to the P-type transistors in the foregoing embodiments, and may also be N-type transistors and the like. For different types of transistors, their corresponding driving methods can also be adaptively adjusted. In addition, the first pixel sub-circuit of this embodiment is not limited to the 7T1C first pixel sub-circuit in the foregoing embodiments, that is, the first pixel sub-circuit may also have other numbers of transistors, so that A light-weight display device, or a more flexible display function with a larger number of transistors, for example, can also be other types of driving circuits such as 3T1C, 6T1C, and 6T2C.

FIG. 9 is a schematic cross-sectional view of a display module according to an embodiment. Referring to FIG. 9 , the display module further includes a gate driving circuit 300 . The gate drive circuit 300 is arranged adjacent to the pixel circuit array 100 in the first direction, and the projection of the gate drive circuit 300 on the virtual plane 201 along the third direction is along the line of the light emitting device array 200 The projections of the third direction on the virtual plane 600 partially overlap, the third direction is the thickness direction of the display module, and the virtual plane 600 is a plane perpendicular to the third direction. It should be noted that the virtual The plane 600 is not a feature that actually exists in the display module, but a reference plane introduced for the convenience of explaining the features of the display module.

FIG. 10 is a third structural schematic diagram of a display module according to an embodiment. In order to simplify the drawing, each driving wire L is not shown in FIG. 10 . Referring to FIG. 10 , the gate driving circuit 300 is respectively connected to each of the first pixel sub-circuits, and the gate driving circuit 300 is used to drive the light emitting device corresponding to each of the first pixel sub-circuits to emit light. Wherein, the gate driving circuit 300 may be a GOA (Gate on Array) circuit. In this embodiment, by disposing the gate driving circuit 300 on the array substrate, the frame size can be further narrowed.

Referring to FIG. 9 and FIG. 10 together, in one embodiment, the gate driving circuit 300 includes a first driving unit 310 and a second driving unit 320 . The first driving unit 310 is connected to the first pixel sub-circuit, and the first driving unit 310 is used to generate a scanning control signal, and the scanning control signal is used to control the first pixel sub-circuit to respectively perform gate reset, Anode reset and data writing, that is, the scan control signal includes a first scan signal Scan(n−1) and a second scan signal Scan(n). The second driving unit 320 is connected with the first pixel sub-circuit, and the second driving unit 320 is used to generate the light emission control signal EM, and the light emission control signal EM is used to control the on-off of the output path of the driving current. The output path is a path between the first pixel sub-circuit and the corresponding light emitting device.

FIG. 11 is a schematic top view of the positions of the first gate sub-circuit 311 and the second gate sub-circuit 312 according to an embodiment. Referring to FIG. 11 , in this embodiment, the first direction is parallel to that of the display module. In the row direction, the display panel includes a display area AA and a non-display area NAA arranged around the display area. The display module also includes a plurality of gate lines 400, and each of the gate lines 400 is respectively connected to a plurality of the first pixel sub-circuits in the pixel circuit array 100 (that is, a plurality of rectangular structures arranged in an array in the figure). Each of them can be understood as a first pixel sub-circuit) connection, and the first driving unit 310 includes a first gate sub-circuit 311 and a second gate sub-circuit 312 arranged in the non-display area NAA. The first gate sub-circuit 311 is disposed on one side of the pixel circuit array 100 in the first direction, and the second gate sub-circuit 312 is disposed on the other side of the pixel circuit array 100 in the first direction. side. Wherein, both ends of each gate line 400 are respectively connected to the first gate sub-circuit 311 and the second gate sub-circuit 312 . In this embodiment, each gate line 400 receives the same signal from both ends, that is, the single-row double-drive driving method can make the voltage difference between any two points on the gate line 400 within the sixth preset within range. Wherein, the sixth preset range may be, for example, 0 mV to 0.02 mV. It can be understood that, with the continuous improvement of the resolution of the display module, the number of loads that each gate line 400 needs to drive continues to increase. Therefore, if the gate line 400 is too long and the gate driving circuit 300 is only provided at one end, the voltage at the other end will be low, and even the driving transistor cannot be turned on effectively, thereby affecting the display quality of the display module. In this embodiment, through the above arrangement, the reliability of the voltage on the gate line 400 can be effectively improved, thereby improving the uniformity of the display module.

FIG. 12 is a schematic cross-sectional view of the positions of the first gate sub-circuit 311 and the second gate sub-circuit 312 of an embodiment. Referring to FIG. 12 , in one embodiment, the first gate sub-circuit 311 is positioned along the The projections of the three directions on the virtual plane 600 and the projection of the light emitting device array 200 along the third direction on the virtual plane 600 have a first overlapping area, and the virtual plane 600 is a plane perpendicular to the third direction. The projection of the second gate sub-circuit 312 on the virtual plane 600 along the third direction and the projection of the light emitting device array 200 on the virtual plane 600 along the third direction have a second overlapping area. Wherein, the first overlapping area is equal to the second overlapping area. In this embodiment, by adopting the first gate sub-circuit 311 and the second gate sub-circuit 312 at symmetrical positions, the symmetry of the frame of the display module can be effectively improved, and the width of the frame on one side is prevented from being too large.

In one of the embodiments, the first pixel sub-circuit and the second pixel sub-circuit respectively include a plurality of thin film transistors, and each of the thin film transistors in the first pixel sub-circuit and the second pixel sub-circuit is Low temperature polycrystalline (Low Temperature Poly-silicon, LTPS) transistor. Specifically, FIG. 13 is a schematic cross-sectional view of an LTPS-structured drive circuit in an embodiment. The LTPS-structured drive circuit is a drive circuit in which all thin film transistors are LTPS transistors. The cross-sectional direction of FIG. 13 is perpendicular to the display surface of the display module. .

Referring to FIG. 13, in this embodiment, the substrate may include polyimide (PI) substrates 1112 and first buffer layers 1113 arranged alternately in sequence. In the embodiment shown in FIG. Two polyimide (PI) substrates 1112 and two first buffer layers 1113 . It can be understood that the substrate may also include more polyimide (PI) substrates 1112 and first buffer layers 1113 . A first gate insulating layer 1114 , an interlayer insulating layer 1115 and a planarization layer 1116 are also disposed on the substrate. In FIG. 13 , the first gate insulating layer 1114 , the interlayer insulating layer 1115 , and the planarization layer 1116 also show two above-mentioned first pixel sub-circuits.

Specifically, the display module further includes a plurality of driving wires L, and a plurality of the first pixel sub-circuits are respectively connected to a plurality of the light emitting devices in one-to-one correspondence through the plurality of driving wires L. The first pixel sub-circuits are respectively used to output driving signals to the anodes 1107 of the connected light emitting devices. For ease of description, in each embodiment of the present application, the wiring connected between the output end of the driving circuit and the anode 1107 of the light emitting device is defined as the driving wiring L. Wherein, the driving trace L may be a transparent metal wire, for example, an indium tin oxide (Indium Tin Oxide, ITO) metal wire, an aluminum zinc oxide (Alumina zinc oxide, AZO) metal wire, and the like.

The first pixel sub-circuit 110a includes a first gate 1101, a first source 1102, a first drain 1103, a source contact structure 1104 and a corresponding drain contact structure 1105, and the anode 1107 layer in the first light emitting device passes through The driving wire L is electrically connected to the first source 1102 . The first pixel sub-circuit 110b may also include a first gate 1101, a first source 1102, a first drain 1103, a source contact structure 1104 and a drain contact structure 1105, and the anode 1107 layer in the second light emitting device is also passed through The driving wire L is electrically connected to the corresponding first source 1102 . Referring to FIG. 13 , since the positions of the plurality of light emitting devices 201 in the same first repeating unit 113 are different, and the positions of the first pixel sub-circuits corresponding to each light emitting device 201 are also different, therefore, it is necessary to set driving lines L of different lengths, for an accurate connection.

In one of the embodiments, the driving circuit based on the LTPS structure, with continued reference to FIG. 7 , the first repeating unit 113 may include a plurality of first pixel sub-circuits arranged in an array of 4n rows×4n columns, and A plurality of second pixel sub-circuits arranged in an array of 4n rows×1 column, wherein n is a positive integer. In the embodiment in FIG. 7, n=1, that is, the first repeat unit 113 includes a plurality of first pixel sub-circuits arranged in an array of 4 rows×4 columns, and a plurality of first pixel sub-circuits arranged in an array of 4 rows×1 column. A plurality of the second pixel sub-circuits are distributed. Referring to FIG. 7, it can be seen that if the number of first pixel sub-circuits in the first repeating unit 113 is too large, the distance between the first pixel sub-circuits on the side close to the second pixel circuit 112 and the corresponding light emitting device is too far, so that As a result, the length of part of the driving wires L is too long, thereby affecting the display quality of the display module. Therefore, the setting method of this embodiment can reduce the difference in driving performance between different light emitting devices on the basis of setting a larger number of first pixel sub-circuits with actual driving functions.

In one embodiment, the second pixel sub-circuit includes a plurality of thin film transistors, at least one of the plurality of thin film transistors is a low temperature polycrystalline oxide (Low Temperature Poly Crystalline Silicon and Oxide, LTPO) transistor. For example, the transistors T3 and T4 affecting leakage in FIG. 8 may be replaced with oxide thin film transistors (Thin Film Transistor, TFT), and oxide transistors have better leakage suppression performance. That is, the transistor T3 and transistor T4 in FIG. 8 are replaced from the LTPS structure to the LTPO structure, and the other transistors are still in the LTPS structure, and the connection structure of the circuit remains unchanged, so as to achieve the purpose of controlling leakage. Specifically, FIG. 14 is a schematic cross-sectional view of a driving circuit with an LTPO structure in an embodiment. The driving circuit with an LTPO structure is a driving circuit in which at least one thin film transistor is an LTPO transistor. The cross-sectional direction of FIG. 14 is perpendicular to the display surface of the display module. .

Referring to FIG. 14 , in this embodiment, the arrangement of the substrate, the first source 1102 , the first drain 1103 and the first gate 1101 is the same as that of the embodiment in FIG. 13 , and will not be repeated here. The light shielding layer 1111 is set on the same layer as the first gate 1101, the second buffer layer 1113 between the interlayer insulating layer 1115 and the second active layer 1108, and the drain contact structure 1105 overlaps the steps of the second active layer 1108 Structurally, the second active layer 1108 is formed with a second source 1102 and a second drain 1103, the shape of the second gate insulating layer 1109 is the same as that of the second gate 1110, the second active layer 1108, the second The gate insulating layer 1109 and the second gate 1110 are stacked in sequence, and the second interlayer dielectric layer covers part of the upper surface of the second gate insulating layer 1109, the second gate 1110 and the second active layer 1108, and the second active The region of the upper surface of the layer 1108 not covered by the second interlayer dielectric layer is a step surface of a step structure overlapping with the first source electrode 1102 and the first drain electrode 1103 to be formed. In this embodiment, the anode 1107 of the light-emitting element can be initialized during the data retention stage by using the driving circuit of the LTPO structure, so as to improve problems such as screen flickering and smearing during low-frequency driving.

In one of the embodiments, the second pixel sub-circuit includes an emission control line (not shown in FIG. 14 ) for transmitting an emission control signal EM, and two of the second pixel subcircuits adjacently arranged in the first direction The pixel sub-circuits are arranged symmetrically with respect to a virtual symmetry plane (as shown by the dotted line 1117 in FIG. 14 ), and share the same light emission control line. The virtual symmetry plane is a plane perpendicular to the first direction. Comparing Figure 13 and Figure 14, it can be seen that the film layer structure of the driving circuit with LTPO structure is relatively complicated. Therefore, by adopting the method of sharing the light-emitting control lines shown in Figure 15 (that is, sharing the thickened signal lines), the total number of light-emitting control lines can be reduced, thereby simplifying the wiring complexity of the display module to provide a smaller volume display module. It can be understood that the circuit structure shown in the embodiment of FIG. 15 includes two first pixel sub-circuits, but the structure of each first pixel sub-circuit is the same as that of the embodiment in FIG. 8 , and will not be repeated here.

FIG. 16 is the fourth structural schematic diagram of a display module in an embodiment. Referring to FIG. 16, the first repeating unit 113 includes a plurality of first pixel sub-circuits arranged in an array of 4n rows×8n columns. The second pixel circuit 112 includes a plurality of second pixel sub-circuits arranged in an array of 4n rows×2m columns, wherein m and n are positive integers. Wherein, as shown in FIG. 16 , m can be 1, and n can also be 1. In this embodiment, two adjacent second pixel sub-circuits are arranged symmetrically with respect to a virtual symmetry plane (as shown by the dotted line 1117 in FIG. 14 ). It can be understood that it is necessary to make the number of columns of the sub-pixel circuits in the first repeating unit 113 an even number to realize the above-mentioned symmetric setting, so as to be compatible with the LTPO process.

It can be understood that, in some embodiments, the first pixel sub-circuit may also use an LTPS structure driving circuit, and the second pixel sub-circuit may use an LTPO structure driving circuit to form a pixel circuit array. Wherein, for the specific structure of each driving circuit, reference may be made to the above-mentioned embodiments, which will not be repeated here.

In one of the embodiments, the length difference between the driving wires connected to the plurality of first pixel sub-circuits at corresponding positions in each of the first pixel circuits is within a fifth preset range. It can be understood that, in order to achieve better display quality, the lengths between the driving wires connected to the plurality of first pixel sub-circuits at corresponding positions should be set to be equal. That is, from a design point of view, the fifth preset range should be 0um. However, due to certain process errors in the manufacturing process, the fifth preset range can be allowed to slightly increase, for example, 0 um to 1 um. For example, the two first pixel sub-circuits in the dotted line box in FIG. 10 can be understood as the first pixel sub-circuits in corresponding positions. If the light emitting devices at the corresponding positions are not turned on at the same time, it will result in uneven display colors. Therefore, the light emitting devices at corresponding positions need to be turned on at the same time, so as to jointly realize the required display color and brightness. It should be emphasized that the same moment is not limited to exactly the same moment, if the difference between the lighting moments of the two light-emitting devices at the corresponding positions is less than a preset threshold, it can be understood that they are turned on at the same moment. The preset threshold may be, for example, 0.01ms. Wherein, the lighting time refers to the time when the light emitting device reaches a stable target brightness, and the display driver chip respectively determines the target brightness of each light emitting device according to the picture to be displayed.

FIG. 17 is a third schematic structural diagram of a pixel circuit array 100 according to an embodiment. Referring to FIG. 17 , in one embodiment, the pixel circuit array 100 further includes a second sub-array 120 . The second sub-array 120 is disposed adjacent to the first sub-array 110 in the first direction, and the second sub-array 120 includes a plurality of the first pixel circuits 111 . FIG. 18 is a schematic structural diagram of a display module formed based on the pixel circuit array 100 in the embodiment of FIG. 17. Referring to FIG. In the second sub-array 120 , a larger number of light-emitting devices can be arranged correspondingly, so as to increase the overlapping area between the light-emitting device array 200 and other peripheral circuits (eg, the gate driving circuit 300 ). Wherein, the overlapping area refers to the overlapping area in the third direction, that is, between the projection of the light emitting device array 200 on the virtual plane perpendicular to the third direction and the projections of other peripheral circuits on the virtual plane perpendicular to the third direction the overlapping area.

It can be understood that when a user uses a display device, the requirement for display uniformity in the middle area is greater than that in the edge area. Therefore, in this embodiment, the first sub-array 110 structure is used in the middle area, and the first sub-array 110 structure is used in the edge area. The structure of the two sub-arrays 120 can not only achieve the purpose of narrowing the display frame to a large extent, but also reduce the impact on user experience. For example, when a layer of ITO is used for wiring, a space of 200um to 400um can be obtained at the left and right borders to provide a display module with a narrower border. It should be noted that although the second sub-array 120 in the embodiment of FIG. 17 only shows 8 columns of first pixel sub-circuits, the second sub-array 120 can actually have more columns of first pixel sub-circuits as required. , to further optimize narrow bezel performance.

Continuing to refer to FIG. 17 and FIG. 18, in one embodiment, one side edge of the second sub-array 120 is aligned with the first side edge of the first sub-array 110 in the second direction, and the second The direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module. It can be understood that, the method of defining each side edge of the first sub-array 110 in this embodiment is the same as the method of defining the side edge of the first pixel circuit in the foregoing embodiment, and details are not repeated here. In this embodiment, through the above method, the design difficulty of the pixel driving circuit can be reduced without affecting the display function.

Referring to FIG. 19, in one embodiment, the pixel circuit array 100 further includes a third sub-array 130, wherein the third sub-array 130 can be understood as being relatively close to the center of the display module, while the first sub-array 110 Relatively close to the frame of the display module. FIG. 20 is a schematic structural diagram of a display module formed based on the pixel circuit array 100 of the embodiment in FIG. 19. Referring to FIG. 19 and FIG. adjacently arranged in the second direction, the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module.

The third sub-array 130 includes a plurality of the first pixel sub-circuits, a plurality of the first isolation sub-structures and a plurality of second isolation sub-structures, each of the second isolation sub-structures is located in the second direction between two adjacent first pixel sub-circuits in the second direction or between two adjacent first isolation sub-structures in the second direction, the plurality of second isolation sub-structures and the plurality of the The relative positions of the first pixel sub-circuits make the difference in length of the driving wires corresponding to the plurality of light emitting devices of the same color within the second preset range. Wherein, the second preset range may be, for example, 0um to 100um. By keeping the length difference of the driving wires L corresponding to the light emitting devices of the same color within the second preset range, the brightness difference of the light emitting device caused by the length difference of the driving wires can be reduced, thereby improving the display of the display module. Uniformity.

Further, the third sub-array 130 may include a plurality of first repeating units 113 and a plurality of second isolation structures, and the second isolation structures are located between two adjacent first repeating units in the second direction. Between 113. By adding a second isolation structure, and the relative positions of multiple second isolation structures and multiple first repeating units 113, the length relationship of the driving wiring can be effectively adjusted, that is, multiple of the same color The lengths of the driving lines corresponding to the light-emitting devices are similar, which avoids the excessive difference in length between the driving lines corresponding to the light-emitting devices of the same color, which will affect the response speed or luminance of the light-emitting devices, thereby improving the display module. display uniformity.

Wherein, the second isolation structure may be a third pixel circuit 131 , that is, the third sub-array 130 includes a plurality of the first repeating units 113 and a plurality of third pixel circuits 131 . Wherein, the third pixel circuit 131 includes a plurality of third pixel sub-circuits, the structure of the third pixel sub-circuit may be the same as that of the first pixel sub-circuit, and the third pixel sub-circuit is not the same as the first pixel sub-circuit. The light emitting device is electrically connected. By setting the third pixel sub-circuit identical to the first pixel sub-circuit, it is possible to ensure that the structure and size of each pixel sub-circuit inside the pixel circuit array 100 are consistent, and to avoid the problem of screen mura caused by inconsistent circuit trace density. Moreover, the consistent size and structure of the pixel sub-circuits is also conducive to the stability of the manufacturing process, ensuring the consistency of the electrical properties of the thin film transistors and the uniformity of the display. Still further, multiple third pixel sub-circuits in the same third pixel circuit 131 may be arranged along the first direction.

Optionally, a second isolation structure is provided between any two adjacent first repeating units 113 in the second direction. That is, one third pixel circuit 131 is provided between any two adjacent first repeating units 113 in the second direction. Wherein, the size of the light emitting device array 200 in the second direction is larger than the size of the pixel circuit array 100 in the second direction. Through the above-mentioned arrangement, the first pixel sub-circuit and the third pixel sub-circuit can be arranged more regularly in the second direction, and the pitch of each pixel sub-circuit inside the pixel circuit array 100 can be guaranteed to be consistent, thereby further improving the circuit due to The screen mura problem of the display module caused by inconsistent trace density.

In one of the embodiments, one side edge of the third sub-array 130 is aligned with the second side edge of the first sub-array 110 in the first direction, the second side edge is connected to the first side edge, And the plurality of third pixel sub-circuits in the third pixel circuit 131 are arranged along the first direction. A difference between the sum of the sizes of the first repeating unit 113 and the third pixel circuit 131 in the second direction and the size of the light emitting repeating unit in the second direction is within a fourth preset range. Wherein, the fourth preset range may be, for example, 0um to 10um. Through the above arrangement, the correspondence between the light-emitting device and the corresponding first pixel sub-circuit can be effectively provided, so as to avoid excessively long driving lines, thereby improving display uniformity.

FIG. 21 is a fifth structural schematic diagram of a pixel circuit array according to an embodiment. Referring to FIG. 21 , in this embodiment, the pixel circuit array 100 further includes a fourth sub-array 140 . The fourth sub-array 140 is arranged adjacent to the third sub-array 130 in the first direction, and is arranged adjacent to the second sub-array 120 in the second direction, and the fourth sub-array 140 includes A plurality of first pixel circuits and a plurality of third isolation structures, the third isolation structures include a plurality of second isolation substructures, and the third isolation structures are located between two adjacent pixel circuits in the second direction between the first pixel circuits. Further, one third isolation structure is provided between any two adjacent first pixel circuits 111 in the second direction in the fourth sub-array 140 .

Continuing to refer to FIG. 21 , the third isolation structure may be a fourth pixel circuit 141 , that is, the fourth sub-array 140 may include a plurality of the first pixel circuits 111 and a plurality of fourth pixel circuits 141 . The fourth pixel circuit 141 includes a plurality of the third pixel sub-circuits. Wherein, a plurality of the third pixel sub-circuits in the fourth pixel circuit 141 may be arranged along the first direction.

Further, in the fourth sub-array 140, one fourth pixel circuit 141 is provided between any two adjacent first pixel circuits 111 in the second direction, so as to improve the pixel sub-circuit Arrangement uniformity. The third side edge of the fourth subarray 140 is aligned with the first side edge of the first subarray 110 in the second direction, and the fourth side edge of the fourth subarray 140 is aligned with the first side edge of the first subarray 110. Second side edges of the sub-array 110 are aligned in the first direction, and the third side edges are connected to the fourth side edges. FIG. 22 is a schematic structural diagram of a display module formed based on the pixel circuit array 100 of the embodiment in FIG. 21. Referring to FIG. A larger number of light emitting devices increases the overlapping area of the light emitting device array 200 and other peripheral circuits (such as gate driving circuits) in the third direction.

Further, FIG. 23 is a schematic diagram of the position of the light emitting device and the gate drive circuit in the display module of an embodiment, and FIG. 24 is a partial schematic diagram of the connection relationship between the light emitting device and the first pixel sub-circuit in the embodiment of FIG. 23 , combined with reference As shown in Fig. 23 and Fig. 24, in this embodiment, light emission can be realized by setting a plurality of second pixel sub-circuits (dummy pixel) arranged along the first direction and a plurality of second pixel sub-circuits (dummy pixel) arranged along the second direction The device shares space with the peripheral circuits such as the gate drive circuit 300 in the third direction, thereby reducing the occupied area of the peripheral circuits in a plane parallel to the display surface, thereby providing a display device with a narrow frame.

Fig. 25 is a schematic cross-sectional view of a display module according to an embodiment. The cross-sectional plane of this embodiment is parallel to the second direction and parallel to the third direction. Referring to Fig. 25, in one embodiment, the display module further includes Fan out trace group 500. The fan-out routing group 500 is arranged adjacent to the pixel circuit array 100 in the second direction, and the projection of the fan-out routing group 500 on the virtual plane 600 along the third direction is the same as that of the light emitting device array 200 along the third direction. The projections of the directions on the virtual plane 600 partially overlap, the third direction is the thickness direction of the display module, and the virtual plane 600 is a plane perpendicular to the third direction. FIG. 26 is a top view schematic diagram of the position of the fan-out routing group in an embodiment. Referring to FIG. 26 , in this embodiment, the display panel further includes a display driving unit located in the non-display area NAA, and the display driving unit communicates with the pixels through the fan-out routing area. The circuit array 100 is connected. The display driving unit may be a display driver IC (Display Driver IC, DDIC). In this embodiment, by partially overlapping the light-emitting device array 200 and the fan-out wiring group 500 in the third direction, when using a layer of ITO wiring, a space of 200um to 400um can be obtained at the upper and lower borders to provide a narrower The display module of the frame.

Further, in one of the embodiments, the projection of the light emitting device array 200 on the virtual plane along the third direction completely covers the projection of the pixel circuit array 100 on the virtual plane along the third direction, and the third direction is the thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction. FIG. 27 is a schematic diagram of the position of the light emitting device array 200 according to an embodiment. Referring to FIG. 27 , based on the above arrangement, the light emitting device array 200 is respectively connected to the first gate sub-circuit 311 and the second gate sub-circuit 312 in the first direction. Partially overlap, and partially overlap with the fan-out routing group 500 , so as to maximize the display area, thereby providing a display module with the narrowest frame.

The present application also provides a display device, including: the above-mentioned display module. In this embodiment, based on the above display module, the frame of the display device can be narrowed, and the display uniformity of the display device can be optimized, thereby improving the comprehensive display performance of the display device.

The various technical features of the above-mentioned embodiments can be combined arbitrarily. For the sake of concise description, all possible combinations of the various technical features in the above-mentioned embodiments are not described. However, as long as there is no contradiction in the combination of these technical features, should be considered as within the scope of this specification.

The above-mentioned embodiments only express several implementation modes of the embodiments of the present application, and the descriptions thereof are relatively specific and detailed, but should not be construed as limiting the scope of the patent for the invention. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the embodiments of the present application, and these all belong to the protection scope of the embodiments of the present application. Therefore, the scope of protection of the embodiment patent of this application should be based on the appended claims.

Claims

A display module, comprising:

A pixel circuit array comprising a first sub-array comprising a plurality of first pixel sub-circuits and a plurality of first isolation sub-structures;

Multiple drive traces; and

The array of light-emitting devices includes a plurality of light-emitting devices, and the plurality of light-emitting devices are electrically connected to the plurality of driving wires in one-to-one correspondence, and the plurality of driving wires are respectively connected to the plurality of first pixel sub-circuits. One-to-one electrical connection, so that the plurality of light-emitting devices and the plurality of first pixel sub-circuits are electrically connected in one-to-one correspondence, and the size of the light-emitting device array in the first direction is larger than that of the pixels. The size of the circuit array in the first direction, the first direction is perpendicular to the thickness direction of the display module;

Wherein, each of the first isolation substructures is located between two adjacent first pixel subcircuits in the first direction, so that the length difference of the driving wires corresponding to the light emitting devices of the same color is between within the first preset range.
The display module according to claim 1, wherein the first preset range is 0um to 200um.
The display module according to claim 1, the display module comprising a plurality of first pixel circuits and a plurality of first isolation structures, each of the first pixel circuits respectively comprising a plurality of the first pixel sub-circuits, Each of the first isolation structures includes a plurality of first isolation substructures, and each of the first isolation structures is respectively located between two adjacent first pixel circuits in the first direction.
According to the display module according to claim 3, one first isolation structure is provided between any two adjacent first pixel circuits in the first direction.
According to the display module according to claim 3, the first isolation structure is a second pixel circuit, the first isolation substructure is a second pixel subcircuit, and the structure of the second pixel subcircuit is the same as that of the first pixel subcircuit. A pixel sub-circuit has the same structure, and the second pixel sub-circuit is not electrically connected to the light emitting device.
According to the display module according to claim 5, the plurality of second pixel sub-circuits in the same second pixel circuit are arranged along a second direction, and the second direction is perpendicular to the first direction and perpendicular to in the thickness direction of the display module.
According to the display module according to claim 3, the length difference between the driving wires connected to the plurality of first pixel sub-circuits located in corresponding positions in each of the first pixel circuits is within a fifth preset range. Inside.
The display module according to claim 3, the pixel circuit array further comprising:

A second sub-array is arranged adjacent to the first sub-array in the first direction, and the second sub-array includes a plurality of the first pixel circuits.
The display module according to claim 8, further comprising:

A gate drive circuit is arranged adjacent to the pixel circuit array in the first direction, and the projection of the gate drive circuit on a virtual plane along the third direction is the same as that of the light emitting device array along the third direction. The projections of the directions on the virtual plane partially overlap, the third direction is the thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction;

The gate drive circuits are respectively connected to the first pixel sub-circuits, and the gate drive circuits are used to drive the light-emitting devices corresponding to the first pixel sub-circuits to emit light.
The display module according to claim 9, wherein the gate driving circuit comprises:

The first driving unit is connected to the first pixel sub-circuit, and the first driving unit is used to generate a scanning control signal, and the scanning control signal is used to control the first pixel sub-circuit to perform gate reset, anode Reset and data write;

The second driving unit is connected to the first pixel sub-circuit, the second driving unit is used to generate a light emission control signal, and the light emission control signal is used to control the on-off of the output path of the driving current, and the output path is A path between the first pixel sub-circuit and the corresponding light emitting device.
The display module according to claim 10, the display module further comprising a plurality of gate lines, each of the gate lines is respectively connected to a plurality of the first pixel sub-circuits, and the first driving unit comprises :

a first gate sub-circuit disposed on one side of the pixel circuit array in the first direction;

a second gate sub-circuit disposed on the other side of the pixel circuit array in the first direction;

Wherein, each of the gate lines is respectively connected to the first gate sub-circuit and the second gate sub-circuit.
The display module according to claim 11, the projection of the first grid sub-circuit on the virtual plane along the third direction and the projection of the light emitting device array on the virtual plane along the third direction have a first Overlapping area, the third direction is the thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction;

A projection of the second gate subcircuit on the virtual plane along the third direction and a projection of the light emitting device array on the virtual plane along the third direction have a second overlapping area;

Wherein, the first overlapping area is equal to the second overlapping area.
The display module according to claim 3, the size of the light emitting device array in the second direction is larger than the size of the pixel circuit array in the second direction, the second direction is perpendicular to the first direction, And perpendicular to the thickness direction of the display module, the pixel circuit array further includes:

The third sub-array is arranged adjacent to the first sub-array in the second direction, the second direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module, the third sub-array The array includes a plurality of first pixel sub-circuits, a plurality of first isolation substructures and a plurality of second isolation substructures, and each of the second isolation substructures is located in two adjacent pixel substructures in the second direction. Between the first pixel sub-circuits or between two adjacent first isolation sub-structures in the second direction, so that a plurality of the light-emitting devices of the same color in the third sub-array are correspondingly driven The length difference between the traces is within the second preset range.
The display module according to claim 13, the second preset range is 0um to 100um.
According to the display module according to claim 13, it is defined that one of the adjacent first pixel circuits and one of the first isolation structures together form a first repeating unit, and the third sub-array includes a plurality of the first pixel circuits. A repeating unit and a plurality of second isolation structures, the second isolation structure includes a plurality of the second isolation substructures, the second isolation structure is located in two adjacent first repetitions in the second direction between units.
The display module according to any one of claim 15, one second isolation unit is provided between any two adjacent first repeating units in the second direction in the third sub-array. structure.
According to the display module according to claim 15, the second isolation structure is a third pixel circuit, the second isolation substructure is a third pixel subcircuit, and the structure of the third pixel subcircuit is the same as that of the first pixel subcircuit. A pixel sub-circuit has the same structure, and the third pixel sub-circuit is not electrically connected to the light emitting device.
According to the display module according to claim 17, a plurality of the third pixel sub-circuits in the same third pixel circuit are arranged along the first direction.
The display module according to claim 13, the pixel circuit array further comprising:

a fourth sub-array, arranged adjacent to the third sub-array in the first direction, the fourth sub-array includes a plurality of the first pixel sub-circuits and a plurality of the second isolation sub-structures, Each of the second isolation substructures is respectively located between two adjacent first pixel subcircuits in the second direction.
The display module according to claim 19, the fourth sub-array includes a plurality of the first pixel circuits and a plurality of third isolation structures, and the third isolation structure includes a plurality of the second isolation sub-structures , the third isolation structure is located between two adjacent first pixel circuits in the second direction.
According to the display module according to claim 20, one second isolation structure is provided between any two adjacent first pixel circuits in the second direction in the fourth sub-array.
The display module according to claim 13, further comprising:

The fan-out wiring group is arranged adjacent to the pixel circuit array in the second direction, and the projection of the fan-out wiring group on the virtual plane along the third direction and the light-emitting device array are on the virtual plane along the third direction The projections on , the third direction is the thickness direction of the display module, and the virtual plane is a plane perpendicular to the third direction.
According to the display module according to claim 15, the light-emitting device array is divided into a plurality of light-emitting repeating units, and the plurality of light-emitting repeating units correspond to the plurality of first pixel circuits respectively, and each of the light-emitting repeating units The units respectively include a plurality of the light emitting devices;

Wherein, the difference between the size of the light-emitting repeating unit in the first direction and the size of the first repeating unit in the first direction is within a third preset range.
The display module according to claim 23, the third preset range is 0um to 5um.
The display module according to claim 23, the difference between the sum of the dimensions of the first repeating unit and the second isolation structure in the second direction and the dimension of the light-emitting repeating unit in the second direction The value is within a fourth preset range.
The display module according to claim 25, the fourth preset range is 0um to 10um.
The display module according to claim 5, the first pixel sub-circuit includes a light emission control line for receiving a light emission control signal, the first pixel sub-circuit includes a plurality of thin film transistors, and among the plurality of thin film transistors At least one of them is a low-temperature polycrystalline oxide transistor, and the two first pixel sub-circuits adjacently arranged in the first direction are symmetrically arranged with respect to a virtual symmetry plane, and share the same light emission control line, the The virtual symmetry plane is a plane perpendicular to the first direction.
According to the display module according to claim 27, it is defined that one adjacent first pixel circuit and one second pixel circuit jointly form a first repeating unit, and the second pixel sub-circuit includes a plurality of thin film transistors , at least one of the thin film transistors in the second pixel sub-circuit is a low-temperature polycrystalline oxide transistor, and the first repeating unit includes a plurality of the first pixel sub-circuits arranged in an array of 4n rows×8n columns , the second pixel circuit includes a plurality of second pixel sub-circuits arranged in an array of 4n rows×2m columns, wherein m and n are positive integers, and the row direction is parallel to the first direction, The row direction is perpendicular to the first direction and perpendicular to the thickness direction of the display module.
According to the display module according to claim 5, it is defined that one of the adjacent first pixel circuits and one of the first isolation structures jointly form a first repeating unit, and the first pixel sub-circuit and the second pixel sub-circuit The circuits respectively include a plurality of thin film transistors, and each of the thin film transistors in the first pixel sub-circuit and the second pixel sub-circuit is a low-temperature polycrystalline transistor, and the first repeating unit includes an array of 4n rows×4n columns a plurality of the first pixel sub-circuits arranged, and the second pixel circuit includes a plurality of the second pixel sub-circuits arranged in an array of 4n rows×1 column, wherein n is a positive integer, and the The row direction is parallel to the first direction, the column direction is perpendicular to the first direction, and perpendicular to the thickness direction of the display module.
According to the display module according to claim 1, the projection of the light-emitting device array on the virtual plane along the third direction completely covers the projection of the pixel circuit array on the virtual plane along the third direction, and the third direction is The thickness direction of the display module, the virtual plane is a plane perpendicular to the third direction.
A display device, comprising: the display module according to any one of claims 1-30.