WO2023000664A1

WO2023000664A1 - On-chip solid-state supercapacitor and preparation method therefor

Info

Publication number: WO2023000664A1
Application number: PCT/CN2022/076717
Authority: WO
Inventors: 朱宝; 尹睿; 张卫
Original assignee: 上海集成电路制造创新中心有限公司
Priority date: 2021-07-19
Filing date: 2022-02-18
Publication date: 2023-01-26
Also published as: CN113436904A; CN113436904B

Abstract

Provided in the present invention is an on-chip solid-state supercapacitor, comprising a first electrode and a second electrode which are structurally identical and symmetrically arranged, the first electrode comprising a silicon substrate, at least two silicon nanorods, a metal silicide layer, a TiVN thin film, an electrically conductive column, and a gel layer. The silicon nanorods are disposed on the silicon substrate, and the silicon nanorods are not in contact with each other. The metal silicide layer covers the silicon nanorods and the substrate. The TiVN thin film covers the metal silicide layer. The gel layer covers the TiVN thin film. The electrically conductive column is disposed on the metal silicide layer on the surface of any of the nanorods that faces away from the silicon substrate, and the electrically conductive column is not covered by the TiVN thin film and the gel layer. This reduces power loss and reduces costs, the structure is simple and convenient to prepare, and cyclic stability is enhanced. Also provided is a preparation method for an on-chip solid-state supercapacitor.

Description

On-chip solid-state supercapacitor and preparation method thereof

cross reference

This application claims the priority of Chinese patent application number 2021108150933 filed on July 19, 2021. The content of the above application is incorporated herein by reference.

technical field

The invention relates to the technical field of semiconductors, in particular to an on-chip solid supercapacitor and a preparation method thereof.

technical background

With the rapid development of wireless charging and the Internet of Things, chips that can achieve energy autonomy are required. Among electronic devices for energy storage, supercapacitors have attracted extensive attention due to their high power density and cycle life. Supercapacitors can store energy through an electrical double layer (electric double layer supercapacitor) or near-surface redox reactions (pseudocapacitance). In general, the energy density of pseudocapacitors is much greater than that of electric double-layer capacitors. In order to be able to integrate with silicon-based chips, supercapacitors need to be fabricated directly on the chip. Second, since additional packaging is required to prevent leakage of the liquid electrolyte, a solid electrolyte is the best choice. In other words, all-solid-state supercapacitors are more suitable for integration with silicon-based chips. In order to make full use of the silicon material, the silicon substrate can be structurally designed and used directly as an electrode material. Based on this idea, a large number of silicon-based nanostructures have been used as templates for the preparation of supercapacitors. Since silicon is easily oxidized and irreversible, the surface of silicon is usually covered with a passivation layer, such as graphene, carbon, titanium nitride, etc. However, these supercapacitors use the electric double layer to store charges, so the available energy density is relatively small.

In order to increase the energy density, metal oxides, such as ruthenium oxide, nickel oxide, manganese oxide, etc., can be introduced. These materials can undergo reversible redox reactions with the electrolyte, so that greater capacitance density and energy density can be obtained. At present, silicon nanopillar arrays are prepared by metal-assisted anode etching, and then a layer of ruthenium oxide is grown on the surface of silicon nanopillars by atomic layer deposition, and finally solid-state supercapacitors are assembled by injecting solid electrolyte. Although they have obtained good supercapacitive performance, ruthenium is a very rare noble metal, so the use of ruthenium oxide as the active electrode material will inevitably greatly increase the manufacturing cost. In addition, gold needs to be used as a catalyst in the metal-assisted anode etching process, which will also increase the manufacturing cost, and the metal-assisted anode etching process is complicated, which involves lithographically defined patterns of noble metals and electrochemical etching. Nickel oxide and manganese oxide have higher resistivities, so using these two materials as active electrode materials will result in lower power densities.

Recently, transition metal nitrides, such as TiN, VN, and MoxN, have also been studied as electrode materials for supercapacitors. Metal nitrides have higher electrical conductivity than oxides, and these materials are also less expensive. Among them, VN can undergo a reversible redox reaction with the electrolyte, so it has high capacitance density and energy density, and is a good pseudocapacitive material. On the contrary, TiN stores charge through the electric double layer, so the capacitance density is lower, but the cycle stability is better. In order to take advantage of the respective advantages of TiN and VN, some researchers used the co-sputtering method to prepare TiVN materials as active electrode materials for supercapacitors. Although higher capacitance density and better cycle stability can be obtained, they use a planar silicon substrate, so the capacitance density cannot be further improved. In addition, the co-sputtering method, that is, the physical vapor deposition method, has a low step coverage and cannot effectively fill TiVN materials in silicon nanostructures with high aspect ratios. Once holes appear, the electrolyte will directly contact the silicon substrate and irreversibly occur with it. The oxidation-reduction reaction affects the capacitance density and stability, and if the electrolyte is a KOH hydrated electrolyte, it is not conducive to integration with the chip.

Therefore, it is necessary to provide a novel on-chip solid-state supercapacitor and its preparation method to solve some of the above-mentioned problems in the prior art.

Summary of the invention

The object of the present invention is to provide an on-chip solid-state supercapacitor and a preparation method thereof, which is beneficial to reduce the cost, has a simple structure and is convenient for preparation.

In order to achieve the above object, the on-chip solid-state supercapacitor of the present invention includes a first electrode and a second electrode with the same structure and arranged symmetrically, and the first electrode includes a silicon substrate, at least two silicon nanocolumns, a metal silicide layer, TiVN thin film, conductive pillars and gel layer, the silicon nanopillars are arranged on the silicon substrate, and the silicon nanopillars are not in contact with each other, and the metal silicide layer covers the silicon nanopillars On the column and the substrate, the TiVN film is covered on the metal silicide layer, the gel layer is covered on the TiVN film, and the conductive column is arranged on any one of the nano-columns facing away from the on the metal silicide layer on one side of the silicon substrate, and the conductive column is not covered by the TiVN thin film and the gel layer.

The beneficial effect of the on-chip solid-state supercapacitor is that: the on-chip solid-state supercapacitor includes a first electrode and a second electrode with the same structure and symmetrically arranged, and the first electrode includes a silicon substrate, at least two silicon nanocolumns, a metal A silicide layer, a TiVN thin film, a conductive pillar and a gel layer, the silicon nanopillars are arranged on the silicon substrate, and the silicon nanopillars are not in contact with each other, and the metal silicide layer covers the On the silicon nanocolumn and the substrate, the TiVN film is covered on the metal silicide layer, the gel layer is covered on the TiVN film, and the conductive column is arranged on any one of the nanocolumn backs On the metal silicide layer on one side of the silicon substrate, and the conductive column is not covered by the TiVN thin film and the gel layer, the TiVN thin film is used as a pseudocapacitive material and has good electrical conductivity , can reduce power loss, and because there is no need to use noble metal materials such as ruthenium, the cost is reduced, and the structure is simple and easy to prepare; in addition, the metal silicide layer has extremely high conductivity relative to the silicon substrate, which can significantly reduce power loss and enhance cycle stability.

Preferably, the material of the metal silicide layer is any one of nickel silicide, titanium silicide, platinum-nickel alloy silicide, and cobalt silicide. The beneficial effect is that nickel silicide, titanium silicide, platinum-nickel alloy silicide, and cobalt silicide have high electrical conductivity, can reduce power loss, and enhance cycle stability.

Preferably, the silicon substrate has a resistivity of 8-12Ω·cm.

Preferably, the thickness of the metal silicide layer is 5-10 nm.

Preferably, the thickness of the TiVN thin film is 3-10 nm.

The present invention also provides a method for preparing an on-chip solid-state supercapacitor, comprising the following steps:

S1: Etching the silicon substrate to form at least two silicon nanopillars on the silicon substrate;

S2: Deposit a layer of metal on the surface of the silicon nanopillar and the substrate, and then form a metal silicide layer by annealing;

S3: forming a layer of TiVN thin film on the surface of the metal silicide layer;

S4: Injecting gel on the TiVN film to form a gel layer, the surface of the gel layer is flat;

S5: Etching the gel layer and the TiVN thin film to expose the metal silicide layer on any one side of the silicon nanocolumn facing away from the silicon substrate;

S6: Deposit and form a conductive column on the exposed metal silicide layer to form a first electrode;

S7: Repeat step S1 to step S6 to form a second electrode;

S8: symmetrically bonding the first electrode and the second electrode together and drying them to form the on-chip solid supercapacitor, wherein the gel layer of the first electrode and the second electrode The gel layer is the adhesive surface.

The beneficial effect of the preparation method of the on-chip solid supercapacitor is that: the TiVN thin film is used as a pseudocapacitive material, and at the same time it has good electrical conductivity, which can reduce power loss, and because it does not need to use noble metal materials such as ruthenium, the cost is reduced, and The structure is simple and easy to prepare; in addition, the metal silicide layer has extremely high electrical conductivity relative to the silicon substrate, which can significantly reduce power loss and enhance cycle stability.

Preferably, said etching the silicon substrate includes:

coating a layer of photoresist on the silicon substrate, and then forming at least two photolithographic patterns that are not connected to each other by photolithography;

The silicon substrate is etched using the photolithography pattern as a mask to form at least two silicon nanopillars on the silicon substrate.

Preferably, the depositing a layer of metal on the surface of the silicon nanocolumn and the substrate includes depositing a layer of metal on the surface of the silicon nanocolumn and the substrate by a physical vapor deposition process.

Preferably, the metal includes any one of nickel, titanium, platinum-nickel alloy, and cobalt.

Preferably, the growing a TiVN film on the surface of the metal silicide layer includes: growing a layer of the TiVN film by an atomic deposition process. The beneficial effect is that the adoption of the atomic layer deposition process can ensure that the grown TiVN thin film has good uniformity and shape retention.

Further preferably, the growing a layer of TiVN film on the surface of the metal silicide layer includes: first growing m-cycle titanium nitride, then growing n-cycle vanadium nitride to obtain a TiVN sub-film, and repeatedly generating the The TiVN sub-film is used to generate the TiVN film with a target thickness, m and n are both natural numbers greater than 0. The beneficial effect is that the atomic ratio of titanium atoms and vanadium atoms is adjusted by controlling the growth cycle ratio of growing titanium nitride and vanadium nitride, and the process is simple.

Preferably, the step S4 further includes mixing potassium hydroxide and polyvinyl alcohol to obtain the gel.

Description of drawings

Fig. 1 is the flow chart of the preparation method of on-chip solid supercapacitor of the present invention;

Fig. 2 is the structure schematic diagram after forming photolithographic pattern on silicon substrate;

FIG. 3 is a schematic structural view of the structure of FIG. 2 after etching;

FIG. 4 is a schematic view of the structure of FIG. 3 after the photoresist is removed;

Fig. 5 is a schematic diagram of the structure of Fig. 4 after depositing metal;

FIG. 6 is a schematic structural view of the structure of FIG. 5 after annealing;

FIG. 7 is a schematic diagram of the structure of FIG. 6 after depositing a TiVN thin film;

Fig. 8 is a schematic diagram of the structure shown in Fig. 7 after injecting gel and forming conductive pillars;

FIG. 9 is a schematic structural diagram of an on-chip solid-state supercapacitor formed with the structure shown in FIG. 8 .

Contents of the invention

In order to make the purpose, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are part of the present invention Examples, not all examples. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the usual meanings understood by those skilled in the art to which the present invention belongs. As used herein, "comprising" and similar words mean that the elements or items appearing before the word include the elements or items listed after the word and their equivalents, without excluding other elements or items.

In view of the problems existing in the prior art, the embodiment of the present invention provides a schematic structural diagram of an on-chip solid-state supercapacitor. The on-chip solid-state supercapacitor includes a first electrode and a second electrode that are symmetrically arranged with the same structure, and the first electrode includes a silicon substrate, at least two silicon nanocolumns, a metal silicide layer, a TiVN film, a conductive column, and a condensate A glue layer, the silicon nanocolumns are arranged on the silicon substrate, and the silicon nanocolumns are not in contact with each other, and the metal silicide layer covers the silicon nanocolumns and the substrate, so The TiVN thin film is covered on the metal silicide layer, the gel layer is covered on the TiVN thin film, and the conductive column is arranged on any metal silicide on the side of the nano-pillar facing away from the silicon substrate. layer, and the conductive pillars are not covered by the TiVN thin film and the gel layer.

In some embodiments, the silicon substrate is a P-type silicon substrate, and the silicon nanocolumns are cylindrical, prismatic, etc., without any restriction on the shape of the silicon nanocolumns, and do not affect the on-chip The technical effect that a solid supercapacitor can finally achieve, the material of the metal silicide layer is any one of nickel silicide, titanium silicide, platinum-nickel alloy silicide, and cobalt silicide.

In some embodiments, the resistivity of the silicon substrate is 8-12 Ω·cm, the thickness of the metal silicide layer is 5-10 nm, and the thickness of the TiVN thin film is 3-10 nm.

Fig. 1 is a flow chart of the preparation method of the on-chip solid supercapacitor of the present invention. FIG. 2 is a schematic structural view after forming a photolithographic pattern on a silicon substrate. FIG. 3 is a schematic structural view of the structure shown in FIG. 2 after etching. FIG. 4 is a schematic diagram of the structure shown in FIG. 3 after removing the photoresist. FIG. 5 is a schematic diagram of the structure of FIG. 4 after depositing metal. FIG. 6 is a schematic diagram of the structure shown in FIG. 5 after annealing. FIG. 7 is a schematic diagram of the structure shown in FIG. 6 after depositing a TiVN thin film. FIG. 8 is a schematic diagram of the structure shown in FIG. 7 after gel is injected to form conductive pillars. FIG. 9 is a structural schematic diagram of two on-chip solid-state supercapacitors formed with the structures shown in FIG. 8 .

Referring to Figures 1-9, the preparation method of the on-chip solid-state supercapacitor comprises the following steps:

S1: Etching the silicon substrate to form at least two silicon nanopillars on the silicon substrate.

In some embodiments, the etching the silicon substrate includes: coating a layer of photoresist on the silicon substrate, and then forming at least two photolithographic patterns that are not connected to each other by photolithography; The pattern is a mask, and the silicon substrate is etched to form at least two silicon nanocolumns on the silicon substrate. Wherein, the etching is dry etching or wet etching, and the dry etching is any one of ion milling etching, plasma etching, reactive ion etching, and laser ablation. Further, the diameter of the silicon nanocolumn can be changed by changing the diameter of the photolithography pattern, the density of the silicon nanocolumn can be changed by changing the density of the photolithography pattern, and the etching power and The height of the silicon nanopillars can be changed over time, and the density is the quantity per unit area.

Specifically, a layer of photoresist is coated on the silicon substrate 200, and then a first cylindrical photoresist pattern 301, a second cylindrical photoresist pattern 302, and a third cylindrical photoresist pattern are formed by photolithography. Pattern 303 and the fourth cylindrical photoresist pattern 304, structure as shown in Figure 2; The engraved pattern 303 and the fourth cylindrical photolithographic pattern 304 are masks, and the silicon substrate 200 is etched by an ion milling etching process to form the first silicon nanocolumn 201, the second silicon nanocolumn 202, the Three silicon nanocolumns 203 and the fourth silicon nanocolumns 204, structure as shown in Figure 3; Then remove described first cylindrical photolithographic pattern 301, described second cylindrical photolithographic pattern 302, described first cylindrical photolithographic pattern 302 by acetone The three cylindrical photolithographic patterns 303 and the fourth cylindrical photolithographic pattern 304 are structured as shown in FIG. 4 .

S2: Deposit a layer of metal on the surface of the silicon nanopillar and the substrate, and then form a metal silicide layer by annealing.

In some embodiments, the depositing a layer of metal on the surface of the silicon nanocolumn and the substrate includes depositing a layer of metal on the surface of the silicon nanocolumn and the substrate by a physical vapor deposition process. Wherein, the metal includes any one of nickel, titanium, platinum-nickel alloy, and cobalt, and the annealing is any one of a rapid thermal annealing process, a laser annealing process, and a microwave annealing process.

Specifically, the surface of the first silicon nanocolumn 201, the surface of the second silicon nanocolumn 202, the surface of the third silicon nanocolumn 203, the fourth silicon nanocolumn 204, etc. The surface of the silicon substrate 200 and the surface of the silicon substrate 200 is deposited with a thickness of 7nm metal nickel layer 400, as shown in FIG. Nickel silicide, that is, the metal silicide layer 401 has a structure as shown in FIG. 6 .

S3: forming a layer of TiVN thin film on the surface of the metal silicide layer.

In some embodiments, the growing a TiVN film on the surface of the metal silicide layer includes: growing a layer of the TiVN film by an atomic deposition process. Specifically, the growing a layer of TiVN film on the surface of the metal silicide layer includes: first growing m-cycle titanium nitride, then growing n-cycle vanadium nitride to obtain a TiVN sub-film, and repeatedly generating the The TiVN sub-film is used to generate the TiVN film with a target thickness, and both m and n are natural numbers greater than 0. Among them, by controlling the growth cycle ratio of growing titanium nitride and vanadium nitride, adjusting the atomic ratio of titanium atoms and vanadium atoms, the process is simple, and the TiVN film is used as the active electrode material of the on-chip solid supercapacitor and the metal The passivation layer of the silicide layer.

Specifically, a TiVN thin film 500 with a thickness of 8 nm is grown on the surface of the metal silicide layer 401 by atomic deposition process, as shown in FIG. 7 .

S4: injecting gel on the TiVN thin film to form a gel layer, the surface of the gel layer is flat.

In some embodiments, the step S4 further includes mixing potassium hydroxide and polyvinyl alcohol to obtain the gel. Wherein, the gel is used as a solid electrolyte for the on-chip solid supercapacitor. Specifically, the side of the gel layer facing away from the silicon substrate is plane and parallel to the surface of the silicon substrate.

S5: Etching the gel layer and the TiVN thin film to expose the metal silicide layer on any one side of the silicon nanocolumn facing away from the silicon substrate.

S6: Deposit and form a conductive column on the exposed metal silicide layer to form a first electrode.

Specifically, etching the gel layer 600 and the TiVN film 500 on the upper side of the first silicon nanocolumn 201 to expose the nickel silicide on the upper side of the first silicon nanocolumn 201, and then The upper side of nickel silicide on the upper side of a silicon nanopillar 201 is deposited to form the conductive pillar 700 to form the first electrode 10 , as shown in FIG. 8 .

S7: Repeat step S1 to step S6 to form the second electrode 20 .

Specifically, with the gel layer of the first electrode 10 and the gel layer of the second electrode 20 as the bonding surface, the first electrode 10 and the second electrode 20 are symmetrically bonded together and Drying is carried out to form the on-chip solid-state supercapacitor, as shown in FIG. 9 .

Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and changes can be made to the embodiments. However, it should be understood that such modifications and changes are within the scope and spirit of the present invention described in the claims. Furthermore, the invention described herein is capable of other embodiments and of being practiced or carried out in various ways.

Claims

An on-chip solid-state supercapacitor is characterized in that it includes a first electrode and a second electrode with the same structure and symmetrically arranged, and the first electrode includes a silicon substrate, at least two silicon nanocolumns, a metal silicide layer, and a TiVN thin film , conductive pillars and a gel layer, the silicon nanopillars are arranged on the silicon substrate, and the silicon nanopillars are not in contact with each other, and the metal silicide layer covers the silicon nanopillars and the silicon nanopillars On the substrate, the TiVN film is covered on the metal silicide layer, the gel layer is covered on the TiVN film, and the conductive column is arranged on any one of the nano-columns facing away from the silicon substrate On one side of the metal silicide layer, and the conductive column is not covered by the TiVN thin film and the gel layer.
The on-chip solid-state supercapacitor according to claim 1, wherein the material of the metal silicide layer is any one of nickel silicide, titanium silicide, platinum-nickel alloy silicide, and cobalt silicide.
The on-chip solid-state supercapacitor according to claim 1, wherein the resistivity of the silicon substrate is 8-12Ω·cm.
The on-chip solid supercapacitor according to claim 1, wherein the metal silicide layer has a thickness of 5-10 nm.
The on-chip solid-state supercapacitor according to claim 1, wherein the thickness of the TiVN thin film is 3-10 nm.
A method for preparing an on-chip solid-state supercapacitor, comprising the following steps:

S1: Etching the silicon substrate to form at least two silicon nanopillars on the silicon substrate;

S2: Deposit a layer of metal on the surface of the silicon nanocolumn and the substrate, and then form a metal silicide layer by annealing;

S3: forming a layer of TiVN thin film on the surface of the metal silicide layer;

S4: Injecting gel on the TiVN film to form a gel layer, the surface of the gel layer is flat;

S5: Etching the gel layer and the TiVN thin film to expose the metal silicide layer on any one side of the silicon nanocolumn facing away from the silicon substrate;

S6: Deposit and form a conductive column on the exposed metal silicide layer to form a first electrode;

S7: Repeat step S1 to step S6 to form a second electrode;

S8: symmetrically bonding the first electrode and the second electrode together and drying them to form the on-chip solid supercapacitor, wherein the gel layer of the first electrode and the second electrode The gel layer is the adhesive surface.
The method for preparing a solid-state supercapacitor according to claim 6, wherein said etching a silicon substrate comprises:

coating a layer of photoresist on the silicon substrate, and then forming at least two photolithographic patterns that are not connected to each other by photolithography;

The silicon substrate is etched using the photolithography pattern as a mask to form at least two silicon nanopillars on the silicon substrate.
The method for preparing a solid supercapacitor according to claim 6, wherein depositing a layer of metal on the surface of the silicon nanocolumn and the substrate comprises depositing a layer of metal on the silicon nanocolumn by a physical vapor deposition process. A layer of metal is deposited on the surface as well as the substrate.
The method for preparing a solid supercapacitor according to claim 6, wherein the metal comprises any one of nickel, titanium, platinum-nickel alloy, and cobalt.
The method for preparing a solid supercapacitor according to claim 6, wherein said growing a layer of TiVN thin film on the surface of said metal silicide layer comprises: growing a layer of said TiVN thin film by an atomic deposition process.
The method for preparing a solid-state supercapacitor according to claim 10, wherein growing a layer of TiVN film on the surface of the metal silicide layer comprises: first growing m-cycle titanium nitride, and then growing n-cycle titanium nitride vanadium nitride to obtain a TiVN sub-film, and repeatedly generate the TiVN sub-film to generate the TiVN film with a target thickness, m and n are both natural numbers greater than 0.
The method for preparing a solid supercapacitor according to claim 6, wherein the step S4 further comprises mixing potassium hydroxide and polyvinyl alcohol to obtain the gel.