WO2022267341A1 - 数据处理装置、方法、计算机设备及存储介质 - Google Patents

数据处理装置、方法、计算机设备及存储介质 Download PDF

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Publication number
WO2022267341A1
WO2022267341A1 PCT/CN2021/133744 CN2021133744W WO2022267341A1 WO 2022267341 A1 WO2022267341 A1 WO 2022267341A1 CN 2021133744 W CN2021133744 W CN 2021133744W WO 2022267341 A1 WO2022267341 A1 WO 2022267341A1
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processor
port
multiplexer
data processing
controller
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PCT/CN2021/133744
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English (en)
French (fr)
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黄炎坡
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深圳市商汤科技有限公司
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Publication of WO2022267341A1 publication Critical patent/WO2022267341A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3006—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system is distributed, e.g. networked systems, clusters, multiprocessor systems

Definitions

  • the present disclosure relates to the field of computer technology, and in particular, to a data processing device, method, computer equipment, and storage medium.
  • edge servers can be constructed by deploying a central processing unit (Central Processing Unit, CPU) system.
  • CPU Central Processing Unit
  • the edge server will not work normally, resulting in poor system stability.
  • Embodiments of the present disclosure at least provide a data processing device, method, computer equipment, and storage medium.
  • an embodiment of the present disclosure provides a data processing device, including: including a controller, one or more multiplexers, a first processor, and a second processor; wherein, the controller and The multiplexer, the first processor, and the second processor are connected; each of the one or more multiplexers is connected to the first processor, and the The second processor is connected; the controller is configured to send a first port strobe signal to the one or more multiplexers in response to detecting that the working state of the first processor is abnormal; Each of the one or more multiplexers is configured to gate the connection between the multiplexer and the second processor in response to receiving the first port gate signal sent by the controller.
  • a data transmission channel; the second processor is configured to switch from a non-working state to a working state in response to the data transmission channel between the one or more multiplexers and the second processor being strobed state.
  • the working state of the first processor when the working state of the first processor is abnormal, it can be switched to the second processor in time, and the second processor can continue to execute the unfinished data processing tasks of the first processor, thereby improving the reliability of the system.
  • each of the one or more multiplexers includes: a first data transmission port connected to the controller, a second port connected to the first processor a data transfer port, a third data transfer port connected to the second processor; each of the one or more multiplexers configured to respond to receiving the The first port gating signal sent by the controller, through the third data transmission port connected between the multiplexer and the second processor, gating the multiplexer and the second processor channels between devices.
  • the multiplexer can receive the first off-on strobe signal sent by the controller through the first port strobe signal, and strobe the connection between the multiplexer and the second processor through the third data transmission port. aisle. Since the multiplexer includes a plurality of data transmission ports, it can effectively receive signals sent by different devices in the data processing device, and similarly, can effectively send signals to different devices in the data processing device; and, using Different ports send different signals, which is more conducive to the normal and safe transmission of different signals.
  • the number of the multiplexers in the data processing device is at least two; different multiplexers are respectively connected to different external devices.
  • each of the one or more multiplexers further includes a fourth data transmission port, and the multiplexer communicates with the corresponding external device through the fourth data transmission port connection; the multiplexer is also used to receive the first signal transmitted by the corresponding external device through the fourth data transmission port, and send the first signal to the second through the third data transmission port A processor; and/or, receiving a second signal sent by the second processor through the third data transmission port, and sending the second signal to a corresponding external device through the fourth data transmission port.
  • the external device includes at least one of the following: a network card, and a hard disk.
  • the controller sends a first port strobe signal to the one or more multiplexers in response to detecting that the working state of the first processor is abnormal
  • a first port strobe signal to the one or more multiplexers in response to detecting that the working state of the first processor is abnormal
  • the controller sends a first port strobe signal to the one or more multiplexers in response to detecting that the working state of the first processor is abnormal
  • it is used for: in response to detecting that the working state of the first processor is abnormal and detecting that the working state of the second processor is normal, sending the first processor to the one or more multiplexers A port strobe signal.
  • the controller is further configured to monitor the working state of the second processor.
  • the controller when monitoring the working state of the processor, is configured to: receive a heartbeat signal sent by the processor; in response to not receiving the heartbeat signal within a preset time period, Then it is determined that the working state of the processor is abnormal; wherein the processor includes: the first processor and/or the second processor.
  • the controller is further configured to: after sending the first port strobe signal to the one or more multiplexers, in response to monitoring the The working state is switched from abnormal to normal, and a second port strobe signal is sent to the one or more multiplexers; each of the one or more multiplexers is also used to respond to receiving After the second port strobe signal sent by the controller, the data transmission channel between the multiplexer and the first processor is gated based on the second port strobe signal.
  • the controller is further configured to: respond to receiving an active switching signal sent by the first processor or the second processor, send the one or more multiplexed
  • Each of the one or more multiplexers is also configured to respond to receiving the third port gating signal sent by the controller, based on the second port Strobe signal, from the first processor and the second processor, determine the target processor that is currently in a non-working state; strobe the data transmission channel between the multiplexer and the target processor .
  • a processor with a lower computing power can be selected as the first processor, and a processor with a higher computing power can be selected as the second processor, and in the process of executing the data processing task, the processing of the data processing task can be dynamically switched.
  • the processor while ensuring normal and accurate data processing tasks, can effectively reduce equipment costs because the cost of the first processor with lower computing power is lower.
  • the controller includes: a complex programmable logic device (Complex Programmable Logic Device, CPLD).
  • CPLD Complex Programmable Logic Device
  • the first processor is further configured to synchronize the working status information to the second processor; the second processor responds to the one or more multiplexed When the data transmission channel between the user and the second processor is gated and switched from the non-working state to the working state, it is used for: responding to the one or more multiplexing in the data processing device The user gates a data transmission channel with the second processor, and rebuilds a working state based on the working state synchronization information.
  • the processor executing the task in the data processing device can continue to complete the data processing task in time. Therefore, for the data processing device, it can ensure the efficiency of data processing by continuously executing data processing tasks.
  • the embodiment of the present disclosure also provides a data processing method, which is applied to the data processing device provided in the embodiment of the present disclosure;
  • the data processing device includes: a controller, one or more multiplexers, a first processor, and a second processor;
  • the data processing method includes: the controller sends the first A port gating signal; each of the one or more multiplexers, in response to receiving a first port gating signal sent by the controller, gating the multiplexer and the multiplexer A data transmission channel between a second processor; the second processor responds to the data transmission channel between the one or more multiplexers and the second processor being gated, by a non-operating The state switches to the working state.
  • each of the one or more multiplexers includes: a first data transmission port connected to the controller, a second port connected to the first processor a data transfer port, a third data transfer port connected to the second processor; each of the one or more multiplexers responding to receiving a first port select communication sent by the controller number, gating the data transmission channel between the multiplexer and the second processor, comprising: each of the one or more multiplexers, in response to passing the first data
  • the transmission port receives the first port strobe signal sent by the controller, and selects the multiplexer and the third data transmission port connected to the second processor through the multiplexer. channel between the second processors.
  • the number of the multiplexers in the data processing device is at least two; different multiplexers are respectively connected to different external devices.
  • the one or more multiplexers in the data processing device further include a fourth data transmission port, and the multiplexer communicates with Corresponding to the external device connection; the data processing method further includes: the multiplexer receives the first signal transmitted by the corresponding external device through the fourth data transmission port, and transmits the first signal through the third data transmission port port to the second processor; and/or, receive the second signal sent by the second processor through the third data transmission port, and pass the second signal through the fourth data transmission port Send to the corresponding external device.
  • the external device includes at least one of the following: a network card, and a hard disk.
  • the controller sends a first port strobe signal to the one or more multiplexers in response to detecting that the working state of the first processor is abnormal, including : the controller sends the one or more multiplexers the The first port strobe signal.
  • the method further includes: the controller monitors the working state of the second processor.
  • the controller monitors the working state of the processor, including: the controller receives a heartbeat signal sent by the processor; in response to not receiving the heartbeat signal within a preset time period, It is determined that the working state of the processor is abnormal; wherein the processor includes: the first processor and/or the second processor.
  • it further includes: after the controller sends a first port strobe signal to the one or more multiplexers, in response to monitoring the operation of the first processor The state is switched from abnormal to normal, and a second port strobe signal is sent to the one or more multiplexers; each of the one or more multiplexers responds to receiving the control After the second port strobe signal sent by the multiplexer, the data transmission channel between the multiplexer and the first processor is gated based on the second port strobe signal.
  • the controller responds to receiving the active switching signal sent by the first processor or the second processor, sending the one or more multiplex The controller sends a third port strobe signal; each of the one or more multiplexers, in response to receiving the third port strobe signal sent by the controller, based on the second port strobe signal, From the first processor and the second processor, determine a target processor that is currently in a non-working state; and select a data transmission channel between the multiplexer and the target processor.
  • the controller includes: a complex programmable logic device CPLD.
  • the data processing method further includes: the first processor synchronizing the working status information to the second processor; the second processor responding to the one or more The data transmission channel between the multiplexer and the second processor is gated, and switched from the non-working state to the working state, including: the second processor responds to the One or more multiplexers gate a data transmission channel with the second processor, and recreate a working state based on the working state synchronization information.
  • an optional implementation manner of the present disclosure further provides a computer device, a processor, and a memory, the memory stores machine-readable instructions executable by the processor, and the processor is used to execute the instructions stored in the memory.
  • the machine-readable instructions execute the steps in any one of the possible implementation manners of the third aspect above when executed by the processor.
  • an optional implementation mode of the present disclosure further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed, any possible implementation in the above-mentioned third aspect is executed. steps in the method.
  • FIG. 1 shows a schematic diagram of a data processing device provided by an embodiment of the present disclosure
  • Fig. 2 shows a schematic circuit connection diagram of a data processing device provided by an embodiment of the present disclosure
  • Fig. 3 shows a schematic diagram of a specific example of a data processing apparatus provided by an embodiment of the present disclosure when performing a data processing task
  • FIG. 4 shows a structural diagram of a Multiplexer provided by an embodiment of the present disclosure
  • Fig. 5 shows a flowchart of a data processing method provided by an embodiment of the present disclosure.
  • edge server when building an edge server, it is usually implemented by deploying a central processing unit, that is, the edge server relies on the central processing unit when performing data processing tasks. Once the central processing unit fails during operation, the edge server will not operate normally, resulting in poor system stability of the edge server.
  • the present disclosure provides a data processing device, which uses a controller to detect the working state of the first processor, and if it is abnormal, it can send a first port strobe signal to the multiplexer to A data transmission channel with the second processor is selected, thereby switching to the second processor.
  • This method can switch to the second processor in time when the working state of the first processor is abnormal, and use the second processor to continue to execute the unfinished data processing tasks of the first processor, thereby improving the reliability of the system.
  • the data processing apparatus provided by the embodiment of the present disclosure can not only be used in an edge server, but also can be used in other computer equipment.
  • the reliability of the computer equipment can be improved by deploying the data processing apparatus provided by the embodiments of the present disclosure in the computer equipment.
  • FIG. 1 it is a schematic diagram of a data processing device provided by an embodiment of the present disclosure; wherein, the data processing device includes a controller 10, a multiplexer 20, a first processor 30, and a second processor 40 ;
  • the controller 10 is connected to the multiplexer 20, the first processor 30, and the second processor 40; the multiplexer 20 is connected to the first processor 30, And the second processor 40 is connected;
  • the controller 10 is configured to send a first port strobe signal to the multiplexer 20 in response to detecting that the working state of the first processor 30 is abnormal;
  • the multiplexer 20 is configured to gate the data transmission between the multiplexer 20 and the second processor 40 in response to receiving the first port gating signal sent by the controller 10 aisle;
  • the second processor 40 is configured to switch from the non-working state to the working state in response to the data transmission channel between the multiplexer 20 and the second processor 40 being gated.
  • a data processing device uses the controller 10 to monitor the working state of the first processor 30, and sends a second A port selection signal, so that the multiplexer 20 can select the data transmission channel between the multiplexer 20 and the second processor 40 based on the first port selection signal.
  • This method can switch to the second processor 40 in time when the working state of the first processor 30 is abnormal, and use the second processor 40 to continue to execute the unfinished data processing tasks of the first processor 30, thereby improving the system performance. reliability.
  • the first processor 30 may be, for example, the same type of processor as the second processor 40; The computing power of the processor 40 is higher than that of the first processor 30 .
  • the corresponding second processor 40 may include backup processors, and there may be at least one second processor 40, for example, to ensure stability.
  • multiple multiplexers 20 connected to each external device may also be provided with multiple multiplexers, wherein the number of multiplexers is related to the second processing The number of switches 40 and the number of second data transmission ports in the multiplexer are related.
  • a complex programmable logic device CPLD may be included.
  • the data processing apparatus includes a first processor 30 and a second processor 40 , and includes a multiplexer 20 and a controller 10 as an example for illustration.
  • the controller 10 responds to detecting that the working state of the first processor 30 is abnormal, for example, by sending a first port strobe signal to the multiplexer 20 to enable
  • the multiplexer 20 responds to the first port strobe signal, gates the data transmission channel between the multiplexer 20 and the second processor 40, so that the second processor 40 is switched from the non-working state to the working state state.
  • the multiplexer 20 includes: a first data transmission port connected to the controller 10, a second data transmission port connected to the first processor 30, and a second data transmission port connected to the second processor 30. 40 connection to the third data transfer port.
  • the controller 10 detects that the working state of the first processor 30 is abnormal, for example, it may send a first port strobe signal to the first data transmission port of the multiplexer 20 .
  • the multiplexer 20 can be connected to the third data transmission port of the second processor 40 to select multiplexers. The channel between the multiplexer 20 and the second processor 40 .
  • the multiplexer 20 further includes, for example, a fourth data transmission port, and the multiplexer 20 is connected to a corresponding external device through the fourth data transmission port.
  • the multiplexer 20 is also configured to receive the first signal transmitted by the corresponding external device through the fourth data transmission port, and send the first signal to the fourth data transmission port through the third data transmission port.
  • the second processor 40 and/or, receive the second signal sent by the second processor 40 through the third data transmission port, and send the second signal to the corresponding through the fourth data transmission port sent by an external device.
  • the external device includes at least one of the following: a network card, and a hard disk.
  • the external device in the data processing apparatus may include, for example, one.
  • the first processor 30 and the second processor 40 are externally connected to the same network card, and are respectively connected to different hard disks; or, the first processor 30 and the second processor 40 are externally connected to the same hard disk, and are respectively connected to different network card.
  • the data processing device includes multiple external devices; correspondingly, the data processing device includes at least two multiplexers 20, and different multiplexers 20 are connected to different External device connection. As shown in Fig. 2, two multiplexers 20 are included, including a multiplexer 1 and a multiplexer 2; wherein the multiplexer 1 is connected to the network card in the external device, multiplexers The multiplexer 2 is connected with the hard disk in the external device.
  • the fourth data transmission port receives the data transmitted by the corresponding external device.
  • first signal the external device is a network card
  • the corresponding first signal may include, for example, a network signal.
  • the fourth data transmission port in the multiplexer 20 receives the first signal
  • the first signal may be sent to the second processor 40 through the third data transmission port.
  • the multiplexer 1 may also receive the second signal sent by the second processor 40 through the third data transmission port.
  • the second signal may include, for example, a feedback signal from the second processor 40 on the network status.
  • the multiplexer 1 may also send the second signal to the corresponding external device through the fourth data transmission port.
  • the corresponding external device is also a network card.
  • the controller 10 when it is determined that any one of the first processor 30 or the second processor 40 executes the data processing task, the controller 10 can be used to monitor the working state of the processor, and determine that the current switch to the second processor 40 is One of the first processor 30 and the second processor 40 .
  • the controller 10 when the controller 10 monitors the working state of the processor, it is used to receive the heartbeat signal sent by the processor; if the heartbeat signal is not received within a preset period of time, then determine the working state of the processor Abnormal.
  • the processor when the processor is working normally, for example, it may send a heartbeat signal at a fixed frequency according to its corresponding clock cycle.
  • its corresponding clock cycle may include, for example, 2 milliseconds, and the first processor 30 will send a heartbeat signal at a frequency of 2 milliseconds per time when the first processor 30 is working normally.
  • the frequency of sending the heartbeat signal will be lower than the frequency of sending the heartbeat signal when it is working normally, or stop sending the heartbeat signal to the controller 10 .
  • the preset duration can be directly determined according to the corresponding clock cycle of the processor, for example, the corresponding preset duration is set to 2 milliseconds for the first processor 30 .
  • the processor can allow self-recovery, set the preset duration to be longer than the clock cycle, for example, 4 milliseconds; if no heartbeat signal is received within 4 milliseconds, the processor is considered to have failed self-recovery, and That is, the working status is abnormal.
  • the preset duration can be determined according to the actual situation.
  • a shorter preset duration can be set; if the timeliness requirement of task processing is low, A longer preset duration can be set; in addition, the preset duration can be dynamically adjusted according to the number of current pending tasks; if the number of pending tasks is large, a shorter preset duration can be set to ensure multi-tasking It can be executed in time; if the number of tasks to be processed is small, a longer preset duration can be set to give the first processor 30 enough time to perform self-recovery and reduce the extra loss caused by processor switching. Let me repeat.
  • the controller 10 can also monitor its working state; the specific process is similar to the way the controller 10 monitors the working state of the first processor 30 above, and will not be repeated here.
  • the obtained monitoring results include: the working state is normal or the working state is abnormal.
  • the controller 10 monitors the corresponding working states of the first processor 30 and the second processor 40 , it includes but not limited to the following three situations (A), (B) and (C).
  • the controller 10 detects that the working state of the first processor 30 is abnormal, and may choose to switch to the second processor 40 to continue processing tasks.
  • it may include but not limited to the following two situations (a1) or (a2):
  • the controller 10 when the controller 10 sends the first port strobe signal to the multiplexer 20, it is used for: responding to detecting that the working state of the first processor 30 is abnormal and detecting that the second processing The working state of the device 40 is normal, and the first port strobe signal is sent to the multiplexer 20 .
  • the controller 10 can send a first port strobe signal to the multiplexer 20 to Complete the processor switch.
  • the first port gate signal is used to instruct the multiplexer 20 to gate the data transmission channel between the multiplexer 20 and the second processor 40 .
  • the second processor 40 can continue to execute the data processing task to be completed by the first processor 30 .
  • the controller 10 in order to prevent the controller 10 from monitoring back and forth between the first processor 30 and the second processor 40 when both the first processor 30 and the second processor 40 have abnormal working states, for example, when the first processor 30 is monitored After the state is abnormal, monitor the working state of the second processor 40; The condition of the processor 40.
  • the controller 10 detects that the working states of the first processor 30 and the second processor 40 are both abnormal, for example, it will stop monitoring and report an error, waiting for maintenance by inspectors. In this way, the loss of the controller 10 during monitoring can also be effectively reduced, and the data processing device can be prevented from falling into an endless loop during operation and unable to jump out, and work normally.
  • the multiplexer 20 is further configured to gate the The data transmission channel between the multiplexer 20 and the first processor 30 .
  • the controller 10 detects that the first processor 30 is changed from abnormal to normal, then the control can be switched to the first processor 30 again.
  • the controller 10 when the controller 10 detects that the working state of the first processor 30 changes from abnormal to normal, it may send the second port strobe signal to the multiplexer 20 .
  • the second port gating signal is used to indicate the data transmission channel between the gating multiplexer 20 and the first processor 30 .
  • the data transmission channel When the data transmission channel is enabled, it can be switched to the first processor 30 continuing to process the data processing task according to the current processing status of the second processor 40 .
  • the second processor 40 can be used as the backup processor when the first processor 30 cannot be used normally. When switching again, the first processor 30 continues to execute the data processing task. In this manner, possible data processing task interruptions and/or excessively long fault delays that may occur when the first processor 30 is in an abnormal working state can be used to ensure safe and stable operation of the data processing tasks.
  • the first processor 30 is more likely to appear in an abnormal working state, but can also self-recover within a short period of time, for example, when the first processor 30 is aging or working for a long time, the second The first processor 30 will work abnormally due to its high temperature due to self-heating; The controller 10 detects that the first processor 30 can work normally, and then switches from the second processor 40 to the first processor 30 . In this way, there will be too frequent high-frequency switching between the first processor 30 and the second processor 40 .
  • the second processor 40 when the second processor 40 is processing the task, even if the controller 10 detects that the working state of the first processor 30 is switched from abnormal to normal, it still chooses to continue to execute the data processing task by the second processor 40 . In this way, the phenomenon of high-frequency switching between the first processor 30 and the second processor 40 can be reduced, and the problem of reduced processing efficiency caused by frequent switching between the first processor 30 and the second processor 40 can be avoided.
  • the controller 10 sends a third port gating signal to the multiplexer 20 in response to receiving the active switching signal sent by the first processor 30 or the second processor 40 .
  • the multiplexer 20 is further configured to, in response to receiving the third port gating signal sent by the controller 10, based on the third port gating signal, from the first processing In the device 30 and the second processor 40, determine the target processor that is currently in a non-working state; select the data transmission channel between the multiplexer 20 and the target processor.
  • the third port strobe signal is used to instruct the multiplexer 20 to strobe the data transmission channel between the multiplexer 20 and the target processor which is currently in a non-working state.
  • the first processor 30 and the second processor 40 can actively send an active switching signal, so that the controller 10 can send a third port gating signal, and control the multiplexer 20 to switch the gating signal.
  • the data transmission channel between the processor in the current non-working state and the multiplexer 20 can be actively sent.
  • the first processor 30 is performing a data processing task, the first processor 30 is connected to the data transmission channel of the multiplexer 20, and the first processor 30 is working normally. At this time, the first processor 30 may actively send an active switching signal, and the second processor 40 will continue to execute the task after switching.
  • the first processor 30 and the second processor 40 may be set as processors of different models and different computing powers.
  • the computing power of the first processor 30 is, for example, low, and the data processing tasks that can be processed are relatively simple; the second processor 40 has higher computing power than the first processor 30, and can handle relatively simple tasks. Complex or large data processing tasks.
  • the cost of the second processor 40 is also higher than that of the first processor 30 .
  • the data processing task includes more simple calculation subtasks and some complex calculation subtasks.
  • the first processor 30 can complete the subtasks of simple calculations, but it is difficult to complete the subtasks of complex calculations; the second processor 40 can complete the subtasks of complex calculations. Subtasks, or support for a larger number of tasks to execute in parallel.
  • the second processor 40 can make up for the shortage of computing power of the first processor 30 .
  • the first processor 30 when executing the processing of the complex calculation subtask, it can send an active switching signal, so that the controller 10 can send the multiplexed
  • the controller 20 sends a third port strobe signal to switch the processor.
  • the second processor 40 continues to execute the more complex subtasks in the data processing task, and after processing the more complex subtasks, sends an active switching signal to the controller 10, and then switches to the first processor 30 again to execute Simpler subtasks.
  • processors in the task dimension For example, tasks that consume more computing power will be switched to the second processor 40 for execution; tasks that consume less computing power will be switched to the first processor 30. implement.
  • the processor currently in use is the first processor 30; the first processor 30 may send an active switching signal to the controller when the current number of data processing tasks is greater than a preset number, so that the controller Send a third port strobe signal to the multiplexer to switch to the second processor 40; when the number of current data processing tasks changes to less than or equal to the preset number, the second processor 40 can also send The controller sends an active switch signal to cause the controller to send a third port strobe signal to the multiplexer to switch back to the first processor 30 .
  • the controller 10 since it is impossible to determine whether the second processor 40 can work normally after the first processor 30 sends the active switching signal, the controller 10 also needs to monitor the working state of the second processor 40; The working state of the second processor 40 is normal, and then the processor is switched.
  • a processor with a lower computing power can be selected as the first processor 30, and a processor with a higher computing power can be selected as the second processor 40, and in the process of executing the data processing task, the data processing task can be dynamically switched.
  • the processor while ensuring that the data processing tasks can be completed normally and accurately, at the same time, because the cost of the first processor 30 with lower computing power is lower, the equipment cost can be effectively reduced.
  • processors can perform different tasks to reduce the loss of each processor, prolong the service life of the processor, and reduce the cost of the processor in disguise.
  • (c2) The first processor 30 is executing a data processing task. At this time, the second processor 40 may actively send an active switching signal, and the second processor 40 will continue to execute the task after switching.
  • the controller 10 may not monitor the second processor 40 .
  • the first processor 30 when the first processor 30 is switched to the second processor 40, the first processor 30 is also used to synchronize the working status information to the second processor 40;
  • the second processor 40 is configured to respond to the data transmission channel between the multiplexer in the data processing device and the second processor 40, and reconstruct the working state based on the working state synchronization information .
  • FIG. 3 is a schematic diagram of a specific example of a data processing device performing a data processing task provided by an embodiment of the present disclosure.
  • the main system CPU is used as the first processor 30, and the backup system CPU is used as the second processor 40; the controller is selected as CPLD; the multiplexer is selected as Multiplexer.
  • the Multiplexer includes two multiplexers, which are respectively used for gating the network port and the hard disk; the main system CPU and the backup system CPU also include their respective corresponding data communication interfaces. Such as input and output (Input/Output) I/O interface, USB interface, and memory.
  • the main system CPU executes the data processing task.
  • the CPLD for example, can receive the heartbeat signal of the main system CPU when monitoring the main system CPU, judge whether its working state is normal, and choose to switch when its working state is abnormal; or, it can also receive the main system CPU. Use the active switching signal sent by the system CPU or the backup system CPU to determine the switching.
  • the CPLD detects that the working state of the primary CPU changes from normal to abnormal, and judges that the CPU of the backup system can work normally by monitoring the CPU of the backup system. At this time, the CPLD sends the first port gating signal to the Multiplexer; specifically, the first port gating signal includes the network port gating signal and the hard disk gating signal shown in FIG. 3 .
  • the backup system CPU can notify the backup system CPU of business information related to data processing tasks through the business and communication interface.
  • the main system CPU when the main system CPU is working normally, it can continuously communicate with the backup system CPU through the service and communication interface, and inform the backup system CPU of service information.
  • the service information may include, for example, file modification, I/O state modification, and internal state modification.
  • the CPU of the backup system can quickly continue to complete unfinished data processing tasks according to the current process of task processing by the CPU of the main system after the CPU of the main system fails to work normally, the reliability of the device when processing tasks can be improved. And effectively reduce business interruption.
  • the user in the process of switching between the CPU of the main system and the CPU of the backup system, the user has no perception, so when the user uses the data processing device to complete related operations, there is no need to manually check the internal status of the device and replace the CPU. , Caton and other situations will be reduced, and the use will be more convenient.
  • the process of the CPLD sending the first port gating signal to the multiplexer includes sending the hard disk gating signal to the multiplexer for gating the hard disk, and sending the network port gating signal to the multiplexer for gating the network port.
  • FIG. 4 is a structural diagram of a multiplexer provided by an embodiment of the present disclosure. The Multiplexer shown in Fig.
  • 4 comprises 4 ports, comprises the port gating (that is the first data transmission port) that is connected with CPLD, the port A (that is the second data transmission port) that is connected with main system CPU, and Port B (that is, the third data transmission port) connected to the CPU of the backup system, and port Y (that is, the fourth data transmission port) connected to the hard disk.
  • the hard disk gating signal may include, for example, a high-level signal indicating that port A is connected to port Y.
  • the main system CPU may, for example, pass The Serial Advanced Technology Attachment (SATA) signal reads and writes the hard disk.
  • the hard disk gating signal may also include, for example, a low-level signal indicating that port B is connected to port Y.
  • the backup system CPU may also pass the SATA signal Read and write to the hard disk.
  • the hard disk may also use a high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) hard disk, and its corresponding signal may also be a signal corresponding to PCIE, which is not limited here.
  • PCIE serial computer expansion bus standard
  • multiple multiplexers can also be set accordingly, so that the multiplexer can be switched to different backup system CPUs. The details will not be repeated here.
  • the Multiplexer used for gating the network port may be the same type of multiplexer as the Multiplexer for gating the hard disk, or a multiplexer of a different type may be selected according to actual conditions.
  • its execution process when it is used for gating the network port is similar to the execution process of the above-mentioned Multiplexer for gating the hard disk when gating the hard disk, and will not be repeated here.
  • the main system CPU and the backup system CPU can work together to improve the stability of the data processing process.
  • the embodiment of the present disclosure also provides a data processing method corresponding to the data processing device. Since the problem-solving principle of the method in the embodiment of the present disclosure is similar to that of the above-mentioned data processing device in the embodiment of the present disclosure, the implementation of the method Reference can be made to the implementation of the device, and repeated descriptions will not be repeated.
  • FIG. 5 it is a flowchart of a data processing method provided by an embodiment of the present disclosure; wherein, the data processing method is applied to a data processing device provided by an embodiment of the present disclosure, and the data processing device includes: a controller, A multiplexer, a first processor, and a second processor; the data processing method includes:
  • S501 The controller sends a first port strobe signal to the multiplexer in response to detecting that the working state of the first processor is abnormal;
  • the multiplexer gates the data transmission channel between the multiplexer and the second processor in response to receiving the first port gate signal sent by the controller;
  • S503 The second processor switches from the non-working state to the working state in response to the data transmission channel between the multiplexer and the second processor being gated.
  • the multiplexer includes: a first data transmission port connected to the controller, a second data transmission port connected to the first processor, and a second data transmission port connected to the first processor.
  • the third data transmission port connected to the two processors; the multiplexer gates the multiplexer and the second processor in response to receiving the first port strobe signal sent by the controller
  • a data transmission channel between devices including: the multiplexer responds to receiving the first port strobe signal sent by the controller through the first data transmission port, through the multiplexer
  • the third data transmission port connected to the second processor gates the channel between the multiplexer and the second processor.
  • the data processing apparatus includes at least two multiplexers; different multiplexers are connected to different external devices.
  • the multiplexer in the data processing device further includes a fourth data transmission port, and the multiplexer communicates with the corresponding external device through the fourth data transmission port connection; the data processing method further includes: the multiplexer receives the first signal transmitted by the corresponding external device through the fourth data transmission port, and sends the first signal through the third data transmission port to the second processor; and/or, receive the second signal sent by the second processor through the third data transmission port, and send the second signal to the corresponding through the fourth data transmission port sent by an external device.
  • the external device includes at least one of the following: a network card, and a hard disk.
  • the controller sends a first port gating signal to the multiplexer in response to detecting that the working state of the first processor is abnormal, including: the controlling The multiplexer sends the first port strobe signal to the multiplexer in response to detecting that the working state of the first processor is abnormal and detecting that the working state of the second processor is normal.
  • the method further includes: the controller monitors the working state of the second processor.
  • the controller monitors the working state of the processor, including: the controller receives a heartbeat signal sent by the processor; in response to not receiving the heartbeat signal within a preset time period, It is determined that the working state of the processor is abnormal; wherein the processor includes: the first processor and/or the second processor.
  • it further includes: after the controller sends the first port strobe signal to the multiplexer, in response to detecting that the working state of the first processor is abnormally switched is normal, sending a second port gating signal to the multiplexer; the multiplexer responds to receiving the second port gating signal sent by the controller, based on the first port gating signal
  • the two-port strobe signal is used to strobe the data transmission channel between the multiplexer and the first processor.
  • the controller sends a third signal to the multiplexer in response to receiving the active switching signal sent by the first processor or the second processor. port gating signal; the multiplexer responds to receiving the third port gating signal sent by the controller, based on the second port gating signal, from the first processor and the second processing In the device, determine the target processor that is currently in a non-working state; select the data transmission channel between the multiplexer and the target processor.
  • the controller includes: a complex programmable logic device CPLD.
  • the data processing method further includes: the first processor synchronizing the working status information to the second processor; the second processor responding to the multiplexed The data transmission channel between the device and the second processor is gated, and switched from the non-working state to the working state, including: the second processor responds to the multiplexer selection in the data processing device Reconstructing a working state based on the working state synchronization information through a data transmission channel with the second processor.
  • the embodiment of the present disclosure also provides a computer device, including: an instruction memory and the data processing device provided in the embodiment of the present disclosure.
  • the electronic devices provided by the embodiments of the present disclosure may include smart terminals such as mobile phones, or other devices for data processing, boards, servers, etc., which are not limited here.
  • the embodiment of the present disclosure also provides a computer-readable storage medium, on which a computer program is stored, and the program is executed by the controller and the multiplexer to execute the method provided in any data processing method embodiment of the present disclosure.
  • the embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of the data processing method described in the above method embodiment, for details, please refer to the above method The embodiment will not be repeated here.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. Wait.
  • the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本公开提供了一种数据处理装置、方法、计算机设备及存储介质，其中，数据处理装置包括控制器、多路复用器、第一处理器、以及第二处理器；其中，控制器与多路复用器、第一处理器、以及第二处理器连接；多路复用器与第一处理器、以及第二处理器连接；控制器，用于响应于监测到第一处理器的工作状态出现异常，向多路复用器发送第一端口选通信号；多路复用器，用于响应于接收到控制器发送的第一端口选通信号，选通多路复用器与第二处理器之间的数据传输通道；第二处理器，用于响应于多路复用器与第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态。这种数据处理装置的可靠性更高。

Description

数据处理装置、方法、计算机设备及存储介质
相关申请的交叉引用
本专利申请要求于2021年6月25日提交的、申请号为202110710099.4、发明名称为“数据处理装置、方法、计算机设备及存储介质”的中国专利申请的优先权，该申请以引用的方式并入文本中。
技术领域
本公开涉及计算机技术领域，具体而言，涉及一种数据处理装置、方法、计算机设备及存储介质。
背景技术
利用边缘服务器可以将数据任务的处理、应用程序的运行、或者功能服务的实现下放至网络边缘的节点上，使得控制系统与中央数据中心之间的通信带宽减少。通常，可以通过部署中央处理器(Central Processing Unit，CPU)系统的方式构建边缘服务器。但是，一旦CPU系统出现故障，就会导致边缘服务器不能正常工作，造成系统稳定性较差。
发明内容
本公开实施例至少提供一种数据处理装置、方法、计算机设备及存储介质。
第一方面，本公开实施例提供了一种数据处理装置，包括：包括控制器、一个或多个多路复用器、第一处理器、以及第二处理器；其中，所述控制器与所述多路复用器、所述第一处理器、以及所述第二处理器连接；所述一个或多个多路复用器中的每一个与所述第一处理器、以及所述第二处理器连接；所述控制器，用于响应于监测到所述第一处理器的工作状态出现异常，向所述一个或多个多路复用器发送第一端口选通信号；所述一个或多个多路复用器中的每一个，用于响应于接收到所述控制器发送的第一端口选通信号，选通该多路复用器与第二处理器之间的数据传输通道；所述第二处理器，用于响应于所述一个或多个多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态。
这样，能够在第一处理器的工作状态出现异常时，及时切换至第二处理器，利用第二处理器继续执行第一处理器未完成的数据处理任务，从而提升了系统的可靠性。
一种可选的实施方式中，所述一个或多个多路复用器中的每一个包括：与所述控制器连接的第一数据传输端口、与所述第一处理器连接的第二数据传输端口、与所述第二处理器连接的第三数据传输端口；所述一个或多个多路复用器中的每一个，用于响应于通过所述第一数据传输端口接收到所述控制器发送的第一端口选通信号，通过该多路复用器与所述第二处理器连接的所述第三数据传输端口，选通该多路复用器与所述第二处理器之间的通道。
这样，多路复用器可以通过第一端口选通信号接收控制器发送的第一断就选通信号，并通过第三数据传输端口选通多路复用器与第二处理器之间的通道。由于多路复用器包含多个数据传输端口，因此可有效的接收数据处理装置中的不同设备发送的信号，同样的，也可以有效的向数据处理装置中不同的设备发送信号；以及，利用不同的端口发送不同的信号，更有利于不同信号的正常、安全传输。
一种可选的实施方式中，所述数据处理装置中所述多路复用器的数量至少为两个；不同的多路复用器分别与不同的外接设备连接。
这样，可以通过多路复用器连接不同的外界设备，增加数据处理装置的可扩展性。
一种可选的实施方式中，所述一个或多个多路复用器中的每一个还包括第四数据传输端口，该多路复用器通过所述第四数据传输端口与对应外接设备连接；该多路复用器，还用于通过所述第四数据传输端口接收对应的外接设备传输的第一信号，并将所述第一信号通过第三数据传输端口发送至所述第二处理器；和/或，通过所述第三数据传输端口接收所述第二处理器发送的第二信号，并将所述第二信号通过所述第四数据传输端口向对应外接设备发送。
这样，通过多路复用器中的第四数据传输端口，还可以实现处理器于外接设备之间的数据传输。
一种可选的实施方式中，所述外接设备包括下述至少一种：网卡、以及硬盘。
一种可选的实施方式中，所述控制器，在响应于监测到所述第一处理器的工作状态出现异常，向所述一个或多个多路复用器发送第一端口选通信号时用于：响应于监测到所述第一处理器的工作状态出现异常、且监测到所述第二处理器的工作状态正常，向所述一个或多个多路复用器发送所述第一端口选通信号。
这样，可以保证及时地对第一处理器的异常工作状态做出响应，并切换至第二处理器继续执行数据处理任务。
一种可选的实施方式中，所述控制器，还用于监测所述第二处理器的工作状态。
一种可选的实施方式中，所述控制器，在监测处理器的工作状态时，用于：接收所述处理器发送的心跳信号；响应于预设时长内未接收到所述心跳信号，则确定所述处理器的工作状态出现异常；其中，所述处理器包括：所述第一处理器和/或所述第二处理器。
这样，利用心跳信号对处理器的工作状态进行判断，可以更准确并且更及时的对处理器的工作状态进行判断，防止出现处理器不能正常工作导致的处理任务停止等情况。
一种可选的实施方式中，所述控制器还用于：在向所述一个或多个多路复用器发送第一端口选通信号后，响应于监测到所述第一处理器的工作状态由异常切换为正常，向所述一个或多个多路复用器发送第二端口选通信号；所述一个或多个多路复用器中的每一个，还用于响应于接收到所述控制器发送的所述第二端口选通信号后，基于所述第二端口选通信号，选通该多路复用器与所述第一处理器之间的数据传输通道。
这样，可以减少第一处理器在工作状态异常时可能出现的数据处理任务中断和/或过长时间的故障延时，能够保证数据处理任务可以安全稳定的运行。
一种可选的实施方式中，所述控制器还用于：响应于接收到所述第一处理器或所述第二处理器发送的主动切换信号，向所述一个或多个多路复用器发送第三端口选通信号；所述一个或多个多路复用器中的每一个，还用于响应于接收到所述控制器发送的第三端口选通信号，基于第二端口选通信号，从所述第一处理器和所述第二处理器中，确定当前处于非工作状态的目标处理器；选通该多路复用器与和目标处理器之间的数据传输通道。
这样，可以选用算力较低的处理器作为第一处理器，并选择算力较高的处理器作为第二处理器，并在执行数据处理任务的过程中，动态切换执行数据处理任务的处理器，在保证能够正常、准确地完整数据处理任务的同时，由于算力较低的第一处理器的成本较低，因此可以有效的降低设备成本。
一种可选的实施方式中，所述控制器包括：复杂可编程逻辑器件(Complex Programmable Logic Device，CPLD)。
一种可选的实施方式中，所述第一处理器，还用于将工作状态信息同步至所述第 二处理器；所述第二处理器在响应于所述一个或多个多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态时，用于：响应于所述数据处理装置中的所述一个或多个多路复用器选通与所述第二处理器之间的数据传输通道，基于所述工作状态同步信息，重建工作状态。
这样，在将处理器由非工作状态切换至工作状态时，在数据处理装置中执行任务的处理器可以及时的继续完成数据处理任务。因此对于数据处理装置而言，其可以通过连续的执行数据处理任务的方式保证数据处理的效率。
第二方面，本公开实施例还提供一种数据处理方法，应用于本公开实施例提供的数据处理装置；所述数据处理装置包括：控制器、一个或多个多路复用器、第一处理器、以及第二处理器；所述数据处理方法包括：所述控制器响应于监测到所述第一处理器的工作状态出现异常，向所述一个或多个多路复用器发送第一端口选通信号；所述一个或多个多路复用器中的每一个，响应于接收到所述控制器发送的第一端口选通信号，选通该多路复用器与所述第二处理器之间的数据传输通道；所述第二处理器响应于所述一个或多个多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态。
一种可选的实施方式中，所述一个或多个多路复用器中的每一个包括：与所述控制器连接的第一数据传输端口、与所述第一处理器连接的第二数据传输端口、与所述第二处理器连接的第三数据传输端口；所述一个或多个多路复用器中的每一个，响应于接收到所述控制器发送的第一端口选通信号，选通该多路复用器与所述第二处理器之间的数据传输通道，包括：所述一个或多个多路复用器中的每一个，响应于通过所述第一数据传输端口接收到所述控制器发送的第一端口选通信号，通过该多路复用器与所述第二处理器连接的所述第三数据传输端口，选通该多路复用器与所述第二处理器之间的通道。
一种可选的实施方式中，所述数据处理装置中所述多路复用器的数量至少为两个；不同的多路复用器分别与不同的外接设备连接。
一种可选的实施方式中，所述数据处理装置中的所述一个或多个多路复用器还包括第四数据传输端口，该多路复用器通过所述第四数据传输端口与对应外接设备连接；所述数据处理方法还包括：该多路复用器通过所述第四数据传输端口接收对应的外接设备传输的第一信号，并将所述第一信号通过第三数据传输端口发送至所述第二处理器；和/或，通过所述第三数据传输端口接收所述第二处理器发送的第二信号，并将所述第二信号通过所述第四数据传输端口向对应外接设备发送。
一种可选的实施方式中，所述外接设备包括下述至少一种：网卡、以及硬盘。
一种可选的实施方式中，所述控制器响应于监测到所述第一处理器的工作状态出现异常，向所述一个或多个多路复用器发送第一端口选通信号，包括：所述控制器响应于监测到所述第一处理器的工作状态出现异常、且监测到所述第二处理器的工作状态正常，向所述一个或多个多路复用器发送所述第一端口选通信号。
一种可选的实施方式中，还包括：所述控制器监测所述第二处理器的工作状态。
一种可选的实施方式中，所述控制器监测处理器的工作状态，包括：所述控制器接收所述处理器发送的心跳信号；响应于预设时长内未接收到所述心跳信号，确定所述处理器的工作状态出现异常；其中，所述处理器包括：所述第一处理器和/或所述第二处理器。
一种可选的实施方式中，还包括：所述控制器在向所述一个或多个多路复用器发送第一端口选通信号后，响应于监测到所述第一处理器的工作状态由异常切换为正常，向所述一个或多个多路复用器发送第二端口选通信号；所述一个或多个多路复用器中的每一个，响应于接收到所述控制器发送的所述第二端口选通信号后，基于所述第二端口选通信号，选通该多路复用器与所述第一处理器之间的数据传输通道。
一种可选的实施方式中，还包括：所述控制器响应于接收到所述第一处理器或所述第二处理器发送的主动切换信号，向所述一个或多个多路复用器发送第三端口选通信号；所述一个或多个多路复用器中的每一个，响应于接收到所述控制器发送的第三端口选通信号，基于第二端口选通信号，从所述第一处理器和所述第二处理器中，确定当前处于非工作状态的目标处理器；选通该多路复用器与和目标处理器之间的数据传输通道。
一种可选的实施方式中，所述控制器包括：复杂可编程逻辑器件CPLD。
一种可选的实施方式中，所述数据处理方法还包括：所述第一处理器将工作状态信息同步至所述第二处理器；所述第二处理器响应于所述一个或多个多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态，包括：所述第二处理器响应于所述数据处理装置中的所述一个或多个多路复用器选通与所述第二处理器之间的数据传输通道，基于所述工作状态同步信息，重建工作状态。
第三方面，本公开可选实现方式还提供一种计算机设备，处理器、存储器，所述存储器存储有所述处理器可执行的机器可读指令，所述处理器用于执行所述存储器中存储的机器可读指令，所述机器可读指令被所述处理器执行时，所述机器可读指令被所述 处理器执行时执行上述第三方面中任一种可能的实施方式中的步骤。
第四方面，本公开可选实现方式还提供一种计算机可读存储介质，该计算机可读存储介质上存储有计算机程序，该计算机程序被运行时执行上述第三方面中任一种可能的实施方式中的步骤。
关于上述数据处理方法、计算机设备、及计算机可读存储介质的效果描述参见上述数据处理装置的说明，这里不再赘述。
为使本公开的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，此处的附图被并入说明书中并构成本说明书中的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种数据处理装置的示意图；
图2示出了本公开实施例所提供的一种数据处理装置的电路连接示意图；
图3示出了本公开实施例所提供的一种数据处理装置在执行数据处理任务时的具体示例的示意图；
图4示出了本公开实施例所提供的一种Multiplexer的结构图；
图5示出了本公开实施例所提供的一种数据处理方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对本公开的实施例的详细 描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
经研究发现，在搭建边缘服务器时，通常是通过部署一个中央处理器的方式实现的，也即边缘服务器在执行数据处理任务时依赖于中央处理器实现。一旦中央处理器在运行的过程中出现故障，就会导致边缘服务器不能正常运行，造成边缘服务器的系统稳定性较差。
基于上述研究，本公开提供了一种数据处理装置，利用控制器对第一处理器的工作状态进行检测，若其出现异常，则可以向多路复用器发送第一端口选通信号，以选通与第二处理器之间的数据传输通道，从而切换至第二处理器。这种方式能够在第一处理器的工作状态出现异常时，及时切换至第二处理器，利用第二处理器继续执行第一处理器未完成的数据处理任务，从而提升了系统的可靠性。
针对以上方案所存在的缺陷，均是发明人在经过实践并仔细研究后得出的结果，因此，上述问题的发现过程以及下文中本公开针对上述问题所提出的解决方案，都应该是发明人在本公开过程中对本公开做出的贡献。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
本公开实施例提供的数据处理装置，不仅能够用于边缘服务器，还可以用于其他的计算机设备中。通过在计算机设备中部署本公开实施例提供的数据处理装置，能够提升计算机设备的可靠性。
为便于对本实施例进行理解，首先对本公开实施例所公开的一种数据处理装置进行详细介绍。
参见图1所示，为本公开实施例提供的一种数据处理装置的示意图；其中，数据处理装置包括控制器10、多路复用器20、第一处理器30、以及第二处理器40；
所述控制器10与所述多路复用器20、所述第一处理器30、以及所述第二处理器40连接；所述多路复用器20与所述第一处理器30、以及所述第二处理器40连接；
所述控制器10，用于响应于监测到所述第一处理器30的工作状态出现异常，向所述多路复用器20发送第一端口选通信号；
所述多路复用器20，用于响应于接收到所述控制器10发送的第一端口选通信号，选通所述多路复用器20与第二处理器40之间的数据传输通道；
所述第二处理器40，用于响应于所述多路复用器20与所述第二处理器40之间的数据传输通道被选通，由非工作状态切换至工作状态。
本公开实施例提供的一种数据处理装置，利用控制器10监测第一处理器30的工作状态，并在监测到第一处理器30的工作状态出现异常时向多路复用器20发送第一端口选通信号，以使多路复用器20可以基于第一端口选通信号选通多路复用器20与第二处理器40之间的数据传输通道。这种方式能够在第一处理器30的工作状态出现异常时，及时切换至第二处理器40，利用第二处理器40继续执行第一处理器30未完成的数据处理任务，从而提升了系统的可靠性。
在本公开实施例中，第一处理器30例如可以是与第二处理器40型号相同的处理器；或者，第一处理器30与第二处理器40分别对应的算力不同，例如第二处理器40的算力高于第一处理器30。另外，若将第一处理器30视为主要承担数据处理任务的主用处理器，对应的第二处理器40可以包括备份的处理器，并且第二处理器40例如可以至少有一个，以保证稳定性。
示例性的，在包括多个第二处理器40的情况下，与每个外接设备连接的多路复用器20也可以设置有多个，其中，多路复用器的数量与第二处理器40的数量、以及多路复用器中第二数据传输端口的数量相关。
针对控制器10，例如可以包括复杂可编程逻辑器件CPLD。
下面，以数据处理装置中包括一个第一处理器30和一个第二处理器40，并包括一个多路复用器20以及一个控制器10为例进行说明。
在一种可能的实施方式中，控制器10响应于监测到所述第一处理器30的工作状态出现异常，例如可以通过向多路复用器20发送第一端口选通信号的方式，使多路复用器20响应于第一端口选通信号，选通多路复用器20与第二处理器40之间的数据传输通道，从而使第二处理器40由非工作状态切换至工作状态。
在具体实施中，多路复用器20包括：与所述控制器10连接的第一数据传输端口、与所述第一处理器30连接的第二数据传输端口、与所述第二处理器40连接的第三数据传输端口。控制器10在监测到第一处理器30的工作状态出现异常时，例如可以向多路复用器20的第一数据传输端口发送第一端口选通信号。对应的，多路复用器20通过第 一数据传输端口接收到第一端口选通信号后，可以通过多路复用器20与第二处理器40连接的第三数据传输端口，选通多路复用器20与第二处理器40之间的通道。
另外，多路复用器20例如还包括第四数据传输端口，所述多路复用器20通过所述第四数据传输端口与对应外接设备连接。具体地，所述多路复用器20，还用于通过所述第四数据传输端口接收对应的外接设备传输的第一信号，并将所述第一信号通过第三数据传输端口发送至所述第二处理器40；和/或，通过所述第三数据传输端口接收所述第二处理器40发送的第二信号，并将所述第二信号通过所述第四数据传输端口向对应外接设备发送。其中，所述外接设备包括下述至少一种：网卡、以及硬盘。
在一种可能的实施方式中，在数据处理装置中的外接设备例如可以包括一个。例如，第一处理器30和第二处理器40外接相同的网卡，并分别对应连接不同的硬盘；又或者，第一处理器30和第二处理器40外接相同的硬盘，并分别对应连接不同的网卡。
在另一种可能的实施方式中，在数据处理装置中包括多个外接设备；对应的，数据处理装置中包括至少两个多路复用器20，不同的多路复用器20与不同的外接设备连接。参见图2所示，其中包括有两个多路复用器20，包括多路复用器1以及多路复用器2；其中多路复用器1与外接设备中的网卡相连接，多路复用器2与外接设备中的硬盘相连接。
以图2中示出的多路复用器1为例，在将第二处理器40的工作状态由非工作状态切换至工作状态的情况下，第四数据传输端口接收对应的外接设备传输的第一信号。此处，外接设备为网卡，对应的第一信号例如可以包括网络信号。在多路复用器20中的第四数据传输端口接收到第一信号后，可以将第一信号通过第三数据传输端口发送至第二处理器40。
类似的，多路复用器1也可以通过第三数据传输端口接收到由第二处理器40发送的第二信号。此处，第二信号例如可以包括第二处理器40对网络状态的反馈信号。多路复用器1接收到第二信号后，也可以将第二信号通过第四数据传输端口向对应的外接设备发送。此处，对应的外接设备也即网卡。
在本公开另一实施例中，在确定由第一处理器30或者第二处理器40中的任一个执行数据处理任务时，可以利用控制器10监测处理器的工作状态，确定当前切换至第一处理器30和第二处理器40中的一个。
示例性地，控制器10在监测处理器的工作状态时，用于接收所述处理器发送的心 跳信号；若预设时长内未接收到所述心跳信号，则确定所述处理器的工作状态出现异常。
其中，处理器在正常工作时，例如可以根据其对应的时钟周期以固定的频率发送心跳信号。以第一处理器30为例，其对应的时钟周期例如可以包括2毫秒，则在第一处理器30正常工作时会以2毫秒/次的频率发送心跳信号。一般地，若处理器不在正常工作的状态下，发送的心跳信号频次会低于正常工作时发送心跳信号的频次，或者停止向控制器10发送心跳信号。
因此，预设时长例如可以直接依据处理器对应的时钟周期确定，例如为第一处理器30设置对应的预设时长为2毫秒。或者，在可以允许处理器有自恢复的情况下，将预设时长设置为大于时钟周期的时长，例如4毫秒；若在4毫秒内没有接收到心跳信号，则认为处理器自恢复失败，也即工作状态异常。具体地，预设时长可以根据实际情况确定，例如若在任务处理的时效性要求较高的情况下，可以设置较短的预设时长；若在任务处理的时效性要求较低的情况下，可以设置较长的预设时长；另外，还可以根据当前的待处理任务的数量动态调整预设时长；若待处理任务的数量较多，则可以设置较短的预设时长，以保证多任务能够及时执行；若待处理任务的数量较少，则可以设置较长的预设时长，给予第一处理器30有足够的时间进行自恢复，减少处理器切换造成的额外损耗，具体在此不再赘述。
针对于第二处理器40，控制器10也可以对其工作状态进行监测；具体过程与上述控制器10监测第一处理器30工作状态的方式相似，这里不再赘述。
另外，在对处理器的工作状态进行监测时，得到的监测结果包括：工作状态正常、或者工作状态异常。
具体地，控制器10在监测到第一处理器30和第二处理器40分别对应的工作状态时，包括但不限于下述(A)、(B)、(C)三种情况。
(A)：控制器10例如监测到第一处理器30的工作状态出现异常，则可以选择切换至第二处理器40继续对任务进行处理。
具体地，例如可以包括但不限于下述(a1)或者(a2)两种情况：
(a1)：控制器10监测到第二处理器40的工作状态正常。
此处，控制器10向多路复用器20发送第一端口选通信号时，用于：响应于监测到所述第一处理器30的工作状态出现异常、且监测到所述第二处理器40的工作状态正常，向所述多路复用器20发送所述第一端口选通信号。
在该种情况下，由于第一处理器30已经无法正常工作、并且监测到第二处理器40可以正常工作，因此控制器10可以向多路复用器20发送第一端口选通信号，以完成处理器的切换。
其中，第一端口选通信号用于指示多路复用器20选通多路复用器20与第二处理器40之间的数据传输通道。在该数据传输通道被选通的情况下，即可以由第二处理器40继续执行第一处理器30待完成的数据处理任务。
(a2)：控制器10监测到第二处理器40的工作状态异常。
此处，为了避免控制器10在第一处理器30和第二处理器40均存在工作状态异常，而在两个处理器之间来回监测的情况，例如在监测到第一处理器30的工作状态异常后，监测第二处理器40的工作状态；并在监测到第二处理器40的工作状态异常后，又重新返回监测第一处理器30的工作状态，这样在反复监测两个第二处理器40的情况。在该种情况下，若控制器10监测到第一处理器30和第二处理器40的工作状态均为异常时，例如会停止监测并报错，等待检测人员的维修。这样，还可以有效的减少控制器10在监测时的损耗，并防止数据处理装置在运行时陷入死循环无法跳出，并正常工作。
(B)：控制器10在向所述多路复用器20发送第一端口选通信号后，响应于监测到所述第一处理器30的工作状态由异常切换为正常，向所述多路复用器20发送第二端口选通信号。
对应的，所述多路复用器20，还用于响应于接收到所述控制器10发送的所述第二端口选通信号后，基于所述第二端口选通信号，选通所述多路复用器20与所述第一处理器30之间的数据传输通道。
示例性的，在第一处理器30无法正常工作时，切换至第二处理器40继续对任务进行处理，然后第一处理器30恢复正常的场景下，控制器10在监测到第一处理器30的工作状态由异常转换为正常，则可以控制重新切换至第一处理器30。
具体地，控制器10在监测到第一处理器30的工作状态由异常转换为正常时，可以向多路复用器20发送第二端口选通信号。此处，第二端口选通信号用于指示选通多路复用器20与第一处理器30之间的数据传输通道。在该数据传输通道被选通的情况下，即可以切换为第一处理器30依据第二处理器40当前处理的当前状态，继续对数据处理任务进行处理。
这样，第二处理器40可以作为解决第一处理器30无法正常使用时的备份处理器， 在第一处理器30无法正常工作时，临时执行处理任务，并在第一处理器30恢复正常工作时重新切换由第一处理器30继续执行数据处理任务。利用这种方式可以减少第一处理器30在工作状态异常时可能出现的数据处理任务中断和/或过长时间的故障延时，能够保证数据处理任务可以安全稳定的运行。
另外，在一种可能的情况下，若第一处理器30较容易出现异常工作状态，但还能够在较短时间内自恢复，例如第一处理器30老化或长时间工作的情况下，第一处理器30因自身发热温度过高，会出现工作异常；在切换至第二处理器40执行数据处理任务时，第一处理器30不再工作，温度下降，恢复可正常工作的状态，然后控制器10监测到第一处理器30可以正常工作，再由第二处理器40切换至第一处理器30。以此往复，会出现过于频繁的在第一处理器30和第二处理器40之间高频率的切换。
因此，在第二处理器40处理任务时，即使控制器10监测到第一处理器30的工作状态由异常切换为正常时，依然选择继续由第二处理器40执行数据处理任务。这样，可以减少在第一处理器30和第二处理器40之间的高频率切换现象发生，避免由于第一处理器30和第二处理器40频繁切换造成的处理效率降低的问题。
(C)：控制器10响应于接收到所述第一处理器30或所述第二处理器40发送的主动切换信号，向所述多路复用器20发送第三端口选通信号。
示例性的，所述多路复用器20，还用于响应于接收到所述控制器10发送的第三端口选通信号，基于所述第三端口选通信号，从所述第一处理器30和所述第二处理器40中，确定当前处于非工作状态的目标处理器；选通所述多路复用器20与和目标处理器之间的数据传输通道。
其中，第三端口选通信号用于指示多路复用器20选通多路复用器20与当前处于非工作状态的目标处理器之间的数据传输通道。
在该种情况下，第一处理器30和第二处理器40可以主动发送主动切换信号，以使控制器10可以发送第三端口选通信号，并控制多路复用器20能够切换选通当前非工作状态的处理器与该多路复用器20之间的数据传输通道。
具体地，可以包括但不限于下述(c1)或者(c2)两种不同的情况：
(c1)：第一处理器30正在进行数据处理任务，第一处理器30和多路复用器20的数据传输通道连通，并且第一处理器30正常工作。此时，第一处理器30可以主动地发送主动切换信号，切换由第二处理器40继续执行任务。
具体地，随着数据处理任务的增加，对中央处理器算力的要求也越来越高，进而造成中央处理器的成本也会较高；本公开实施例中，为了降低中央处理器的成本，可以将第一处理器30与第二处理器40设置为不同型号、不同算力的处理器。其中，第一处理器30的算力例如是较低的，可以处理的数据处理任务较为简单；第二处理器40相较于第一处理器30而言具有更高的算力，可以处理较为复杂、或者数量较多的数据处理任务。对应的，第二处理器40的成本相较于第一处理器30也较高。
在一种可能的情况下，数据处理任务包括较多简单运算的子任务、以及部分复杂运算的子任务。对于第一处理器30和第二处理器40而言，第一处理器30可以完成其中简单运算的子任务，但难以完成复杂运算的子任务；第二处理器40则可以完成其中复杂运算的子任务、或者支持更多的数量的任务并行执行。此处，第二处理器40可以弥补第一处理器30算力的不足。
示例性的，在第一处理器30在对数据处理任务中较简单的运算进行处理后，在执行对复杂运算子任务的处理时，可以发送主动切换信号，以使控制器10向多路复用器20发送第三端口选通信号，对处理器进行切换。然后，第二处理器40继续执行数据处理任务中较为复杂的子任务，并在对其中较为复杂的子任务处理完毕后，向控制器10发送主动切换信号，再次切换至第一处理器30执行较为简单的子任务。
另外，也可以在任务维度上，进行处理器的切换，例如耗费算力较多的任务，会切换至第二处理器40执行；而耗费算力较少的任务，切换至第一处理器30执行。
另一示例中，当前正在使用的处理器为第一处理器30；第一处理器30可以在当前数据处理任务数量大于预设数量的情况下，向控制器发送主动切换信号，以使控制器向多路复用器发送第三端口选通信号，以切换至第二处理器40；在当前数据处理任务的数量变化至小于或者等于预设数量的情况下，第二处理器40还可以向控制器发送主动切换信号，以使控制器向多路复用器发送第三端口选通信号，以切换回到第一处理器30。
其中，由于在第一处理器30发送主动切换信号后，还无法确定第二处理器40此时是否可以正常工作，因此控制器10还需要对第二处理器40的工作状态进行监测；若第二处理器40的工作状态正常，再进行处理器的切换。
这样，可以选用算力较低的处理器作为第一处理器30，并选择算力较高的处理器作为第二处理器40，并在执行数据处理任务的过程中，动态切换执行数据处理任务的处理器，在保证能够正常、准确地完整数据处理任务的同时，由于算力较低的第一处理器 30的成本较低，因此可以有效的降低设备成本。
另外，还可以通过不同的处理器执行不同的任务，来降低对每个处理器的损耗，延长处理器的使用寿命，变相降低处理器的成本。
(c2)：第一处理器30正在执行数据处理任务。此时，第二处理器40可以主动地发送主动切换信号，切换由第二处理器40继续执行任务。
此处，由于第二处理器40是主动发送主动切换信号要求对当前的正在处理数据的第一处理器30进行切换的，也即可以确定第二处理器40可以正常工作，因此在该种情况下，控制器10可以不对该第二处理器40进行监测。
具体地应用场景例如可以与上述(c1)相似，在此不再赘述。
本公开另一实施例中，在将第一处理器30切换为第二处理器40的情况下，第一处理器30还用于将工作状态信息同步至所述第二处理器40；所述第二处理器40，用于响应于所述数据处理装置中的多路复用器选通与所述第二处理器40之间的数据传输通道，基于所述工作状态同步信息，重建工作状态。
具体地，参见图3所示，为本公开实施例提供的一种数据处理装置在执行数据处理任务时的具体示例的示意图。在该示例中，将主用系统CPU作为第一处理器30、将备份系统CPU作为第二处理器40；控制器选用CPLD；多路复用器选用Multiplexer。其中，多路复用器Multiplexer包括两个，分别用于选通网口以及硬盘；主用系统CPU和备份系统CPU还包括其分别对应数据通信接口。例如输入输出(Input/Output)I/O接口、USB接口、以及内存。
示例性的，当前数据处理装置中由主用系统CPU执行数据处理任务。此时，CPLD例如可以在对主用系统CPU进行监测时，接收主用系统CPU的心跳信号，判断其工作状态是否正常，在其工作状态不正常的情况下选择切换；或者，也可以接收主用系统CPU、或者备份系统CPU发送的主动切换信号，并确定切换。
在该示例中，CPLD监测到主用CPU的工作状态由正常变化为异常，并通过对备份系统CPU的监测，判断备份系统CPU可以正常工作。此时，CPLD向Multiplexer发送第一端口选通信号；具体地，第一端口选通信号包括图3中示出的网口选通信号、以及硬盘选通信号。
同时，为了使备份系统CPU能够继续执行主用系统CPU仍未执行完毕的任务，备份系统CPU可以通过业务及通信接口将数据处理任务相关的业务信息告知备份系统 CPU。具体地，在主用系统CPU正常工作时，可以利用业务及通信接口不断与备份系统CPU不断通信，并将业务信息告知备份系统CPU。其中，业务信息例如可以包括文件修改、I/O状态修改、内部状态的修改。
这样，由于备份系统CPU在主用系统CPU不能正常工作后，可以快速的依据主用系统CPU当前对任务处理的进程，继续完成未完成数据处理任务，因此可以提高装置处理任务时的可靠性，并有效减少业务中断。同时，对于用户而言，在主用系统CPU和备份系统CPU切换的过程中，用户是无感知的，因此用户在使用该数据处理装置完成相关的操作时，无需人工检查装置内部的状态并更换，卡顿等情况也会变少，使用更加便捷。
另外，CPLD向Multiplexer发送第一端口选通信号的过程，包括向用于选通硬盘的Multiplexer发送硬盘选通信号、以及向用于选通网口的Multiplexer发送网口选通信号。以CPLD向用于选通硬盘的Multiplexer发送硬盘选通信号为例，参见图4所示，为本公开实施例提供的一种Multiplexer的结构图。图4中示出的Multiplexer包括4个端口，包括与CPLD连接的端口选通(也即第一数据传输端口)、与主用系统CPU连接的端口A(也即第二数据传输端口)、与备份系统CPU连接的端口B(也即第三数据传输端口)、以及与硬盘连接的端口Y(也即第四数据传输端口)。
在具体实施中，硬盘选通信号例如可以包括指示由端口A连接端口Y的高电平信号，Multiplexer在基于该硬盘选通信号将端口A与端口Y选通后，主用系统CPU例如可以通过串行高级技术附件(Serial Advanced Technology Attachment，SATA)信号对硬盘进行读写。另外，硬盘选通信号例如还可以包括指示由端口B连接端口Y的低电平信号，Multiplexer在基于该硬盘选通信号将端口B与端口Y选通后，备份系统CPU例如也可以通过SATA信号对硬盘进行读写。其中，硬盘也可以使用高速串行计算机扩展总线标准(Peripheral Component Interconnect Express，PCIE)接口的硬盘，其对应的信号也可以是与PCIE对应的信号，在此不做限定。
另外，对于Multiplexer而言，若存在多个备份系统CPU，也可以相应的设置多个Multiplexer，以使Multiplexer可以切换至不同的备份系统CPU。具体地在此不再赘述。
对于用于选通网口的Multiplexer，其可以是与用于选通硬盘的Multiplexer型号相同的多路复用器，或者根据实际情况选取不同型号的多路复用器。另外，其在用于选通网口时的执行过程与上述用于选通硬盘的Multiplexer在选通硬盘时的执行过程相似，在此不再赘述。
这样，通过数据处理装置，主用系统CPU和备份系统CPU可以协同工作，提升数据处理过程的稳定性。
基于同一发明构思，本公开实施例中还提供了与数据处理装置对应的数据处理方法，由于本公开实施例中的方法解决问题的原理与本公开实施例上述数据处理装置相似，因此方法的实施可以参见装置的实施，重复之处不再赘述。
参见图5所示，为本公开实施例提供的一种数据处理方法的流程图；其中，该数据处理方法应用于本公开实施例提供的数据处理装置，所述数据处理装置包括：控制器、多路复用器、第一处理器、以及第二处理器；所述数据处理方法包括：
S501：控制器响应于监测到第一处理器的工作状态出现异常，向多路复用器发送第一端口选通信号；
S502：所述多路复用器响应于接收到所述控制器发送的第一端口选通信号，选通所述多路复用器与第二处理器之间的数据传输通道；
S503：所述第二处理器响应于所述多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态。
一种可选的实施方式中，所述多路复用器包括：与所述控制器连接的第一数据传输端口、与所述第一处理器连接的第二数据传输端口、与所述第二处理器连接的第三数据传输端口；所述多路复用器响应于接收到所述控制器发送的第一端口选通信号，选通所述多路复用器与所述第二处理器之间的数据传输通道，包括：所述多路复用器响应于通过所述第一数据传输端口接收到所述控制器发送的第一端口选通信号，通过所述多路复用器与所述第二处理器连接的所述第三数据传输端口，选通所述多路复用器与所述第二处理器之间的通道。
一种可选的实施方式中，所述数据处理装置至少包括两个多路复用器；不同的所述多路复用器与不同的外接设备连接。
一种可选的实施方式中，所述数据处理装置中的所述多路复用器还包括第四数据传输端口，所述多路复用器通过所述第四数据传输端口与对应外接设备连接；所述数据处理方法还包括：所述多路复用器通过所述第四数据传输端口接收对应的外接设备传输的第一信号，并将所述第一信号通过第三数据传输端口发送至所述第二处理器；和/或，通过所述第三数据传输端口接收所述第二处理器发送的第二信号，并将所述第二信号通过所述第四数据传输端口向对应外接设备发送。
一种可选的实施方式中，所述外接设备包括下述至少一种：网卡、以及硬盘。
一种可选的实施方式中，所述控制器响应于监测到所述第一处理器的工作状态出现异常，向所述多路复用器发送第一端口选通信号，包括：所述控制器响应于监测到所述第一处理器的工作状态出现异常、且监测到所述第二处理器的工作状态正常，向所述多路复用器发送所述第一端口选通信号。
一种可选的实施方式中，还包括：所述控制器监测所述第二处理器的工作状态。
一种可选的实施方式中，所述控制器监测处理器的工作状态，包括：所述控制器接收所述处理器发送的心跳信号；响应于预设时长内未接收到所述心跳信号，确定所述处理器的工作状态出现异常；其中，所述处理器包括：所述第一处理器和/或所述第二处理器。
一种可选的实施方式中，还包括：所述控制器在向所述多路复用器发送第一端口选通信号后，响应于监测到所述第一处理器的工作状态由异常切换为正常，向所述多路复用器发送第二端口选通信号；所述多路复用器响应于接收到所述控制器发送的所述第二端口选通信号后，基于所述第二端口选通信号，选通所述多路复用器与所述第一处理器之间的数据传输通道。
一种可选的实施方式中，还包括：所述控制器响应于接收到所述第一处理器或所述第二处理器发送的主动切换信号，向所述多路复用器发送第三端口选通信号；所述多路复用器响应于接收到所述控制器发送的第三端口选通信号，基于第二端口选通信号，从所述第一处理器和所述第二处理器中，确定当前处于非工作状态的目标处理器；选通所述多路复用器与和目标处理器之间的数据传输通道。
一种可选的实施方式中，所述控制器包括：复杂可编程逻辑器件CPLD。
一种可选的实施方式中，所述数据处理方法还包括：所述第一处理器将工作状态信息同步至所述第二处理器；所述第二处理器响应于所述多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态，包括：所述第二处理器响应于所述数据处理装置中的多路复用器选通与所述第二处理器之间的数据传输通道，基于所述工作状态同步信息，重建工作状态。
本公开实施例还提供一种计算机设备，包括：指令存储器和本公开实施例提供的数据处理装置。
本公开实施例提供的电子设备可以包括手机等智能终端，或者也可以是进行数据 处理的其他设备、板卡、服务器等，这里并不限制。
本公开实施例还提供一种计算机可读存储介质，其上存储有计算机程序，所述程序被控制器、多路复用器执行本公开任一数据处理方法实施例提供的方法。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的数据处理方法的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各 个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上所述实施例，仅为本公开的具体实施方式，用以说明本公开的技术方案，而非对其限制，本公开的保护范围并不局限于此，尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本公开实施例技术方案的精神和范围，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (15)

  1. 一种数据处理装置，其特征在于，包括控制器、一个或多个多路复用器、第一处理器、以及第二处理器；其中，
    所述控制器与所述多路复用器、所述第一处理器、以及所述第二处理器连接；所述一个或多个多路复用器中的每一个与所述第一处理器、以及所述第二处理器连接；
    所述控制器，用于响应于监测到所述第一处理器的工作状态出现异常，向所述一个或多个多路复用器发送第一端口选通信号；
    所述一个或多个多路复用器中的每一个，用于响应于接收到所述控制器发送的第一端口选通信号，选通该多路复用器与第二处理器之间的数据传输通道；
    所述第二处理器，用于响应于所述一个或多个多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态。
  2. 根据权利要求1所述的数据处理装置，其特征在于，所述一个或多个多路复用器中的每一个包括：与所述控制器连接的第一数据传输端口、与所述第一处理器连接的第二数据传输端口、与所述第二处理器连接的第三数据传输端口；
    所述一个或多个多路复用器中的每一个，用于响应于通过所述第一数据传输端口接收到所述控制器发送的第一端口选通信号，通过该多路复用器与所述第二处理器连接的所述第三数据传输端口，选通该多路复用器与所述第二处理器之间的通道。
  3. 根据权利要求1或2所述的数据处理装置，其特征在于，所述数据处理装置中所述多路复用器的数量至少为两个；不同的多路复用器分别与不同的外接设备连接。
  4. 根据权利要求1-3任一项所述的数据处理装置，其特征在于，所述一个或多个多路复用器中的每一个还包括第四数据传输端口，该多路复用器通过所述第四数据传输端口与对应外接设备连接；
    该多路复用器，还用于通过所述第四数据传输端口接收对应的外接设备传输的第一信号，并将所述第一信号通过第三数据传输端口发送至所述第二处理器；和/或，通过所述第三数据传输端口接收所述第二处理器发送的第二信号，并将所述第二信号通过所述第四数据传输端口向对应外接设备发送。
  5. 根据权利要求4所述的数据处理装置，其特征在于，所述外接设备包括下述至少一种：
    网卡、以及硬盘。
  6. 根据权利要求1-5任一项所述的数据处理装置，其特征在于，所述控制器，在响应于监测到所述第一处理器的工作状态出现异常，向所述一个或多个多路复用器发送第一端口选通信号时用于：
    响应于监测到所述第一处理器的工作状态出现异常、且监测到所述第二处理器的工作状态正常，向所述一个或多个多路复用器发送所述第一端口选通信号。
  7. 根据权利要求6所述的数据处理装置，其特征在于，所述控制器，还用于监测所述第二处理器的工作状态。
  8. 根据权利要求1-7任一项所述的数据处理装置，其特征在于，所述控制器，在监测处理器的工作状态时，用于：
    接收所述处理器发送的心跳信号；
    响应于预设时长内未接收到所述心跳信号，确定所述处理器的工作状态出现异常；
    其中，所述处理器包括：所述第一处理器和/或所述第二处理器。
  9. 根据权利要求1-8任一项所述的数据处理装置，其特征在于，所述控制器还用于：
    在向所述一个或多个多路复用器发送第一端口选通信号后，响应于监测到所述第一处理器的工作状态由异常切换为正常，向所述一个或多个多路复用器发送第二端口选通信号；
    所述一个或多个多路复用器中的每一个，还用于响应于接收到所述控制器发送的所述第二端口选通信号后，基于所述第二端口选通信号，选通该多路复用器与所述第一处理器之间的数据传输通道。
  10. 根据权利要求1-9任一项所述的数据处理装置，其特征在于，所述控制器还用于：响应于接收到所述第一处理器或所述第二处理器发送的主动切换信号，向所述一个或多个多路复用器发送第三端口选通信号；
    所述一个或多个多路复用器中的每一个，还用于响应于接收到所述控制器发送的第三端口选通信号，基于第二端口选通信号，从所述第一处理器和所述第二处理器中，确定当前处于非工作状态的目标处理器；选通该多路复用器与和目标处理器之间的数据传输通道。
  11. 根据权利要求1-10任一项所述的数据处理装置，其特征在于，所述控制器包括：复杂可编程逻辑器件。
  12. 根据权利要求1-11任一项所述的数据处理装置，其特征在于，
    所述第一处理器，还用于将工作状态信息同步至所述第二处理器；
    所述第二处理器在响应于所述一个或多个多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态时，用于：
    响应于所述数据处理装置中的所述一个或多个多路复用器选通与所述第二处理器之间的数据传输通道，基于所述工作状态同步信息，重建工作状态。
  13. 一种数据处理方法，其特征在于，应用于数据处理装置；所述数据处理装置包括：控制器、一个或多个多路复用器、第一处理器、以及第二处理器；所述数据处理方法包括：
    所述控制器响应于监测到所述第一处理器的工作状态出现异常，向所述一个或多个多路复用器发送第一端口选通信号；
    所述一个或多个多路复用器中的每一个，响应于接收到所述控制器发送的第一端口选通信号，选通该多路复用器与所述第二处理器之间的数据传输通道；
    所述第二处理器响应于所述一个或多个多路复用器与所述第二处理器之间的数据传输通道被选通，由非工作状态切换至工作状态。
  14. 一种计算机设备，其特征在于，包括：指令存储器和如权利要求1-12中任一项所述的数据处理装置。
  15. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时执行如权利要求13所述的数据处理方法的步骤。
PCT/CN2021/133744 2021-06-25 2021-11-26 数据处理装置、方法、计算机设备及存储介质 WO2022267341A1 (zh)

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