WO2022267303A1 - 基于复杂可编程逻辑器件cpld的串口控制系统及其通信方法 - Google Patents

基于复杂可编程逻辑器件cpld的串口控制系统及其通信方法 Download PDF

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WO2022267303A1
WO2022267303A1 PCT/CN2021/129522 CN2021129522W WO2022267303A1 WO 2022267303 A1 WO2022267303 A1 WO 2022267303A1 CN 2021129522 W CN2021129522 W CN 2021129522W WO 2022267303 A1 WO2022267303 A1 WO 2022267303A1
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serial port
register
cpld
controller
processor
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PCT/CN2021/129522
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French (fr)
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刘刚
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东莞华贝电子科技有限公司
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Priority to US18/569,727 priority Critical patent/US12086093B2/en
Publication of WO2022267303A1 publication Critical patent/WO2022267303A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0002—Serial port, e.g. RS232C
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P90/00—Enabling technologies with a potential contribution to greenhouse gas [GHG] emissions mitigation
    • Y02P90/02—Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]

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  • the present application relates to the technical field of switch and server hardware design, in particular to a serial port control system based on a complex programmable logic device CPLD and a communication method thereof.
  • the current server or switch system design generally includes multiple processors, such as X86 processors, BMC (Baseboard Management Controller, Baseboard Management Controller) and other devices with UART interfaces, such as CPLD (Complex Programmable Logic Device, complex programmable logic device) and FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), etc.
  • processors such as X86 processors, BMC (Baseboard Management Controller, Baseboard Management Controller) and other devices with UART interfaces, such as CPLD (Complex Programmable Logic Device, complex programmable logic device) and FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), etc.
  • CPLD Combin Programmable Logic Device, complex programmable logic device
  • FPGA Field-Programmable Gate Array
  • the connection method between these ports and the console (Console) mainly uses the Debug header. This method requires manual intervention. For example, it is required to manually debug the connector after shutdown, and for different processors, it is more complicated to switch De
  • the application discloses a serial port control system based on a complex programmable logic device CPLD, which includes a console, a plurality of processors, and a CPLD arranged between the console and the plurality of processors, and the CPLD includes controllers and registers;
  • CPLD complex programmable logic device
  • the console is configured to send an instruction to the controller, the instruction includes a corresponding register address and register content of the serial port of the processor;
  • the controller is configured to parse the instruction to obtain the corresponding register address and the register content and write the register;
  • the controller communicates with the corresponding serial port of the processor.
  • the controller is further configured to modify the serial port mode parameter of the CPLD according to the serial port mode parameter of the processor.
  • serial port mode parameters include baud rate and/or check bits.
  • the console is further configured to read status information of the register.
  • the state information includes a state machine and state parameters.
  • the controller communicates with the processor according to the configuration of the register to obtain status information returned by the processor.
  • the controller obtains state information of the processor at preset time intervals.
  • the register is configured through the console and/or the processor.
  • the information sent by one of the processors is sent to the other of the processors through the serial port group of the CPLD.
  • the present application also provides a communication method of the serial port control system based on the complex programmable logic device CPLD as described above, which includes:
  • the console sends instructions to the controller
  • the controller parses the instruction to obtain the corresponding register address and the register content and writes it into the register;
  • the controller communicates with the corresponding serial port of the processor.
  • This application is equipped with a controller and a register in the CPLD.
  • the console sends an instruction to the controller, and then the controller parses the received instruction to obtain the corresponding register address and register content and write it into the register. Finally, according to the register address and register contents, the controller communicates with the corresponding processor. Therefore, the present application utilizes the controller and register of the CPLD to automatically switch the serial port to communicate with the corresponding processor, thereby improving efficiency.
  • FIG. 1 is a schematic structural diagram of a serial port control system based on a complex programmable logic device CPLD according to an embodiment of the present application.
  • Fig. 2 is a schematic structural diagram of a serial port control system based on a complex programmable logic device CPLD according to another embodiment of the present application.
  • FIG. 3 is a schematic flowchart of a communication method of a serial port control system based on a complex programmable logic device CPLD according to an embodiment of the present application.
  • the embodiment of the present application discloses a serial port control system based on complex programmable logic device CPLD, which includes a console 1, a plurality of processors 2 and is arranged between the console 1 and a plurality of processors 2
  • the CPLD includes a controller 31 and a register 32.
  • the console 1 is configured to send an instruction to the controller 31 , the instruction includes the corresponding register address and register content of the serial port of the processor 2 .
  • the controller 31 is configured to parse the instruction to obtain the corresponding register address and register content and write it into the register 32 . According to the register address and register content, the controller 31 communicates with the corresponding serial port of the processor 2 .
  • This application is provided with a controller 31 and a register 32 in the CPLD.
  • the console 1 sends an instruction to the controller 31, and then the controller 31 parses the received instruction to obtain the corresponding register address and register content and write it into the register 32. Finally, according to the register address and register content, the controller 31 communicates with the corresponding processor 2. Therefore, the present application utilizes the controller 31 and the register 32 of the CPLD to automatically switch the serial port to communicate with the corresponding processor 2, thereby improving efficiency.
  • the console 1 is connected to the CPLD through a serial interface, and multiple processors 2 are respectively connected to the CPLD through the serial interface.
  • multiple processors 2 can include X86 processor 21, BMC 22 and other various devices with UART interface, such as CPLD/FPGA 23 etc.
  • the serial port interface is a UART interface, and the console 1 is connected to the CPLD using an RS-232C standard interface.
  • the specific form of the serial port interface can also be other forms, which are not limited here.
  • the console 1 sends instructions to the controller 31 of the CPLD through the serial port interface.
  • controller 31 parses the instruction to obtain the register address and register content of the serial port corresponding to the instruction and write it into register 32, wherein the register address refers to the serial port address of the corresponding processor 2, for example, X86 processor 21, BMC 22 serial port address.
  • the contents of the registers refer to the contents of communication with the corresponding processor 2 , for example, actions to be executed, functions, and data to be transmitted.
  • an instruction may include one or more register addresses and one or more register contents.
  • the controller 31 communicates with the corresponding serial port of the processor 2 according to the register address and register content.
  • the controller 31 is further configured to modify the serial port mode parameters of the CPLD according to the serial port mode parameters of the processor 2 .
  • controller 31 it is beneficial for the controller 31 to communicate with the processor 2 having different serial port mode parameters, and the applicability of the system is improved.
  • the serial port mode parameters of the processor 2 may be different, the controller 31 first obtains the serial port mode parameters of the processor 2 that needs to communicate, and then the controller 31 modifies the serial port mode parameters of the CPLD according to the obtained serial port mode parameters, so that The serial port mode parameter of the CPLD matches the serial port mode parameter of the processor 2 that needs to communicate.
  • serial port mode parameters include but not limited to baud rate and/or check bit.
  • the serial port mode parameter can only include the baud rate, because the baud rate is an index to measure the data transmission rate, and the serial ports communicate with each other simultaneously, must use the same baud rate to operate, so modify the CPLD by the controller 31
  • the baud rate is the same as the baud rate of the processor 2 that needs to communicate, which is conducive to the normal communication between the controller 31 and the serial port of the corresponding processor 2 .
  • the serial port mode parameters may only include check digits, and the correctness of data transmission can be verified by distinguishing check digits.
  • the serial port mode parameters can also include baud rate and check digit at the same time, which is not limited here.
  • the above settings can communicate normally with the processor 2 with different serial port mode parameters without modifying the hardware of the system.
  • the console 1 is also configured to read the status information of the register 32 .
  • the console 1 is also configured to read the status information of the register 32 .
  • the console 1 obtains the state information of the register 32 of the CPLD through the serial port.
  • the state information includes state machine and state parameters.
  • the state machine can feed back the operation process of the CPLD, and the state parameters refer to the data in each state of the CPLD during operation.
  • the controller 31 communicates with the processor 2 according to the configuration of the register 32 to obtain status information returned by the processor 2.
  • controller 31 acquires status information of the processor 2 at preset time intervals.
  • the controller 31 can communicate with one or more processors 2 according to a preset time interval, wherein the specific value of the preset time interval can be set on the CPLD, which is not limited in this application.
  • the register 32 is configured with the information of the processor 2 that needs to be monitored, and the controller 31 sends instructions to the processor 2 that needs to be monitored through the serial port of the CPLD according to the configuration information of the register 32, and the processor that needs to be monitored 2 After receiving the instruction, return the state information of the processor 2 to the CPLD, which is beneficial for the CPLD to obtain the state information of each processor 2.
  • the above process does not require the intervention of the console 1 , and at the same time requires that the processor 2 to be monitored does not need to spend additional processes, thereby reducing the workload of the processor 2 .
  • the CPLD obtains the status information corresponding to the processor 2, it analyzes the obtained status information, and then makes corresponding action instructions, such as shutting down, restarting or reporting an interruption.
  • registers 32 are configured via console 1 and/or processor 2 .
  • Configuring the register 32 in various ways can improve the convenience of the system and enrich its functions.
  • the register 32 can be configured only through the console 1, for example, the console 1 can configure the register 32 in the form of sending instructions through the serial port.
  • the register 32 can also be configured only by the processor 2, and the processor 2 can configure the register 32 through I2C, LPC, etc., and this setting can get rid of the intervention of the console 1.
  • the register 32 can be configured by the console 1 and the processor 2 at the same time, which is not limited here.
  • the specific configuration of the register 32 includes at least one of the following:
  • the controller 31 switches the corresponding serial port communication mode according to the working mode configured by the register 32 .
  • the controller 31 modifies the serial port mode parameters of the CPLD according to the serial port mode parameters configured in the register 32 .
  • the controller 31 obtains the state information of the processor 2 according to the function of obtaining the state information of the processor 2 configured by the register 32 .
  • the configuration of the register 32 is not limited to the specific form described above.
  • the information sent by one of the processors 2 is sent to the other of the processors 2 through the serial port group on the CPLD.
  • the serial port for sending information can be monitored through the serial port for receiving information.
  • the serial port group on the CPLD is composed of multiple serial ports, and multiple processors 2 are respectively connected to the CPLD through the serial ports.
  • the processor 2 first sends information to the CPLD through the serial port, and the CPLD then sends the information to one or more other processors 2 through the corresponding serial port.
  • the application also provides a kind of communication method of the above-mentioned serial port control system based on complex programmable logic device CPLD, and it comprises the following steps:
  • the console 1 sends an instruction to the controller 31;
  • the controller 31 parses the instruction to obtain the corresponding register address and register content and writes it into the register 32;
  • the controller 31 communicates with the corresponding serial port of the processor 2 .
  • the serial port can be automatically switched to communicate with the corresponding processor 2, thereby improving efficiency.

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Abstract

一种基于复杂可编程逻辑器件CPLD的串口控制系统及其通信方法，其中串口控制系统包括控制台、多个处理器以及设置在控制台与多个处理器之间的CPLD，CPLD包括控制器和寄存器；控制台被配置为发送指令至控制器，指令包括对应的处理器的串口的寄存器地址和寄存器内容；控制器被配置为解析指令以获取对应的寄存器地址和寄存器内容并写入寄存器；根据寄存器地址和寄存器内容，控制器与对应的处理器的串口进行通信。利用CPLD的控制器和寄存器能够自动切换串口以与对应的处理器进行通信，进而提高效率。

Description

基于复杂可编程逻辑器件CPLD的串口控制系统及其通信方法
本申请要求于2021年06月22日提交中国专利局、申请号为202110694686.9、发明名称为“基于复杂可编程逻辑器件CPLD的串口控制系统及其通信方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及交换机和服务器硬件设计技术领域，尤其涉及一种基于复杂可编程逻辑器件CPLD的串口控制系统及其通信方法。
背景技术
当前的服务器或交换机的系统设计中，一般包括多个处理器，例如X86处理器、BMC(Baseboard Management Controller，基板管理控制器)以及其他带有UART接口的器件，如CPLD(Complex Programmable Logic Device，复杂可编程逻辑器件)和FPGA(Field－Programmable Gate Array，现场可编程门阵列)等。目前这些端口与控制台(Console)连接方法主要采用Debug header，这种方法需要人工介入，例如需求关机后手动进行连接器Debug，并且针对不同的处理器，要进行多次切换Debug，较为复杂，切换效率较低。
发明内容
本申请公开了一种基于复杂可编程逻辑器件CPLD的串口控制系统，其包括控制台、多个处理器以及设置在所述控制台与所述多个处理器之间的CPLD，所述CPLD包括控制器和寄存器；
所述控制台被配置为发送指令至所述控制器，所述指令包括对应的所述处理器的串口的寄存器地址和寄存器内容；
所述控制器被配置为解析所述指令以获取对应的所述寄存器地址和所述寄存器内容并写入所述寄存器；
根据所述寄存器地址和所述寄存器内容，所述控制器与对应的所述处 理器的串口进行通信。
可选地，所述控制器还被配置为根据所述处理器的串口模式参数修改所述CPLD的串口模式参数。
可选地，所述串口模式参数包括波特率和/或检验位。
可选地，所述控制台还被配置为读取所述寄存器的状态信息。
可选地，所述状态信息包括状态机和状态参数。
可选地，所述控制器根据所述寄存器的配置与所述处理器通讯以获取所述处理器返回的状态信息。
可选地，所述控制器以预设时间间隔获取所述处理器的状态信息。
可选地，所述寄存器通过所述控制台和/或所述处理器进行配置。
可选地，所述处理器中的一者发送出的信息通过所述CPLD的串口组发送至所述处理器中的另一者。
本申请还提供一种如上所述的基于复杂可编程逻辑器件CPLD的串口控制系统的通信方法，其包括：
所述控制台发送指令至所述控制器；
所述控制器解析所述指令以获取对应的所述寄存器地址和所述寄存器内容并写入所述寄存器；
根据所述寄存器地址和所述寄存器内容，所述控制器与对应的所述处理器的串口进行通信。
本申请在CPLD内设置有控制器和寄存器，在使用时，控制台发送指令至控制器，接着控制器解析接收到的指令以获取对应的寄存器地址和寄存器内容并写入寄存器，最后根据寄存器地址和寄存器内容，控制器与对应的处理器通信。因此，本申请利用CPLD的控制器和寄存器能够自动切换串口以与对应的处理器进行通信，进而提高效率。
附图说明
图1为本申请实施例基于复杂可编程逻辑器件CPLD的串口控制系统的结构示意图。
图2为本申请另一实施例基于复杂可编程逻辑器件CPLD的串口控制 系统的结构示意图。
图3是本申请实施例基于复杂可编程逻辑器件CPLD的串口控制系统的通信方法的流程示意图。
具体实施方式
为详细说明本申请的技术内容、结构特征、实现原理及所实现目的及效果，以下结合实施方式并配合附图详予说明。
请参阅图1，本申请实施例公开了一种基于复杂可编程逻辑器件CPLD的串口控制系统，其包括控制台1、多个处理器2以及设置在控制台1与多个处理器2之间的CPLD，CPLD包括控制器31和寄存器32。控制台1被配置为发送指令至控制器31，指令包括对应的处理器2的串口的寄存器地址和寄存器内容。控制器31被配置为解析指令以获取对应的寄存器地址和寄存器内容并写入寄存器32。根据寄存器地址和寄存器内容，控制器31与对应的处理器2的串口进行通信。
本申请在CPLD内设置有控制器31和寄存器32，在使用时，控制台1发送指令至控制器31，接着控制器31解析接收到的指令以获取对应的寄存器地址和寄存器内容并写入寄存器32，最后根据寄存器地址和寄存器内容，控制器31与对应的处理器2通信。因此，本申请利用CPLD的控制器31和寄存器32能够自动切换串口以与对应的处理器2进行通信，进而提高效率。
具体地，控制台1通过串口接口与CPLD连接，多个处理器2分别通过串口接口与CPLD连接。优选地，多个处理器2可包括X86处理器21、BMC 22及其他带有UART接口的各种器件，如CPLD/FPGA 23等。串口接口为UART接口，控制台1采用RS-232C标准的接口与CPLD进行连接，当然串口接口的具体形式也可以是其他形式，在此不作限制。
本申请的基于复杂可编程逻辑器件CPLD的串口控制系统在使用时，控制台1通过串口接口发送指令至CPLD的控制器31。接着控制器31解析该指令以获取该指令对应的串口的寄存器地址和寄存器内容并将其写入 寄存器32，其中，寄存器地址指对应处理器2的串口地址，例如，X86处理器21、BMC 22的串口地址。而寄存器内容指与对应处理器2通信的内容，例如，需要执行的动作、功能及传输数据等。当然一个指令可以包括一个或一个以上寄存器地址以及一个或一个以上寄存器内容。最后，控制器31根据寄存器地址和寄存器内容，与对应的处理器2的串口进行通信。
在一些实施例中，控制器31还被配置为根据处理器2的串口模式参数修改CPLD的串口模式参数。
通过上述技术手段，有利于控制器31与具有不同串口模式参数的处理器2进行通信，提高系统的适用性。
具体地，处理器2的串口模式参数可能存在不同，控制器31先获取需要进行通信的处理器2的串口模式参数，接着控制器31根据获取的串口模式参数，修改CPLD的串口模式参数，使CPLD的串口模式参数与需要进行通信的处理器2的串口模式参数匹配。
进一步地，串口模式参数包括但不限于波特率和/或检验位。
具体地，串口模式参数可以只包括波特率，由于波特率是衡量数据传送速率的指标，同时串口彼此之间通信，必须使用相同的波特率进行操作，因此通过控制器31修改CPLD的波特率以与需要进行通信的处理器2的波特率相同，有利于控制器31与对应的处理器2的串口正常通信。另外串口模式参数也可以只包括检验位，通过辨别检验位可以校验数据传送的正确性。当然串口模式参数也可以同时包括波特率和检验位，在此不作限制。
上述设置无需修改系统的硬件即可与具有不同串口模式参数的处理器2进行正常通信。
在一些实施例中，控制台1还被配置为读取寄存器32的状态信息。通过上述方式，有利于及时获取CPLD的状态信息，便于清楚了解CPLD运作状况，方便监控和后期调试。
具体地，控制台1通过串口获取CPLD的寄存器32的状态信息。
进一步地，状态信息包括状态机和状态参数。状态机能够反馈CPLD的运行流程，状态参数指CPLD在运行时处于各状态的数据。
在一些实施例中，控制器31根据寄存器32的配置与处理器2通讯以 获取处理器2返回的状态信息。
通过上述技术手段，有利于及时获取各处理器2的状态信息，便于监控和调试各处理器2。
进一步地，控制器31以预设时间间隔获取处理器2的状态信息。
具体地，控制器31可根据预设时间间隔与一个或多个处理器2通信，其中，预设时间间隔的具体数值可在CPLD上设定，本申请对此不作限定。在运行过程中，寄存器32配置有需要被监控的处理器2的信息，控制器31根据寄存器32的配置信息，通过CPLD的串口发送指令至需要被监控的处理器2，需要被监控的处理器2接收到指令后，返回该处理器2的状态信息于CPLD，有利于CPLD获取各处理器2的状态信息。上述过程无需控制台1的介入，同时需要被监控的处理器2无需花费额外的进程，进而减少处理器2的工作量。另外，当CPLD获取到对应处理器2的状态信息时，对获取到的状态信息进行分析，接着可作出相应的动作指令，例如关机，重启或者上报中断等。
在一些实施例中，寄存器32通过控制台1和/或处理器2进行配置。
采用多种方式配置寄存器32，能够提高系统的便捷性以及丰富其功能。
具体地，寄存器32可以只通过控制台1进行配置，如控制台1可通过串口发送指令的形式配置寄存器32。寄存器32也可以只通过处理器2配置，处理器2可通过I2C、LPC等方式配置寄存器32，该设置可以摆脱控制台1的介入。当然寄存器32可以由控制台1和处理器2同时配置，在此不作限定。
寄存器32的具体配置至少包括以下一种：
(1)配置工作模式。控制器31根据寄存器32配置的工作模式，切换对应的串口通信模式。
(2)配置串口模式参数。控制器31根据寄存器32配置的串口模式参数，修改CPLD的串口模式参数。
(3)配置读取寄存器32状态信息的功能，控制器31根据寄存器32配置的读取状态信息的功能，读取寄存器32的状态信息。
(4)获取处理器2状态信息的功能，控制器31根据寄存器32配置的获取处理器2状态信息的功能，获取处理器2的状态信息。
当然，寄存器32的配置并不限于上述具体形式。
请参阅图2，在一些实施例中，处理器2中的一者发送出的信息通过CPLD上的串口组发送至处理器2中的另一者。
通过上述技术手段，有利于处理器2之间信息传递，扩展了CPLD的功能应用，比如，可以通过接收信息的串口对发送信息的串口进行监控。
具体地，CPLD上的串口组由多个串口组成，多个处理器2分别通过串口与CPLD连接。处理器2先通过串口发送信息至CPLD，CPLD再将该信息通过对应串口发送到至另外的一个或多个处理器2。
请参阅图3，本申请还提供一种上述的基于复杂可编程逻辑器件CPLD的串口控制系统的通信方法，其包括以下步骤：
101、控制台1发送指令至控制器31；
102、控制器31解析指令以获取对应的寄存器地址和寄存器内容并写入寄存器32；
103、根据寄存器地址和寄存器内容，控制器31与对应的处理器2的串口进行通信。
通过上述方法能够自动切换串口以与对应的处理器2进行通信，进而提高效率。
以上所揭露的仅为本申请的较佳实例而已，当然不能以此来限定本申请之权利范围，因此依本申请申请专利范围所作的等同变化，仍属于本申请所涵盖的范围。

Claims (10)

  1. 一种基于复杂可编程逻辑器件CPLD的串口控制系统，其特征在于，包括控制台、多个处理器以及设置在所述控制台与所述多个处理器之间的CPLD，所述CPLD包括控制器和寄存器；
    所述控制台被配置为发送指令至所述控制器，所述指令包括对应的所述处理器的串口的寄存器地址和寄存器内容；
    所述控制器被配置为解析所述指令以获取对应的所述寄存器地址和所述寄存器内容并写入所述寄存器；
    根据所述寄存器地址和所述寄存器内容，所述控制器与对应的所述处理器的串口进行通信。
  2. 如权利要求1所述的串口控制系统，其特征在于，
    所述控制器还被配置为根据所述处理器的串口模式参数修改所述CPLD的串口模式参数。
  3. 如权利要求2所述的串口控制系统，其特征在于，所述串口模式参数包括波特率和/或检验位。
  4. 如权利要求1所述的串口控制系统，其特征在于，
    所述控制台还被配置为读取所述寄存器的状态信息。
  5. 如权利要求4所述的串口控制系统，其特征在于，
    所述状态信息包括状态机和状态参数。
  6. 如权利要求1所述的串口控制系统，其特征在于，
    所述控制器根据所述寄存器的配置与所述处理器通讯以获取所述处理器返回的状态信息。
  7. 如权利要求6所述的串口控制系统，其特征在于，
    所述控制器以预设时间间隔获取所述处理器的状态信息。
  8. 如权利要求1所述的串口控制系统，其特征在于，
    所述寄存器通过所述控制台和/或所述处理器进行配置。
  9. 如权利要求1所述的串口控制系统，其特征在于，
    所述处理器中的一者发送出的信息通过所述CPLD的串口组发送至所述处理器中的另一者。
  10. 一种如权利要求1至9任一项所述的基于复杂可编程逻辑器件CPLD的串口控制系统的通信方法，其特征在于，包括：
    所述控制台发送指令至所述控制器；
    所述控制器解析所述指令以获取对应的所述寄存器地址和所述寄存器内容并写入所述寄存器；
    根据所述寄存器地址和所述寄存器内容，所述控制器与对应的所述处理器的串口进行通信。
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