WO2022259918A1 - 積層体及び積層体の製造方法 - Google Patents

積層体及び積層体の製造方法 Download PDF

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WO2022259918A1
WO2022259918A1 PCT/JP2022/022163 JP2022022163W WO2022259918A1 WO 2022259918 A1 WO2022259918 A1 WO 2022259918A1 JP 2022022163 W JP2022022163 W JP 2022022163W WO 2022259918 A1 WO2022259918 A1 WO 2022259918A1
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glass substrate
amorphous glass
aln layer
laminate
layer
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English (en)
French (fr)
Japanese (ja)
Inventor
雅延 池田
有親 石田
智 上山
素顕 岩谷
哲也 竹内
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Meijo University
Japan Display Inc
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Meijo University
Japan Display Inc
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Priority to CN202280040757.6A priority Critical patent/CN117441225A/zh
Priority to JP2023527634A priority patent/JP7597339B2/ja
Publication of WO2022259918A1 publication Critical patent/WO2022259918A1/ja
Priority to US18/532,505 priority patent/US20240113174A1/en
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2922—Materials being non-crystalline insulating materials, e.g. glass or polymers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
    • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/38—Nitrides
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
    • C30B29/10—Inorganic compounds or compositions
    • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/015—Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H10H20/01335—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials the light-emitting regions comprising nitride materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/817—Bodies characterised by the crystal structures or orientations, e.g. polycrystalline, amorphous or porous
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/22—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials using physical deposition, e.g. vacuum deposition or sputtering
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2924—Structures
    • H10P14/2925—Surface structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3416—Nitrides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3466—Crystal orientation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
    • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
    • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
    • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/343—Gate regions of field-effect devices having PN junction gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/822—Materials of the light-emitting regions
    • H10H20/824—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP
    • H10H20/825—Materials of the light-emitting regions comprising only Group III-V materials, e.g. GaP containing nitrogen, e.g. GaN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2921—Materials being crystalline insulating materials

Definitions

  • the present disclosure relates to a laminate and a method for manufacturing the laminate.
  • Non-Patent Document 1 It is known to interpose an AlN buffer layer between the sapphire substrate and the GaN when growing GaN on the sapphire substrate (see, for example, Non-Patent Document 1). This technique has the problem that the film formation temperature is high and the substrate is expensive.
  • Patent Documents 1, 2 and 3, for example attempts have been made to grow GaN using glass as a substrate.
  • An object of the present disclosure is to provide a laminate that promotes high-quality crystal growth of a GaN layer and a method for manufacturing the laminate.
  • a laminate according to one aspect of the present disclosure includes an amorphous glass substrate and an AlN layer formed on the amorphous glass substrate, and the AlN layer is formed on the amorphous glass substrate.
  • the amorphous glass substrate is c-axis oriented, has a glass transition temperature (Tg) of 720° C. or more and 810° C. or less, and has a coefficient of thermal expansion (CTE) of 3.5 ⁇ . 10 ⁇ 6 [1/K] or more and 4.0 ⁇ 10 ⁇ 6 [1/K] or less, and the softening point of the amorphous glass substrate is 950° C. or more and 1050° C. or less.
  • a method for manufacturing a laminate according to another aspect of the present disclosure has a glass transition temperature (Tg) of 720° C. or higher and 810° C. or lower and a thermal expansion coefficient (CTE) of 3.5 ⁇ 10 ⁇ 6 [1/K] or higher.
  • Tg glass transition temperature
  • CTE thermal expansion coefficient
  • FIG. 1 is an explanatory view showing a method for manufacturing a laminate according to Embodiment 1.
  • FIG. 2 is a cross-sectional view of a laminate according to Embodiment 1.
  • FIG. 3A and 3B are schematic diagrams for explaining the first film forming process of the first embodiment.
  • FIG. 4 is a table showing evaluation results of evaluation examples of the first embodiment.
  • 5 is a diagram showing the XRD spectrum of Example 1.
  • FIG. 6 is a diagram showing the XRD spectrum of Example 1.
  • FIG. 7 is a diagram showing an XRD spectrum of Comparative Example 1.
  • FIG. 8 is a diagram showing an XRD spectrum of Comparative Example 2.
  • FIG. 9 is a cross-sectional view of a semiconductor device including a laminate according to Embodiment 2.
  • FIG. 10A and 10B are explanatory diagrams showing a method of manufacturing a semiconductor device including the laminate according to the second embodiment.
  • 11 is a cross-sectional view of a semiconductor device including a laminate according to Embodiment 3.
  • FIG. 12A and 12B are explanatory diagrams showing a method of manufacturing a semiconductor device including the laminate according to the third embodiment.
  • FIG. 1 is an explanatory view showing a method for manufacturing a laminate according to Embodiment 1.
  • FIG. 2 is a cross-sectional view of a laminate according to Embodiment 1.
  • FIG. 3A and 3B are schematic diagrams for explaining the first film forming process of the first embodiment.
  • the amorphous glass substrate 1 is prepared as the substrate of the laminate 10 shown in FIG. 2 (step ST1).
  • the substrate preparation process is defined as the first process.
  • the glass transition temperature (Tg) of the amorphous glass substrate 1 is 720° C. or higher and 810° C. or lower.
  • the coefficient of thermal expansion (CTE) of the amorphous glass substrate 1 is 3.5 ⁇ 10 ⁇ 6 [1/K] or more and 4.0 ⁇ 10 ⁇ 6 [1/K] or less.
  • the softening point of the amorphous glass substrate 1 is 950° C. or higher and 1050° C. or lower.
  • the AlN layer 2 is formed in direct contact with the amorphous glass substrate 1, as shown in FIG.
  • the first film forming process is referred to as the second process.
  • the AlN layer 2 is formed as a thin film by the sputtering apparatus 51 shown in FIG. 3, not by metal organic chemical vapor deposition (MOCVD).
  • MOCVD metal organic chemical vapor deposition
  • the amorphous glass substrate 1 is attached to the anode 53 of the sputtering device 51, and the Al target 55 is attached to the cathode 52 of the sputtering device.
  • the anode 53 and cathode 52 are each connected to a power supply 54 .
  • the exhaust valve 59 is closed, and argon gas and nitrogen gas are enclosed in the sputtering device 51 through the argon introduction valve and the nitrogen introduction valve.
  • the AlN layer 2 is formed directly on the amorphous glass substrate 1 at a film forming temperature of 400° C. or higher and 600° C. or lower by magnetron sputtering. If the film formation temperature is lower than 400° C., the AlN layer 2 is difficult to be c-axis oriented, and if the film formation temperature exceeds 600° C., degassing from the film formation chamber makes it difficult for the AlN layer 2 to be c-axis oriented. Since the AlN layer 2 is formed at a temperature of 400° C. or higher and 600° C. or lower, the AlN layer 2 can be formed on the amorphous glass in a c-axis oriented state.
  • the coefficient of thermal expansion (CTE) of the AlN layer 2 to be deposited is 4.2 ⁇ 10 ⁇ 6 [1/K] or more and 5.3 ⁇ 10 ⁇ 6 [1/K] or less. Even if the film forming temperature rises and the amorphous glass substrate 1 thermally expands, the thermal expansion coefficient (CTE) of the amorphous glass substrate 1 and the thermal expansion coefficient (CTE) of the AlN layer 2 are close to each other. Expansion deviation is less likely to occur, and the AlN layer 2 is more likely to be c-axis oriented.
  • the glass transition temperature (Tg) of the amorphous glass substrate 1 is 720°C or higher and 810°C or lower, and the softening point of the amorphous glass substrate 1 is 950°C or higher and 1050°C or lower. Since the film formation temperature is low, the stability of the amorphous glass substrate 1 during film formation can be kept high. If the glass transition temperature (Tg) of the amorphous glass substrate 1 is lower than 720° C. and the softening point is lower than 950° C., the deposited AlN layer 2 is difficult to be c-axis oriented. If the glass transition temperature (Tg) of the amorphous glass substrate 1 exceeds 810° C. and the softening point exceeds 1050° C., the film formation temperature can be set high, but the c-axis orientation of the formed AlN becomes difficult.
  • the thickness of the amorphous glass substrate 1 is 0.4 mm or more and 1.0 mm or less. If the thickness of the amorphous glass substrate 1 is less than 0.4 mm, the amorphous glass substrate 1 tends to warp due to the film stress of the AlN layer 2 caused by the film formation temperature. If the thickness of the amorphous glass substrate 1 exceeds 1.0 mm, it tends to be difficult to transport the substrate in the steps after the process of forming the AlN layer 2 when forming a semiconductor device, resulting in increased product and manufacturing costs. Not good for reduction.
  • the film thickness of the AlN layer 2 is 20 nm or more and 400 nm or less. If the thickness of the AlN layer 2 is less than 20 nm, the c-axis orientation tends to be difficult. When the thickness of the AlN layer exceeds 400 nm, the film stress of the AlN layer 2 tends to warp the substrate.
  • FIG. 4 is a table showing evaluation results of evaluation examples of the first embodiment. Substrates of Example 1, Example 2, Example 3, Comparative Example 1 and Comparative Example 2 were prepared.
  • composition of the substrate of Example 1 is alkaline earth aluminoborosilicate glass.
  • composition of the substrate of Example 2 is alkali-free aluminosilicate glass.
  • composition of the substrate of Example 3 is alkali-free aluminosilicate glass different from that of Example 2.
  • Comparative Example 1 is a highly heat-resistant borosilicate crown glass called BK7.
  • Comparative Example 2 is quartz.
  • each substrate of Examples 1, 2, 3, Comparative Examples 1 and 2 is 0.50 mm.
  • the glass transition temperature (Tg), coefficient of thermal expansion (CTE), softening point and density of Example 1, Example 2, Example 3, Comparative Example 1 and Comparative Example 2 are shown in FIG.
  • the arithmetic average roughness (Ra) of the substrate surfaces of Examples 1, 2 and 3 was measured and shown in FIG. Arithmetic mean roughness (Ra) was measured with an atomic force microscope (AFM).
  • the surface of the amorphous glass substrate 1 has an arithmetic mean roughness (Ra) of 3 nm or less.
  • Ra arithmetic mean roughness
  • An AlN layer with a thickness of 200 nm was formed on each substrate surface of Examples 1, 2, 3, and Comparative Examples 1 and 2 by magnetron sputtering at a film formation temperature of 500°C.
  • X-ray diffraction X-Ray Diffraction
  • the vertical axis is the X-ray diffraction intensity (arbitrary unit) and the horizontal axis is the rotation angle 2 ⁇ [deg].
  • the XRD spectrum was measured using an X-ray diffractometer manufactured by Rigaku Corporation. As the X-ray source, the characteristic X-ray of CuK ⁇ (wavelength: 1.5418 ⁇ ) was used, and the XRD spectrum was measured by X-ray diffraction measurement in 2 ⁇ - ⁇ mode (or ⁇ mode). As a result, the rotation angle 2 ⁇ / ⁇ [deg ], the peak intensity near 36 [deg] is estimated to be due to the c-axis orientation of the AlN layer, and is listed in Table 1.
  • the vertical axis is the X-ray diffraction intensity (arbitrary unit) and the horizontal axis is the rotation angle 2 ⁇ [deg].
  • the XRD spectrum was measured using an X-ray diffractometer manufactured by Rigaku Corporation.
  • the substrate of Example 1 exhibits a broad XRD spectrum, indicating that it is an amorphous glass substrate. Although illustration is omitted, the substrates of Examples 2 and 3 also exhibit broad XRD spectra, and thus are amorphous glass substrates.
  • the peak intensity PI near 22 [deg] in the XRD spectrum shown in FIG. 6 indicates the presence of a local Si—O crystal structure. It was confirmed that the AlN layer 2 was easily oriented along the c-axis due to the presence of this Si—O crystal structure. The regular crystal structure of Si—O existing on the surface of the amorphous glass substrate 1 facilitates the c-axis orientation of the AlN layer 2 .
  • FIG. 10A and 10B are explanatory diagrams showing a method of manufacturing a semiconductor device including the laminate according to the second embodiment.
  • the same reference numerals are assigned to the same configurations and steps as in the first embodiment, and detailed descriptions thereof are omitted.
  • a semiconductor device 30 shown in FIG. 9 is an LED (Light Emitting Diode), which is a light emitting element.
  • the semiconductor device 30 has the electrode 35 electrically connected to the cathode and the electrode 36 electrically connected to the anode.
  • a semiconductor device 30 is formed on the laminate 10 of the first embodiment.
  • the semiconductor device 30 has a junction layer 31 , an n-type clad layer 32 , a light emitting layer 33 and a p-type clad layer 34 .
  • the light emitting layer 33 has a multiple quantum well structure (MQW structure) in which well layers and barrier layers each having several atomic layers are periodically laminated for high efficiency.
  • MQW structure multiple quantum well structure
  • the second film formation process is performed.
  • the bonding layer 31 is formed on the AlN layer 2 (step ST3).
  • the bonding layer 31 is an undoped GaN layer.
  • step ST3 After the second film formation process (step ST3), the third film formation process is performed.
  • an n-type cladding layer 32 of gallium nitride (GaN) doped with silicon (Si) is formed on the bonding layer 31 (step ST4).
  • a light emitting layer 33 is formed on the n-type cladding layer 32 by repeatedly stacking multiple layers of indium gallium nitride (InxGa(1-x)N) and gallium nitride (GaN). (Step ST5).
  • a magnesium (Mg)-doped gallium nitride (GaN) p-type clad layer 34 is formed on the n-type clad layer 32 (step ST6).
  • step ST6 patterning is performed by plasma etching or the like in the photolithography process.
  • the n-type electrode forming process is performed.
  • the electrode 35 is formed from indium (In) (step ST8).
  • step ST8 After the n-type electrode formation process (step ST8), the p-type electrode formation process is performed. In the p-type electrode forming step, a palladium-gold alloy (PdAu) electrode 36 is formed (step ST9).
  • PdAu palladium-gold alloy
  • FIG. 11 is a cross-sectional view of a semiconductor device including a laminate according to Embodiment 3.
  • FIG. 12A and 12B are explanatory diagrams showing a method of manufacturing a semiconductor device including the laminate according to the third embodiment.
  • the same reference numerals are assigned to the same configurations and steps as in Embodiment 1, and detailed description thereof will be omitted.
  • a semiconductor device 40 shown in FIG. 11 is a HEMT (High Electron Mobility Transistor) device.
  • HEMT High Electron Mobility Transistor
  • the semiconductor device 40 has an electron transit layer 41, an electron supply layer 42, a barrier layer 43, a gate electrode 44, a source electrode 45 and a drain electrode 46.
  • Gate electrode 44 sandwiched between source electrode 45 and drain electrode 46 forms Schottky contact with barrier layer 43 .
  • the second film formation process is performed.
  • the electron transit layer 41 is formed on the AlN layer 2 (step ST11).
  • the electron transit layer 41 is an undoped GaN layer.
  • the third film formation process is performed.
  • the electron supply layer 42 is formed on the electron transit layer 41 (step ST12).
  • Electron supply layer 42 is undoped indium gallium nitride (InxGa(1-x)N).
  • the fourth film formation process is performed.
  • the barrier layer 43 is formed on the electron supply layer 42 (step ST13).
  • the barrier layer 43 is gallium nitride (GaN) doped with magnesium (Mg).
  • the fifth film formation process is performed.
  • the gate electrode 44 is formed on the barrier layer 43 (step ST14).
  • the shapes of the barrier layer 43 and the gate electrode 44 are patterned by plasma etching or the like in the photolithography process (step ST15).
  • the electrode film formation process is performed.
  • metal layers to be the source electrode 45 and the drain electrode 46 are formed (step ST16).
  • the shape of the metal layer formed in the electrode film formation process is patterned by plasma etching or the like in the photolithography process (step ST17) to form the source electrode 45 and the drain. Electrodes 46 are formed.

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  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
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  • Metallurgy (AREA)
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PCT/JP2022/022163 2021-06-11 2022-05-31 積層体及び積層体の製造方法 Ceased WO2022259918A1 (ja)

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CN202280040757.6A CN117441225A (zh) 2021-06-11 2022-05-31 层叠体及层叠体的制造方法
JP2023527634A JP7597339B2 (ja) 2021-06-11 2022-05-31 積層体及び積層体の製造方法
US18/532,505 US20240113174A1 (en) 2021-06-11 2023-12-07 Laminate and method of manufacturing laminate

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JP2021098291 2021-06-11

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WO2024181028A1 (ja) * 2023-02-28 2024-09-06 株式会社ジャパンディスプレイ Ｌｅｄ素子、ｌｅｄアレイ基板及びｌｅｄ素子の製造方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07109573A (ja) * 1993-10-12 1995-04-25 Semiconductor Energy Lab Co Ltd ガラス基板および加熱処理方法
US20080289420A1 (en) * 2004-07-01 2008-11-27 The University Of Paisley Ultrasound Transducers
JP2012224539A (ja) * 2011-04-19 2012-11-15 Samsung Electronics Co Ltd ＧａＮ薄膜構造物、その製造方法、及びそれを含む半導体素子
CN103334090A (zh) * 2013-07-17 2013-10-02 辽宁太阳能研究应用有限公司 InN/AlN/玻璃结构的制备方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2013158210A2 (en) * 2012-02-17 2013-10-24 Yale University Heterogeneous material integration through guided lateral growth
DE102014104798B4 (de) * 2014-04-03 2021-04-22 Schott Ag Harte anti-Reflex-Beschichtungen sowie deren Herstellung und Verwendung
WO2015181648A1 (en) * 2014-05-27 2015-12-03 The Silanna Group Pty Limited An optoelectronic device
TWI892641B (zh) * 2019-01-31 2025-08-01 美商伊雷克托科學工業股份有限公司 光學系統

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07109573A (ja) * 1993-10-12 1995-04-25 Semiconductor Energy Lab Co Ltd ガラス基板および加熱処理方法
US20080289420A1 (en) * 2004-07-01 2008-11-27 The University Of Paisley Ultrasound Transducers
JP2012224539A (ja) * 2011-04-19 2012-11-15 Samsung Electronics Co Ltd ＧａＮ薄膜構造物、その製造方法、及びそれを含む半導体素子
CN103334090A (zh) * 2013-07-17 2013-10-02 辽宁太阳能研究应用有限公司 InN/AlN/玻璃结构的制备方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
KUSAKA K, TANIGUCHI D, HANABUSA T, TOMINAGA K: "Effect of sputtering gas pressure and nitrogen concentration on crystal orientation and residual stress in sputtered AlN films", VACUUM., PERGAMON PRESS., GB, vol. 66, no. 3-4, 1 August 2002 (2002-08-01), GB , pages 441 - 446, XP093012927, ISSN: 0042-207X, DOI: 10.1016/S0042-207X(02)00168-9 *

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024181028A1 (ja) * 2023-02-28 2024-09-06 株式会社ジャパンディスプレイ Ｌｅｄ素子、ｌｅｄアレイ基板及びｌｅｄ素子の製造方法

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