WO2022257592A1 - 一种开关切换方法及相关装置 - Google Patents

一种开关切换方法及相关装置 Download PDF

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Publication number
WO2022257592A1
WO2022257592A1 PCT/CN2022/086439 CN2022086439W WO2022257592A1 WO 2022257592 A1 WO2022257592 A1 WO 2022257592A1 CN 2022086439 W CN2022086439 W CN 2022086439W WO 2022257592 A1 WO2022257592 A1 WO 2022257592A1
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Prior art keywords
mipi
switch
instruction
control
bit
Prior art date
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PCT/CN2022/086439
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English (en)
French (fr)
Inventor
陈丹
江成
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荣耀终端有限公司
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Application filed by 荣耀终端有限公司 filed Critical 荣耀终端有限公司
Priority to EP22764989.4A priority Critical patent/EP4123397A4/en
Priority to US17/913,554 priority patent/US20240126224A1/en
Publication of WO2022257592A1 publication Critical patent/WO2022257592A1/zh

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B15/00—Systems controlled by a computer
    • G05B15/02—Systems controlled by a computer electric
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423—Input/output
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/18—Input circuits, e.g. for coupling to an antenna or a transmission line
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00—Program-control systems
    • G05B2219/20—Pc systems
    • G05B2219/25—Pc structure of the system
    • G05B2219/25257—Microcontroller
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the solution relates to the field of radio frequency technology, in particular to a switching method and a related device.
  • This application provides a switch switching method and related devices, which can realize multiple MIPI switches sharing one MIPI address, thereby realizing one MIPI command to control multiple MIPI switches, which not only overcomes the platform's limitation on the number of MIPI switches, but also reduces the number of MIPI switches.
  • the response time of the switch reduces the delay of switching MIPI switches.
  • the present application provides a switch switching method, which can be applied to a mobile industry processor interface MIPI switch.
  • MIPI switches can receive MIPI commands.
  • the MIPI switch may include a first pin.
  • MIPI commands may include control commands.
  • the MIPI switch may determine the Y-bit instruction in the control instruction according to the state of the first pin.
  • the control instructions include X-bit instructions, and Y is less than or equal to X.
  • the MIPI switch switches according to the Y-bit instruction.
  • the MIPI switch can determine which part of the control command to respond to according to the state of the first pin it includes, that is, the Y-bit command mentioned in the above method. It can be understood that the decoder in the MIPI switch can convert the Y-bit command into a device state, that is, control the opening and closing of the sub-switches in the MIPI switch. It should be noted that, according to the above method, one MIPI command can contain different Y-bit commands, so one MIPI command can be used to control multiple MIPI switches. The method can reduce the delay of switching the MIPI switch, so that the MIPI switch responds in time, and can also overcome the limitation of the platform on the number of MIPI switches.
  • the MIPI switch corresponds to the first MIPI address; the MIPI command includes a second MIPI address; when it is determined that the MIPI command is used to control the MIPI switch, the MIPI switch is configured according to the first pin
  • the switch switching method may also include: the MIPI switch parses the MIPI instruction to obtain the second MIPI address and the control instruction; in the case of determining that the MIPI instruction is used to control the MIPI switch, the MIPI switch according to The state of the first pin determines the Y-bit instruction in the control instruction, which may specifically include: the MIPI switch judges whether the first MIPI address is consistent with the second MIPI address; if the first MIPI address is consistent with the second MIPI address, the MIPI switch is configured according to The state of a pin determines the Y bit command in the control command.
  • the Y-bit command that the MIPI switch responds to can be determined according to the state of the first pin, so that the MIPI switch can smoothly respond to the corresponding MIPI command.
  • the first pin has N states; the MIPI switch can determine the Y-bit command in the control command according to the state of the first pin, specifically including: the MIPI switch is based on the first
  • the control logic can determine the Y bit instruction in the control instruction corresponding to the state of the first pin; the first control logic includes the correspondence between N states and the Y bit instruction, wherein different connection states correspond to different Y bits in the control instruction instruction.
  • the first pin may be a Mode pin.
  • the MIPI switch may include a Mode identification module. Based on the first control logic and the state of the Mode pin, the Mode identification module can determine the Y-bit instruction in the control instructions corresponding to the state of the Mode pin.
  • the Mode pin can have two states: 1) the Mode pin is connected to a high level; 2) the Mode pin is connected to a low level.
  • the Mode pin can have four states: 1) the Mode pin is connected to a high level; 2) the Mode pin is connected to a high level with a load; 3) the Mode pin is connected to a low level ; 4) The Mode pin is connected to a low level with a load.
  • the K-bit instruction in the Y-bit instruction is a flag bit instruction; K is a positive integer not less than 1; the MIPI switch is switched according to the Y-bit instruction, which may specifically include : if the flag bit instruction indicates the first state, the MIPI switch does not respond to the Y bit instruction; if the flag bit instruction indicates the second state, the MIPI switch responds to the Y bit instruction.
  • the flag bit instruction can be set in the Y bit instruction.
  • the MIPI switch can judge whether the switch responds to the Y bit command according to the flag bit command in the Y bit command. Therefore, when one MIPI command can control multiple MIPI switches, not every switch controlled by the MIPI command must respond to the MIPI command.
  • the MIPI switch can respond to MIPI commands when it needs to switch between the open state and the closed state. Unnecessary decoding process can be saved, thereby reducing the response time of the MIPI switch.
  • the MIPI switch may further include general-purpose input and output GPIO pins. At least one of the GPIO pins in the MIPI switch is connected to a GPIO switch, wherein different GPIO pins are connected to different GPIO switches.
  • the switch switching method may also include: the MIPI switch determines the Z-bit instruction in the control instruction corresponding to the GPIO pin based on the second control logic; the second control logic includes the corresponding relationship between the GPIO pin and the Z-bit instruction, wherein different GPIO tubes The pins correspond to different Z-bit commands in the control command; Z is less than or equal to X; the MIPI switch switches the GPIO switch according to the Z-bit command.
  • the MIPI switch may further include GPIO pins, and be connected to the GPIO switch through the GPIO pins. Moreover, the MIPI switch can also use part of the control instructions to control the GPIO switch. Therefore, not only can one MIPI command be used to control multiple MIPI switches, but also one MIPI command can be used to control multiple MIPI switches and at least one GPIO switch. Switching of more kinds of switches can be realized, so that switching of multiple antenna frequencies can be realized more conveniently.
  • the present application provides a MIPI switch
  • the MIPI switch may include: a pin module, a sub-switch module, and a controller.
  • the pin module may include a first pin.
  • the sub-switch module may include at least one sub-switch.
  • the controller can be used to receive MIPI instructions.
  • MIPI commands may include control commands.
  • the controller may also be configured to determine the Y-bit instruction in the control instruction according to the state of the first pin when it is determined that the MIPI instruction is used to control the MIPI switch.
  • the control instructions may include X bit instructions, Y being less than or equal to X.
  • the controller can also be used to switch at least one sub-switch according to the Y bit instruction.
  • the MIPI command includes the second MIPI address.
  • the controller includes: an address register, the first MIPI address is stored in the address register; a decoder for parsing the MIPI instruction to obtain the second MIPI address and a control instruction; judging whether the first MIPI address and the second MIPI address consistent; the data register is used to store the control instruction; the Mode identification module is used to determine the Y bit instruction in the control instruction according to the state of the first pin when the first MIPI address is consistent with the second MIPI address.
  • the first pin has N states.
  • the Mode identification module when used to determine the Y-bit instruction in the control instruction according to the state of the first pin, is specifically used to: determine the Y-bit instruction in the control instruction corresponding to the state of the first pin based on the first control logic .
  • the first control logic includes correspondences between N states and Y-bit instructions, wherein different connection states correspond to different Y-bit instructions in the control instructions.
  • the K-bit instructions in the Y-bit instructions are flag bit instructions.
  • K is a positive integer not less than 1.
  • the controller may further include: a decoder for switching the at least one sub-switch according to the Y-bit instruction; when the decoder is used for switching the at least one sub-switch according to the Y-bit instruction, specifically use In: if the flag bit instruction indicates the first state, the decoder does not respond to the Y bit instruction; if the flag bit instruction indicates the second state, the decoder responds to the Y bit instruction.
  • the MIPI switch further includes general-purpose input and output GPIO pins. At least one of the GPIO pins in the MIPI switch is connected to a GPIO switch, wherein different GPIO pins are connected to different GPIO switches.
  • the decoder can also be used to: determine the Z-bit instruction in the control instructions corresponding to the GPIO pins based on the second control logic.
  • the second control logic includes a correspondence between GPIO pins and Z-bit instructions, wherein different GPIO pins correspond to different Z-bit instructions in the control instructions. Z is less than or equal to X.
  • the controller can also be used to toggle the GPIO switch according to the Z bit command.
  • the present application provides an electronic device.
  • the electronic device includes the above-mentioned second aspect and the MIPI switch provided in combination with any one of the implementation manners of the above-mentioned second aspect.
  • the present application provides a computer storage medium, including instructions.
  • the above-mentioned instructions are run on the MIPI switch or the electronic device, the above-mentioned MIPI switch or the electronic device executes the above-mentioned first aspect and any combination of the above-mentioned first aspect.
  • a switch switching method provided by an implementation manner.
  • the embodiment of the present application provides a computer program product containing instructions, when the above-mentioned computer program product runs on the MIPI switch or the electronic device, the above-mentioned MIPI switch or the electronic device executes the above-mentioned first aspect and combines the above-mentioned first The switching method provided by any one of the implementation manners in the aspect.
  • the embodiment of the present application provides a chip, the chip is applied to an electronic device, the chip includes one or more processors, and the processor is used to invoke computer instructions so that the electronic device executes the above-mentioned first aspect and in combination with the above-mentioned The switching method provided by any one of the implementation manners in the first aspect.
  • the above-mentioned MIPI switch provided by the second aspect, the electronic device provided by the third aspect, the computer storage medium provided by the fourth aspect, the computer program product provided by the fifth aspect, and the chip provided by the sixth aspect are all used to execute the present application The method provided by the embodiment. Therefore, the beneficial effects that it can achieve can refer to the beneficial effects in the corresponding method, and will not be repeated here.
  • FIG. 1 is a schematic diagram of a MIPI switch provided in an embodiment of the present application
  • FIG. 2 is a schematic diagram of a MIPI instruction provided by an embodiment of the present application.
  • FIG. 3 is a schematic diagram of the principle of a MIPI command control switch provided in an embodiment of the present application
  • FIG. 4A is a schematic diagram of another MIPI switch provided in the embodiment of the present application.
  • FIG. 4B is a schematic diagram of another MIPI switch provided by the embodiment of the present application.
  • FIG. 5 is a schematic diagram of a switching method provided in an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a switching system provided by an embodiment of the present application.
  • FIG. 7 is a flow chart of a switching method provided in an embodiment of the present application.
  • FIG. 8 is a schematic diagram of the structure and principle of a controller provided in the embodiment of the present application.
  • FIG. 9 is a schematic diagram of the principle of a Mode identification module provided by an embodiment of the present application.
  • FIG. 10 is a schematic diagram of the principle of another MIPI command control switch provided in the embodiment of the present application.
  • FIG. 11 is a schematic diagram of the principle of another MIPI command control switch provided by the embodiment of the present application.
  • FIG. 12 is a schematic diagram of the principle of another MIPI command control switch provided in the embodiment of the present application.
  • FIG. 13 is a schematic diagram of the state of a Mode pin provided in an embodiment of the present application.
  • FIG. 14 is a schematic diagram of connection of a MIPI switch provided by an embodiment of the present application.
  • FIG. 15 is a schematic diagram of a MIPI switch provided in an embodiment of the present application.
  • FIG. 16 is a schematic diagram of the principle of another MIPI instruction control switch provided by the embodiment of the present application.
  • FIG. 17 is a schematic diagram of connection of another MIPI switch provided in the embodiment of the present application.
  • FIG. 18 is a schematic diagram of connection of another MIPI switch provided in the embodiment of the present application.
  • FIG. 19 is a schematic diagram of the principle of a decoder provided in the embodiment of the present application.
  • FIG. 20 is a schematic structural diagram of a MIPI switch provided in an embodiment of the present application.
  • FIG. 21 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • MIPI Mobile Industry Processor Interface
  • MIPI Mobile Industry Processor Interface
  • MIPI Mobile Industry Processor Interface
  • GPIO General-purpose input/output
  • GPI general output
  • GPO general output
  • GPIO general input and output
  • Pins also called pins, are called Pins in English. They are the connections between the internal circuit of the integrated circuit (chip) and the peripheral circuit. All the pins constitute the interface of this chip. A section of the end of a lead that is soldered to form a solder joint with a pad on a printed board.
  • FIG. 1 is a schematic diagram of a MIPI switch provided in an embodiment of the present application.
  • the MIPI switch includes a controller and sub-switches inside. Among them, the role of the controller is to translate MIPI instructions into control signals for the internal sub-switches; the opening and closing of the sub-switches are controlled by the level output by the controller, and the number of sub-switches can be one or more. One end of each sub-switch port is grounded and the other end is connected to a matching element.
  • the matching elements connected to the sub-switches in the MIPI switch are connected to the antenna in parallel, as shown in Figure 1.
  • Sub-switch 1 One end is connected to GND (ground), the other end is connected to matching element 1
  • one end of sub-switch 2 is connected to GND (ground)
  • the other end is connected to matching element 2, that is, sub-switch 1 is connected in series with matching element 1
  • sub-switch 2 is connected in series with matching element 2 connection, then matching element 1 and matching element 2 are connected in parallel to the antenna.
  • the MIPI switch may also include some other pins and devices, which are not limited in this application.
  • the MIPI switch is controlled by the MIPI command.
  • the MIPI command includes address bits and control command bits.
  • the address bits have a total of 4 bits, which are used to indicate the address information (MIPI address) of the MIPI switch controlled by the MIPI command, and the control command bits A total of 8 bits, these 8-bit control instructions are specifically used to control the state of the MIPI switch, that is, to control the opening and closing of the MIPI switch sub-switch, as shown in Figure 2, Bit0-Bit8 are used to indicate the specific content of the MIPI instruction.
  • each MIPI switch corresponds to an independent MIPI address
  • the MIPI command is broadcast on the MIPI bus
  • only the MIPI switch corresponding to the MIPI address in the MIPI command will respond to the MIPI command.
  • Figure 3 is a schematic diagram of the principle of a MIPI command control switch provided by the embodiment of the present application
  • MIPI command A is broadcast on the bus
  • the address bit in the command is 0101
  • the MIPI address of switch A is 0101
  • the address of switch A is the same as the address indicated by the address bits in MIPI instruction A, so switch A responds to MIPI instruction A, while the address of switch B is 0001, and the address of switch C is 1011.
  • the addresses of these two switches are the same as MIPI
  • the addresses indicated by the address bits in command A are different, so switch B and switch C do not respond to MIPI command A.
  • the MIPI command controls the MIPI switch to control the opening and closing of the sub-switches in the MIPI switch.
  • the MIPI switch in FIG. 4A and FIG. 4B includes two sub-switches.
  • the MIPI command controls the MIPI switch as shown in FIG. 4A, the sub-switch 1 can be controlled to be closed, and the sub-switch 2 is turned off at this time, or, as shown in FIG. 4B As shown, the sub-switch 2 can be controlled to be closed, and the sub-switch 1 is turned off at this time.
  • multiple MIPI switches can be connected to the MIPI bus to support the switching of different operating frequencies.
  • the MIPI command can only control the MIPI address corresponding to the command.
  • MIPI switch, and MIPI commands can only be sent serially on the MIPI bus, so when it is necessary to switch the state of multiple MIPI switches, multiple MIPI commands need to be sent serially, as shown in Figure 5, if you want to switch switch 1 to switch 5
  • a total of 5 MIPI switch states for example, switching from the open state to the closed state, or switching from the closed state to the open state, need to send 5 MIPI commands, and the MIPI addresses in the 5 MIPI commands correspond to 5
  • the MIPI address of a MIPI switch because MIPI commands are sent serially on the MIPI bus (the next command can only be sent after one command is sent), so 5 MIPI switches cannot respond at the same time. It can be understood that in the above switch switching method, the response time of the switch is very long, which leads to too long
  • the platform will also have restrictions on the number of MIPI switches.
  • the modem communication baseband chip
  • the modem has requirements on the total delay of antenna switching, so the number of MIPI switches is limited.
  • the present application provides a switch switching method and a related device, which can realize multiple MIPI switches sharing one address, thereby realizing one MIPI instruction to control multiple MIPI switches, overcoming the limitation of the platform on the number of MIPI switches, and reducing The response time of the switch is improved, that is, the delay of switching the switch is reduced.
  • FIG. 6 is a schematic diagram of a switch switching system provided by an embodiment of the present application.
  • the switch switching system includes at least one MIPI switch, MIPI bus, matching element and antenna.
  • the inside of the MIPI switch includes a controller and at least one sub- The controller of the switch is connected to the MIPI bus, one end of the sub-switch is connected in series with the matching element and then connected to the antenna, and the other end is grounded. It should be noted that when a MIPI switch includes multiple sub-switches, these sub-switches are connected in parallel.
  • the switching system includes more than one MIPI switch
  • two or more MIPI switches can share one address, so as to implement one MIPI instruction to control multiple switches.
  • the control command bits in the MIPI command (as shown in Figure 2, a total of 8 bits) can be set. divided.
  • the MIPI switch may include a controller and a first pin, and there is a connection relationship between the controller and the first pin.
  • the first pin may include but not limited to a Mode pin. The following descriptions take the Mode pin as an example.
  • the different states of the Mode pins can be corresponding to the divided control command bits one by one, so that when the MIPI switch reads the MIPI command, it can distinguish which bits the MIPI switch corresponds to at this time according to the different states of the Mode pins. instruction bits.
  • the controller inside the MIPI switch parses the MIPI command to determine whether the address in the MIPI command is the same as the address of the MIPI switch. If not, the MIPI switch does not respond to the MIPI command; if they are the same , the controller continues to analyze the control command of the MIPI command, and recognize the state of the Mode pin to determine which bits of the control command control the MIPI switch, and then convert these control commands into the device state , so as to achieve switching.
  • S701 Receive a MIPI command, where the MIPI command includes a MIPI address and a control command.
  • the main control device or platform issues a corresponding MIPI command, and then the MIPI bus broadcasts the MIPI command, and the MIPI switch receives the MIPI command.
  • the MIPI switch includes a first pin, and the first pin may include but not limited to a Mode pin (the Mode pin is used as an example for description below).
  • MIPI commands may include MIPI address and control commands.
  • the MIPI command is received by a controller in the MIPI switch.
  • FIG. 8 is a schematic structural diagram of a controller provided in an embodiment of the present application.
  • the controller includes a decoder, an address register, a data register, a Mode identification module, and a decoder, wherein the decoder is used for Parse the MIPI instruction to obtain the MIPI address and control instruction in the MIPI instruction; the address register is used to save the address of the memory unit accessed by the current CPU, and in one embodiment of the application, the address register is used to save the currently received MIPI instruction The MIPI address; the data register is used to temporarily store the data to be transmitted between the microprocessor and the memory or the input/output interface circuit, and in one embodiment of the application, the data register is used to temporarily store the control instruction in the MIPI instruction;
  • the Mode identification module is used to identify the current state of the Mode pin; the decoder is used to convert the control command in the MIPI command into the device state for display.
  • S702 Preliminarily analyze the MIPI instruction.
  • the MIPI switch initially parses the MIPI command to obtain the MIPI address and the X-bit control command.
  • the MIPI address is used to indicate the address of the MIPI switch controlled by the MIPI instruction
  • the control instruction is used to control opening and closing of each sub-switch in the MIPI switch.
  • the controller in the MIPI switch preliminarily parses the MIPI command, specifically, the decoder in the controller preliminarily parses the MIPI command to obtain a 4-bit MIPI address and an 8-bit control command.
  • S703 Determine whether the MIPI address in the MIPI instruction is consistent with the MIPI address of the MIPI switch.
  • the MIPI switch judges whether the MIPI address in the MIPI instruction (that is, the MIPI address obtained by preliminary analysis) is consistent with the MIPI address of the MIPI switch itself, and if not, the MIPI instruction cannot control the MIPI switch, that is, the MIPI switch does not Response; if consistent, the MIPI switch writes the control command to the data register.
  • the data register includes 8 data bits D0-D7, which are used to store the 8-bit control instruction (Bit0-Bit7) written by the MIPI switch.
  • S704 Determine that the MIPI command responds to the Y bit command in the control command.
  • the MIPI switch determines that the MIPI address in the received MIPI command is consistent with its own MIPI address, it is also necessary to determine which part of the MIPI switch responds to the control command, that is, to determine which bit or bits of the control command are controlled by the MIPI switch.
  • the MIPI switch determines which part of the MIPI switch responds to the control command, that is, to determine which bit or bits of the control command are controlled by the MIPI switch.
  • the Mode identification module can be used to identify the state of the Mode pin, so as to determine which bit or bits of the control instruction bit control the MIPI switch. That is to say, when it is determined that the MIPI instruction is used to control the MIPI switch (the address in the MIPI instruction is consistent with the address of the MIPI switch), the MIPI switch can determine the Y bit instruction in the control instruction according to the state of the Mode pin.
  • the Y-bit command is the command for switching the MIPI switch.
  • the Mode identification module has two inputs: 1. The control command input by the data register; 2. The state of the Mode pin.
  • FIG. 9 is a schematic diagram of the principle of a Mode identification module provided by the embodiment of the present application, and the data register writes the control instruction (Bit0-Bit7) after the decoder performs preliminary analysis into its data bit ( D0-D7) are transmitted to the Mode identification module, and the Mode pin transmits its state to the Mode identification module, and the Mode identification module judges which bits of the control instruction bits control the MIPI switch according to the state of the Mode pin, and then determines which Part of the control command controls the MIPI switch, that is, there is a mapping relationship between different states of the Mode pin and different parts of the control command bit.
  • the 8-bit control instruction bits are divided, and M combinations can be obtained for each division.
  • the Mode pin can have N states, and the N states can be one or more of the states of connecting high level, connecting high level with load, connecting low level, connecting low level with load, and open circuit.
  • Each state of the Mode pin corresponds to a combination obtained by dividing the control command bits. It can be understood that not necessarily every combination obtained after dividing the control instruction bits corresponds to a certain state of the Mode pin, and the types of states that can be realized by the Mode pin do not exceed the number of combinations obtained after dividing the control instruction bits, that is, The relationship between M and N is M ⁇ N.
  • the Mode pin has two states: 1.
  • the Mode pin is connected to a high level; 2.
  • the control command bits can be divided into at least two combinations. As shown in Figure 10, the control command bits can be divided into two combinations—combination 1 and combination 2.
  • the MIPI switch Response to the control command bits contained in combination 1; when the Mode pin of the MIPI switch is connected to low level, the MIPI switch responds to the control command bits contained in combination 2.
  • A includes 4 bits (Bit4-Bit7), B includes 4 bits (Bit0-Bit3); A includes 2 bits (Bit6-Bit7), B includes 6 bits (Bit0-Bit5); A includes 3 bits (Bit5-Bit7 ), B includes 3 bits (Bit0-Bit2).
  • one MIPI instruction can control two MIPI switches, as shown in Figure 11, the Mode pin of switch A is connected to high level, and the Mode pin of switch B is connected to low level Level, if the MIPI address of switch A and switch B is the same as the address of the MIPI command shown in the figure, the MIPI command can control switch A and switch B at the same time, specifically, switch A responds to the combination 1 in the MIPI command , switch B responds to combination 2 in this MIPI command.
  • the mode of connecting the Mode pin to a high level includes connecting the Mode pin to the power supply, and the mode of connecting the Mode pin to a low level includes grounding the Mode pin.
  • High/low level which is not limited in this application.
  • FIG. 12 is a schematic diagram of the principle of another MIPI command control switch provided by the embodiment of the present application.
  • the MIPI bus broadcasts the MIPI command.
  • the MIPI address included in the MIPI command is 0101, switch A, switch B and switch C
  • the MIPI address of switch A is 0101
  • the MIPI address of switch B is 0101
  • the MIPI address of switch C is 0001
  • the MIPI addresses of switch A and switch B The address of the MIPI instruction is the same, the switch A and the switch B respond to the MIPI instruction, but the MIPI address of the switch C is different from the address of the MIPI instruction, and the switch C does not respond to the MIPI instruction.
  • the internal Mode identification module identifies the state of the Mode pin.
  • the Mode pin of switch A is connected to the power supply, so the Mode pin of switch A is connected to high level, and the mode pin of switch A is connected to high level.
  • Respond to the combination 1 in the control command bit that is, respond to the control command of the upper four bits (Bit4-Bit7) in the control command bit, and the Mode pin of switch B is grounded, so the Mode pin of switch B is connected to low level, and the switch B Respond to the combination 2 in the control command bits, that is, respond to the control command of the lower four bits (Bit0-Bit3) in the control command bits.
  • one MIPI instruction can control up to four MIPI switches, as shown in Figure 14, the Mode pin of switch A is connected to high level, and the Mode pin of switch B is connected to The load is connected to a high level, the Mode pin of switch C is connected to a low level, and the Mode pin of switch D is connected to a low level with a load.
  • the MIPI instruction can control switch A, switch B, switch C and switch D at the same time.
  • the mode of connecting the Mode pin to a high level includes connecting the Mode pin to the power supply
  • the mode of connecting the Mode pin to a high level with a load includes connecting the Mode pin to a resistor and other devices and then connecting the power supply
  • connecting the Mode pin to a low level The implementation of the level includes the mode pin being grounded, the mode of connecting the mode pin to a low level with a load, including connecting the mode pin to a resistor and other devices and then grounding, of course, there are many other ways to make the mode pin connected to high/low level Low level, which is not limited in this application.
  • mapping relationship between the different states of the Mode pins and the combinations of control instruction bits described above refers to the logic of the Mode identification module, that is, the first control logic. It can also be understood that the logic (first control logic) of the Mode identification module includes the corresponding relationship between N states of Mode pins and Y-bit instructions.
  • Mode identification module can be defined by a truth table. According to the above example and combined with Table 1, the logic of the Mode identification module is explained:
  • the output signal refers to the data bits output by the Mode identification module to the decoder.
  • the Mode identification module when the Mode pin is connected to a high level, the Mode identification module outputs the upper 4 bits (D4-D7) of the data bits (D0-D7) in the data register to the decoder; when the Mode pin is connected to a low level Normally, the Mode identification module outputs the lower 4 bits (D0-D3) of the data bits (D0-D7) in the data register to the decoder.
  • the Z-bit instruction among the X-bit control instructions can be used to control other switches (for example, GPIO switches).
  • switches for example, GPIO switches.
  • the Z-bit instruction in the 8-bit control instruction can be used to control GPIO switch. Understandably, Z ⁇ 8.
  • FIG 15 is a schematic diagram of a MIPI switch provided by the embodiment of the present application.
  • the MIPI switch receives the MIPI command broadcast by the MIPI bus, the MIPI command is initially analyzed by the decoder to obtain the 4-bit MIPI address and 8-bit control instructions.
  • the MIPI switch compares whether the MIPI address in the address register is consistent with the MIPI address parsed by the decoder, and if they are consistent, the 8-bit control command is written into the data register.
  • the data register then transmits the control instruction to the Mode identification module and the decoder respectively.
  • the Mode identification module judges which bits of the control command control the MIPI switch according to the state of the Mode pin, and transmits these control commands to the decoder, and then the decoder specifically controls the MIPI switch according to the second control logic The opening and closing of the sub-switch.
  • the decoder specifically controls the opening and closing of the GPIO switch according to the second control logic. Specifically, the decoder determines which bits of the control instruction control the GPIO switch, and transmits different levels to corresponding GPIO pins according to the second control logic.
  • the upper 3 bits (Bit5-Bit7) of the control instruction bit are set to control the MIPI switch of the same MIPI address
  • the other bits (Bit0-Bit4) are GPIO control bits, specifically Output of the GPIO pins (GPIO1-GPIO5) that control the MIPI switch of the same MIPI address.
  • the GPIO pin of the MIPI switch can be connected to the GPIO switch.
  • the output signal of the GPIO of the MIPI switch is the input signal of the GPIO switch connected to the MIPI switch.
  • the MIPI command Not only the MIPI switch with the same address can be controlled, but also the GPIO switch connected to the MIPI switch can be controlled.
  • Figure 17 is a schematic diagram of connection of another MIPI switch provided by the embodiment of the present application
  • switch A is a MIPI switch
  • switch B and switch C are GPIO switches
  • switch A includes two GPIO transistors Pins - GPIO_1 and GPIO_2, where switch A is connected to switch B through GPIO_1 and connected to switch C through GPIO_2.
  • switch A After switch A receives the MIPI instruction and judges that the MIPI address in the MIPI instruction is the same as its own MIPI address, it writes the control instruction (Bit0-Bit7) in the MIPI instruction into the data register, and the data register then writes the written control instruction ( D0-D7) are respectively transmitted to the Mode identification module and the decoder, and the Mode identification module is used to determine which bits of the control command control the switch A, and the decoder will correspond to the GPIO control bits in the MIPI command according to the control logic The command is converted into an external output level, which is used to control the connected GPIO switch.
  • the decoder controls the sub-switch of switch A according to the upper 3 bits of the control instruction bit (Bit5-Bit7, that is, the upper 3 data bits of the data register: D5-D7) , and transmit the fifth bit (Bit4) of the control command bit to switch B through GPIO_1, and transmit the fourth bit (Bit3) of the control command bit to switch C through GPIO_2.
  • the logic for controlling the GPIO switch by the control instruction may be defined by a truth table.
  • the second control logic is described by taking Bit0-Bit4 as GPIO control bits as an example. As shown in Table 2 below:
  • Bit0-Bit4 are GPIO control bits, which respectively control the GPIO switches connected through pins GPIO1-5.
  • the logic that is, the second control logic
  • the logic for controlling the GPIO switch through the control command can be realized by a decoder (as shown in FIG. 17 ), and can also be realized by a data register. If the logic of controlling the GPIO switch by the control command is implemented by the data register, the data register does not need to transmit the control command to the decoder, but directly transmits the control command for controlling the GPIO switch to the GPIO pin.
  • the GPIO switch is switched by the level transmitted by the GPIO pin. For example, when the GPIO pin input of the GPIO switch is a high level, the GPIO switch is closed; when the GPIO pin input of the GPIO switch is Low level, the GPIO switch is closed.
  • multiple MIPI switches can be mounted on the MIPI bus, and these MIPI switches can be connected to multiple GPIO switches.
  • switch A and switch B mounted on the MIPI bus.
  • the pin is connected to the switch C, and is connected to the switch D through the GPIO_2 pin, and the switch B is connected to the switch E through the GPIO_1 pin, and is connected to the switch F through the GPIO_2 pin. If the MIPI addresses of switch A and switch B are the same, the MIPI commands with the same address can control switch A, switch B, switch C, switch D, switch E and switch F at the same time.
  • the decoder in the MIPI switch controls the opening and closing of the sub-switch according to the output signal of the Mode identification module (that is, the Y bit instruction), that is, the input signal of the decoder is the output signal of the Mode identification module, or, the MIPI
  • the decoder in the switch controls the opening and closing of the sub-switch according to the output signal of the data register, that is, the input signal of the decoder is the output signal of the data register.
  • the logic of the decoder controlling the sub-switches according to the input signal can also be defined by a truth table.
  • the input signal of the decoder has 4 bits, and the decoder controls 4 sub-switches—sub-switch 1, sub-switch 2, sub-switch C, and sub-switch D according to the 4-bit input signal.
  • the decoder keeps the sub-switch in the original state and does not switch its state; when the input signal of the decoder is 1000 (sorted from high to low ), the output signal is 0000, and the decoder controls all sub-switches to be disconnected; when the input signal of the decoder is 1001 (sorted from high to low), the output signal is 0001, and the decoder controls sub-switch 1 to close; When the input signal of the decoder is 1010 (sorted from high to low), the output signal is 0010, and the decoder controls the sub-switch 2 to close; when the input signal of the decoder is 1011 (sorted from high to low), When the output signal is 0100, the decoder controls sub-switch C to close; when the input signal of the decoder is 1100 (sorted from high to low), the output signal is 1000, and the decoder controls sub-switch D to close.
  • the flag bit can be set in the input signal of the decoder (in the combination of the control instruction bits corresponding to the different states of the Mode pin).
  • the flag bit includes a K-bit flag bit instruction. It can be understood that K is a positive integer not less than 1 and not greater than X.
  • the decoder can judge according to the flag bit instruction whether to switch the state of the sub-switch according to the input signal.
  • the highest bit in the input signal is set as a flag bit.
  • the input signal of the decoder is the upper 4 bits (D4-D7) of the data bits (D0-D7) in the data register.
  • D7 is the flag bit, when the bit instruction (flag bit instruction) of D7 is 0, the decoder does not switch the state of the sub-switch after receiving the input signal, when the bit instruction of D7 (flag bit instruction) instruction) is 1, the decoder switches the state of the sub-switch according to the input signal after receiving the input signal;
  • the Mode pin is connected to low level, the input signal of the decoder is the data bit in the data register (D0-D7)
  • the lower 4 bits (D0-D3) at this time, D3 is the flag bit, when the D3 bit instruction (flag bit instruction) is 0, the decoder does not switch the state of the sub-switch after receiving the input signal, when D3 When this bit instruction (flag bit
  • the MIPI command cannot control the MIPI switch, that is, the MIPI switch does not respond to the control command in the MIPI command.
  • the present application provides a MIPI switch, as shown in FIG. 20 , the MIPI switch can be used in the switching system shown in FIG. 6 , and can also be used to implement the switching method shown in FIG. 7 .
  • the MIPI switch 2000 may include a pin module 2010 , a sub-switch module 2020 and a controller 2030 .
  • the pin module 2010 includes pins (pins) required for connecting the MIPI switch 2000 with peripheral circuits, and these pins are closely related to the internal structure of the MIPI switch 2000 .
  • the pin module 2010 includes a Mode pin.
  • the pin module 2010 includes a Mode pin and at least one GPIO pin.
  • the sub-switch module 2020 includes at least one sub-switch, and the sub-switch may be connected to the antenna through a matching element. When the sub-switch module 2020 includes multiple sub-switches, these sub-switches may be connected to the antenna through different matching elements.
  • the controller 2030 specifically implements related processing for MIPI instructions. As shown in FIG. 20 , the controller 2030 may include a decoder 2031 , a data register 2032 , an address register 2033 , a decoder 2034 and a Mode identification module 2035 .
  • the decoder 2031 is used for preliminary parsing of the received MIPI instruction, thereby obtaining the address and control instruction in the MIPI instruction;
  • the data register 2032 is used for storing the control instruction, and the data register 2032 can transmit the written control instruction to Mode identification Module 2035 and decoder;
  • the address register 2033 is used to store the address of the MIPI switch 2000 itself;
  • the decoder 2034 is used to convert the control instruction into a device state;
  • the Mode identification module 2035 is used to determine which bits of the control instruction are specifically controlled In the MIPI switch 2000, specifically, the Mode identification module 2035 identifies the state of the Mode pin, and according to the state of the Mode pin and the logic of the Mode identification module 2035, it is judged which bits of the control command control the MIPI switch 2000, and these bits The bit control instructions are transmitted to the decoder 2034 .
  • the MIPI switch 2000 may also include more or fewer modules, and the above content is only an implementation manner of the present application, and is not regarded as a limitation of the present application.
  • the present application also provides an electronic device, which includes the MIPI switch 2000 .
  • the electronic device may be a mobile phone, a PC, a tablet computer, a smart watch, a smart speaker, and the like including the MIPI switch 2000 .
  • FIG. 21 is a schematic structural diagram of an electronic device provided in the present application, and the electronic device includes a MIPI switch 2000 .
  • the electronic device 2100 shown in FIG. 21 is specifically described below:
  • the electronic device 2100 may include a processor 2110, an external memory interface 2120, an internal memory 2121, a universal serial bus (Universal Serial Bus, USB) interface 2130, a charging management module 2140, a power management module 2141, a battery 2142, an antenna 1, and an antenna 2 , mobile communication module 2150, wireless communication module 2160, audio module 2170, speaker 2170A, receiver 2170B, microphone 2170C, earphone jack 2170D, sensor module 2180, button 2190, motor 2191, indicator 2192, camera 2193, display screen 2194, and Subscriber Identification Module (Subscriber Identification Module, SIM) card interface 2195, etc.
  • a processor 2110 an external memory interface 2120, an internal memory 2121, a universal serial bus (Universal Serial Bus, USB) interface 2130, a charging management module 2140, a power management module 2141, a battery 2142, an antenna 1, and an antenna 2 , mobile communication module 2150, wireless communication module 2160, audio module 2170, speaker 2170A, receiver 21
  • the sensor module 2180 can include pressure sensor 2180A, gyroscope sensor 2180B, air pressure sensor 2180C, magnetic sensor 2180D, acceleration sensor 2180E, distance sensor 2180F, proximity light sensor 2180G, fingerprint sensor 2180H, temperature sensor 2180J, touch sensor 2180K, ambient light Sensor 2180L, bone conduction sensor 2180M, etc.
  • the structure shown in the embodiment of the present invention does not constitute a specific limitation on the electronic device 2100 .
  • the electronic device 2100 may include more or fewer components than shown in the illustration, or combine some components, or separate some components, or arrange different components.
  • the illustrated components can be realized in hardware, software or a combination of software and hardware.
  • the processor 2110 may include one or more processing units, for example: the processor 2110 may include an application processor (Application Processor, AP), a modem processor, a graphics processor (Graphics Processing unit, GPU), an image signal processor (Image Signal Processor, ISP), controller, memory, video codec, digital signal processor (Digital Signal Processor, DSP), baseband processor, and/or neural network processor (Neural-network Processing Unit, NPU) Wait. Wherein, different processing units may be independent devices, or may be integrated in one or more processors.
  • Application Processor Application Processor, AP
  • modem processor a graphics processor
  • ISP image signal processor
  • controller memory
  • video codec digital signal processor
  • DSP Digital Signal Processor
  • baseband processor baseband processor
  • neural network processor Neural-network Processing Unit, NPU
  • the controller may be the nerve center and command center of the electronic device 2100 .
  • the controller can generate an operation control signal according to the instruction opcode and timing signal, and complete the control of fetching and executing the instruction.
  • the processor 2110 may also include an AE system.
  • the AE system can be specifically set in the ISP.
  • the AE system can be used to realize automatic adjustment of exposure parameters.
  • the AE system may also be integrated in other processor chips. This embodiment of the present application does not limit it.
  • the electronic device 2100 may execute the method for adjusting the exposure intensity through the processor 2110 .
  • a memory may also be provided in the processor 2110 for storing instructions and data.
  • the memory in processor 2110 is a cache memory.
  • the memory may hold instructions or data that the processor 2110 has just used or recycled. If the processor 2110 needs to use the instruction or data again, it can be called directly from the memory. Repeated access is avoided, and the waiting time of the processor 2110 is reduced, thereby improving the efficiency of the system.
  • processor 2110 may include one or more interfaces.
  • the interface can include an integrated circuit (Inter-Integrated Circuit, I2C) interface, an integrated circuit built-in audio (Inter-Integrated Circuit Sound, I2S) interface, a pulse code modulation (Pulse Code Modulation, PCM) interface, a universal asynchronous transmitter (Universal Asynchronous Receiver/Transmitter, UART) interface, mobile industry processor interface (Mobile Industry Processor Interface, MIPI), general-purpose input and output (General-Purpose Input/Output, GPIO) interface, subscriber identity module (Subscriber Identity Module, SIM) interface, and /or Universal Serial Bus (Universal Serial Bus, USB) interface, etc.
  • I2C Inter-Integrated Circuit
  • I2S integrated circuit built-in audio
  • PCM pulse code modulation
  • PCM pulse code modulation
  • UART Universal Asynchronous Receiver/Transmitter
  • MIPI Mobile Industry Processor Interface
  • GPIO General-purpose input and output
  • SIM Subscriber Identity Module
  • USB Universal Serial Bus
  • the I2C interface is a bidirectional synchronous serial bus, including a serial data line (Serial Data Line, SDA) and a serial clock line (Serial Clock Line, SCL).
  • processor 2110 may include multiple sets of I2C buses.
  • the processor 2110 can be respectively coupled to the touch sensor 2180K, the charger, the flashlight, the camera 2193 and the like through different I2C bus interfaces.
  • the processor 2110 may be coupled to the touch sensor 2180K through the I2C interface, so that the processor 2110 and the touch sensor 2180K communicate through the I2C bus interface to realize the touch function of the electronic device 2100 .
  • the I2S interface can be used for audio communication.
  • processor 2110 may include multiple sets of I2S buses.
  • the processor 2110 may be coupled to the audio module 2170 through an I2S bus to implement communication between the processor 2110 and the audio module 2170 .
  • the audio module 2170 can transmit audio signals to the wireless communication module 2160 through the I2S interface, so as to realize the function of answering calls through the Bluetooth headset.
  • the PCM interface can also be used for audio communication, sampling, quantizing and encoding the analog signal.
  • the audio module 2170 and the wireless communication module 2160 can be coupled through a PCM bus interface.
  • the audio module 2170 can also transmit audio signals to the wireless communication module 2160 through the PCM interface, so as to realize the function of answering calls through the Bluetooth headset. Both the I2S interface and the PCM interface can be used for audio communication.
  • the UART interface is a universal serial data bus used for asynchronous communication.
  • the bus can be a bidirectional communication bus. It converts the data to be transmitted between serial communication and parallel communication.
  • a UART interface is generally used to connect the processor 2110 and the wireless communication module 2160 .
  • the processor 2110 communicates with the Bluetooth module in the wireless communication module 2160 through the UART interface to realize the Bluetooth function.
  • the audio module 2170 can transmit audio signals to the wireless communication module 2160 through the UART interface, so as to realize the function of playing music through the Bluetooth headset.
  • the MIPI interface can be used to connect the processor 2110 with the display screen 2194, the camera 2193 and other peripheral devices.
  • MIPI interface includes camera serial interface (Camera Serial Interface, CSI), display serial interface (Display Serial Interface, DSI), etc.
  • the processor 2110 communicates with the camera 2193 through the CSI interface to realize the shooting function of the electronic device 2100 .
  • the processor 2110 communicates with the display screen 2194 through the DSI interface to realize the display function of the electronic device 2100 .
  • the GPIO interface can be configured by software.
  • the GPIO interface can be configured as a control signal or as a data signal.
  • the GPIO interface can be used to connect the processor 2110 with the camera 2193 , the display screen 2194 , the wireless communication module 2160 , the audio module 2170 , the sensor module 2180 and so on.
  • the GPIO interface can also be configured as an I2C interface, I2S interface, UART interface, MIPI interface, etc.
  • the USB interface 2130 is an interface conforming to the USB standard specification, specifically, it may be a Mini USB interface, a Micro USB interface, a USB Type C interface, and the like.
  • the USB interface 2130 can be used to connect a charger to charge the electronic device 2100, and can also be used to transmit data between the electronic device 2100 and peripheral devices. It can also be used to connect headphones and play audio through them.
  • the interface can also be used to connect other electronic devices 2100, such as AR devices.
  • the interface connection relationship between the modules shown in the embodiment of the present invention is only a schematic illustration, and does not constitute a structural limitation of the electronic device 2100 .
  • the electronic device 2100 may also adopt different interface connection methods in the above embodiments, or a combination of multiple interface connection methods.
  • the charging management module 2140 is used for receiving charging input from the charger.
  • the charger may be a wireless charger or a wired charger.
  • the charging management module 2140 can receive the charging input of the wired charger through the USB interface 2130 .
  • the charging management module 2140 can receive wireless charging input through the wireless charging coil of the electronic device 2100 . While the charging management module 2140 is charging the battery 2142 , it can also supply power to the electronic device 2100 through the power management module 2141 .
  • the power management module 2141 is used for connecting the battery 2142 , the charging management module 2140 and the processor 2110 .
  • the power management module 2141 receives the input of the battery 2142 and/or the charging management module 2140, and supplies power for the processor 2110, the internal memory 2121, the external memory, the display screen 2194, the camera 2193, and the wireless communication module 2160, etc.
  • the power management module 2141 can also be used to monitor parameters such as battery capacity, battery cycle times, and battery health status (leakage, impedance).
  • the power management module 2141 can also be set in the processor 2110 .
  • the power management module 2141 and the charging management module 2140 can also be set in the same device.
  • the wireless communication function of the electronic device 2100 can be realized by the antenna 1, the antenna 2, the mobile communication module 2150, the wireless communication module 2160, the modem processor and the baseband processor.
  • Antenna 1 and Antenna 2 are used to transmit and receive electromagnetic wave signals.
  • Each antenna in electronic device 2100 may be used to cover single or multiple communication frequency bands. Different antennas can also be multiplexed to improve the utilization of the antennas.
  • Antenna 1 can be multiplexed as a diversity antenna of a wireless local area network.
  • the antenna may be used in conjunction with a tuning switch.
  • the mobile communication module 2150 can provide wireless communication solutions including 2G/3G/4G/5G applied on the electronic device 2100 .
  • the mobile communication module 2150 may include at least one filter, switch, power amplifier, low noise amplifier (Low Noise Amplifier, LNA) and the like.
  • the mobile communication module 2150 can receive electromagnetic waves through the antenna 1, filter and amplify the received electromagnetic waves, and send them to the modem processor for demodulation.
  • the mobile communication module 2150 can also amplify the signal modulated by the modem processor, convert it into electromagnetic wave and radiate it through the antenna 1 .
  • at least part of the functional modules of the mobile communication module 2150 may be set in the processor 2110 .
  • at least part of the functional modules of the mobile communication module 2150 and at least part of the modules of the processor 2110 may be set in the same device.
  • a modem processor may include a modulator and a demodulator.
  • the modulator is used for modulating the low-frequency baseband signal to be transmitted into a medium-high frequency signal.
  • the demodulator is used to demodulate the received electromagnetic wave signal into a low frequency baseband signal. Then the demodulator sends the demodulated low-frequency baseband signal to the baseband processor for processing.
  • the low-frequency baseband signal is passed to the application processor after being processed by the baseband processor.
  • the application processor outputs sound signals through audio equipment (not limited to speaker 2170A, receiver 2170B, etc.), or displays images or videos through display screen 2194 .
  • the modem processor may be a stand-alone device.
  • the modem processor may be independent of the processor 2110, and be set in the same device as the mobile communication module 2150 or other functional modules.
  • the wireless communication module 2160 can provide wireless local area network (Wireless Local Area Networks, WLAN) (such as wireless fidelity (Wireless Fidelity, Wi-Fi) network), bluetooth (Bluetooth, BT), global navigation satellite System (Global Navigation Satellite System, GNSS), frequency modulation (Frequency Modulation, FM), near field communication technology (Near Field Communication, NFC), infrared technology (Infrared, IR) and other wireless communication solutions.
  • the wireless communication module 2160 may be one or more devices integrating at least one communication processing module.
  • the wireless communication module 2160 receives electromagnetic waves via the antenna 2 , frequency-modulates and filters the electromagnetic wave signals, and sends the processed signals to the processor 2110 .
  • the wireless communication module 2160 can also receive the signal to be sent from the processor 2110 , frequency-modulate it, amplify it, and convert it into electromagnetic waves through the antenna 2 to radiate out.
  • the wireless communication module 2160 is used to realize the interaction between the first device and the second device.
  • the first device has a wireless communication module, and the first device sends a verification request to the second device through this module, and receives Authentication data sent by the device.
  • the antenna 1 of the electronic device 2100 is coupled to the mobile communication module 2150, and the antenna 2 is coupled to the wireless communication module 2160, so that the electronic device 2100 can communicate with the network and other devices through wireless communication technology.
  • the wireless communication technology may include Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), broadband Code Division Multiple Access (WCDMA), Time-Division Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), BT, GNSS, WLAN, NFC , FM, and/or IR techniques, etc.
  • the GNSS may include Global Positioning System (Global Positioning System, GPS), Global Navigation Satellite System (Global Navigation Satellite System, GLONASS), Beidou Navigation Satellite System (Beidou Navigation Satellite System, BDS), Quasi Zenith Satellite System (Quasi - Zenith Satellite System (QZSS) and/or Satellite Based Augmentation Systems (SBAS).
  • Global Positioning System Global Positioning System, GPS
  • Global Navigation Satellite System Global Navigation Satellite System
  • GLONASS Global Navigation Satellite System
  • Beidou Navigation Satellite System Beidou Navigation Satellite System
  • BDS Beidou Navigation Satellite System
  • QZSS Quasi Zenith Satellite System
  • SBAS Satellite Based Augmentation Systems
  • the electronic device 2100 realizes the display function through the GPU, the display screen 2194, and the application processor.
  • the GPU is a microprocessor for image processing, connected to the display screen 2194 and the application processor. GPUs are used to perform mathematical and geometric calculations for graphics rendering.
  • Processor 2110 may include one or more GPUs that execute program instructions to generate or change display information.
  • the display screen 2194 is used to display images, videos and the like.
  • Display 2194 includes a display panel.
  • the display panel can adopt liquid crystal display (Liquid Crystal Display, LCD), organic light-emitting diode (Organic Light-Emitting Diode, OLED), active matrix organic light-emitting diode or active-matrix organic light-emitting diode (Active-Matrix Organic Light Emitting Diode, AMOLED), flexible light-emitting diode (Flex Light-Emitting Diode, FLED), Mini LED, Micro LED, Micro-OLED, quantum dot light-emitting diode (Quantum Dot Light Emitting Diodes, QLED), etc.
  • the electronic device 2100 may include 1 or N display screens 2194, where N is a positive integer greater than 1.
  • the electronic device 2100 may realize the acquisition function through an ISP, a camera 2193, a video codec, a GPU, a display screen 2194, an application processor, and the like.
  • the ISP is used to process data fed back by the camera 2193 .
  • the light is transmitted to the photosensitive element of the camera through the lens, the light signal is converted into an electrical signal, and the photosensitive element of the camera transmits the electrical signal to the ISP for processing, and converts it into an image or video visible to the naked eye.
  • ISP can also perform algorithm optimization on image noise, brightness, and skin color. ISP can also optimize the exposure, color temperature and other parameters of the shooting scene.
  • the ISP may be located in the camera 2193.
  • Camera 2193 is used to capture still images or video.
  • the object generates an optical image through the lens and projects it to the photosensitive element.
  • the photosensitive element can be a charge coupled device (Charge Coupled Device, CCD) or a complementary metal oxide semiconductor (Complementary Metal-Oxide-Semiconductor, CMOS) phototransistor.
  • CCD Charge Coupled Device
  • CMOS complementary metal oxide semiconductor
  • the photosensitive element converts the light signal into an electrical signal, and then transmits the electrical signal to the ISP for conversion into a digital image or video signal.
  • ISP outputs digital image or video signal to DSP for processing.
  • DSP converts digital images or video signals into standard RGB, YUV and other formats of images or video signals.
  • the electronic device 2100 may include 1 or N cameras 2193, where N is a positive integer greater than 1.
  • the electronic device 2100 can use N cameras 2193 to acquire images with multiple exposure coefficients, and then, in video post-processing, the electronic device 2100 can synthesize HDR images using the HDR technology based on the images with multiple exposure coefficients. image.
  • Digital signal processors are used to process digital signals. In addition to digital image or video signals, they can also process other digital signals. For example, when the electronic device 2100 selects a frequency point, the digital signal processor is used to perform Fourier transform on the energy of the frequency point.
  • Video codecs are used to compress or decompress digital video.
  • the electronic device 2100 may support one or more video codecs. In this way, the electronic device 2100 can play or record videos in various encoding formats, such as: Moving Picture Experts Group (Moving Picture Experts Group, MPEG) 1, MPEG2, MPEG3, MPEG4, etc.
  • MPEG Moving Picture Experts Group
  • MPEG2 Moving Picture Experts Group
  • MPEG3 Moving Picture Experts Group
  • NPU is a neural network (Neural-Network, NN) computing processor.
  • NN neural network
  • Applications such as intelligent cognition of the electronic device 2100 can be implemented through the NPU, such as image recognition, face recognition, speech recognition, text understanding, and the like.
  • the external memory interface 2120 can be used to connect an external memory card, such as a Micro SD card, to expand the storage capacity of the electronic device 2100.
  • the external memory card communicates with the processor 2110 through the external memory interface 2120 to realize data storage function. Such as saving music, video and other files in the external memory card.
  • the internal memory 2121 may be used to store computer-executable program codes including instructions.
  • the processor 2110 executes various functional applications and data processing of the electronic device 2100 by executing instructions stored in the internal memory 2121 .
  • the internal memory 2121 may include an area for storing programs and an area for storing data.
  • the stored program area can store an operating system, at least one application program required by a function (such as a sound playing function, an image and video playing function, etc.) and the like.
  • the storage data area can store data created during the use of the electronic device 2100 (such as audio data, phonebook, etc.) and the like.
  • the internal memory 2121 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (Universal Flash Storage, UFS), and the like.
  • a non-volatile memory such as at least one magnetic disk storage device, a flash memory device, a universal flash memory (Universal Flash Storage, UFS), and the like.
  • the electronic device 2100 can implement audio functions through an audio module 2170, a speaker 2170A, a receiver 2170B, a microphone 2170C, an earphone interface 2170D, and an application processor. Such as music playback, recording, etc.
  • the audio module 2170 is used for converting digital audio information into analog audio signal output, and also used for converting analog audio input into digital audio signal.
  • the audio module 2170 may also be used to encode and decode audio signals.
  • the audio module 2170 may be set in the processor 2110 , or some functional modules of the audio module 2170 may be set in the processor 2110 .
  • Loudspeaker 2170A also called “horn" is used to convert audio electrical signals into sound signals.
  • Electronic device 2100 can listen to music through speaker 2170A, or listen to hands-free calls.
  • Receiver 2170B also called “earpiece” is used to convert audio electrical signals into audio signals.
  • the receiver 2170B can be placed close to the human ear to receive the voice.
  • the microphone 2170C also called “microphone” or “microphone” is used to convert sound signals into electrical signals.
  • the user can put his mouth close to the microphone 2170C to make a sound, and input the sound signal to the microphone 2170C.
  • the electronic device 2100 may be provided with at least one microphone 2170C.
  • the electronic device 2100 may be provided with two microphones 2170C, which may also implement a noise reduction function in addition to acquiring sound signals.
  • the electronic device 2100 can also be provided with three, four or more microphones 2170C, so as to obtain sound signals, reduce noise, identify sound sources, and realize directional recording functions, etc.
  • the earphone interface 2170D is used to connect wired earphones.
  • the earphone interface 2170D may be a USB interface 2130, or a 3.5mm Open Mobile Terminal Platform (OMTP) standard interface, or a Cellular Telecommunications Industry Association of the USA (CTIA) standard interface .
  • OMTP Open Mobile Terminal Platform
  • CTIA Cellular Telecommunications Industry Association of the USA
  • the sensor module 2180 may include one or more sensors, which may be of the same type or of different types. It can be understood that the sensor module 2180 shown in FIG. 1 is only an exemplary division manner, and there may be other division manners, which are not limited in the present application.
  • the pressure sensor 2180A is used to sense the pressure signal and convert the pressure signal into an electrical signal.
  • pressure sensor 2180A may be located on display screen 2194 .
  • pressure sensors 2180A such as resistive pressure sensors, inductive pressure sensors, and capacitive pressure sensors.
  • a capacitive pressure sensor may be comprised of at least two parallel plates with conductive material.
  • the electronic device 2100 determines the intensity of pressure according to the change in capacitance.
  • the electronic device 2100 detects the intensity of the touch operation according to the pressure sensor 2180A.
  • the electronic device 2100 may also calculate the touched position according to the detection signal of the pressure sensor 2180A.
  • touch operations acting on the same touch position but with different touch operation intensities may correspond to different operation instructions. For example: when a touch operation with a touch operation intensity less than the first pressure threshold is applied to the short message application icon, the instruction of viewing the short message is executed. When a touch operation whose intensity is greater than or equal to the first pressure threshold acts on the icon of the short message application, the instruction of creating a new short message is executed.
  • the gyro sensor 2180B can be used to determine the motion posture of the electronic device 2100 .
  • the angular velocity of the electronic device 2100 about three axes ie, x, y and z axes
  • the gyro sensor 2180B can be used for image stabilization.
  • the gyro sensor 2180B detects the shaking angle of the electronic device 2100, calculates the distance that the lens module needs to compensate according to the angle, and allows the lens to counteract the shaking of the electronic device 2100 through reverse motion to achieve anti-shake.
  • the gyro sensor 2180B can also be used for navigation and somatosensory game scenes.
  • the air pressure sensor 2180C is used to measure air pressure.
  • the electronic device 2100 calculates the altitude based on the air pressure value measured by the air pressure sensor 2180C to assist positioning and navigation.
  • the magnetic sensor 2180D includes a Hall sensor.
  • the electronic device 2100 may detect opening and closing of the flip holster using the magnetic sensor 2180D.
  • the electronic device 2100 can detect the opening and closing of the flip according to the magnetic sensor 2180D.
  • features such as automatic unlocking of the flip cover are set.
  • the acceleration sensor 2180E can detect the acceleration of the electronic device 2100 in various directions (generally three axes). When the electronic device 2100 is stationary, the magnitude and direction of gravity can be detected. It can also be used to identify the posture of the electronic device 2100, and it can be used in applications such as horizontal and vertical screen switching, pedometers, etc.
  • the electronic device 2100 may measure the distance by infrared or laser. In some embodiments, when shooting a scene, the electronic device 2100 can use the distance sensor 2180F for distance measurement to achieve fast focusing.
  • Proximity light sensor 2180G may include, for example, light emitting diodes (LEDs) and light detectors, such as photodiodes.
  • the light emitting diodes may be infrared light emitting diodes.
  • the electronic device 2100 emits infrared light through the light emitting diode.
  • the electronic device 2100 uses photodiodes to detect infrared reflected light from nearby objects. When sufficient reflected light is detected, it may be determined that there is an object near the electronic device 2100 . When insufficient reflected light is detected, the electronic device 2100 may determine that there is no object near the electronic device 2100 .
  • the electronic device 2100 can use the proximity light sensor 2180G to detect that the user holds the electronic device 2100 close to the ear to make a call, so as to automatically turn off the screen to save power.
  • Proximity light sensor 2180G can also be used in leather case mode, automatic unlock and lock screen in pocket mode.
  • the ambient light sensor 2180L is used for sensing ambient light brightness.
  • the electronic device 2100 can adaptively adjust the brightness of the display screen 2194 according to the perceived ambient light brightness.
  • the ambient light sensor 2180L can also be used to automatically adjust the white balance when taking pictures.
  • the ambient light sensor 2180L can also cooperate with the proximity light sensor 2180G to detect whether the electronic device 2100 is in the pocket to prevent accidental touch.
  • the fingerprint sensor 2180H is used to acquire fingerprints.
  • the electronic device 2100 can utilize the acquired fingerprint characteristics to implement fingerprint unlocking, access to application locks, take pictures with fingerprints, answer incoming calls with fingerprints, and the like.
  • the temperature sensor 2180J is used to detect temperature.
  • the electronic device 2100 uses the temperature detected by the temperature sensor 2180J to implement a temperature processing strategy. For example, when the temperature reported by the temperature sensor 2180J exceeds the threshold, the electronic device 2100 may reduce the performance of the processor located near the temperature sensor 2180J, so as to reduce power consumption and implement thermal protection.
  • the electronic device 2100 when the temperature is lower than another threshold, the electronic device 2100 heats the battery 2142 to prevent the electronic device 2100 from being shut down abnormally due to the low temperature.
  • the electronic device 2100 boosts the output voltage of the battery 2142 to avoid abnormal shutdown caused by low temperature.
  • Touch sensor 2180K also known as "touch panel”.
  • the touch sensor 2180K can be arranged on the display screen 2194, and the touch sensor 2180K and the display screen 2194 form a touch screen, also called “touch screen”.
  • the touch sensor 2180K is used to detect a touch operation acting on or near it.
  • the touch sensor can pass the detected touch operation to the application processor to determine the type of touch event.
  • Visual output related to the touch operation can be provided through the display screen 2194 .
  • the touch sensor 2180K may also be disposed on the surface of the electronic device 2100, which is different from the position of the display screen 2194.
  • the user uses the electronic device 2100 to perform time-lapse photography or continuous shooting, and needs to acquire a series of images.
  • the electronic device 2100 can adopt the AE mode. That is, the electronic device 2100 automatically adjusts the AE value.
  • the touchAE mode may be triggered.
  • the electronic device 2100 can adjust the brightness of the corresponding position where the user touches the display screen, and perform light metering with high weight. Therefore, when calculating the average brightness of the screen, the weight of the area touched by the user is obviously higher than that of other areas, and the average brightness of the screen finally calculated is closer to the average brightness of the area touched by the user.
  • the bone conduction sensor 2180M can acquire vibration signals.
  • the bone conduction sensor 2180M can acquire the vibration signal of the vibrating bone mass of the human voice.
  • the bone conduction sensor 2180M can also contact the human pulse and receive the blood pressure beating signal.
  • the bone conduction sensor 2180M can also be set in the earphone, combined into a bone conduction earphone.
  • the audio module 2170 can analyze the voice signal based on the vibration signal of the vibrating bone mass of the vocal part acquired by the bone conduction sensor 2180M, so as to realize the voice function.
  • the application processor can analyze the heart rate information based on the blood pressure beating signal acquired by the bone conduction sensor 2180M, so as to realize the heart rate detection function.
  • the keys 2190 include a power key, a volume key and the like.
  • the key 2190 may be a mechanical key. It can also be a touch button.
  • the electronic device 2100 may receive key input and generate key signal input related to user settings and function control of the electronic device 2100 .
  • the motor 2191 can generate a vibrating prompt.
  • the motor 2191 can be used for incoming call vibration prompts, and can also be used for touch vibration feedback.
  • touch operations applied to different applications may correspond to different vibration feedback effects.
  • the motor 2191 can also correspond to different vibration feedback effects for touch operations on different areas of the display screen 2194 .
  • Different application scenarios for example: time reminder, receiving information, alarm clock, games, etc.
  • the touch vibration feedback effect can also support customization.
  • the indicator 2192 can be an indicator light, which can be used to indicate the charging status, the change of the battery capacity, and can also be used to indicate messages, missed calls, notifications, etc.
  • SIM card interface 2195 is used for connecting SIM card.
  • the SIM card can be connected and separated from the electronic device 2100 by inserting it into the SIM card interface 2195 or pulling it out from the SIM card interface 2195 .
  • the electronic device 2100 may support 1 or N SIM card interfaces, where N is a positive integer greater than 1.
  • SIM card interface 2195 can support Nano SIM card, Micro SIM card, SIM card, etc. Multiple cards can be inserted into the same SIM card interface 2195 at the same time. The types of the multiple cards may be the same or different.
  • the SIM card interface 2195 is also compatible with different types of SIM cards.
  • the SIM card interface 2195 is also compatible with external memory cards.
  • the electronic device 2100 interacts with the network through the SIM card to implement functions such as calling and data communication.
  • the electronic device 2100 adopts an eSIM, that is, an embedded SIM card.
  • the eSIM card can be embedded in the electronic device 2100 and cannot be separated from the electronic device 2100 .

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Abstract

提供了一种开关切换方法及相关装置。开关切换方法包括：MIPI开关接收MIPI指令，对MIPI指令进行初步解析，得到MIPI指令中的地址和控制指令；MIPI开关判断MIPI指令中的地址与MIPI开关自身的地址是否一致，若一致，将控制指令写入MIPI开关的数据寄存器中；MIPI开关将其数据寄存器中的控制指令传输给Mode识别模块，由Mode识别模块判断由控制指令的哪几位控制该MIPI开关，并将这几位控制指令发送给MIPI开关中的译码器；MIPI开关中的译码器将控制指令转换为器件状态。开关切换方法可以利用一条MIPI指令控制多个MIPI开关，既克服了平台对开关数量的限制，又减少了开关的响应时间。

Description

一种开关切换方法及相关装置
本申请要求于2021年06月11日提交中国专利局、申请号为202110654892.7、申请名称为“一种开关切换方法及相关装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本方案涉及射频技术领域，尤其涉及一种开关切换方法及相关装置。
背景技术
随着技术不断发展，天线数量日趋增多，也需要越来越多的切换状态，因此天线开关数量也越来越多。现有技术中，给每个开关分配一个MIPI地址，每个开关串行接收MIPI指令，这会导致开关响应时间长，另外，由于平台会限制MIPI指令数量，而一条MIPI指令作用于一个开关，从而使得开关的数量也会受到限制，严重制约了天线设计。
因此，如何减少开关的响应时间并克服平台对开关数量的限制是目前亟待解决的问题。
发明内容
本申请提供了一种开关切换方法及相关装置，可以实现多个MIPI开关共享一个MIPI地址，从而实现一条MIPI指令控制多个MIPI开关，不但克服了平台对MIPI开关数量的限制，还减少了MIPI开关的响应时间，降低了切换MIPI开关的时延。
第一方面，本申请提供一种开关切换方法，该方法可应用于移动产业处理器接口MIPI开关。在该方法中，MIPI开关可以接收MIPI指令。MIPI开关可以包括第一管脚。MIPI指令可以包括控制指令。在确定MIPI指令用于控制所述MIPI开关的情况下，MIPI开关可以根据第一管脚的状态确定控制指令中的Y位指令。控制指令包括X位指令，Y小于或等于X。MIPI开关根据所述Y位指令进行切换。
在本申请提供的方案中，MIPI开关可以根据其包括的第一管脚的状态来确定响应控制指令的哪一部分，即上述方法中提到的Y位指令。可理解，MIPI开关中的译码器可以将这Y位指令转换为器件状态，即控制MIPI开关中子开关的断开和闭合。需要说明的是，根据上述方法，一条MIPI指令可以包含不同的Y位指令，所以一条MIPI指令可以用于控制多个MIPI开关。该方法可以降低切换MIPI开关的时延，使得MIPI开关及时响应，还可以克服平台对MIPI开关数量的限制。
结合第一方面，在一种可能的实现方式中，MIPI开关对应第一MIPI地址；MIPI指令包括第二MIPI地址；在确定MIPI指令用于控制MIPI开关的情况下，MIPI开关根据第一管脚的状态确定控制指令中的Y位指令之前，开关切换方法还可以包括：MIPI开关解析MIPI指令，得到第二MIPI地址和控制指令；在确定MIPI指令用于控制MIPI开关的情况下，MIPI开关根据第一管脚的状态确定控制指令中的Y位指令，具体可以包括：MIPI开关判断第一MIPI地址和第二MIPI地址是否一致；若第一MIPI地址与第二MIPI地址一致，MIPI开关根据第一管脚的状态确定控制指令中的Y位指令。
在本申请提供的方案中，在确定MIPI开关响应的Y位指令之前，需要判断MIPI开关的地址与MIPI指令中的地址是否一致。若MIPI开关的地址与MIPI指令中的地址一致，则可以根据第一管脚的状态确定MIPI开关响应的Y位指令，使得MIPI开关能顺利响应相应的MIPI指令。
结合第一方面，在一种可能的实现方式中，第一管脚有N种状态；MIPI开关可以根据第一管脚的状态确定控制指令中的Y位指令，具体包括：MIPI开关基于第一控制逻辑，可以确定第一管脚的状态对应的控制指令中的Y位指令；第一控制逻辑包括N种状态与Y位指令的对应关系，其中不同的连接状态对应控制指令中不同的Y位指令。
在本申请提供的方案中，第一管脚可以为Mode管脚。相应地，MIPI开关可以包括Mode识别模块。Mode识别模块基于第一控制逻辑和Mode管脚的状态，可以确定Mode管脚的状态对应的控制指令中的Y位指令。在本申请的一个实施例中，Mode管脚可以有两种状态：1)Mode管脚接高电平；2)Mode管脚接低电平。在本申请的又一个实施例中，Mode管脚可以有四种状态：1)Mode管脚接高电平；2)Mode管脚带负载接高电平；3)Mode管脚接低电平；4)Mode管脚带负载接低电平。
结合第一方面，在一种可能的实现方式中，Y位指令中的K位指令为标志位指令；K为不小于1的正整数；MIPI开关根据所述Y位指令进行切换，具体可以包括：若标志位指令表示为第一状态，MIPI开关不响应Y位指令；若标志位指令表示为第二状态，MIPI开关响应所述Y位指令。
在本申请提供的方案中，可以在Y位指令中设置标志位指令。MIPI开关可以根据Y位指令中的标志位指令判断该开关是否响应这Y位指令。因此，一条MIPI指令可以控制多个MIPI开关时，不一定该MIPI指令控制的每一个开关都必须响应该MIPI指令。MIPI开关可以在需要在断开状态和闭合状态之间切换时，响应MIPI指令。可以节省不必要的译码过程，从而降低MIPI开关的响应时间。
结合第一方面，在一种可能的实现方式中，MIPI开关还可以包括通用输入与输出GPIO管脚。MIPI开关中的至少一个所述GPIO管脚与GPIO开关连接，其中不同的GPIO管脚与不同的GPIO开关连接。开关切换方法还可以包括：MIPI开关基于第二控制逻辑，确定GPIO管脚对应的控制指令中的Z位指令；第二控制逻辑包括GPIO管脚与Z位指令的对应关系，其中不同的GPIO管脚对应控制指令中不同的Z位指令；Z小于或等于X；MIPI开关根据Z位指令切换GPIO开关。
在本申请提供的方案中，MIPI开关还可以包括GPIO管脚，并通过GPIO管脚与GPIO开关相连。并且，MIPI开关还可以利用控制指令中的一部分来控制GPIO开关。因此，不仅可以用一条MIPI指令来控制多个MIPI开关，还可以用一条MIPI指令来控制多个MIPI开关和至少一个GPIO开关。可以实现更多种开关的切换，从而更便利地实现多种天线频率的切换。
第二方面，本申请提供一种MIPI开关，该MIPI开关可以包括：管脚模块、子开关模块和控制器。管脚模块可以包括第一管脚。子开关模块可以包括至少一个子开关。控制器，可以用于接收MIPI指令。MIPI指令可以包括控制指令。控制器，还可以用于在确定MIPI 指令用于控制所述MIPI开关的情况下，根据第一管脚的状态确定控制指令中的Y位指令。控制指令可以包括X位指令，Y小于或等于X。控制器，还可以用于根据Y位指令切换至少一个子开关。
结合第二方面，在一种可能的实现方式中，MIPI指令包括第二MIPI地址。所述控制器包括：地址寄存器，所述地址寄存器中存储有第一MIPI地址；解码器，用于解析MIPI指令，得到第二MIPI地址和控制指令；判断第一MIPI地址和第二MIPI地址是否一致；数据寄存器，用于存储控制指令；Mode识别模块，用于当第一MIPI地址与第二MIPI地址一致时，根据第一管脚的状态确定控制指令中的Y位指令。
结合第二方面，在一种可能的实现方式中，第一管脚有N种状态。Mode识别模块，在用于根据第一管脚的状态确定控制指令中的Y位指令时，具体用于：基于第一控制逻辑，确定第一管脚的状态对应的控制指令中的Y位指令。第一控制逻辑包括N种状态与Y位指令的对应关系，其中不同的连接状态对应控制指令中不同的Y位指令。
结合第二方面，在一种可能的实现方式中，Y位指令中的K位指令为标志位指令。K为不小于1的正整数。控制器还可以包括：译码器，用于所述根据所述Y位指令切换所述至少一个子开关；所述译码器，在用于根据Y位指令切换至少一个子开关时，具体用于：若标志位指令表示为第一状态，译码器不响应Y位指令；若标志位指令表示为第二状态，译码器响应Y位指令。
结合第二方面，在一种可能的实现方式中，MIPI开关还包括通用输入与输出GPIO管脚。所述MIPI开关中的至少一个所述GPIO管脚与GPIO开关连接，其中不同的GPIO管脚与不同的GPIO开关连接。译码器还可以用于：基于第二控制逻辑，确定GPIO管脚对应的控制指令中的Z位指令。第二控制逻辑包括GPIO管脚与Z位指令的对应关系，其中不同的GPIO管脚对应所述控制指令中不同的Z位指令。Z小于或等于X。控制器，还可以用于根据Z位指令切换GPIO开关。
第三方面，本申请提供一种电子设备。该电子设备包括上述第二方面以及结合上述第二方面中的任意一种实现方式所提供的MIPI开关。
第四方面，本申请提供一种计算机存储介质，包括指令，当上述指令在MIPI开关或电子设备上运行时，使得上述MIPI开关或电子设备执行上述第一方面以及结合上述第一方面中的任意一种实现方式所提供的开关切换方法。
第五方面，本申请实施例提供一种包含指令的计算机程序产品，当上述计算机程序产品在MIPI开关或电子设备上运行时，使得上述MIPI开关或电子设备执行上述第一方面以及结合上述第一方面中的任意一种实现方式所提供的开关切换方法。
第六方面，本申请实施例提供一种芯片，该芯片应用于电子设备，该芯片包括一个或多个处理器，该处理器用于调用计算机指令以使得该电子设备执行上述第一方面以及结合上述第一方面中的任意一种实现方式所提供的开关切换方法。
可理解，上述第二方面提供的MIPI开关、第三方面提供的电子设备、第四方面提供的计算机存储介质、第五方面提供的计算机程序产品、第六方面提供的芯片均用于执行本申 请实施例所提供的方法。因此，其所能达到的有益效果可参考对应方法中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种MIPI开关的示意图；
图2为本申请实施例提供的一种MIPI指令的示意图；
图3为本申请实施例提供的一种MIPI指令控制开关的原理示意图；
图4A为本申请实施例提供的又一种MIPI开关的示意图；
图4B为本申请实施例提供的又一种MIPI开关的示意图；
图5为本申请实施例提供的一种开关切换方法的示意图；
图6为本申请实施例提供的一种开关切换系统的示意图；
图7为本申请实施例提供的一种开关切换方法的流程图；
图8为本申请实施例提供的一种控制器的结构原理示意图；
图9为本申请实施例提供的一种Mode识别模块的原理示意图；
图10为本申请实施例提供的又一种MIPI指令控制开关的原理示意图；
图11为本申请实施例提供的又一种MIPI指令控制开关的原理示意图；
图12为本申请实施例提供的又一种MIPI指令控制开关的原理示意图；
图13为本申请实施例提供的一种Mode管脚的状态示意图；
图14为本申请实施例提供的一种MIPI开关的连接示意图；
图15为本申请实施例提供的一种MIPI开关的原理图；
图16为本申请实施例提供的又一种MIPI指令控制开关的原理示意图；
图17为本申请实施例提供的又一种MIPI开关的连接示意图；
图18为本申请实施例提供的又一种MIPI开关的连接示意图；
图19为本申请实施例提供的一种译码器的原理示意图；
图20为本申请实施例提供的一种MIPI开关的结构示意图；
图21为本申请实施例提供的一种电子设备的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述。其中，在本申请实施例的描述中，除非另有说明，“/”表示或的意思，例如，A/B可以表示A或B；文本中的“和/或”仅仅是一种描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B这三种情况，另外，在本申请实施例的描述中，“多个”是指两个或多于两个。
应当理解，本申请的说明书和权利要求书及附图中的术语“第一”、“第二”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本申请中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包 含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本申请所描述的实施例可以与其它实施例相结合。
首先，对本申请中所涉及的部分用语和相关技术进行解释说明，以便于本领域技术人员理解。
MIPI(移动行业处理器接口)是Mobile Industry Processor Interface的缩写。MIPI(移动行业处理器接口)是MIPI联盟发起的为移动应用处理器制定的开放标准。
GPIO(英语：General-purpose input/output)，通用型之输入输出的简称，功能类似8051的P0—P3，其接脚可以供使用者由程控自由使用，PIN脚依现实考量可作为通用输入(GPI)或通用输出(GPO)或通用输入与输出(GPIO)，如当clk generator,chip select等。
引脚，又叫管脚，英文叫Pin，是从集成电路(芯片)内部电路引出与外围电路的接线，所有的引脚就构成了这块芯片的接口。引线末端的一段，通过软钎焊使这一段与印制板上的焊盘共同形成焊点。
随着通信技术不断发展，不仅天线的数量日益增多，还要求天线能支持不同的工作频率，这个时候就需要利用开关来切换不同的状态，以便天线能支持不同的工作频率，即使得天线能接收/发送不同频率的信号。
MIPI开关是目前广泛使用的一种开关，可以利用MIPI开关帮助天线切换不同工作频率。如图1所示，图1为本申请实施例提供的一种MIPI开关的示意图，MIPI开关内部包括控制器和子开关。其中，控制器的作用是把MIPI指令翻译成对内部各子开关的控制信号；子开关的断开和闭合由控制器输出的电平控制，子开关数量可以是1个或多个。每个子开关端口一端接地另一端连接一个匹配元件，当MIPI开关中的子开关数量不止一个时，该MIPI开关中的子开关连接的匹配元件并联连接到天线，如图1所示，子开关1一端接GND(接地)，另一端连接匹配元件1，子开关2一端接GND(接地)，另一端连接匹配元件2，即子开关1与匹配元件1串联连接，子开关2与匹配元件2串联连接，然后匹配元件1和匹配元件2并联连接到天线。
可理解，MIPI开关还可以包括一些其他管脚和器件，本申请对此不作限制。
MIPI开关是由MIPI指令来控制的，MIPI指令中包括地址位和控制指令位，其中，地址位共4位，用来表示该MIPI指令控制的MIPI开关的地址信息(MIPI地址)，控制指令位共8位，这8位控制指令具体用来控制MIPI开关的状态，即控制MIPI开关子开关的断开和闭合，如图2所示，Bit0-Bit8用来表示MIPI指令的具体内容。可理解，每一个MIPI开关对应一个独立的MIPI地址，而MIPI指令是在MIPI总线上广播的，只有与MIPI指令中的MIPI地址对应的MIPI开关才会响应该MIPI指令。如图3所示，图3为本申请实施例提供的一种MIPI指令控制开关的原理示意图，MIPI指令A在总线上广播，该指令中的地址位为0101，开关A的MIPI地址为0101，开关A的地址与MIPI指令A中地址位所表示的地址是相同的，所以开关A响应MIPI指令A，而开关B的地址为0001，开关C的地址为1011，这两个开关的地址与MIPI指令A中地址位所表示的地址是不同的，所以开关B和开关C不响应MIPI指令A。
需要说明的是，MIPI指令控制MIPI开关表现为控制MIPI开关中的子开关的断开和闭合，当MIPI开关内部包括一个以上的子开关时，MIPI指令一般只控制一个子开关的断开和闭合，所以不会出现一个以上的子开关都闭合的情况。例如，图4A和图4B中的MIPI开关包括2个子开关，MIPI指令控制该MIPI开关时，如图4A所示，可以控制子开关1闭合，此时子开关2断开，或者，如图4B所示，可以控制子开关2闭合，此时子开关1断开。
目前，MIPI总线上可以连接多个MIPI开关以支持不同工作频率的切换，当需要切换多个MIPI开关的状态来支持某个频率时，由于MIPI指令只能控制该指令中的MIPI地址所对应的MIPI开关，并且MIPI总线上只能串行发送MIPI指令，所以在需要切换多个MIPI开关的状态的时候，需要串行发送多条MIPI指令，如图5所示，若要切换开关1到开关5共5个MIPI开关的状态，例如，由断开状态切换为闭合状态，或者，由闭合状态切换为断开状态，需要发送5条MIPI指令，该5条MIPI指令中的MIPI地址分别对应5个MIPI开关的MIPI地址，由于在MIPI总线上MIPI指令是串行发送的(一个指令发送完成之后才能发下一个指令)，所以5个MIPI开关无法同时响应。可理解，上述开关切换方法中，开关的响应时间很长，从而导致整个开关切换过程的时延过长，使得无法及时切换开关以支持不同的工作频率。
另外，平台对于MIPI开关的数量也会有限制，例如，modem(通信基带芯片)对天线切换的总时延有要求，所以限制了MIPI开关的数量。
基于上述内容，本申请提供了一种开关切换方法及相关装置，可以实现多个MIPI开关共享一个地址，从而实现一条MIPI指令控制多个MIPI开关，克服了平台对MIPI开关数量的限制，并且减少了开关的响应时间，即降低了切换开关的时延。
下面首先介绍本申请实施例所涉及的系统架构。
请参阅图6，图6为本申请实施例提供的一种开关切换系统的示意图，该开关切换系统包括至少一个MIPI开关、MIPI总线、匹配元件以及天线，MIPI开关内部包括控制器和至少一个子开关，其控制器与MIPI总线相连，其子开关一端与匹配元件串联再与天线连接，另一端接地，需要说明的是，当一个MIPI开关包括多个子开关时，这些子开关并联连接。
可理解，当开关切换系统包括一个以上的MIPI开关时，两个及两个以上的MIPI开关可以共享一个地址，从而实现一条MIPI指令控制多个开关。为了使这些相同地址的不同MIPI开关能独立切换，即相同地址的不同MIPI开关的断开和闭合互不影响，可以将MIPI指令中的控制指令位(如图2所示，共8位)进行划分。
另外，MIPI开关中可以包括控制器和第一管脚，且控制器与第一管脚之间存在连接关系。可理解，第一管脚可以包括但不限于Mode管脚。以下描述均以Mode管脚为例进行说明。
可理解，控制器与Mode管脚之间存在连接关系。可以将Mode管脚的不同状态与划分后的控制指令位一一对应，使得MIPI开关在读取MIPI指令时，能根据Mode管脚的不同状态区分该MIPI开关此时对应的是哪几位控制指令位。
MIPI总线广播MIPI指令后，MIPI开关内部的控制器解析该MIPI指令，判断该MIPI指令中的地址与本MIPI开关的地址是否相同，若不相同，则MIPI开关对该MIPI指令不响应；若相同，则控制器继续对该MIPI指令的控制指令进行解析，并识别Mode管脚的状态，来判断具体由控制指令的哪几位来控制该MIPI开关，然后将这几位控制指令转换为器件状态，从而实现切换。
下面结合图7所示的流程图介绍本申请的具体实现方式。
S701：接收MIPI指令，MIPI指令包括MIPI地址和控制指令。
具体地，当需要切换至不同的工作频率时，主控器件或平台下发相应的MIPI指令，然后由MIPI总线广播该MIPI指令，MIPI开关接收该MIPI指令。可理解，MIPI开关包括第一管脚，第一管脚可以包括但不限于Mode管脚(下文中均以Mode管脚为例进行说明)。另外，MIPI指令可以包括MIPI地址和控制指令。
在本申请的一个实施例中，由MIPI开关中的控制器接收该MIPI指令。
如图8所示，图8为本申请实施例提供的一种控制器的结构原理示意图，该控制器包括解码器、地址寄存器、数据寄存器、Mode识别模块以及译码器，其中，解码器用于解析MIPI指令来获得MIPI指令中的MIPI地址和控制指令；地址寄存器用于保存当前CPU所访问的内存单元的地址，在本申请的一个实施例中，地址寄存器用于保存当前接收的MIPI指令中的MIPI地址；数据寄存器用来暂存微处理器与存储器或输入/输出接口电路之间待传送的数据，在本申请的一个实施例中，数据寄存器用于暂存MIPI指令中的控制指令；Mode识别模块用于识别Mode管脚的当前状态；译码器用于将MIPI指令中的控制指令转换为器件状态进行显示。
S702：初步解析MIPI指令。
具体地，MIPI开关初步解析MIPI指令，得到MIPI地址和X位控制指令。其中，MIPI地址用于指明所述MIPI指令所控制的MIPI开关的地址，控制指令用于控制所述MIPI开关中各子开关的断开和闭合。
在本申请的一个实施例中，由MIPI开关中的控制器初步解析MIPI指令，具体由控制器中的解码器对MIPI指令进行初步解析，得到4位MIPI地址和8位控制指令。
S703：判断MIPI指令中的MIPI地址与MIPI开关的MIPI地址是否一致。
具体地，MIPI开关判断MIPI指令中的MIPI地址(即初步解析得到的MIPI地址)与该MIPI开关自身的MIPI地址是否一致，若不一致，则该MIPI指令不能控制该MIPI开关，即该MIPI开关不响应；若一致，MIPI开关将控制指令写入数据寄存器。
在本申请的一个实施例中，数据寄存器中包括D0-D7共8个数据位，用于存储MIPI开关写入的8位控制指令(Bit0-Bit7)。
S704：确定MIPI指令响应控制指令中的Y位指令。
具体地，在MIPI开关判断接收的MIPI指令中的MIPI地址与自身的MIPI地址一致后，还需要确定该MIPI开关响应控制指令的哪一部分，即判断由控制指令的哪一位或哪几位控制该MIPI开关。
可理解，可以通过Mode识别模块来识别Mode管脚的状态，从而判断由控制指令位的 哪一位或哪几位控制该MIPI开关。也就是说，在确定MIPI指令用于控制MIPI开关(MIPI指令中的地址与MIPI开关的地址一致)的情况下，MIPI开关根据Mode管脚的状态可以确定控制指令中的Y位指令。这Y位指令即为用于切换该MIPI开关的指令。
需要说明的是，如图8所示，Mode识别模块有两个输入：1、数据寄存器输入的控制指令；2、Mode管脚的状态。具体地，如图9所示，图9为本申请实施例提供的一种Mode识别模块的原理示意图，数据寄存器将解码器进行初步解析后的控制指令(Bit0-Bit7)写入其数据位(D0-D7)传输给Mode识别模块，Mode管脚将其状态传输给Mode识别模块，Mode识别模块根据Mode管脚的状态判断由控制指令位的哪几位控制该MIPI开关，进而判断具体由哪部分控制指令控制该MIPI开关，也就是说，Mode管脚的不同状态与控制指令位的不同部分存在映射关系。
具体地，根据上文可知控制指令位有8位，将这8位控制指令位进行划分，每次划分可以得到M个组合，这里所说的组合指的是由不同控制指令位构成的组合，所以也可以理解为将这8位控制指令位划分为M个部分，其中，每个部分包含的控制指令位的位数不一定相同，每个部分包含的控制指令位也不一定是相邻的，例如，将8位控制指令位进行划分，得到3个组合(M＝3)，这3个组合分别为：①Bit0、Bit2；②Bit1、Bit3和Bit4；③Bit5-Bit7。而Mode管脚可以有N种状态，这N种状态可以为接高电平、带负载接高电平、接低电平、带负载接低电平和开路等状态中的一种或多种，Mode管脚的每一种状态对应控制指令位经划分后得到的一个组合。可理解，不一定划分控制指令位后所得的每个组合都与Mode管脚的某个状态相对应，Mode管脚可以实现的状态的种类不超过控制指令位划分后所得的组合的数量，即M与N的关系是M≥N。
在本申请的一个实施例中，Mode管脚有两个状态：1、Mode管脚接高电平；2、Mode管脚接低电平，即N＝2。因为M≥N，所以M≥2。控制指令位经划分可以得到至少两种组合，如图10所示，控制指令位经划分得到两个组合——组合1和组合2，当MIPI开关的Mode管脚接高电平时，该MIPI开关响应组合1包含的控制指令位；当MIPI开关的Mode管脚接低电平时，该MIPI开关响应组合2包含的控制指令位。可理解，组合1包含的控制指令位的位数与组合2包含的控制指令位的位数都可以改变，但是，由于控制指令位有8位，所以组合1和组合2两部分包含的控制指令位的位数总和不超过8位(Bit0-Bit7)。也就是说，Y不是定值，但是Y≤8。例如，A包括4位(Bit4-Bit7)，B包括4位(Bit0-Bit3)；A包括2位(Bit6-Bit7)，B包括6位(Bit0-Bit5)；A包括3位(Bit5-Bit7)，B包括3位(Bit0-Bit2)。
根据上述内容可知，当Mode管脚有两个状态时，一条MIPI指令可以控制两个MIPI开关，如图11所示，开关A的Mode管脚接高电平，开关B的Mode管脚接低电平，若开关A和开关B的MIPI地址与图中所示的MIPI指令的地址相同，则该MIPI指令可以同时控制开关A和开关B，具体地，开关A响应该MIPI指令中的组合1，开关B响应该MIPI指令中的组合2。
可理解，Mode管脚接高电平的实现方式包括Mode管脚接电源，Mode管脚接低电平的实现方式包括Mode管脚接地，当然，还有很多其他的实现方式使得Mode管脚接高/低电平，本申请对此不作限制。
示例性的，当MIPI开关的Mode管脚接高电平时，该MIPI开关响应控制指令位中的 高四位(Bit4-Bit7)控制指令；当MIPI开关的Mode管脚接低电平时，该MIPI开关响应控制指令位中的低四位(Bit0-Bit3)控制指令。如图12所示，图12为本申请实施例提供的又一种MIPI指令控制开关的原理示意图，MIPI总线广播MIPI指令，该MIPI指令包括的MIPI地址为0101，开关A、开关B和开关C接收该MIPI指令后判断其地址是否与自身的MIPI地址相同，因为开关A的MIPI地址为0101，开关B的MIPI地址为0101，开关C的MIPI地址为0001，所以开关A和开关B的MIPI地址与该MIPI指令的地址相同，开关A和开关B响应该MIPI指令，而开关C的MIPI地址与该MIPI指令的地址不同，开关C不响应该MIPI指令。开关A和开关B进行地址校验后，由其内部的Mode识别模块对Mode管脚的状态进行识别，开关A的Mode管脚接电源，所以开关A的Mode管脚接高电平，开关A响应控制指令位中的组合1，即响应控制指令位中的高四位(Bit4-Bit7)控制指令，而开关B的Mode管脚接地，所以开关B的Mode管脚接低电平，开关B响应控制指令位中的组合2，即响应控制指令位中的低四位(Bit0-Bit3)控制指令。可理解，在上述示例中，Y＝4。
在本申请的又一个实施例中，如图13所示，Mode管脚有四个状态：1、Mode管脚接高电平；2、Mode管脚带负载接高电平；3、Mode管脚接低电平；4、Mode管脚带负载接低电平，即N＝4。
根据上述内容可知，当Mode管脚有四个状态时，一条MIPI指令最多可以控制四个MIPI开关，如图14所示，开关A的Mode管脚接高电平，开关B的Mode管脚带负载接高电平，开关C的Mode管脚接低电平，开关D的Mode管脚带负载接低电平，若开关A、开关B、开关C和开关D的MIPI地址与某条MIPI指令的地址相同，则该MIPI指令可以同时控制开关A、开关B、开关C和开关D。
可理解，Mode管脚接高电平的实现方式包括Mode管脚接电源，Mode管脚带负载接高电平的实现方式包括Mode管脚连接电阻等器件后再接电源，Mode管脚接低电平的实现方式包括Mode管脚接地，Mode管脚带负载接低电平的实现方式包括Mode管脚连接电阻等器件后接地，当然，还有很多其他的实现方式使得Mode管脚接高/低电平，本申请对此不作限制。
需要说明的是，上文中所描述的Mode管脚的不同状态与控制指令位的组合之间的映射关系是指Mode识别模块的逻辑，即第一控制逻辑。也可以理解为，Mode识别模块的逻辑(第一控制逻辑)包括Mode管脚的N种状态与Y位指令的对应关系。
可理解，Mode识别模块的逻辑可以由真值表定义。根据上述示例并结合表1，对Mode识别模块的逻辑进行说明：
表1
Figure PCTCN2022086439-appb-000001
将Mode管脚接高电平定义为“1”，将Mode管脚接低电平定义为“0”，数据寄存器中的八个数据位(D0-D7)存储的是8位(Bit0-Bit7)控制指令，输出信号指的是Mode识别模块向译码器输出的数据位。
根据表1，当Mode管脚接高电平时，Mode识别模块将数据寄存器中的数据位(D0-D7)的高4位(D4-D7)输出给译码器；当Mode管脚接低电平时，Mode识别模块将数据寄存器中的数据位(D0-D7)的低4位(D0-D3)输出给译码器。
可理解，可以将X位控制指令中的Z位指令用于控制其他开关(例如，GPIO开关)。例如，当划分8位控制指令位得到的组合数比Mode管脚的状态要多时，即当M与N的关系是M>N时，可以将8位控制指令中的Z位指令用于控制GPIO开关。可理解，Z≤8。
如图15所示，图15为本申请实施例提供的一种MIPI开关的原理图，MIPI开关接收MIPI总线广播的MIPI指令后，通过解码器对MIPI指令进行初步解析，得到4位MIPI地址和8位控制指令。MIPI开关比较地址寄存器中的MIPI地址与解码器解析得到的MIPI地址是否一致，若一致，则将8位控制指令写入数据寄存器。数据寄存器再将该控制指令分别传输给Mode识别模块和译码器。Mode识别模块根据Mode管脚的状态判断由控制指令的哪几位控制该MIPI开关，并将这几位控制指令传输给译码器，再由译码器根据第二控制逻辑具体控制该MIPI开关的子开关的断开和闭合。另外，译码器还根据第二控制逻辑具体控制GPIO开关的断开和闭合。具体地，译码器判断控制指令的哪几位控制GPIO开关，并根据第二控制逻辑传输不同的电平给相应的GPIO管脚。
如图16所示，在本申请的一个实施例中，设置控制指令位的高3位(Bit5-Bit7)控制相同MIPI地址的MIPI开关，其他几位(Bit0-Bit4)为GPIO控制位，具体控制相同MIPI地址的MIPI开关的GPIO管脚(GPIO1-GPIO5)的输出。可理解，MIPI开关的GPIO管脚可以连接GPIO开关，当MIPI开关的GPIO管脚连接GPIO开关时，MIPI开关的GPIO的输出信号即为MIPI开关连接的GPIO开关的输入信号，此时，MIPI指令不仅可以控制同地址的MIPI开关，还可以控制与该MIPI开关相连的GPIO开关。
示例性的，如图17所示，图17为本申请实施例提供的又一种MIPI开关的连接示意图，开关A为MIPI开关，开关B和开关C为GPIO开关，开关A包括两个GPIO管脚——GPIO_1和GPIO_2，其中，开关A通过GPIO_1与开关B相连接，且通过GPIO_2与开关C相连接。开关A接收MIPI指令并判断该MIPI指令中的MIPI地址与自身的MIPI地址相同后，将该MIPI指令中的控制指令(Bit0-Bit7)写入数据寄存器，数据寄存器再将写入的控制指令(D0-D7)分别传输给Mode识别模块和译码器，通过Mode识别模块来判断由控制指令的哪几位控制该开关A，而译码器会根据控制逻辑将MIPI指令中的GPIO控制位对应的指令转换成对外输出电平，利用该电平控制连接的GPIO开关。若采取图15所示的MIPI指令的控制逻辑，译码器根据控制指令位的高3位(Bit5-Bit7，也就是数据寄存器的高3位数据位：D5-D7)控制开关A的子开关，并将控制指令位的第5位(Bit4)通过GPIO_1传输给开关B，将控制指令位的第4位(Bit3)通过GPIO_2传输给开关C。
可理解，控制指令控制GPIO开关的逻辑(即第二控制逻辑)可以由真值表定义。以 Bit0-Bit4为GPIO控制位为例对第二控制逻辑进行说明。如下表2所示：
表2
Figure PCTCN2022086439-appb-000002
如表2所示，无论D5-D7的指令是多少，最终仅由D0-D4(Bit0-Bit4)控制GPIO开关的切换。也就是说，Bit0-Bit4为GPIO控制位，分别控制通过管脚GPIO1-5连接的GPIO开关。可理解，通过控制指令控制GPIO开关的逻辑(即第二控制逻辑)可以由译码器实现(如图17所示)，还可以由数据寄存器实现。若由数据寄存器实现控制指令控制GPIO开关的逻辑，数据寄存器无需将控制指令传输给译码器，而是直接将控制GPIO开关的控制指令直接传输至GPIO引脚。
需要说明的是，GPIO开关通过GPIO管脚传输的电平来进行切换，例如，当GPIO开关的GPIO管脚输入的是高电平，该GPIO开关闭合；当GPIO开关的GPIO管脚输入的是低电平，该GPIO开关闭合。
还需要说明的是，MIPI总线上可以挂载多个MIPI开关，这些MIPI开关可以连接多个GPIO开关，如图18所示，MIPI总线上挂载有开关A和开关B，开关A通过GPIO_1管脚与开关C相连接，且通过GPIO_2管脚与开关D相连接，开关B通过GPIO_1管脚与开关E相连接，且通过GPIO_2管脚与开关F相连接。若开关A和开关B的MIPI地址相同，则与它们地址相同的MIPI指令可以同时控制开关A、开关B、开关C、开关D、开关E和开关F。
S705：根据Y位指令切换MIPI开关的状态。
具体地，MIPI开关中的译码器根据Mode识别模块的输出信号(即Y位指令)控制子开关的断开和闭合，即译码器的输入信号是Mode识别模块的输出信号，或者，MIPI开关中的译码器根据数据寄存器的输出信号控制子开关的断开和闭合，即译码器的输入信号是数据寄存器的输出信号。
与Mode识别模块的逻辑类似，译码器根据输入信号控制子开关的逻辑也可以由真值表定义。
示例性的，如图19所示，译码器的输入信号有4位，译码器根据这4位输入信号控制4个子开关——子开关1、子开关2、子开关C和子开关D。如表3所示，当译码器的输入信号的最高位为0时，译码器保持子开关处于原状态，不切换其状态；当译码器的输入信 号为1000(排序为高位到低位)时，输出信号为0000，译码器控制所有子开关断开；当译码器的输入信号为1001(排序为高位到低位)时，输出信号为0001，译码器控制子开关1闭合；当译码器的输入信号为1010(排序为高位到低位)时，输出信号为0010，译码器控制子开关2闭合；当译码器的输入信号为1011(排序为高位到低位)时，输出信号为0100，译码器控制子开关C闭合；当译码器的输入信号为1100(排序为高位到低位)时，输出信号为1000，译码器控制子开关D闭合。
表3
Figure PCTCN2022086439-appb-000003
需要说明的是，可以在译码器的输入信号中(在Mode管脚的不同状态所对应的控制指令位的组合中)设置标志位。标志位中包括K位标志位指令。可理解，K为不小于1且不大于X的正整数。译码器可以根据该标志位指令判断是否根据输入信号切换子开关的状态。
示例性的，将输入信号中的最高位设置成标志位，当Mode管脚接高电平时，译码器的输入信号为数据寄存器中的数据位(D0-D7)的高4位(D4-D7)，此时，D7为标志位，当D7这一位指令(标志位指令)是0时，译码器收到输入信号后不切换子开关的状态，当D7这一位指令(标志位指令)是1时，译码器收到输入信号后根据输入信号切换子开关的状态；当Mode管脚接低电平时，译码器的输入信号为数据寄存器中的数据位(D0-D7)的低4位(D0-D3)，此时，D3为标志位，当D3这一位指令(标志位指令)是0时，译码器收到输入信号后不切换子开关的状态，当D3这一位指令(标志位指令)是1时，译码器收到输入信号后根据输入信号切换子开关的状态。
S706：MIPI开关不响应控制指令。
具体地，当MIPI指令中的MIPI地址与MIPI开关的MIPI地址不一致时，该MIPI指令不能控制该MIPI开关，即该MIPI开关不响应该MIPI指令中的控制指令。
下面介绍本申请提供的装置。
本申请提供了一种MIPI开关，如图20所示，该MIPI开关可用于图6所示的开关切换系统，还可以用于执行图7所示的开关切换方法。
如图20所示，MIPI开关2000可以包括管脚模块2010、子开关模块2020和控制器2030。
其中，管脚模块2010包括MIPI开关2000与外围电路连接所需要的管脚(引脚)，这些管脚与MIPI开关2000的内部结构紧密相关。在本申请的一个实施例中，管脚模块2010 包括Mode管脚。在本申请的另一个实施例中，管脚模块2010包括Mode管脚和至少一个GPIO管脚。
子开关模块2020包括至少一个子开关，子开关可以通过匹配元件与天线连接。当子开关模块2020包括多个子开关时，这些子开关可以通过不同的匹配元件与天线连接。控制器2030具体实现对MIPI指令的相关处理。如图20所示，控制器2030可以包括解码器2031、数据寄存器2032、地址寄存器2033、译码器2034和Mode识别模块2035。其中，解码器2031用于对接收的MIPI指令进行初步解析，从而得到MIPI指令中的地址和控制指令；数据寄存器2032用于存储控制指令，数据寄存器2032可以将写入的控制指令传输给Mode识别模块2035和译码器；地址寄存器2033用于存储MIPI开关2000自身的地址；译码器2034用于将控制指令转换为器件状态；Mode识别模块2035用于判断具体由控制指令的哪几位控制MIPI开关2000，具体地，Mode识别模块2035识别Mode管脚的状态，并根据Mode管脚的状态以及Mode识别模块2035的逻辑来判断是控制指令的哪几位控制MIPI开关2000，并将这几位控制指令传输给译码器2034。
可理解，MIPI开关2000还可以包括更多或更少的模块，上述内容仅为本申请的一种实现方式，不视为对本申请的限制。
本申请还提供了一种电子设备，该电子设备包括MIPI开关2000。可理解，该电子设备可以为包括MIPI开关2000的手机、PC、平板电脑、智能手表、智能音箱等设备。
示例性的，图21为本申请提供的一种电子设备的结构示意图，该电子设备包括MIPI开关2000。下面对图21所示的电子设备2100进行具体说明：
电子设备2100可以包括处理器2110，外部存储器接口2120，内部存储器2121，通用串行总线(Universal Serial Bus，USB)接口2130，充电管理模块2140，电源管理模块2141，电池2142，天线1，天线2，移动通信模块2150，无线通信模块2160，音频模块2170，扬声器2170A，受话器2170B，麦克风2170C，耳机接口2170D，传感器模块2180，按键2190，马达2191，指示器2192，摄像头2193，显示屏2194，以及用户标识模块(Subscriber Identification Module，SIM)卡接口2195等。其中传感器模块2180可以包括压力传感器2180A，陀螺仪传感器2180B，气压传感器2180C，磁传感器2180D，加速度传感器2180E，距离传感器2180F，接近光传感器2180G，指纹传感器2180H，温度传感器2180J，触摸传感器2180K，环境光传感器2180L，骨传导传感器2180M等。
可以理解的是，本发明实施例示意的结构并不构成对电子设备2100的具体限定。在本申请另一些实施例中，电子设备2100可以包括比图示更多或更少的部件，或者组合某些部件，或者拆分某些部件，或者不同的部件布置。图示的部件可以以硬件，软件或软件和硬件的组合实现。
处理器2110可以包括一个或多个处理单元，例如：处理器2110可以包括应用处理器(Application Processor，AP)，调制解调处理器，图形处理器(Graphics Processing unit，GPU)，图像信号处理器(Image Signal Processor，ISP)，控制器，存储器，视频编解码器，数字信号处理器(Digital Signal Processor，DSP)，基带处理器，和/或神经网络处理器(Neural-network Processing Unit，NPU)等。其中，不同的处理单元可以是独立的器件， 也可以集成在一个或多个处理器中。
其中，控制器可以是电子设备2100的神经中枢和指挥中心。控制器可以根据指令操作码和时序信号，产生操作控制信号，完成取指令和执行指令的控制。
可理解，处理器2110中还可以包括AE系统。AE系统可以具体设置在ISP中。AE系统可用于实现曝光参数的自动调整。可选的，AE系统还可以集成在其它处理器芯片中。本申请实施例对此不作限定。
在本申请提供的实施例中，电子设备2100可以通过处理器2110执行所述曝光强度调节方法。
处理器2110中还可以设置存储器，用于存储指令和数据。在一些实施例中，处理器2110中的存储器为高速缓冲存储器。该存储器可以保存处理器2110刚用过或循环使用的指令或数据。如果处理器2110需要再次使用该指令或数据，可从所述存储器中直接调用。避免了重复存取，减少了处理器2110的等待时间，因而提高了系统的效率。
在一些实施例中，处理器2110可以包括一个或多个接口。接口可以包括集成电路(Inter-Integrated Circuit，I2C)接口，集成电路内置音频(Inter-Integrated Circuit Sound，I2S)接口，脉冲编码调制(Pulse Code Modulation，PCM)接口，通用异步收发传输器(Universal Asynchronous Receiver/Transmitter，UART)接口，移动产业处理器接口(Mobile Industry Processor Interface，MIPI)，通用输入输出(General-Purpose Input/Output，GPIO)接口，用户标识模块(Subscriber Identity Module，SIM)接口，和/或通用串行总线(Universal Serial Bus，USB)接口等。
I2C接口是一种双向同步串行总线，包括一根串行数据线(Serial Data Line，SDA)和一根串行时钟线(Serial Clock Line，SCL)。在一些实施例中，处理器2110可以包含多组I2C总线。处理器2110可以通过不同的I2C总线接口分别耦合触摸传感器2180K，充电器，闪光灯，摄像头2193等。例如：处理器2110可以通过I2C接口耦合触摸传感器2180K，使处理器2110与触摸传感器2180K通过I2C总线接口通信，实现电子设备2100的触摸功能。
I2S接口可以用于音频通信。在一些实施例中，处理器2110可以包含多组I2S总线。处理器2110可以通过I2S总线与音频模块2170耦合，实现处理器2110与音频模块2170之间的通信。在一些实施例中，音频模块2170可以通过I2S接口向无线通信模块2160传递音频信号，实现通过蓝牙耳机接听电话的功能。
PCM接口也可以用于音频通信，将模拟信号抽样，量化和编码。在一些实施例中，音频模块2170与无线通信模块2160可以通过PCM总线接口耦合。在一些实施例中，音频模块2170也可以通过PCM接口向无线通信模块2160传递音频信号，实现通过蓝牙耳机接听电话的功能。所述I2S接口和所述PCM接口都可以用于音频通信。
UART接口是一种通用串行数据总线，用于异步通信。该总线可以为双向通信总线。它将要传输的数据在串行通信与并行通信之间转换。在一些实施例中，UART接口通常被用于连接处理器2110与无线通信模块2160。例如：处理器2110通过UART接口与无线通信模块2160中的蓝牙模块通信，实现蓝牙功能。在一些实施例中，音频模块2170可以通过UART接口向无线通信模块2160传递音频信号，实现通过蓝牙耳机播放音乐的功能。
MIPI接口可以被用于连接处理器2110与显示屏2194，摄像头2193等外围器件。MIPI接口包括摄像头串行接口(Camera Serial Interface，CSI)，显示屏串行接口(Display Serial Interface，DSI)等。在一些实施例中，处理器2110和摄像头2193通过CSI接口通信，实现电子设备2100的拍摄功能。处理器2110和显示屏2194通过DSI接口通信，实现电子设备2100的显示功能。
GPIO接口可以通过软件配置。GPIO接口可以被配置为控制信号，也可被配置为数据信号。在一些实施例中，GPIO接口可以用于连接处理器2110与摄像头2193，显示屏2194，无线通信模块2160，音频模块2170，传感器模块2180等。GPIO接口还可以被配置为I2C接口，I2S接口，UART接口，MIPI接口等。
USB接口2130是符合USB标准规范的接口，具体可以是Mini USB接口，Micro USB接口，USB Type C接口等。USB接口2130可以用于连接充电器为电子设备2100充电，也可以用于电子设备2100与外围设备之间传输数据。也可以用于连接耳机，通过耳机播放音频。该接口还可以用于连接其他电子设备2100，例如AR设备等。
可以理解的是，本发明实施例示意的各模块间的接口连接关系，只是示意性说明，并不构成对电子设备2100的结构限定。在本申请另一些实施例中，电子设备2100也可以采用上述实施例中不同的接口连接方式，或多种接口连接方式的组合。
充电管理模块2140用于从充电器接收充电输入。其中，充电器可以是无线充电器，也可以是有线充电器。在一些有线充电的实施例中，充电管理模块2140可以通过USB接口2130接收有线充电器的充电输入。在一些无线充电的实施例中，充电管理模块2140可以通过电子设备2100的无线充电线圈接收无线充电输入。充电管理模块2140为电池2142充电的同时，还可以通过电源管理模块2141为电子设备2100供电。
电源管理模块2141用于连接电池2142，充电管理模块2140与处理器2110。电源管理模块2141接收电池2142和/或充电管理模块2140的输入，为处理器2110，内部存储器2121，外部存储器，显示屏2194，摄像头2193，和无线通信模块2160等供电。电源管理模块2141还可以用于监测电池容量，电池循环次数，电池健康状态(漏电，阻抗)等参数。在其他一些实施例中，电源管理模块2141也可以设置于处理器2110中。在另一些实施例中，电源管理模块2141和充电管理模块2140也可以设置于同一个器件中。
电子设备2100的无线通信功能可以通过天线1，天线2，移动通信模块2150，无线通信模块2160，调制解调处理器以及基带处理器等实现。
天线1和天线2用于发射和接收电磁波信号。电子设备2100中的每个天线可用于覆盖单个或多个通信频带。不同的天线还可以复用，以提高天线的利用率。例如：可以将天线1复用为无线局域网的分集天线。在另外一些实施例中，天线可以和调谐开关结合使用。
移动通信模块2150可以提供应用在电子设备2100上的包括2G/3G/4G/5G等无线通信的解决方案。移动通信模块2150可以包括至少一个滤波器，开关，功率放大器，低噪声放大器(Low Noise Amplifier，LNA)等。移动通信模块2150可以由天线1接收电磁波，并对接收的电磁波进行滤波，放大等处理，传送至调制解调处理器进行解调。移动通信模块2150还可以对经调制解调处理器调制后的信号放大，经天线1转为电磁波辐射出去。在一些实施例中，移动通信模块2150的至少部分功能模块可以被设置于处理器2110中。在一 些实施例中，移动通信模块2150的至少部分功能模块可以与处理器2110的至少部分模块被设置在同一个器件中。
调制解调处理器可以包括调制器和解调器。其中，调制器用于将待发送的低频基带信号调制成中高频信号。解调器用于将接收的电磁波信号解调为低频基带信号。随后解调器将解调得到的低频基带信号传送至基带处理器处理。低频基带信号经基带处理器处理后，被传递给应用处理器。应用处理器通过音频设备(不限于扬声器2170A，受话器2170B等)输出声音信号，或通过显示屏2194显示图像或视频。在一些实施例中，调制解调处理器可以是独立的器件。在另一些实施例中，调制解调处理器可以独立于处理器2110，与移动通信模块2150或其他功能模块设置在同一个器件中。
无线通信模块2160可以提供应用在电子设备2100上的包括无线局域网(Wireless Local Area Networks，WLAN)(如无线保真(Wireless Fidelity，Wi-Fi)网络)，蓝牙(Bluetooth，BT)，全球导航卫星系统(Global Navigation Satellite System，GNSS)，调频(Frequency Modulation，FM)，近距离无线通信技术(Near Field Communication，NFC)，红外技术(Infrared，IR)等无线通信的解决方案。无线通信模块2160可以是集成至少一个通信处理模块的一个或多个器件。无线通信模块2160经由天线2接收电磁波，将电磁波信号调频以及滤波处理，将处理后的信号发送到处理器2110。无线通信模块2160还可以从处理器2110接收待发送的信号，对其进行调频，放大，经天线2转为电磁波辐射出去。本实施例中，无线通信模块2160用于实现第一设备与第二设备的交互，例如，第一设备具备无线通信模块，第一设备通过该模块向第二设备发送验证请求，并接收第二设备发送的验证数据。
在一些实施例中，电子设备2100的天线1和移动通信模块2150耦合，天线2和无线通信模块2160耦合，使得电子设备2100可以通过无线通信技术与网络以及其他设备通信。所述无线通信技术可以包括全球移动通讯系统(Global System for Mobile Communications，GSM)，通用分组无线服务(General Packet Radio Service，GPRS)，码分多址接入(Code Division Multiple Access，CDMA)，宽带码分多址(Wideband Code Division Multiple Access，WCDMA)，时分码分多址(Time-Division Code Division Multiple Access，TD-SCDMA)，长期演进(Long Term Evolution，LTE)，BT，GNSS，WLAN，NFC，FM，和/或IR技术等。所述GNSS可以包括全球卫星定位系统(Global Positioning System，GPS)，全球导航卫星系统(Global Navigation Satellite System，GLONASS)，北斗卫星导航系统(Beidou Navigation Satellite System，BDS)，准天顶卫星系统(Quasi-Zenith Satellite System，QZSS)和/或星基增强系统(Satellite Based Augmentation Systems，SBAS)。
电子设备2100通过GPU，显示屏2194，以及应用处理器等实现显示功能。GPU为图像处理的微处理器，连接显示屏2194和应用处理器。GPU用于执行数学和几何计算，用于图形渲染。处理器2110可包括一个或多个GPU，其执行程序指令以生成或改变显示信息。
显示屏2194用于显示图像，视频等。显示屏2194包括显示面板。显示面板可以采用液晶显示屏(Liquid Crystal Display，LCD)，有机发光二极管(Organic Light-Emitting Diode，OLED)，有源矩阵有机发光二极体或主动矩阵有机发光二极体(Active-Matrix Organic Light Emitting Diode的，AMOLED)，柔性发光二极管(Flex Light-Emitting Diode，FLED)，Mini LED，Micro LED，Micro-OLED，量子点发光二极管(Quantum Dot Light Emitting Diodes， QLED)等。在一些实施例中，电子设备2100可以包括1个或N个显示屏2194，N为大于1的正整数。
电子设备2100可以通过ISP，摄像头2193，视频编解码器，GPU，显示屏2194以及应用处理器等实现获取功能。
ISP用于处理摄像头2193反馈的数据。例如，拍照时，打开快门，光线通过镜头被传递到摄像头感光元件上，光信号转换为电信号，摄像头感光元件将所述电信号传递给ISP处理，转化为肉眼可见的图像或视频。ISP还可以对图像的噪点，亮度，肤色进行算法优化。ISP还可以对拍摄场景的曝光，色温等参数优化。在一些实施例中，ISP可以设置在摄像头2193中。
摄像头2193用于捕获静态图像或视频。物体通过镜头生成光学图像投射到感光元件。感光元件可以是电荷耦合器件(Charge Coupled Device，CCD)或互补金属氧化物半导体(Complementary Metal-Oxide-Semiconductor，CMOS)光电晶体管。感光元件把光信号转换成电信号，之后将电信号传递给ISP转换成数字图像或视频信号。ISP将数字图像或视频信号输出到DSP加工处理。DSP将数字图像或视频信号转换成标准的RGB，YUV等格式的图像或视频信号。在一些实施例中，电子设备2100可以包括1个或N个摄像头2193，N为大于1的正整数。例如，在一些实施例中，电子设备2100可以利用N个摄像头2193获取多个曝光系数的图像，进而，在视频后处理中，电子设备2100可以根据多个曝光系数的图像，通过HDR技术合成HDR图像。
数字信号处理器用于处理数字信号，除了可以处理数字图像或视频信号，还可以处理其他数字信号。例如，当电子设备2100在频点选择时，数字信号处理器用于对频点能量进行傅里叶变换等。
视频编解码器用于对数字视频压缩或解压缩。电子设备2100可以支持一种或多种视频编解码器。这样，电子设备2100可以播放或录制多种编码格式的视频，例如：动态图像专家组(Moving Picture Experts Group，MPEG)1，MPEG2，MPEG3，MPEG4等。
NPU为神经网络(Neural-Network，NN)计算处理器，通过借鉴生物神经网络结构，例如借鉴人脑神经元之间传递模式，对输入信息快速处理，还可以不断的自学习。通过NPU可以实现电子设备2100的智能认知等应用，例如：图像识别，人脸识别，语音识别，文本理解等。
外部存储器接口2120可以用于连接外部存储卡，例如Micro SD卡，实现扩展电子设备2100的存储能力。外部存储卡通过外部存储器接口2120与处理器2110通信，实现数据存储功能。例如将音乐，视频等文件保存在外部存储卡中。
内部存储器2121可以用于存储计算机可执行程序代码，所述可执行程序代码包括指令。处理器2110通过运行存储在内部存储器2121的指令，从而执行电子设备2100的各种功能应用以及数据处理。内部存储器2121可以包括存储程序区和存储数据区。其中，存储程序区可存储操作系统，至少一个功能所需的应用程序(比如声音播放功能，图像视频播放功能等)等。存储数据区可存储电子设备2100使用过程中所创建的数据(比如音频数据，电话本等)等。此外，内部存储器2121可以包括高速随机存取存储器，还可以包括非易失性存储器，例如至少一个磁盘存储器件，闪存器件，通用闪存存储器(Universal Flash Storage， UFS)等。
电子设备2100可以通过音频模块2170，扬声器2170A，受话器2170B，麦克风2170C，耳机接口2170D，以及应用处理器等实现音频功能。例如音乐播放，录音等。
音频模块2170用于将数字音频信息转换成模拟音频信号输出，也用于将模拟音频输入转换为数字音频信号。音频模块2170还可以用于对音频信号编码和解码。在一些实施例中，音频模块2170可以设置于处理器2110中，或将音频模块2170的部分功能模块设置于处理器2110中。
扬声器2170A，也称“喇叭”，用于将音频电信号转换为声音信号。电子设备2100可以通过扬声器2170A收听音乐，或收听免提通话。
受话器2170B，也称“听筒”，用于将音频电信号转换成声音信号。当电子设备2100接听电话或语音信息时，可以通过将受话器2170B靠近人耳接听语音。
麦克风2170C，也称“话筒”，“传声器”，用于将声音信号转换为电信号。当拨打电话或发送语音信息时，用户可以通过人嘴靠近麦克风2170C发声，将声音信号输入到麦克风2170C。电子设备2100可以设置至少一个麦克风2170C。在另一些实施例中，电子设备2100可以设置两个麦克风2170C，除了获取声音信号，还可以实现降噪功能。在另一些实施例中，电子设备2100还可以设置三个，四个或更多麦克风2170C，实现获取声音信号，降噪，还可以识别声音来源，实现定向录音功能等。
耳机接口2170D用于连接有线耳机。耳机接口2170D可以是USB接口2130，也可以是3。5mm的开放移动电子设备平台(Open Mobile Terminal Platform，OMTP)标准接口，美国蜂窝电信工业协会(Cellular Telecommunications Industry Association of the USA，CTIA)标准接口。
传感器模块2180可以包括1个或多个传感器，这些传感器可以为相同类型或不同类型。可理解，图1所示的传感器模块2180仅为一种示例性的划分方式，还可能有其他划分方式，本申请对此不作限制。
压力传感器2180A用于感受压力信号，可以将压力信号转换成电信号。在一些实施例中，压力传感器2180A可以设置于显示屏2194。压力传感器2180A的种类很多，如电阻式压力传感器，电感式压力传感器，电容式压力传感器等。电容式压力传感器可以是包括至少两个具有导电材料的平行板。当有力作用于压力传感器2180A，电极之间的电容改变。电子设备2100根据电容的变化确定压力的强度。当有触摸操作作用于显示屏2194，电子设备2100根据压力传感器2180A检测所述触摸操作强度。电子设备2100也可以根据压力传感器2180A的检测信号计算触摸的位置。
在一些实施例中，作用于相同触摸位置，但不同触摸操作强度的触摸操作，可以对应不同的操作指令。例如：当有触摸操作强度小于第一压力阈值的触摸操作用于短消息应用图标时，执行查看短消息的指令。当有触摸操作强度大于或等于第一压力阈值的触摸操作作用于短消息应用图标时，执行新建短消息的指令。
陀螺仪传感器2180B可以用于确定电子设备2100的运动姿态。在一些实施例中，可以通过陀螺仪传感器2180B确定电子设备2100围绕三个轴(即，x，y和z轴)的角速度。陀螺仪传感器2180B可以用于拍摄防抖。示例性的，当按下快门，陀螺仪传感器2180B检 测电子设备2100抖动的角度，根据角度计算出镜头模组需要补偿的距离，让镜头通过反向运动抵消电子设备2100的抖动，实现防抖。陀螺仪传感器2180B还可以用于导航，体感游戏场景。
气压传感器2180C用于测量气压。在一些实施例中，电子设备2100通过气压传感器2180C测得的气压值计算海拔高度，辅助定位和导航。
磁传感器2180D包括霍尔传感器。电子设备2100可以利用磁传感器2180D检测翻盖皮套的开合。在一些实施例中，当电子设备2100是翻盖机时，电子设备2100可以根据磁传感器2180D检测翻盖的开合。进而根据检测到的皮套的开合状态或翻盖的开合状态，设置翻盖自动解锁等特性。
加速度传感器2180E可检测电子设备2100在各个方向上(一般为三轴)加速度的大小。当电子设备2100静止时可检测出重力的大小及方向。还可以用于识别电子设备2100姿态，应用于横竖屏切换，计步器等应用。
距离传感器2180F，用于测量距离。电子设备2100可以通过红外或激光测量距离。在一些实施例中，拍摄场景，电子设备2100可以利用距离传感器2180F测距以实现快速对焦。
接近光传感器2180G可以包括例如发光二极管(LED)和光检测器，例如光电二极管。发光二极管可以是红外发光二极管。电子设备2100通过发光二极管向外发射红外光。电子设备2100使用光电二极管检测来自附近物体的红外反射光。当检测到充分的反射光时，可以确定电子设备2100附近有物体。当检测到不充分的反射光时，电子设备2100可以确定电子设备2100附近没有物体。电子设备2100可以利用接近光传感器2180G检测用户手持电子设备2100贴近耳朵通话，以便自动熄灭屏幕达到省电的目的。接近光传感器2180G也可用于皮套模式，口袋模式自动解锁与锁屏。
环境光传感器2180L用于感知环境光亮度。电子设备2100可以根据感知的环境光亮度自适应调节显示屏2194亮度。环境光传感器2180L也可用于拍照时自动调节白平衡。环境光传感器2180L还可以与接近光传感器2180G配合，检测电子设备2100是否在口袋里，以防误触。
指纹传感器2180H用于获取指纹。电子设备2100可以利用获取的指纹特性实现指纹解锁，访问应用锁，指纹拍照，指纹接听来电等。
温度传感器2180J用于检测温度。在一些实施例中，电子设备2100利用温度传感器2180J检测的温度，执行温度处理策略。例如，当温度传感器2180J上报的温度超过阈值，电子设备2100执行降低位于温度传感器2180J附近的处理器的性能，以便降低功耗实施热保护。在另一些实施例中，当温度低于另一阈值时，电子设备2100对电池2142加热，以避免低温导致电子设备2100异常关机。在其他一些实施例中，当温度低于又一阈值时，电子设备2100对电池2142的输出电压执行升压，以避免低温导致的异常关机。
触摸传感器2180K，也称“触控面板”。触摸传感器2180K可以设置于显示屏2194，由触摸传感器2180K与显示屏2194组成触摸屏，也称“触控屏”。触摸传感器2180K用于检测作用于其上或附近的触摸操作。触摸传感器可以将检测到的触摸操作传递给应用处理器，以确定触摸事件类型。可以通过显示屏2194提供与触摸操作相关的视觉输出。在另一些实施例中，触摸传感器2180K也可以设置于电子设备2100的表面，与显示屏2194所处 的位置不同。
在本申请的一个实施例中，用户利用电子设备2100进行延时摄影或连拍，需要获取一系列图像。在延时摄像或连拍的场景中，电子设备2100可以采取AE模式。即电子设备2100自动调整AE值，在预览这一系列图像的过程中，若用户有触摸操作作用于显示屏2194，可能触发touchAE模式。在touchAE模式下，电子设备2100可以调整用户触摸显示屏的相应位置的亮度，并进行高权重测光。使得计算画面平均亮度的时候，用户触摸区域的权重明显高于其他区域，最终计算所得的画面平均亮度更加靠近用户触摸区域的平均亮度。
骨传导传感器2180M可以获取振动信号。在一些实施例中，骨传导传感器2180M可以获取人体声部振动骨块的振动信号。骨传导传感器2180M也可以接触人体脉搏，接收血压跳动信号。在一些实施例中，骨传导传感器2180M也可以设置于耳机中，结合成骨传导耳机。音频模块2170可以基于所述骨传导传感器2180M获取的声部振动骨块的振动信号，解析出语音信号，实现语音功能。应用处理器可以基于所述骨传导传感器2180M获取的血压跳动信号解析心率信息，实现心率检测功能。
按键2190包括开机键，音量键等。按键2190可以是机械按键。也可以是触摸式按键。电子设备2100可以接收按键输入，产生与电子设备2100的用户设置以及功能控制有关的键信号输入。
马达2191可以产生振动提示。马达2191可以用于来电振动提示，也可以用于触摸振动反馈。例如，作用于不同应用(例如拍照，音频播放等)的触摸操作，可以对应不同的振动反馈效果。作用于显示屏2194不同区域的触摸操作，马达2191也可对应不同的振动反馈效果。不同的应用场景(例如：时间提醒，接收信息，闹钟，游戏等)也可以对应不同的振动反馈效果。触摸振动反馈效果还可以支持自定义。
指示器2192可以是指示灯，可以用于指示充电状态，电量变化，也可以用于指示消息，未接来电，通知等。
SIM卡接口2195用于连接SIM卡。SIM卡可以通过插入SIM卡接口2195，或从SIM卡接口2195拔出，实现和电子设备2100的接触和分离。电子设备2100可以支持1个或N个SIM卡接口，N为大于1的正整数。SIM卡接口2195可以支持Nano SIM卡，Micro SIM卡，SIM卡等。同一个SIM卡接口2195可以同时插入多张卡。所述多张卡的类型可以相同，也可以不同。SIM卡接口2195也可以兼容不同类型的SIM卡。SIM卡接口2195也可以兼容外部存储卡。电子设备2100通过SIM卡和网络交互，实现通话以及数据通信等功能。在一些实施例中，电子设备2100采用eSIM，即：嵌入式SIM卡。eSIM卡可以嵌在电子设备2100中，不能和电子设备2100分离。
以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (12)

  1. 一种MIPI开关，其特征在于，所述MIPI开关包括：
    管脚模块；所述管脚模块包括第一管脚；
    子开关模块；所述子开关模块包括至少一个子开关；
    控制器，用于接收MIPI指令；所述MIPI指令包括控制指令；在确定所述MIPI指令用于控制所述MIPI开关的情况下，根据所述第一管脚的状态确定所述控制指令中的Y位指令；所述控制指令包括X位指令，所述Y小于或等于所述X；根据所述Y位指令切换所述至少一个子开关。
  2. 如权利要求1所述的MIPI开关，其特征在于，所述控制器包括：
    地址寄存器，所述地址寄存器中存储有第一MIPI地址；所述MIPI指令包括第二MIPI地址；
    解码器，用于解析MIPI指令，得到所述第二MIPI地址和所述控制指令；判断所述第一MIPI地址和所述第二MIPI地址是否一致；
    数据寄存器，用于存储所述控制指令；
    Mode识别模块，用于当所述第一MIPI地址与所述第二MIPI地址一致时，根据所述第一管脚的状态确定所述控制指令中的Y位指令。
  3. 如权利要求2所述的MIPI开关，其特征在于，所述第一管脚有N种状态；所述Mode识别模块，在用于根据所述第一管脚的状态确定所述控制指令中的Y位指令时，具体用于：
    基于第一控制逻辑，确定所述第一管脚的状态对应的所述控制指令中的Y位指令；所述第一控制逻辑包括所述N种状态与Y位指令的对应关系，其中不同的状态对应所述控制指令中不同的Y位指令。
  4. 如权利要求1-3任一项所述的MIPI开关，其特征在于，所述Y位指令中的K位指令为标志位指令；K为不小于1且不大于X的正整数；所述控制器，还包括：译码器，用于所述根据所述Y位指令切换所述至少一个子开关；所述译码器，在用于根据所述Y位指令切换所述至少一个子开关时，具体用于：
    若所述标志位指令表示为第一状态，所述译码器不响应所述Y位指令；
    若所述标志位指令表示为第二状态，所述译码器响应所述Y位指令。
  5. 如权利要求1-4任一项所述的MIPI开关，其特征在于，所述MIPI开关还包括通用输入与输出GPIO管脚，所述MIPI开关中的至少一个所述GPIO管脚与GPIO开关连接，其中不同的GPIO管脚与不同的GPIO开关连接；所述译码器，还用于：
    基于第二控制逻辑，确定所述GPIO管脚对应的所述控制指令中的Z位指令；所述第二控制逻辑包括所述GPIO管脚与Z位指令的对应关系，其中不同的GPIO管脚对应所述控制指令中不同的Z位指令；所述Z小于或等于所述X；
    根据所述Z位指令切换所述GPIO开关。
  6. 一种开关切换方法，其特征在于，应用于如权利要求1-5任一项所述的MIPI开关，所述方法包括：
    所述MIPI开关接收MIPI指令；所述MIPI开关包括第一管脚；所述MIPI指令包括控制指令；
    在确定所述MIPI指令用于控制所述MIPI开关的情况下，所述MIPI开关根据所述第一管脚的状态确定所述控制指令中的Y位指令；所述控制指令包括X位指令，所述Y小于或等于所述X；
    所述MIPI开关根据所述Y位指令进行切换。
  7. 如权利要求6所述的方法，其特征在于，所述MIPI开关对应第一MIPI地址；所述MIPI指令包括第二MIPI地址；所述在确定所述MIPI指令用于控制所述MIPI开关的情况下，所述MIPI开关根据所述第一管脚的状态确定所述控制指令中的Y位指令之前，所述方法还包括：
    所述MIPI开关解析MIPI指令，得到所述第二MIPI地址和所述控制指令；
    所述在确定所述MIPI指令用于控制所述MIPI开关的情况下，所述MIPI开关根据所述第一管脚的状态确定所述控制指令中的Y位指令，具体包括：
    所述MIPI开关判断所述第一MIPI地址和所述第二MIPI地址是否一致；
    若所述第一MIPI地址与所述第二MIPI地址一致，所述MIPI开关根据所述第一管脚的状态确定所述控制指令中的Y位指令。
  8. 如权利要求6或7所述的方法，其特征在于，所述第一管脚有N种状态；所述MIPI开关根据所述第一管脚的状态确定所述控制指令中的Y位指令，具体包括：
    所述MIPI开关基于第一控制逻辑，确定所述第一管脚的状态对应的所述控制指令中的Y位指令；所述第一控制逻辑包括所述N种状态与Y位指令的对应关系，其中不同的连接状态对应所述控制指令中不同的Y位指令。
  9. 如权利要求6-8任一项所述的方法，其特征在于，所述Y位指令中的K位指令为标志位指令；K为不小于1的正整数；所述MIPI开关根据所述Y位指令进行切换，具体包括：
    若所述标志位指令表示为第一状态，所述MIPI开关不响应所述Y位指令；
    若所述标志位指令表示为第二状态，所述MIPI开关响应所述Y位指令。
  10. 如权利要求6-9任一项所述的方法，其特征在于，所述MIPI开关还包括通用输入与输出GPIO管脚，所述MIPI开关中的至少一个所述GPIO管脚与GPIO开关连接，其中不同的GPIO管脚与不同的GPIO开关连接；所述方法还包括：
    所述MIPI开关基于第二控制逻辑，确定所述GPIO管脚对应的所述控制指令中的Z位指令；所述第二控制逻辑包括所述GPIO管脚与Z位指令的对应关系，其中不同的GPIO管脚对应所述控制指令中不同的Z位指令；所述Z小于或等于所述X；
    所述MIPI开关根据所述Z位指令切换所述GPIO开关。
  11. 一种电子设备，其特征在于，所述电子设备包括如权利要求1-5任一项所述的MIPI开关。
  12. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，该计算机程序被处理器执行时实现上述权利要求1-5任一项所述的方法。
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