WO2022252060A1

WO2022252060A1 - Power device, preparation method for power device, drive circuit, and integrated circuit board

Info

Publication number: WO2022252060A1
Application number: PCT/CN2021/097436
Authority: WO
Inventors: 唐高飞; 侯召政
Original assignee: 华为技术有限公司
Priority date: 2021-05-31
Filing date: 2021-05-31
Publication date: 2022-12-08
Also published as: CN115699301A

Abstract

A power device, a preparation method for a power device, a drive circuit, and an integrated circuit board, which are used for solving the problems of an increase in the on-resistance of a power device and a poor batch of on-resistance caused by oxidation of a top-layer pad, enabling the on-resistance of the power device to return to a normal value. The power device comprises a die, and a first top-layer pad, a first oxide layer, a first seed layer, and a first conductive bump which are sequentially stacked on the die, and further comprises a second top-layer pad, a second oxide layer, a second seed layer, and a second conductive bump which are sequentially stacked on the die, the first top-layer pad communicating with the second top-layer pad by means of the die.

Description

Power device, preparation method of power device, driving circuit and integrated circuit board

technical field

The present application relates to the field of chip technology, and in particular to a power device, a method for preparing the power device, a driving circuit and an integrated circuit board.

Background technique

With the development of the power electronics industry, the market share of power devices as core components is getting higher and higher. New packaging technologies such as embedded component packaging (ECP) and strip packaging (CLIP) have gradually been widely used in the field of power device packaging due to their small parasitic inductance. In this type of package, it is necessary to perform pad metallization on the chip to facilitate the layout and routing of subsequent packages.

As shown in FIG. 1 , during chip processing, the top-layer pad metal is generally made of metal aluminum (doped with a small amount of copper). When the top pad is made, the passivation layer will be opened, and a dense aluminum oxide film is easily formed after the top pad is exposed to the air. After attaching a seed layer (such as Ti/Cu, TiW/Cu, etc.) and copper plating on the top pad in Figure 1, the electrodes of the power device can be formed through interconnection, as shown in Figure 2.

After the electrodes are formed, the aluminum oxide film causes an increase in the contact resistance between the plated metal (copper) and the top pad, which in turn leads to an increase in the on-resistance of the power device. That is to say, the aluminum oxide film between the seed layer and the top pad will introduce additional package contact resistance, as shown in Figure 3, which is the equivalent circuit of the power device after the package contact resistance is introduced. The additional package contact resistance introduced will make the on-resistance of the power device significantly different from the normal value.

In order to solve the problem of oxidation on the surface of the top pad, in the prior art, the aluminum oxide film on the surface of the top pad is usually etched away by argon plasma etching in a vacuum chamber, and then a seed layer (seed layer) is formed. ) sputtering growth, and then form electrodes through interconnection after copper plating, as shown in Figure 4.

With the solution shown in Figure 4, it is difficult for the vacuum chamber to maintain a high degree of vacuum during operations such as etching and sputtering. Therefore, there will still be a large number of power devices with over-standard on-resistance, resulting in a large number of on-resistance bad batches.

Contents of the invention

The embodiment of the present application provides a power device, a preparation method of the power device, a driving circuit, and an integrated circuit board, which are used to solve the problem that the on-resistance of the power device becomes larger and the batch of on-resistance is poor due to the oxidation of the top pad. The problem makes the on-resistance of the power device return to the normal value.

In the first aspect, the embodiment of the present application provides a power device, the power device includes a die, and a first top-layer pad, a first oxide layer, a first seed layer, and a first conductive bump stacked sequentially on the die The block also includes a second top-layer pad, a second oxide layer, a second seed layer and a second conductive bump sequentially stacked on the die, and the first top-layer pad communicates with the second top-layer pad through the die.

Wherein, the first conductive bump can be used to form the drain of the power device, and the second conductive bump can be used to form the source of the power device.

By using the power device provided in the first aspect, the on-resistance value of the power device can meet the specification requirements without using other processes to etch off the oxide layer, which reduces the process steps and reduces the manufacturing cost of the power device compared with the prior art. cost.

In one possible design, the first oxide layer and the second oxide layer are broken down.

Among them, breakdown refers to that when the voltage applied to a certain insulating medium is higher than a certain level (breakdown voltage), the insulating medium will suddenly collapse and its resistance will drop rapidly, and then a part of the insulating medium will become for the conductor. Taking the first oxide layer as an example, when the voltage applied to the first oxide layer is higher than a certain level, the resistance of the first oxide layer will drop rapidly, so that the first oxide layer changes from an insulating medium to a conductor.

Using the above scheme, after the first oxide layer is broken down, the resistance of the first oxide layer decreases; after the second oxide layer is broken down, the resistance of the second oxide layer decreases, so the on-resistance of the power device decreases, Return to normal value and meet power device specifications. By adopting the solution, it is not necessary to etch the oxide layer by other processes, and compared with the prior art, the process steps are reduced, and the cost of manufacturing power devices is reduced.

In a possible design, in the case of applying a step-by-step first voltage between the first conductive bump and the second conductive bump, the ratio of the first voltage to the first current can reach the power device Within the calibration range of the on-resistance value, the first current is the current flowing between the first conductive bump and the second conductive bump.

Using the above solution, applying a gradually increasing first voltage between the first oxide layer and the second oxide layer can cause the first oxide layer and the second oxide layer to be broken down, thereby reducing the on-resistance of the power device , until it returns to the normal value and meets the specifications of the power device. In addition, stopping receiving the first voltage after the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device can make the on-resistance of each power device meet the specification without occurrence of In the prior art scheme shown in FIG. 4 , there is a problem of defective batches due to the difficulty in process control (the vacuum chamber is difficult to maintain a high degree of vacuum).

In a possible design, the power device provided in the first aspect may further include a third top-layer pad, a third oxide layer, a third seed layer, and a third conductive bump sequentially stacked on the die, and The fourth top-layer pad, the fourth oxide layer, the fourth seed layer and the fourth conductive bump are sequentially stacked on the bare chip, and the third top-layer pad communicates with the fourth top-layer pad through the bare chip.

Wherein, the third conductive bump or the fourth conductive bump can be used to form the gate of the power device.

With the above solution, the ratio of the voltage applied to the gate of the power device to the current flowing can meet the specification requirements without using other processes to etch the oxide layer. Compared with the existing technology, the process steps are reduced and the power device The cost of preparation.

In one possible design, the third and fourth oxide layers are broken down.

Using the above solution, after the third oxide layer and the fourth oxide layer are broken down, the equivalent resistance value decreases, which can reduce the ratio of the voltage applied to the gate of the power device to the current flowing until it meets the specifications of the power device Require.

In a possible design, when a second voltage that increases step by step is applied between the third conductive bump and the fourth conductive bump, the ratio of the second voltage to the second current can reach the power device The second current is the current flowing between the third conductive bump and the fourth conductive bump within the calibration range of the ratio of the voltage applied to the gate to the flowing current.

Using the above solution, a second voltage is applied between the third conductive bump and the fourth conductive bump, so that the third oxide layer and the fourth oxide layer break down, and then the ratio of the second voltage to the second current is reduced to Within the calibration range of the ratio of the voltage applied to the gate of the power device to the flowing current, the problem of poor electrical connection of the gate caused by the package contact resistance additionally introduced by the third oxide layer and the fourth oxide layer can be solved.

In a possible design, the first conductive bump and the second conductive bump are respectively coupled to two output terminals of a first voltage source or a current source, and the first voltage source or current source is used to output the first voltage.

In a possible design, the third conductive bump and the fourth conductive bump are respectively coupled to two output terminals of the second voltage source, and the second voltage source is used to output the second voltage.

In a second aspect, an embodiment of the present application provides a method for fabricating a power device. The power device includes a first electrode, a second electrode, and a first oxide layer and a second oxide layer between the first electrode and the second electrode. Specifically, the preparation method of the power device includes the following steps: applying a first voltage between the first electrode and the second electrode, so that the ratio of the first voltage to the first current reaches the calibration range of the on-resistance value of the power device , the first current is the current flowing between the first electrode and the second electrode.

Wherein, the ratio of the first voltage to the first current is the sum of the equivalent resistances of the first electrode, the second electrode, the first oxide layer and the second oxide layer.

Specifically, the on-resistance of the power device is the ratio of the voltage applied between the other two electrodes except the gate to the current flowing when the power device is in normal operation. For example, for a MOSFET, the on-resistance of the MOSFET is the ratio of the voltage applied between the drain and the source to the current flowing when the MOSFET is operating normally.

Wherein, if the power device is a MOSFET or a GaN transistor, the first electrode is the drain and the second electrode is the source; if the power device is a BJT, the first electrode is the collector and the second electrode is the emitter. That is to say, the first electrode and the second electrode are two electrodes through which current flows when the power device is turned on, rather than control electrodes for controlling the power device to be turned on and off.

Further, after the application of the first voltage is stopped, the equivalent resistance of the first oxide layer is smaller than that of the first oxide layer before the application of the first voltage, and the equivalent resistance of the second oxide layer is smaller than that of the second oxide layer before the application of the first voltage. The equivalent resistance of the oxide layer.

By adopting the preparation method of the power device provided in the second aspect, by applying the first voltage between the first electrode and the second electrode, the first oxide layer and the second oxide layer are broken down, thereby reducing the on-resistance of the power device. small until it returns to the normal value and meets the specifications of the power device. By adopting the preparation method, the oxide layer does not need to be etched away by other processes, and compared with the prior art, the process steps are reduced, and the cost of power device preparation is reduced. In addition, after the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device, stopping the application of the first voltage can make the on-resistance of each power device meet the specification, and will not In the prior art solution shown in FIG. 4 , there is a problem of defective batches due to the difficulty in process control (the vacuum chamber is difficult to maintain a high degree of vacuum).

In addition, the power device may further include a first gate, a second gate, and a third oxide layer and a fourth oxide layer located between the first gate and the second gate. Correspondingly, the manufacturing method of the power device may further include: applying a second voltage between the first gate and the second gate, so that the ratio of the second voltage to the second current reaches the voltage applied to the gate of the power device and within the calibrated range of the ratio of the flowing currents. Wherein, the second current is the current flowing between the first grid and the second grid.

Wherein, the ratio of the second voltage to the second current is the sum of the equivalent resistances of the first gate, the second gate, the third oxide layer and the fourth oxide layer.

Using the above scheme, a second voltage is applied between the first gate and the second gate, so that the third oxide layer and the fourth oxide layer break down, thereby reducing the ratio of the second voltage to the second current to the power device Within the calibrated range of the ratio of the voltage applied to the gate to the flowing current, the problem of poor electrical connection of the gate caused by the package contact resistance additionally introduced by the third oxide layer and the fourth oxide layer can be solved.

Further, after the application of the second voltage is stopped, the equivalent resistance of the third oxide layer is smaller than the equivalent resistance of the third oxide layer before the application of the second voltage, and the equivalent resistance of the fourth oxide layer is smaller than that of the third oxide layer before the application of the second voltage. The equivalent resistance of the oxide layer.

In a possible design, the first voltage can be applied between the first electrode and the second electrode through a first voltage source or a current source.

In a possible design, a second voltage can be applied between the first gate and the second gate through a second voltage source.

In a possible design, the manufacturing method of the power device further includes: applying a control signal to the power device through the first gate or the second gate, so as to control the power device to be turned on and off.

With the above solution, the power device can be controlled to be turned on and off through the first gate or the second gate, and one of them can be used.

In a third aspect, an embodiment of the present application further provides a driving circuit, which includes a gate driver and the power device provided in the second aspect and any possible design thereof. Wherein, the third conductive bump and the fourth conductive bump of the power device are coupled to the signal output terminal of the gate driver.

In the fourth aspect, the embodiment of the present application also provides an integrated circuit board, which includes a circuit board body and the power device provided in the second aspect and any possible design thereof, or the third aspect and any possible design thereof The drive circuit provided in the design. Wherein, the integrated circuit board body has pins, and the power device or the driving circuit is connected to the circuit board body through the pins.

In addition, it should be understood that the technical effects brought about by the second aspect to the fourth aspect and any possible design methods thereof may refer to the technical effects brought about by different design methods in the first aspect, which will not be repeated here.

Description of drawings

Fig. 1 is a schematic structural diagram of a semiconductor chip provided by the prior art;

FIG. 2 is a schematic structural view of another semiconductor chip provided by the prior art;

Fig. 3 is an equivalent circuit diagram of a power device provided by the prior art after the package contact resistance is introduced;

Fig. 4 is a schematic flow chart of etching an aluminum oxide film provided by the prior art;

FIG. 5 is a schematic structural diagram of a first power device provided in an embodiment of the present application;

FIG. 6 is a schematic flowchart of a method for manufacturing a power device provided in an embodiment of the present application;

FIG. 7 is a schematic diagram of an Id-Vd curve provided in an embodiment of the present application;

FIG. 8 is a schematic diagram of a Vd-Id curve provided in an embodiment of the present application;

FIG. 9 is a schematic structural diagram of a second power device provided by an embodiment of the present application;

FIG. 10 is a schematic structural diagram of a third power device provided by an embodiment of the present application;

FIG. 11 is a schematic diagram of an Igg-Vgg curve provided in the embodiment of the present application;

FIG. 12 is a schematic diagram of applying a voltage between the drain and the source provided by the embodiment of the present application;

FIG. 13 is another schematic diagram of applying a voltage between the drain and the source provided by the embodiment of the present application;

FIG. 14 is a schematic diagram of applying a voltage between double gates according to an embodiment of the present application;

FIG. 15 is a schematic structural diagram of a fourth power device provided by an embodiment of the present application;

FIG. 16 is a schematic structural diagram of a driving circuit provided by an embodiment of the present application;

FIG. 17 is a schematic structural diagram of an integrated circuit board provided by an embodiment of the present application.

Detailed ways

The embodiments of the present application will be further described in detail below in conjunction with the accompanying drawings.

It should be noted that, in the embodiments of the present application, a plurality refers to two or more. In addition, in the description of the present application, words such as "first" and "second" are only used for the purpose of distinguishing descriptions, and cannot be understood as indicating or implying relative importance, nor can they be understood as indicating or implying order. The "coupling" mentioned in the embodiments of the present application refers to electrical connection, which may specifically include direct connection or indirect connection.

An embodiment of the present application provides a method for manufacturing a power device, and the power device includes a first electrode, a second electrode, and a first oxide layer and a second oxide layer located between the first electrode and the second electrode.

Wherein, the power device includes but not limited to metal-oxide-semiconductor field-effect transistor (MOSFET), gallium nitride (gallium nitride, GaN) transistor, insulated gate bipolar transistor (insulated gate bipolar transistor, IGBT), bipolar junction transistor (bipolar junction transistor, BJT), triode. If the power device is a MOSFET or a GaN transistor, the first electrode is the drain and the second electrode is the source; if the power device is a BJT, the first electrode is the collector and the second electrode is the emitter. That is to say, the first electrode and the second electrode are two electrodes through which current flows when the power device is turned on, rather than control electrodes for controlling the power device to be turned on and off.

It should be noted that, in the embodiment of the present application, a first oxide layer and a second oxide layer are included between the first electrode and the second electrode. That is to say, by using the embodiment of the present application, the on-resistance of the power device can meet the specifications of the power device without using other processes to etch away the oxide layer.

In practical applications, the first oxide layer and the second oxide layer may be aluminum oxide films. Of course, if the top pad is made of other metal materials when preparing the power device, the first oxide layer and the second oxide layer may also be thin films formed after oxidation of other metals.

Taking aluminum oxide films as an example for the first oxide layer and the second oxide layer, a possible structural schematic diagram of a power device may be shown in FIG. 5 . In the example of Figure 5, the first electrode and the second electrode of the power device are formed through interconnection after attaching a seed layer (such as Ti/Cu, TiW/Cu, etc.) and copper plating on the top pad, and the first electrode There is a layer of aluminum oxide film (first oxide layer) between the seed layer and the top pad of the second electrode, and there is a layer of aluminum oxide film (second oxide layer) between the seed layer and the top pad of the second electrode.

Specifically, referring to FIG. 6 , the manufacturing method of the power device includes the following steps.

S601: Apply a first voltage between the first electrode and the second electrode.

S602: Increase the first voltage, and measure the voltage value of the first voltage and the current value of the first current.

Wherein, the first current is the current flowing between the first electrode and the second electrode.

S603: Stop applying the first voltage when the ratio of the first voltage to the first current reaches the calibration range of the on-resistance value of the power device.

It can be seen from the structure shown in FIG. 5 that the ratio of the first voltage to the first current is the sum of the equivalent resistances of the first electrode, the second electrode, the first oxide layer and the second oxide layer.

In the embodiment of the present application, the on-resistance of the power device is the ratio of the voltage applied between the other two electrodes except the gate to the current flowing when the power device works normally. For example, for a MOSFET, the on-resistance of the MOSFET is the ratio of the voltage applied between the drain and the source to the current flowing when the MOSFET is operating normally. Still taking the MOSFET as an example, the on-resistance of the MOSFET determines the power consumed when the MOSFET is turned on. Usually, for a MOSFET of a certain specification and model, there are requirements for the calibration range of its on-resistance value when it leaves the factory. For example, the calibration range of the on-resistance value can be 25mΩ±5mΩ. When within, the power device is considered to meet the factory requirements. In the embodiment of the present application, during the preparation process of the power device, by continuously testing the ratio of the first voltage to the first current, when the ratio of the first voltage to the first current falls within the calibration range of the on-resistance value ( For example, when it is 25mΩ±5mΩ), it can be considered that the on-resistance value of the power device has met the factory requirement, and at this time, the application of the first voltage can be stopped.

Specifically, in S601, the first voltage may be applied between the first electrode and the second electrode through the first voltage source, or the first voltage may be applied between the first electrode and the second electrode through the current source.

In practical applications, when the first voltage is applied by the first voltage source, the output voltage of the first voltage source can be gradually increased, for example, gradually increased from 0V to 5V. Then, when the applied voltage is small, due to the existence of the first oxide layer and the second oxide layer, the conduction current (that is, the first current) of the power device is very small; The oxide layer breaks down under the action of the electric field. When the first oxide layer is destroyed, the resistance of the first oxide layer suddenly decreases. When the second oxide layer is destroyed, the resistance of the second oxide layer suddenly decreases. At this time, the current can normally flow through the first oxide layer and the second oxide layer, and the conduction current of the power device will have a jump and quickly return to the ideal level. Specifically, the relationship between the output voltage Vd (ie, the first voltage) of the first voltage source and the conduction current Id (ie, the first current) of the power device can be as shown in FIG. 7 . When the Id-Vd curve nearly coincides with the ideal Id-Vd curve, it can be considered that the on-current of the power device returns to the ideal level, that is, the on-resistance of the power device returns to the ideal level.

In the embodiment of the present application, breakdown refers to that when the voltage applied to a certain insulating medium is higher than a certain level (breakdown voltage), the insulating medium will suddenly collapse and its resistance will drop rapidly, and then make the Part of the insulating medium becomes a conductor. Taking the first oxide layer as an example, when the voltage applied to the first oxide layer is higher than a certain level, the resistance of the first oxide layer will drop rapidly, so that the first oxide layer changes from an insulating medium to a conductor.

In practical applications, when the first voltage is applied through the current source, the output current of the current source can gradually increase. Then, when the applied current is small, due to the existence of the first oxide layer and the second oxide layer, the potential difference between the first electrode and the second electrode is large; when the current continues to increase, the first oxide layer and the second The oxide layer breaks down under the action of the electric field. The moment the first oxide layer is destroyed, the resistance of the first oxide layer suddenly decreases, and the moment the second oxide layer is destroyed, the resistance of the second oxide layer suddenly decreases, resulting in The potential difference between the first electrode and the second electrode suddenly decreases and quickly returns to the ideal level. Specifically, the relationship between the potential difference Vd between the first electrode and the second electrode and the output current Id of the current source can be as shown in FIG. 8 . When the Vd-Id curve nearly coincides with the ideal Vd-Id curve, it can be considered that the on-resistance of the power device returns to the ideal level.

After the on-resistance of the power device returns to an ideal level (ie, the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance of the power device), the application of the first voltage may be stopped. For example, in the example of FIG. 7, when the Id-Vd curve nearly coincides with the Id-Vd curve under the ideal state, it can be considered that the ratio of the first voltage to the first current reaches the calibration range of the on-resistance value of the power device, Stop applying the first voltage at this moment; in the example of Fig. 8, when the Vd-Id curve and the Vd-Id curve under the ideal state nearly coincide, it can be considered that the ratio of the first voltage to the first current reaches the turn-on of the power device The calibration range of the resistance value, at this moment, stop applying the first voltage.

After stopping the application of the first voltage, the equivalent resistance of the first oxide layer is smaller than that of the first oxide layer before the application of the first voltage, and the equivalent resistance of the second oxide layer is smaller than that of the second oxide layer before the application of the first voltage. equivalent resistance. Although the first oxide layer and the second oxide layer still exist in the power device, the impact of the package contact resistance introduced by the first oxide layer and the second oxide layer on the on-resistance of the power device is almost negligible. The on-resistance returned to the normal value.

Using the preparation method of the power device shown in FIG. 6, by applying the first voltage between the first electrode and the second electrode, the first oxide layer and the second oxide layer are broken down, thereby reducing the on-resistance of the power device. small until it returns to the normal value and meets the specifications of the power device. By adopting the preparation method, the oxide layer does not need to be etched away by other processes, and compared with the prior art, the process steps are reduced, and the cost of power device preparation is reduced. In addition, after the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device, stopping the application of the first voltage can make the on-resistance of each power device meet the specification, and will not In the prior art solution shown in FIG. 4 , there is a problem of defective batches due to the difficulty in process control (the vacuum chamber is difficult to maintain a high degree of vacuum).

In addition, the control electrodes of power devices (eg, GATE) also introduce package contact resistance due to oxidation of the top pad metal. Since the gate of the power device cannot pass a large current, the power device can form a double-gate structure during chip design, and applying pressure between the two gates can also solve the problem of poor electrical connection caused by the contact resistance of the package. .

In the embodiment of the present application, the power device may further include a first gate, a second gate, and a third oxide layer and a fourth oxide layer located between the first gate and the second gate. The preparation method of the power device further includes: applying a second voltage between the first grid and the second grid, increasing the voltage value of the second voltage, and measuring the ratio of the second voltage to the second current; when the second voltage When the ratio to the second current reaches the calibration range of the ratio of the voltage applied to the gate of the power device to the current flowing, the application of the second voltage is stopped. Wherein, the second current is the current flowing between the first grid and the second grid.

It is not difficult to understand that the ratio of the second voltage to the second current is the sum of the equivalent resistances of the first gate, the second gate, the third oxide layer and the fourth oxide layer.

In practical applications, the third oxide layer and the fourth oxide layer may be aluminum oxide films. Of course, if the top pad is made of other metal materials when preparing the power device, the third oxide layer and the fourth oxide layer may also be thin films formed by oxidation of other metals.

Taking the third oxide layer and the fourth oxide layer as an example of aluminum oxide film, in the example of Figure 9, the package contact resistance introduced by oxidation is equivalent to a layer of aluminum oxide film, the first grid G1 and the second grid There are two layers of aluminum oxide films between G2, that is, the third oxide layer and the fourth oxide layer. In this example, a possible structural schematic diagram of a power device may be shown in FIG. 10 . In the example of FIG. 10, the first gate and the second gate of the power device are formed through interconnection after attaching a seed layer (such as Ti/Cu, TiW/Cu, etc.) and copper plating on the top pad. There is a layer of aluminum oxide film (third oxide layer) between the seed layer of the first grid and the top pad, and there is a layer of aluminum oxide film (fourth oxide layer) between the seed layer of the second grid and the top pad .

It should be noted that, in the example of FIG. 10 , for simplicity of illustration, the first electrode and the second electrode in the power device are not shown, and the structure of the first electrode and the second electrode can refer to the example in FIG. 5 , here I won't repeat them here.

Similar to the calibration range of the on-resistance value of the power device mentioned above, when the power device leaves the factory, there is also a calibration range for the ratio of the voltage applied to the gate to the current flowing. Only when the ratio of the voltage applied to the gate to the current flowing is within the calibration range When it is within the range, the power device is considered to meet the factory requirements. In the embodiment of the present application, during the preparation process of the power device, the ratio of the second voltage to the second current is continuously tested. When the ratio is within the calibration range, it can be considered that the on-resistance value of the power device has met the factory requirements, and at this time, the application of the second voltage can be stopped.

Specifically, a second voltage may be applied between the first gate and the second gate by a second voltage source. When the second voltage is applied by the second voltage source, the output voltage of the second voltage source can gradually increase. Then, when the applied voltage is small, due to the existence of the third oxide layer and the fourth oxide layer, the current Igg flowing between the first gate and the second gate is very small; The first layer and the fourth oxide layer break down under the action of the electric field, the current can flow through the third oxide layer and the fourth oxide layer normally, Igg will have a jump, and quickly return to the ideal level. Specifically, the relationship between the output voltage Vgg (that is, the second voltage) of the second voltage source and Igg (that is, the second current) can be as shown in FIG. 11 . When the Igg-Vgg curve nearly coincides with the ideal Igg-Vgg curve, it can be considered that the ratio of the second voltage to the second current reaches the calibration range of the ratio of the voltage applied to the gate of the power device to the current flowing.

After the ratio of the second voltage to the second current decreases to within a calibrated range of the ratio of the voltage applied to the gate of the power device to the current flowing, the application of the second voltage may be stopped. For example, in the example of FIG. 11 , when the Igg-Vgg curve nearly coincides with the ideal Igg-Vgg curve, the application of the second voltage may be stopped.

After stopping the application of the second voltage, the equivalent resistance of the third oxide layer is less than that of the third oxide layer before applying the second voltage, and the equivalent resistance of the fourth oxide layer is less than that of the fourth oxide layer before applying the second voltage. equivalent resistance. Although the third oxide layer and the fourth oxide layer still exist in the power device, the problem of poor electrical connection of the gate caused by the package contact resistance additionally introduced by the third oxide layer and the fourth oxide layer is almost negligible.

It should be understood that the above-mentioned solution of applying the second voltage between the first grid and the second grid to solve the problem of poor electrical connection of the grid is the same as the above-mentioned solution of applying the first voltage between the first electrode and the second electrode to solve the problem of poor electrical connection of the grid. The solution to the problem of poor electrical connection between the first electrode and the second electrode is not strictly limited in execution sequence.

In addition, after performing the above preparation method, the on-resistance value of the power device can meet the factory requirements. During the use of the power device after leaving the factory, a control signal can be applied to the power device through the first gate or the second gate, so as to control the power device to be turned on and off. That is to say, after leaving the factory, both the first gate and the second gate can be used as the gate of the power device to control the turn-on and turn-off of the power device, and one can be used in practical applications.

It should be noted that, when S601 is executed, a control signal needs to be applied to the gate of the power device to control the power device to be turned on. In practical applications, the control signal can be applied to the first gate, or the control signal can be applied to the second gate.

In summary, using the method for fabricating a power device provided in the embodiment of the present application, by applying the first voltage between the first electrode and the second electrode, the first oxide layer and the second oxide layer are broken down, thereby making the power device The on-resistance decreases until it returns to a normal value, meeting the specifications of the power device. By adopting the preparation method, the oxide layer does not need to be etched away by other processes, and the process steps are reduced compared with the prior art. After the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device, stop applying the first voltage, so that the on-resistance of each power device meets the specification, and no phenomenon occurs. There is a problem of bad batches that appear in the technical solution.

In addition, a second voltage is applied between the first gate and the second gate, so that the third oxide layer and the fourth oxide layer break down, thereby reducing the ratio of the second voltage to the second current to the gate of the power device. Within the calibrated range of the ratio of the applied voltage to the flowing current, the poor electrical connection problem of the gate caused by the package contact resistance additionally introduced by the third oxide layer and the fourth oxide layer can be solved.

Next, taking the power device shown in FIG. 9 as an example, the preparation scheme of the power device provided by the embodiment of the present application will be introduced in detail.

Step 1: Test the output characteristics of the device under a high-current testing machine (or a test board that can provide high current). The specific process is to apply a positive voltage to Vgs to turn on the power device, and apply a voltage between D and S.

Specifically, the high-current testing machine can be equivalent to a current source, as shown in FIG. 12 ; the high-current testing machine can also be equivalent to a voltage source, as shown in FIG. 13 .

At first, due to the existence of the oxide layer between D and S, the conduction current of the power device is very small; when the pressure is continued, the oxide layer between D and S starts to break through under the action of the electric field, and the current can pass through normally. Over oxide layer, the current of the power device will return to the level of the ideal device. At this point, stop applying voltage between D and S.

Step 2: Apply a voltage across G1 and G2, as shown in Figure 14. At first, due to the existence of the oxide layer between G1 and G2, the current flowing through G1 is very small; when the pressurization continues, the oxide layer between G1 and G2 begins to penetrate under the action of the electric field, and the current can pass through normally oxide layer, the current flowing through G1 returns to the level of the ideal device. At this point, stop applying voltage between G1 and G2.

It should be noted that there is no strict restriction on the order of execution of the above steps 1 and 2. Step 1 may be executed first, and then step 2 may be executed, or step 2 may be executed first, and then step 1 may be executed.

The embodiment of the present application also provides a power device. As shown in FIG. 15 , the power device 1500 includes a bare chip 1501, and a first top-layer pad 1502a, a first oxide layer 1502b, a first The seed layer 1502c and the first conductive bump 1502d also include the second top layer pad 1503a, the second oxide layer 1503b, the second seed layer 1503c and the second conductive bump 1503d stacked on the die 1501 in order, the first The top pad 1502a communicates with the second top pad 1503a through the die 1501 .

Wherein, the first conductive bump 1502d can be used to form the drain of the power device 1500 , and the second conductive bump 1503d can be used to form the source of the power device 1500 .

Optionally, the first oxide layer 1502b and the second oxide layer 1503b are broken down.

After the first oxide layer 1502b is broken down, the equivalent resistance value decreases; after the second oxide layer 1503b is broken down, the equivalent resistance value decreases, so that the equivalent resistance value of the power device 1500 can be reduced to the power device The on-resistance value of 1500 is within the calibration range.

Since the first top pad 1502a communicates with the second top pad 1503a through the bare chip 1501, when the first voltage is applied between the first conductive bump 1502d and the second conductive bump 1503d, it is not difficult to understand that the first The current flow path is first conductive bump 1502d→first seed layer 1502c→first oxide layer 1502b→first top pad 1502a→bare chip 1501→second top pad 1503a→second oxide layer 1503b→the first The second sublayer 1503c→the second conductive bump 1503d. Since the on-resistance of the first seed layer 1502c, the first top layer pad 1502a, the second top layer pad 1503a, and the second seed layer 1503c is small, it can be considered that the ratio of the first voltage to the first current is approximately equal to the first conductive The sum of the equivalent resistances of the bump 1502d, the second conductive bump 1503d, the first oxide layer 1502b, and the second oxide layer 1503b.

The power device 1500 includes but not limited to MOSFET, GaN transistor, IGBT, BJT, triode. If the power device 1500 is a MOSFET or a GaN transistor, the first conductive bump 1502d is the drain, and the second conductive bump 1503d is the source; if the power device 1500 is a BJT, the first conductive bump 1502d is the collector, and the second conductive bump 1503d is the source. The two conductive bumps 1503d are emitters. That is to say, the first conductive bump 1502d and the second conductive bump 1503d are two electrodes through which current flows when the power device 1500 is turned on, rather than control electrodes for controlling the power device 1500 to be turned on and off ( such as gates).

Optionally, in the case where a gradually increasing first voltage is applied between the first conductive bump 1502d and the second conductive bump 1503d, the ratio of the first voltage to the first current can reach the conductance of the power device 1500. within the calibrated range of on-resistance values. Wherein, the first current is the current flowing between the first conductive bump 1502d and the second conductive bump 1503d.

The first voltage applied between the first conductive bump 1502d and the second conductive bump 1503d can cause the breakdown of the first oxide layer 1502b and the second oxide layer 1503b, thereby reducing the on-resistance of the power device 1500, Until it returns to the normal value and meets the specifications of the power device 1500 . After the ratio of the first voltage to the first current decreases to within the calibrated range of the on-resistance value of the power device 1500, the application of the first voltage can be stopped, so that the on-resistance of the power device 1500 can meet the specifications, and no phenomenon will occur. There is a problem of bad batches that appear in the technical solution.

In addition, the power device 1500 may also include a third top-layer pad, a third oxide layer, a third seed layer, and a third conductive bump sequentially stacked on the die 1501, and a first stacked sequentially on the die. Four top-layer pads, a fourth oxide layer, a fourth seed layer, and a fourth conductive bump, and the third top-layer pad communicates with the fourth top-layer pad through the die 1501 .

Wherein, the third conductive bump or the fourth conductive bump can be used to form the gate of the power device 1500 .

Optionally, the third oxide layer and the fourth oxide layer are broken down.

After the third oxide layer and the fourth oxide layer are broken down, the equivalent resistance decreases, which can reduce the ratio of the voltage applied to the gate of the power device 1500 to the current flowing until the specifications of the power device 1500 are met.

Optionally, under the condition that a gradually increasing second voltage is applied between the third conductive bump and the fourth conductive bump, the ratio of the second voltage to the second current can reach the desired value of the gate of the power device 1500 . Within the calibrated range of the ratio of applied voltage to flowing current. Wherein, the second current is the current flowing between the third conductive bump and the fourth conductive bump.

Since the third top-layer pad is connected to the fourth top-layer pad through the bare chip 1501, when the second voltage is applied between the third conductive bump and the fourth conductive bump, it is not difficult to understand that the flow of the second current The path is the third conductive bump→third seed layer→third oxide layer→third top pad→bare chip 1501→fourth top pad→fourth oxide layer→fourth seed layer→fourth conductive bump. Since the on-resistance of the third seed layer, the third top layer pad, the fourth top layer pad, and the fourth seed layer is small, it can be considered that the ratio of the second voltage to the second current is approximately equal to the third conductive bump, the second conductive bump, and the fourth seed layer. The sum of the equivalent resistances of the four conductive bumps, the third oxide layer, and the fourth oxide layer.

Applying a second voltage between the third conductive bump and the fourth conductive bump causes breakdown of the third oxide layer and the fourth oxide layer, thereby reducing the ratio of the second voltage to the second current to that of the power device 1500 Within the calibrated range of the ratio of the voltage applied to the gate to the flowing current, the problem of poor electrical connection of the gate caused by the package contact resistance additionally introduced by the third oxide layer and the fourth oxide layer can be solved.

In practical applications, the first conductive bump 1502d and the second conductive bump 1503d may be coupled to two output terminals of a first voltage source or a current source respectively, the first voltage source or current source is used to output the first voltage, and When the ratio of the second voltage to the second current decreases to within the calibrated range of the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through it, the output of the first voltage is stopped. Exemplarily, the first conductive bump 1502d and the second conductive bump 1503d are respectively coupled to the two output terminals of the first voltage source as shown in FIG. 13 (wherein D corresponds to the first conductive bump 1502d, S Corresponding to the second conductive bump 1503d), the first conductive bump 1502d and the second conductive bump 1503d are respectively coupled with the two output terminals of the current source as shown in Figure 12 (wherein D is equivalent to the first conductive bump The block 1502d, S corresponds to the second conductive bump 1503d).

In practical applications, the third conductive bump and the fourth conductive bump are respectively coupled to two output terminals of the second voltage source, and the second voltage source is used to output the second voltage, and the ratio of the second voltage to the second current is Stop outputting the second voltage when the ratio of the voltage applied to the gate of the power device 1500 to the current flowing is within the calibrated range. Exemplarily, the manner in which the third conductive bump and the fourth conductive bump are respectively coupled to the two output terminals of the second voltage source can be shown in FIG. 14 (wherein G1 is equivalent to the third conductive bump, and G2 is equivalent to the second Four conductive bumps).

In addition, the third conductive bump and the fourth conductive bump can also be used to apply a control signal to control the power device 1500 to be turned on and off.

It should be noted that, for implementations and technical effects not described in detail in the power device 1500 , reference may be made to the related description in the method for manufacturing the power device shown in FIG. 6 , which will not be repeated here.

The embodiment of the present application also provides a driving circuit. As shown in FIG. 16 , the driving circuit 1600 includes a gate driver 1601 and the aforementioned power device 1500 . Wherein, the third conductive bump and the fourth conductive bump of the power device 1500 are coupled to the signal output terminal of the gate driver 1601 .

In addition, the embodiment of the present application also provides an integrated circuit board. As shown in FIG. The circuit board body 1701 and the power device 1500 are taken as an example for illustration. Wherein, the circuit board body 1701 has pins, and the power device 1500 is electrically connected to the circuit board body 1701 through the pins.

It should be noted that, in FIG. 17 , the shape of the pins is only a specific example. In practical applications, the pins of the circuit board body 1701 may be point-shaped, sheet-shaped or planar-shaped. In the embodiment of the present application, the specific shape of the pins of the circuit board body 1701 is not limited.

Apparently, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the scope of the embodiments of the present application. In this way, if the modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and equivalent technologies, the present application also intends to include these modifications and variations.

Claims

A power device, characterized in that it includes a bare chip, and a first top layer pad, a first oxide layer, a first seed layer and a first conductive bump stacked sequentially on the bare chip, and also includes a The second top-layer pad, the second oxide layer, the second seed layer and the second conductive bump are stacked in sequence on the die, and the first top-layer pad passes through the die and the second top-layer pad connected.
The power device of claim 1, wherein the first oxide layer and the second oxide layer are broken down.
The power device according to claim 1 or 2, characterized in that, when a first voltage increasing step by step is applied between the first conductive bump and the second conductive bump, the The ratio of the first voltage to the first current reaches within the calibration range of the on-resistance value of the power device, and the first current flows between the first conductive bump and the second conductive bump. current.
The power device according to any one of claims 1 to 3, wherein the first conductive bump is used to form the drain of the power device, and the second conductive bump is used to form the power source of the device.
The power device according to any one of claims 1 to 4, further comprising a third top-layer pad, a third oxide layer, a third seed layer and a third conductive layer sequentially stacked on the die. bump, and a fourth top-layer pad, a fourth oxide layer, a fourth seed layer, and a fourth conductive bump stacked sequentially on the die, the third top-layer pad passes through the die and the connected to the fourth top layer pad.
The power device according to claim 5, wherein the third oxide layer and the fourth oxide layer are broken down.
The power device according to claim 5 or 6, characterized in that, when a second voltage increasing step by step is applied between the third conductive bump and the fourth conductive bump, the The ratio of the second voltage to the second current reaches the calibration range of the ratio of the voltage applied to the gate of the power device to the current flowing, and the second current is the third conductive bump and the fourth conductive bump. The current flowing between the bumps.
The power device according to claim 7, wherein the third conductive bump or the fourth conductive bump is used to form a gate of the power device.
The power device according to any one of claims 1-8, wherein the first conductive bump and the second conductive bump are respectively coupled to two output terminals of a first voltage source or a current source, The first voltage source or current source is used to output the first voltage.
The power device according to any one of claims 5-9, wherein the third conductive bump and the fourth conductive bump are respectively coupled to two output terminals of the second voltage source, and the first Two voltage sources are used to output the second voltage.
A method for manufacturing a power device, characterized in that the power device includes a first electrode, a second electrode, and a first oxide layer and a second oxide layer located between the first electrode and the second electrode, The methods include:

A first voltage is applied between the first electrode and the second electrode, so that the ratio of the first voltage to the first current reaches within the calibration range of the on-resistance value of the power device, and the first The current is the current flowing between the first electrode and the second electrode.
The method according to claim 11, wherein the ratio of the first voltage to the first current is the ratio of the first electrode, the second electrode, the first oxide layer and the second The sum of the equivalent resistance of the oxide layer.
The method according to claim 11 or 12, wherein the power device further comprises a first gate, a second gate, and a third gate located between the first gate and the second gate an oxide layer and a fourth oxide layer, the method further comprising:

Applying a second voltage between the first gate and the second gate, so that the ratio of the second voltage to the second current reaches the ratio of the voltage applied to the gate of the power device to the current flowing through it. Within the calibration range of , the second current is the current flowing between the first grid and the second grid.
The method according to claim 13, wherein the ratio of the second voltage to the second current is the ratio of the first gate, the second gate, the third oxide layer and the The sum of the equivalent resistances of the fourth oxide layer.
The method according to any one of claims 11-14, wherein applying a first voltage between the first electrode and the second electrode comprises:

The first voltage is applied between the first electrode and the second electrode by a first voltage source or a current source.
The method according to any one of claims 13-15, wherein applying a second voltage between the first gate and the second gate comprises:

The second voltage is applied between the first gate and the second gate by a second voltage source.
The method according to any one of claims 11-16, wherein the first electrode is a drain, and the second electrode is a source.
The method according to any one of claims 13-17, further comprising:

A control signal is applied to the power device through the first gate or the second gate to control the power device to be turned on and off.
A drive circuit, characterized by comprising a gate driver and the power device according to any one of claims 1 to 10; wherein the third conductive bump and the fourth conductive bump of the power device block coupled to the signal output of the gate driver.
An integrated circuit board, characterized in that it includes a circuit board body and the power device according to any one of claims 1 to 10, or includes the drive circuit according to claim 19; wherein the circuit board body has Pins, the power device and the circuit board body are electrically connected through the pins.