CN115699301A - Power device, preparation method of power device, driving circuit and integrated circuit board - Google Patents
Power device, preparation method of power device, driving circuit and integrated circuit board Download PDFInfo
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- CN115699301A CN115699301A CN202180009730.6A CN202180009730A CN115699301A CN 115699301 A CN115699301 A CN 115699301A CN 202180009730 A CN202180009730 A CN 202180009730A CN 115699301 A CN115699301 A CN 115699301A
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- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 14
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES OR LIGHT-SENSITIVE DEVICES, OF THE ELECTROLYTIC TYPE
- H01G9/00—Electrolytic capacitors, rectifiers, detectors, switching devices, light-sensitive or temperature-sensitive devices; Processes of their manufacture
- H01G9/004—Details
- H01G9/08—Housing; Encapsulation
- H01G9/10—Sealing, e.g. of lead-in wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/62—Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
- H01R4/00—Electrically-conductive connections between two or more conductive members in direct contact, i.e. touching one another; Means for effecting or maintaining such contact; Electrically-conductive connections having two or more spaced connecting locations for conductors and using contact members penetrating insulation
- H01R4/02—Soldered or welded connections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
Abstract
A power device, a preparation method of the power device, a driving circuit and an integrated circuit board are used for solving the problems that the on-resistance of the power device is increased and the batch of the on-resistance is poor due to the oxidation of a top bonding pad, so that the on-resistance of the power device returns to a normal value. The power device comprises a bare chip, a first top layer bonding pad, a first oxidation layer, a first seed layer and a first conductive bump which are sequentially stacked on the bare chip, and a second top layer bonding pad, a second oxidation layer, a second seed layer and a second conductive bump which are sequentially stacked on the bare chip, wherein the first top layer bonding pad is communicated with the second top layer bonding pad through the bare chip.
Description
The present disclosure relates to the field of chip technologies, and in particular, to a power device, a method for manufacturing the power device, a driving circuit, and an integrated circuit board.
With the development of the power electronics industry, the market share of power devices as core elements is higher and higher. Due to the characteristic of small parasitic inductance, novel packaging technologies such as Embedded Component Packaging (ECP) and strip packaging (CLIP) are gradually widely applied in the field of power device packaging. In such a package, a pad metallization operation is required for the chip to facilitate layout and routing of the subsequent package.
As shown in fig. 1, during the chip processing, the top pad metal is generally made of a metal aluminum (doped with a small amount of copper). When the top bonding pad is manufactured, the passivation layer is opened, and a compact aluminum oxide film is easily formed on the top bonding pad after the top bonding pad is exposed in the air. The electrodes of the power device can be formed by interconnecting after performing an adhesion seed layer (such as Ti/Cu, tiW/Cu, etc.) and a copper plating operation on the top pad in fig. 1, as shown in fig. 2.
After the electrodes are formed, the aluminum oxide film may cause an increase in contact resistance between the plating metal (copper) and the top pad, which in turn may cause an increase in on-resistance of the power device. That is, the presence of the aluminum oxide film between the seed layer and the top pad introduces an additional package contact resistance, as shown in fig. 3, which is an equivalent circuit of the power device after the introduction of the package contact resistance. The additionally introduced package contact resistance may cause the on-resistance of the power device to be very different from the normal value.
In order to solve the problem of surface oxidation of the top pad, in the prior art, an aluminum oxide film on the surface of the top pad is usually etched away in a vacuum chamber by using an argon plasma etching method, then a seed layer (seed layer) is sputtered to grow, and then an electrode is formed by interconnection after copper plating, as shown in fig. 4.
With the scheme shown in fig. 4, when performing operations such as etching and sputtering, it is difficult to maintain a high vacuum degree in the vacuum chamber, so that a large number of power devices with on-resistance exceeding the specification still exist, which brings about a problem of bad batch of on-resistance.
Disclosure of Invention
The embodiment of the application provides a power device, a preparation method of the power device, a driving circuit and an integrated circuit board, and aims to solve the problems that the on-resistance of the power device is increased and the batch of the on-resistance is poor due to the oxidation of a top pad, so that the on-resistance of the power device returns to a normal value.
In a first aspect, an embodiment of the present application provides a power device, which includes a die, and a first top layer pad, a first oxide layer, a first seed layer, and a first conductive bump that are sequentially stacked on the die, and further includes a second top layer pad, a second oxide layer, a second seed layer, and a second conductive bump that are sequentially stacked on the die, where the first top layer pad is communicated with the second top layer pad through the die.
The first conductive bump can be used for forming a drain electrode of the power device, and the second conductive bump can be used for forming a source electrode of the power device.
By adopting the power device provided by the first aspect, the on-resistance value of the power device can meet the specification requirement without adopting other processes to etch off the oxide layer, and compared with the prior art, the process steps are reduced, and the preparation cost of the power device is reduced.
In one possible design, the first oxide layer and the second oxide layer are broken down.
The term "breakdown" refers to a situation where, when the voltage applied to an insulating medium is higher than a certain level (breakdown voltage), the insulating medium collapses to rapidly lower the resistance of the insulating medium, and then a part of the insulating medium becomes a conductor. Taking the first oxide layer as an example, when the voltage applied to the first oxide layer is over a certain level, the resistance of the first oxide layer will decrease rapidly, so that the first oxide layer is changed from an insulating medium to a conductor.
By adopting the scheme, after the first oxide layer is broken down, the resistance of the first oxide layer is reduced; after the second oxide layer is broken down, the resistance of the second oxide layer is reduced, so that the on-resistance of the power device is reduced and returns to a normal value, and the specification of the power device is met. By adopting the scheme, the oxide layer is not required to be etched by adopting other processes, compared with the prior art, the process steps are reduced, and the preparation cost of the power device is reduced.
In one possible design, in a case where a first voltage that increases step by step is applied between the first conductive bump and the second conductive bump, a ratio of the first voltage to a first current flowing between the first conductive bump and the second conductive bump may be within a calibrated range of an on-resistance value of the power device.
By adopting the scheme, the first voltage which is gradually increased is applied between the first oxide layer and the second oxide layer, so that the first oxide layer and the second oxide layer can be broken down, the on-resistance of the power device is further reduced until the normal value is returned, and the specification of the power device is met. In addition, the first voltage stops being received after the ratio of the first voltage to the first current is reduced to the calibrated range of the on-resistance of the power device, so that the on-resistance of each power device can meet the specification, and the problem of poor batch due to the difficulty in process control (the vacuum chamber is difficult to maintain a high vacuum degree) in the prior art scheme shown in fig. 4 can be avoided.
In a possible design, the power device provided in the first aspect may further include a third top layer pad, a third oxide layer, a third sub-layer, and a third conductive bump stacked in this order on the die, and a fourth top layer pad, a fourth oxide layer, a fourth sub-layer, and a fourth conductive bump stacked in this order on the die, where the third top layer pad is in communication with the fourth top layer pad through the die.
The third conductive bump or the fourth conductive bump can be used for forming a gate of the power device.
By adopting the scheme, the ratio of the voltage applied to the grid electrode of the power device to the current flowing through the grid electrode can meet the specification requirement without etching the oxide layer by adopting other processes, and compared with the prior art, the method has the advantages that the process steps are reduced, and the preparation cost of the power device is reduced.
In one possible design, the third oxide layer and the fourth oxide layer are broken down.
By adopting the scheme, after the third oxide layer and the fourth oxide layer are broken down, the equivalent resistance value is reduced, so that the ratio of the voltage applied to the grid electrode of the power device to the current flowing through the grid electrode is reduced until the specification requirement of the power device is met.
In one possible design, in the case where a second voltage that increases stepwise is applied between the third conductive bump and the fourth conductive bump, a ratio of the second voltage to a second current flowing between the third conductive bump and the fourth conductive bump may be made to be within a nominal range of a ratio of a voltage applied to a gate of the power device to a current flowing through the gate.
By adopting the scheme, the second voltage is applied between the third conductive bump and the fourth conductive bump, so that the third oxide layer and the fourth oxide layer are broken down, the ratio of the second voltage to the second current is reduced to the calibration range of the ratio of the voltage applied to the grid of the power device to the current flowing through the grid, and the problem of poor electric connection of the grid caused by the additionally introduced packaging contact resistance of the third oxide layer and the fourth oxide layer can be solved.
In one possible design, the first conductive bump and the second conductive bump are respectively coupled to two output terminals of a first voltage source or a current source, and the first voltage source or the current source is used for outputting a first voltage.
In one possible design, the third conductive bump and the fourth conductive bump are respectively coupled to two output terminals of a second voltage source, and the second voltage source is used for outputting a second voltage.
In a second aspect, embodiments of the present application provide a method for manufacturing a power device, where the power device includes a first electrode, a second electrode, and a first oxide layer and a second oxide layer located between the first electrode and the second electrode. Specifically, the preparation method of the power device comprises the following steps: and applying a first voltage between the first electrode and the second electrode, so that the ratio of the first voltage to a first current reaches a nominal range of the on-resistance value of the power device, wherein the first current is a current flowing between the first electrode and the second electrode.
The ratio of the first voltage to the first current is the sum of the equivalent resistances of the first electrode, the second electrode, the first oxide layer and the second oxide layer.
Specifically, the on-resistance of the power device is a ratio of a voltage applied between two other electrodes except the gate electrode to a current flowing through the power device when the power device normally operates. For example, in the case of a MOSFET, the on-resistance of the MOSFET is the ratio of the voltage applied between the drain and the source to the current flowing through the MOSFET when the MOSFET is operating normally.
If the power device is an MOSFET or a GaN transistor, the first electrode is a drain electrode and the second electrode is a source electrode; if the power device is a BJT, the first electrode is a collector and the second electrode is an emitter. That is, the first electrode and the second electrode are two electrodes through which current passes when the power device is turned on, rather than a control electrode for controlling the power device to be turned on and off.
Further, after the application of the first voltage is stopped, the equivalent resistance of the first oxide layer is smaller than that of the first oxide layer before the application of the first voltage, and the equivalent resistance of the second oxide layer is smaller than that of the second oxide layer before the application of the first voltage.
By applying the first voltage between the first electrode and the second electrode, the first oxide layer and the second oxide layer are broken down, so that the on-resistance of the power device is reduced until the normal value is returned, and the specification of the power device is met. By adopting the preparation method, the oxide layer does not need to be etched by other processes, compared with the prior art, the process steps are reduced, and the preparation cost of the power device is reduced. In addition, after the ratio of the first voltage to the first current is reduced to the calibrated range of the on-resistance of the power device, the application of the first voltage is stopped, so that the on-resistance of each power device can meet the specification, and the problem of poor batch due to the difficulty in process control (the vacuum chamber is difficult to maintain a high vacuum degree) in the prior art scheme shown in fig. 4 is solved.
In addition, the power device may further include a first gate, a second gate, and a third oxide layer and a fourth oxide layer between the first gate and the second gate. Correspondingly, the preparation method of the power device can further comprise the following steps: and applying a second voltage between the first grid and the second grid, so that the ratio of the second voltage to the second current is within a nominal range of the ratio of the voltage applied to the grid of the power device to the current flowing through the grid of the power device. The second current is a current flowing between the first grid and the second grid.
And the ratio of the second voltage to the second current is the sum of equivalent resistances of the first grid, the second grid, the third oxide layer and the fourth oxide layer.
By adopting the scheme, the second voltage is applied between the first grid and the second grid, so that the third oxide layer and the fourth oxide layer are broken down, the ratio of the second voltage to the second current is reduced to the calibration range of the ratio of the voltage applied to the grid of the power device to the current flowing through the grid, and the problem of poor electric connection of the grid caused by the additionally introduced packaging contact resistance of the third oxide layer and the fourth oxide layer can be solved.
Further, after the application of the second voltage is stopped, the equivalent resistance of the third oxide layer is smaller than that of the third oxide layer before the application of the second voltage, and the equivalent resistance of the fourth oxide layer is smaller than that of the third oxide layer before the application of the second voltage.
In one possible design, a first voltage may be applied between the first electrode and the second electrode by a first voltage source or current source.
In one possible design, a second voltage may be applied between the first gate and the second gate by a second voltage source.
In one possible design, the method for manufacturing the power device further includes: and applying a control signal to the power device through the first grid or the second grid to control the on and off of the power device.
By adopting the scheme, the power device can be controlled to be switched on and off through the first grid or the second grid, and the first grid or the second grid can be alternatively used.
In a third aspect, embodiments of the present application further provide a driving circuit, which includes the gate driver and the power device provided in the second aspect and any possible design thereof. Wherein the third conductive bump and the fourth conductive bump of the power device are coupled to the signal output terminal of the gate driver.
In a fourth aspect, embodiments of the present application further provide an integrated circuit board, where the integrated circuit board includes a circuit board body and a power device provided in the second aspect and any possible design thereof or a driving circuit provided in the third aspect and any possible design thereof. The integrated circuit board body is provided with pins, and the power device or the driving circuit is connected with the circuit board body through the pins.
In addition, it should be understood that technical effects brought by the second aspect to the fourth aspect and any one of the possible design manners of the second aspect to the fourth aspect may refer to technical effects brought by different design manners of the first aspect, and are not described herein again.
Fig. 1 is a schematic structural diagram of a semiconductor chip provided in the prior art;
FIG. 2 is a schematic diagram of another semiconductor chip provided in the prior art;
fig. 3 is an equivalent circuit diagram of a power device after a package contact resistance is introduced according to the prior art;
FIG. 4 is a schematic diagram of a process for etching an alumina film according to the prior art;
fig. 5 is a schematic structural diagram of a first power device provided in an embodiment of the present application;
fig. 6 is a schematic flowchart of a method for manufacturing a power device according to an embodiment of the present application;
FIG. 7 is a schematic view of an Id-Vd curve provided by an embodiment of the present application;
FIG. 8 is a schematic diagram of a Vd-Id curve according to an embodiment of the present disclosure;
fig. 9 is a schematic structural diagram of a second power device according to an embodiment of the present application;
fig. 10 is a schematic structural diagram of a third power device provided in an embodiment of the present application;
FIG. 11 is a schematic illustration of an Igg-Vgg curve provided in an embodiment of the present application;
FIG. 12 is a schematic diagram illustrating a voltage applied between the drain and the source according to an embodiment of the present disclosure;
FIG. 13 is a schematic diagram illustrating another example of applying a voltage between the drain and the source according to the present disclosure;
FIG. 14 is a schematic diagram of applying a voltage between dual gates according to an embodiment of the present application;
fig. 15 is a schematic structural diagram of a fourth power device according to an embodiment of the present application;
fig. 16 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;
fig. 17 is a schematic structural diagram of an integrated circuit board according to an embodiment of the present application.
Embodiments of the present application will be described in further detail below with reference to the accompanying drawings.
In the embodiments of the present application, a plurality means two or more. In addition, in the description of the present application, the terms "first," "second," and the like are used for descriptive purposes only and are not intended to indicate or imply relative importance nor order to be construed. The term "couple" in the embodiments of the present application refers to electrical connection, and may specifically include direct connection or indirect connection.
The embodiment of the application provides a preparation method of a power device, and the power device comprises a first electrode, a second electrode, and a first oxide layer and a second oxide layer which are arranged between the first electrode and the second electrode.
The power device includes, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a gallium nitride (GaN) transistor, an Insulated Gate Bipolar Transistor (IGBT), a Bipolar Junction Transistor (BJT), and a triode. If the power device is an MOSFET or a GaN transistor, the first electrode is a drain electrode, and the second electrode is a source electrode; if the power device is a BJT, the first electrode is a collector and the second electrode is an emitter. That is, the first electrode and the second electrode are two electrodes through which current passes when the power device is turned on, rather than a control electrode for controlling the power device to be turned on and off.
It is noted that, in the embodiments of the present application, a first oxide layer and a second oxide layer are included between the first electrode and the second electrode. That is to say, with the embodiment of the present application, the on-resistance of the power device can meet the specification of the power device without etching the oxide layer by using other processes.
In practical applications, the first oxide layer and the second oxide layer may be aluminum oxide films. Certainly, if the top pad is made of other metal materials when the power device is manufactured, the first oxide layer and the second oxide layer may also be films formed after other metals are oxidized.
Taking the first oxide layer and the second oxide layer as aluminum oxide films as an example, a schematic diagram of a possible structure of the power device can be shown in fig. 5. In the example of fig. 5, after performing an adhesion seed layer (such as Ti/Cu, tiW/Cu, etc.) and a copper plating operation on the top pad, a first electrode and a second electrode of the power device are formed through interconnection, wherein an aluminum oxide thin film (a first oxide layer) exists between the seed layer of the first electrode and the top pad, and an aluminum oxide thin film (a second oxide layer) exists between the seed layer of the second electrode and the top pad.
Specifically, referring to fig. 6, the method for manufacturing the power device includes the following steps.
S601: a first voltage is applied between the first electrode and the second electrode.
S602: and increasing the first voltage, and measuring the voltage value of the first voltage and the current value of the first current.
Wherein the first current is a current flowing between the first electrode and the second electrode.
S603: and stopping applying the first voltage when the ratio of the first voltage to the first current reaches the calibration range of the on-resistance value of the power device.
As can be seen from the structure shown in fig. 5, the ratio of the first voltage to the first current is the sum of the equivalent resistances of the first electrode, the second electrode, the first oxide layer, and the second oxide layer.
In the embodiment of the present application, the on-resistance of the power device is a ratio of a voltage applied between two other electrodes except the gate to a current flowing through the power device when the power device normally operates. For example, in the case of a MOSFET, the on-resistance of the MOSFET is the ratio of the voltage applied between the drain and the source to the current flowing through the MOSFET when the MOSFET is operating normally. Still taking the MOSFET as an example, the on-resistance of the MOSFET determines the power consumed when the MOSFET is on. Generally, for a MOSFET of a certain specification and model, there is a requirement for a calibration range of on-resistance values when the MOSFET is shipped, for example, the calibration range of the on-resistance values may be 25m Ω ± 5m Ω, and only when the on-resistance values are within the calibration range, the power device is considered to meet the shipping requirement. In the embodiment of the application, in the preparation process of the power device, by continuously testing the ratio of the first voltage to the first current, when the ratio of the first voltage to the first current falls within the calibration range of the on-resistance value (for example, 25m Ω ± 5m Ω), it can be considered that the on-resistance value of the power device has satisfied the factory requirement, and at this time, the application of the first voltage can be stopped.
Specifically, in S601, a first voltage may be applied between the first electrode and the second electrode by the first voltage source, or may be applied between the first electrode and the second electrode by the current source.
In practical applications, when the first voltage is applied by the first voltage source, the output voltage of the first voltage source may be gradually increased, for example, gradually increased from 0V to 5V. Then, when the applied voltage is small, the on current of the power device (i.e., the first current) is small due to the presence of the first oxide layer and the second oxide layer; when the voltage continues to be increased, the first oxide layer and the second oxide layer break down under the action of the electric field, the resistance of the first oxide layer suddenly decreases at the moment when the first oxide layer is damaged, and the resistance of the second oxide layer suddenly decreases at the moment when the second oxide layer is damaged. At this time, the current can normally flow through the first oxide layer and the second oxide layer, and the on current of the power device will jump and quickly return to the desired level. Specifically, the relationship between the output voltage Vd of the first voltage source (i.e., the first voltage) and the on-current Id of the power device (i.e., the first current) may be as shown in fig. 7. When the Id-Vd curve closely coincides with the Id-Vd curve in an ideal state, it can be considered that the on-current of the power device is restored to an ideal level, that is, the on-resistance of the power device is restored to an ideal level.
In the embodiment of the present application, the breakdown refers to when the voltage applied to an insulating medium is higher than a certain level (breakdown voltage), the insulating medium is collapsed to rapidly decrease its resistance, and then a part of the insulating medium becomes a conductor. Taking the first oxide layer as an example, when the voltage applied to the first oxide layer is over a certain level, the resistance of the first oxide layer will decrease rapidly, so that the first oxide layer is changed from an insulating medium to a conductor.
In practical applications, when the first voltage is applied by the current source, the output current of the current source can be gradually increased. Then, when the applied current is small, the potential difference between the first electrode and the second electrode is large due to the presence of the first oxide layer and the second oxide layer; when the current is increased continuously, the first oxide layer and the second oxide layer break down under the action of the electric field, the resistance of the first oxide layer suddenly decreases at the moment when the first oxide layer is damaged, and the resistance of the second oxide layer suddenly decreases at the moment when the second oxide layer is damaged, so that the potential difference between the first electrode and the second electrode is suddenly reduced, and the potential difference is quickly restored to an ideal level. Specifically, the relationship between the potential difference Vd between the first electrode and the second electrode and the output current Id of the current source may be as shown in fig. 8. When the Vd-Id curve closely coincides with the Vd-Id curve in the ideal state, the on-resistance of the power device can be considered to be restored to the ideal level.
The application of the first voltage may be stopped after the on-resistance of the power device returns to a desired level (i.e., the ratio of the first voltage to the first current decreases to within a nominal range of the on-resistance value of the power device). For example, in the example of fig. 7, when the Id-Vd curve closely coincides with the Id-Vd curve in an ideal state, it is considered that the ratio of the first voltage to the first current reaches the calibration range of the on-resistance value of the power device, and the application of the first voltage is stopped; in the example of fig. 8, when the Vd-Id curve closely coincides with the Vd-Id curve in the ideal state, it is considered that the ratio of the first voltage to the first current reaches the calibration range of the on-resistance value of the power device, and the application of the first voltage is stopped.
After the application of the first voltage is stopped, the equivalent resistance of the first oxide layer is smaller than that of the first oxide layer before the application of the first voltage, and the equivalent resistance of the second oxide layer is smaller than that of the second oxide layer before the application of the first voltage. Although the first oxide layer and the second oxide layer still exist in the power device, the influence of package contact resistance additionally introduced by the first oxide layer and the second oxide layer on the on-resistance of the power device is almost negligible, and the on-resistance of the power device returns to a normal value.
By applying the first voltage between the first electrode and the second electrode, the first oxide layer and the second oxide layer are broken down, so that the on-resistance of the power device is reduced until the normal value returns, and the specification of the power device is met. By adopting the preparation method, the oxide layer does not need to be etched by other processes, compared with the prior art, the process steps are reduced, and the preparation cost of the power device is reduced. In addition, after the ratio of the first voltage to the first current is reduced to the calibrated range of the on-resistance of the power device, the application of the first voltage is stopped, so that the on-resistance of each power device can meet the specification, and the problem of poor batch due to the difficulty in process control (the vacuum chamber is difficult to maintain a high vacuum degree) in the prior art scheme shown in fig. 4 is solved.
In addition, the control electrode (e.g., GATE) of the power device may also introduce package contact resistance due to oxidation of the top pad metal. Because the grid of the power device can not pass large current, the power device can form a double-grid structure when a chip is designed, and the problem of poor electric connection caused by packaging contact resistance can be solved by pressurizing between the two grids.
In this embodiment, the power device may further include a first gate, a second gate, and a third oxide layer and a fourth oxide layer between the first gate and the second gate. The preparation method of the power device further comprises the following steps: applying a second voltage between the first gate and the second gate, increasing a voltage value of the second voltage, and measuring a ratio of the second voltage and the second current; and stopping applying the second voltage when the ratio of the second voltage to the second current reaches the calibration range of the ratio of the voltage applied to the grid electrode of the power device to the current flowing through the grid electrode of the power device. The second current is a current flowing between the first grid and the second grid.
It is understood that the ratio of the second voltage to the second current is the sum of the equivalent resistances of the first gate, the second gate, the third oxide layer and the fourth oxide layer.
In practical applications, the third oxide layer and the fourth oxide layer may be aluminum oxide films. Of course, if the top pad is made of other metal materials when the power device is manufactured, the third oxide layer and the fourth oxide layer may also be films formed by oxidizing other metals.
Taking the third oxide layer and the fourth oxide layer as aluminum oxide films as an example, in the example of fig. 9, the package contact resistance introduced due to oxidation is equivalent to one aluminum oxide film, and two aluminum oxide films, i.e., the third oxide layer and the fourth oxide layer, are included between the first gate G1 and the second gate G2. In this example, a schematic diagram of a possible structure of the power device may be as shown in fig. 10. In the example of fig. 10, after performing an adhesion seed layer (such as Ti/Cu, tiW/Cu, etc.) and a copper plating operation on the top pad, a first gate and a second gate of the power device are formed through interconnection, where an aluminum oxide thin film (a third oxide layer) exists between the seed layer of the first gate and the top pad, and an aluminum oxide thin film (a fourth oxide layer) exists between the seed layer of the second gate and the top pad.
It should be noted that, in the example in fig. 10, for simplicity of illustration, the first electrode and the second electrode in the power device are not shown, and the structures of the first electrode and the second electrode may refer to the example in fig. 5, which is not described again here.
Similar to the calibration range of the on-resistance value of the power device, when the power device leaves a factory, the ratio of the voltage applied to the gate to the current flowing through the gate also has the calibration range, and the power device is considered to meet the factory requirement only when the ratio of the voltage applied to the gate to the current flowing through the gate is within the calibration range. In the embodiment of the application, the ratio of the second voltage to the second current is continuously tested in the preparation process of the power device, and when the ratio of the second voltage to the second current falls within the calibration range of the ratio of the voltage applied to the gate to the current flowing through the gate, the on-resistance value of the power device can be considered to meet the factory requirement, and at this time, the application of the second voltage can be stopped.
In particular, a second voltage may be applied between the first gate and the second gate by a second voltage source. When the second voltage is applied by the second voltage source, the output voltage of the second voltage source can be made to gradually increase. Then, when the applied voltage is small, the current Igg flowing between the first gate and the second gate is small due to the presence of the third oxide layer and the fourth oxide layer; when the voltage is continuously increased, the third oxide layer and the fourth oxide layer break down under the action of the electric field, the current can normally flow through the third oxide layer and the fourth oxide layer, the Igg has a jump, and the Igg is quickly recovered to an ideal level. Specifically, the relationship between the output voltage Vgg (i.e., the second voltage) and Igg (i.e., the second current) of the second voltage source may be as shown in fig. 11. When the Igg-Vgg curve is approximately coincident with the Igg-Vgg curve in an ideal state, it can be considered that the ratio of the second voltage to the second current reaches a calibration range of the ratio of the voltage applied to the gate of the power device to the current flowing through the gate of the power device.
The application of the second voltage may be stopped after the ratio of the second voltage to the second current decreases to within a nominal range of the ratio of the voltage applied to the gate of the power device to the current flowing therethrough. For example, in the example of FIG. 11, the application of the second voltage may be stopped when the Igg-Vgg curve closely coincides with the Igg-Vgg curve in an ideal state.
After the application of the second voltage is stopped, the equivalent resistance of the third oxide layer is smaller than that of the third oxide layer before the application of the second voltage, and the equivalent resistance of the fourth oxide layer is smaller than that of the fourth oxide layer before the application of the second voltage. Although the third oxide layer and the fourth oxide layer still exist in the power device, the problem of poor electrical connection of the gate caused by the package contact resistance additionally introduced by the third oxide layer and the fourth oxide layer is almost negligible.
It should be understood that the above-mentioned solution of applying the second voltage between the first gate and the second gate to solve the problem of poor electrical connection between the gates and the aforementioned solution of applying the first voltage between the first electrode and the second electrode to solve the problem of poor electrical connection between the first electrode and the second electrode are not strictly limited in the execution order.
In addition, after the preparation method is executed, the on-resistance value of the power device can reach the factory requirement. In the use process of the power device after leaving factory, a control signal can be applied to the power device through the first grid or the second grid so as to control the on and off of the power device. That is to say, after leaving the factory, both the first gate and the second gate may be used as gates of the power device to control on and off of the power device, and may be used alternatively in practical applications.
In S601, a control signal needs to be applied to the gate of the power device to control the power device to be turned on. In practical applications, the control signal may be applied to the first gate, or may be applied to the second gate.
In summary, according to the preparation method of the power device provided by the embodiment of the application, the first oxide layer and the second oxide layer are broken down by applying the first voltage between the first electrode and the second electrode, so that the on-resistance of the power device is reduced until the on-resistance returns to a normal value, and the specification of the power device is met. By adopting the preparation method, the oxide layer does not need to be etched by other processes, and compared with the prior art, the process steps are reduced. After the ratio of the first voltage to the first current is reduced to the calibration range of the on-resistance value of the power device, the application of the first voltage is stopped, so that the on-resistance value of each power device can meet the specification, and the problem of poor batch in the prior art is solved.
In addition, a second voltage is applied between the first grid and the second grid, so that the third oxide layer and the fourth oxide layer are broken down, the ratio of the second voltage to the second current is reduced to a calibrated range of the ratio of the voltage applied to the grid of the power device to the current flowing through the grid, and the problem of poor grid electrical connection caused by packaging contact resistance additionally introduced by the third oxide layer and the fourth oxide layer can be solved.
Next, a power device shown in fig. 9 is taken as an example, and a detailed description is given to a manufacturing scheme of the power device provided in the embodiment of the present application.
Step 1: the device is tested for output characteristics under a high-current tester (or a test board capable of providing high current), specifically, vgs is applied to positive voltage, so that the power device is conducted, and voltage is applied between D and S.
Specifically, the high current tester may correspond to a current source, as shown in fig. 12; the high current tester may also correspond to a voltage source, as shown in fig. 13.
Initially, the on-current of the power device is small due to the presence of the oxide layer between D and S; when the voltage is continuously increased, the oxide layer between D and S starts to punch through under the action of the electric field, the current can normally pass through the oxide layer, and the current of the power device can be restored to the level of an ideal device. At this time, the voltage application between D and S is stopped.
Step 2: a voltage is applied between G1 and G2 as shown in FIG. 14. Initially, the current flowing through G1 is small due to the presence of the oxide layer between G1 and G2; when the voltage is increased, the oxide layer between G1 and G2 starts to punch through under the action of the electric field, the current can normally pass through the oxide layer, and the current flowing through G1 is restored to the level of an ideal device. At this time, the voltage application between G1 and G2 is stopped.
It should be noted that the execution order of step 1 and step 2 is not strictly limited, and step 1 may be executed first and then step 2 may be executed, or step 2 may be executed first and then step 1 may be executed.
The embodiment of the present application further provides a power device, as shown in fig. 15, the power device 1500 includes a die 1501, and a first top layer pad 1502a, a first oxidation layer 1502b, a first seed layer 1502c, and a first conductive bump 1502d stacked in sequence on the die 1501, and further includes a second top layer pad 1503a, a second oxidation layer 1503b, a second seed layer 1503c, and a second conductive bump 1503d stacked in sequence on the die 1501, wherein the first top layer pad 1502a is in communication with the second top layer pad 1503a through the die 1501.
The first conductive bump 1502d may be used to form a drain of the power device 1500, and the second conductive bump 1503d may be used to form a source of the power device 1500.
Alternatively, the first oxide layer 1502b and the second oxide layer 1503b are broken down.
After the first oxide layer 1502b is broken down, the equivalent resistance value decreases; after the second oxide layer 1503b is broken down, the equivalent resistance value is reduced, so that the equivalent resistance value of the power device 1500 can be reduced to be within the calibration range of the on resistance value of the power device 1500.
Since the first top layer pad 1502a communicates with the second top layer pad 1503a through the die 1501, when a first voltage is applied between the first conductive bump 1502d and the second conductive bump 1503d, it is understood that a first current flows through the first conductive bump 1502d → the first seed layer 1502c → the first oxide layer 1502b → the first top layer pad 1502a → the die 1501 → the second top layer pad 1503a → the second oxide layer 1503b → the second seed layer 1503c → the second conductive bump 1503d. Since the on-resistances of the first seed layer 1502c, the first top pad 1502a, the second top pad 1503a and the second seed layer 1503c are small, the ratio of the first voltage to the first current can be considered to be approximately equal to the sum of the equivalent resistances of the first conductive bump 1502d, the second conductive bump 1503d, the first oxide layer 1502b and the second oxide layer 1503 b.
Alternatively, in the case where a gradually increasing first voltage is applied between the first conductive bump 1502d and the second conductive bump 1503d, the ratio of the first voltage to the first current can be made to be within the nominal range of the on-resistance value of the power device 1500. The first current is a current flowing between the first conductive bump 1502d and the second conductive bump 1503d.
The first voltage applied between the first conductive bump 1502d and the second conductive bump 1503d may break down the first oxide layer 1502b and the second oxide layer 1503b, so that the on-resistance of the power device 1500 is reduced until the normal value returns to meet the specification of the power device 1500. After the ratio of the first voltage to the first current is reduced to the calibrated range of the on-resistance value of the power device 1500, the application of the first voltage is stopped, so that the on-resistance values of the power device 1500 can all meet the specification, and the problem of poor batch in the prior art is solved.
In addition, the power device 1500 may further include a third top layer pad, a third oxide layer, a third sub-layer, and a third conductive bump stacked in sequence on the die 1501, and a fourth top layer pad, a fourth oxide layer, a fourth sub-layer, and a fourth conductive bump stacked in sequence on the die, where the third top layer pad is in communication with the fourth top layer pad through the die 1501.
The third conductive bump or the fourth conductive bump may be used to form a gate of the power device 1500.
Optionally, the third oxide layer and the fourth oxide layer are broken down.
After the third oxide layer and the fourth oxide layer are broken down, the equivalent resistance value is reduced, so that the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through the gate is reduced until the specification requirement of the power device 1500 is met.
Alternatively, in the case where a gradually increasing second voltage is applied between the third conductive bump and the fourth conductive bump, the ratio of the second voltage to the second current may be made to be within a nominal range of the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through the gate. The second current is a current flowing between the third conductive bump and the fourth conductive bump.
Since the third top pad is communicated with the fourth top pad through the die 1501, when a second voltage is applied between the third conductive bump and the fourth conductive bump, it is understood that a second current flows through the third conductive bump → the third sub-layer → the third oxide layer → the third top pad → the die 1501 → the fourth top pad → the fourth oxide layer → the fourth sub-layer → the fourth conductive bump. Since the on-resistances of the third sublayer, the third top pad, the fourth top pad, and the fourth sublayer are relatively small, it can be considered that the ratio of the second voltage to the second current is approximately equal to the sum of the equivalent resistances of the third conductive bump, the fourth conductive bump, the third oxide layer, and the fourth oxide layer.
A second voltage is applied between the third conductive bump and the fourth conductive bump, so that the third oxide layer and the fourth oxide layer are broken down, and further the ratio of the second voltage to the second current is reduced to a calibrated range of the ratio of the voltage applied to the gate of the power device 1500 to the current flowing through the gate, thereby solving the problem of poor gate electrical connection caused by the package contact resistance additionally introduced by the third oxide layer and the fourth oxide layer.
In practical applications, the first conductive bump 1502d and the second conductive bump 1503d can be respectively coupled to two output terminals of a first voltage source or a current source, wherein the first voltage source or the current source is used for outputting a first voltage and stopping outputting the first voltage when a ratio of the second voltage to the second current decreases to be within a calibration range of a ratio of a voltage applied to a gate of the power device 1500 to a current flowing through the power device. For example, the first conductive bump 1502D and the second conductive bump 1503D can be coupled to two outputs of the first voltage source respectively as shown in fig. 13 (where D corresponds to the first conductive bump 1502d and s corresponds to the second conductive bump 1503D), and the first conductive bump 1502D and the second conductive bump 1503D can be coupled to two outputs of the current source respectively as shown in fig. 12 (where D corresponds to the first conductive bump 1502d and s corresponds to the second conductive bump 1503D).
In practical applications, the third conductive bump and the fourth conductive bump are respectively coupled to two output terminals of a second voltage source, where the second voltage source is configured to output a second voltage and stop outputting the second voltage when a ratio of the second voltage to the second current decreases to a value within a calibration range of a ratio of a voltage applied to a gate of the power device 1500 to a current flowing through the gate. For example, the third conductive bump and the fourth conductive bump are respectively coupled to the two output terminals of the second voltage source in a manner as shown in fig. 14 (wherein G1 corresponds to the third conductive bump, and G2 corresponds to the fourth conductive bump).
In addition, the third conductive bump and the fourth conductive bump may also be used to apply a control signal to control the turn-on and turn-off of the power device 1500.
It should be noted that, for implementation and technical effects of the power device 1500 that are not described in detail, reference may be made to the description related to the manufacturing method of the power device shown in fig. 6, and details are not described here again.
The embodiment of the present application further provides a driving circuit, as shown in fig. 16, the driving circuit 1600 includes a gate driver 1601 and the aforementioned power device 1500. Wherein the third conductive bump and the fourth conductive bump of the power device 1500 are coupled to the signal output terminal of the gate driver 1601.
In addition, as shown in fig. 17, the integrated circuit board 1700 includes a circuit board body 1701 and the power device 1500 (or the driving circuit 1600), and fig. 17 illustrates an example in which the integrated circuit board 1700 includes the circuit board body 1701 and the power device 1500. The circuit board body 1701 has pins, and the power device 1500 is electrically connected to the circuit board body 1701 through the pins.
In fig. 17, the form of the lead is merely a specific example. In practice, the leads of the circuit board body 1701 may be point-shaped, sheet-shaped, or planar. The embodiment of the present application is not limited to the specific form of the lead of circuit board body 1701.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present application without departing from the scope of the embodiments of the present application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to encompass such modifications and variations.
Claims (20)
- A power device is characterized by comprising a bare chip, a first top layer bonding pad, a first oxidation layer, a first seed layer and a first conductive bump which are sequentially stacked on the bare chip, and a second top layer bonding pad, a second oxidation layer, a second seed layer and a second conductive bump which are sequentially stacked on the bare chip, wherein the first top layer bonding pad is communicated with the second top layer bonding pad through the bare chip.
- The power device of claim 1, wherein the first oxide layer and the second oxide layer are broken down.
- The power device according to claim 1 or 2, wherein when a first voltage that increases in steps is applied between the first conductive bump and the second conductive bump, a ratio of the first voltage to a first current flowing between the first conductive bump and the second conductive bump reaches a nominal range of an on-resistance value of the power device.
- The power device of any of claims 1-3, wherein the first conductive bump is used to form a drain of the power device and the second conductive bump is used to form a source of the power device.
- The power device of any of claims 1-4, further comprising a third top layer pad, a third oxide layer, a third sub-layer, and a third conductive bump stacked in sequence over the die, and a fourth top layer pad, a fourth oxide layer, a fourth sub-layer, and a fourth conductive bump stacked in sequence over the die, the third top layer pad in communication with the fourth top layer pad through the die.
- The power device of claim 5, wherein the third oxide layer and the fourth oxide layer are broken down.
- The power device according to claim 5 or 6, wherein, when a second voltage that increases in steps is applied between the third conductive bump and the fourth conductive bump, a ratio of the second voltage to a second current flowing between the third conductive bump and the fourth conductive bump reaches a nominal range of a ratio of a voltage applied to a gate of the power device to a current flowing therethrough.
- The power device of claim 7, wherein the third conductive bump or the fourth conductive bump is used to form a gate of the power device.
- The power device of any of claims 1-8, wherein the first conductive bump and the second conductive bump are coupled to two output terminals of a first voltage source or current source, respectively, the first voltage source or current source for outputting the first voltage.
- The power device according to any one of claims 5 to 9, wherein the third conductive bump and the fourth conductive bump are respectively coupled to two output terminals of a second voltage source for outputting the second voltage.
- A method of manufacturing a power device, the power device including a first electrode, a second electrode, and a first oxide layer and a second oxide layer between the first electrode and the second electrode, the method comprising:and applying a first voltage between the first electrode and the second electrode, so that the ratio of the first voltage to a first current reaches a calibrated range of the on-resistance value of the power device, wherein the first current is the current flowing between the first electrode and the second electrode.
- The method of claim 11, wherein a ratio of the first voltage to the first current is a sum of equivalent resistances of the first electrode, the second electrode, the first oxide layer, and the second oxide layer.
- The method of claim 11 or 12, wherein the power device further comprises a first gate, a second gate, and a third oxide layer and a fourth oxide layer between the first gate and the second gate, the method further comprising:and applying a second voltage between the first grid and the second grid so that the ratio of the second voltage to a second current reaches a calibrated range of the ratio of the voltage applied to the grid of the power device to the current flowing through the grid, wherein the second current is the current flowing between the first grid and the second grid.
- The method of claim 13, wherein a ratio of the second voltage to the second current is a sum of equivalent resistances of the first gate, the second gate, the third oxide layer, and the fourth oxide layer.
- The method of any one of claims 11-14, wherein applying a first voltage between the first electrode and the second electrode comprises:the first voltage is applied between the first electrode and the second electrode by a first voltage source or current source.
- The method of any of claims 13 to 15, wherein applying a second voltage between the first gate and the second gate comprises:applying the second voltage between the first gate and the second gate by a second voltage source.
- The method of any one of claims 11-16, wherein the first electrode is a drain electrode and the second electrode is a source electrode.
- The method of any one of claims 13 to 17, further comprising:and applying a control signal to the power device through the first gate or the second gate to control the power device to be switched on and off.
- A driving circuit comprising a gate driver and a power device according to any one of claims 1 to 10; wherein the third and fourth conductive bumps of the power device are coupled to a signal output of the gate driver.
- An integrated circuit board comprising a circuit board body and a power device according to any one of claims 1 to 10, or comprising a driver circuit according to claim 19; the circuit board body is provided with a pin, and the power device is electrically connected with the circuit board body through the pin.
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| Application Number | Priority Date | Filing Date | Title |
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| PCT/CN2021/097436 WO2022252060A1 (en) | 2021-05-31 | 2021-05-31 | Power device, preparation method for power device, drive circuit, and integrated circuit board |
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| US7005752B2 (en) * | 2003-10-20 | 2006-02-28 | Texas Instruments Incorporated | Direct bumping on integrated circuit contacts enabled by metal-to-insulator adhesion |
| US8698308B2 (en) * | 2012-01-31 | 2014-04-15 | Taiwan Semiconductor Manufacturing Company, Ltd. | Bump structural designs to minimize package defects |
| US8957694B2 (en) * | 2012-05-22 | 2015-02-17 | Broadcom Corporation | Wafer level package resistance monitor scheme |
| CN104241102A (en) * | 2014-08-26 | 2014-12-24 | 南通富士通微电子股份有限公司 | Under bump metal layer sputtering method |
| CN105006437B (en) * | 2015-07-28 | 2018-06-26 | 江阴长电先进封装有限公司 | A kind of manufacturing method of high density projection cube structure |
| US10026707B2 (en) * | 2016-09-23 | 2018-07-17 | Microchip Technology Incorportated | Wafer level package and method |
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