WO2022248537A2

WO2022248537A2 - Process for producing a vertical semiconductor component

Info

Publication number: WO2022248537A2
Application number: PCT/EP2022/064169
Authority: WO
Inventors: Dick Scholten; Christian Huber; Thomas Kaden
Original assignee: Robert Bosch Gmbh
Priority date: 2021-05-27
Filing date: 2022-05-25
Publication date: 2022-12-01
Also published as: WO2022248537A3; DE102021205375A1

Abstract

A process for producing a vertical semiconductor component (100) is provided, said process comprising: forming a gallium nitride layer system (15, 16, 17) on or atop a first side of the substrate (61, 61A); forming a frontside contact structure (23, 41) on or atop the gallium nitride layer system (15, 16, 17), wherein the frontside contact structure (23, 41) has at least a first electrode structure (41) and a second electrode structure (23) that are electrically insulated from one another; forming a backside contact structure (52) on or atop a second side of the substrate (61, 61A) which is opposite the first side, and/or on or atop the gallium nitride layer system (15, 16, 17) on the second side, wherein the backside contact structure (52) is electrically insulated from the first electrode structure (42) and the second electrode structure (23); applying a carrier (101) on or atop the frontside contact structure (23, 41) by means of a joining material (112), wherein the carrier (101) is set up such that the first electrode structure (41) is coupled to the second electrode structure (23); and processing, from the second side of the substrate (61, 61A), at least one of the gallium nitride layer system (15, 16, 17), the substrate (61, 61A) and the backside contact structure (52); and removing a portion of the carrier (101) in such a way that the first electrode structure (41) and the second electrode structure (23) are at least electrically insulated from one another after the removal.

Description

description

title

METHOD OF MAKING A VERTICAL SEMICONDUCTOR DEVICE

State of the art

Transistors based on gallium nitride (GaN) offer the possibility of realizing components with lower on-resistances and at the same time higher breakdown voltages than comparable components based on silicon or silicon carbide.

GaN transistors are primarily known for what are known as high-electron mobility transistors (HEMTs), in which the current flow takes place laterally on the top side of the substrate through a two-dimensional electron gas that forms the transistor channel. Such lateral components can be produced by heteroepitaxy of the functional GaN layers on silicon wafers. However, for high breakdown voltage with small on-resistance per unit area, vertical devices, in which the current flows from the front of the substrate to the back of the substrate, are more advantageous in terms of both the size and the electric field distribution inside the device. Such a component cannot be produced directly using heteroepitaxial GaN layers on silicon (Si), since insulating intermediate layers (a so-called buffer) are required to adapt the lattice mismatch between GaN and Si and to reduce the substrate curvature.

The buffer itself is mechanically strained in such a way that it just compensates for the strain of the GaN layers at room temperature. Because the buffer one is an insulator, the current flow from the front of the substrate to the back of the substrate is prevented by the buffer.

Native GaN substrates are also known on which the required additional epitaxial GaN layers of the device can be grown without the need for an insulating buffer. However, such GaN substrates are small (typically 50 mm in diameter) and expensive.

In order to reduce the transistor price per area element, it can be advantageous to use the available heteroepitaxial GaN layers on large silicon substrates. Vertical components (trench MOSFET, pn diode) are known for this purpose, in which the silicon substrate and the insulating buffer under the component are selectively removed, whereby a backside trench (backside trench) is formed in order to directly cover the backside of the drift zone of the component to be able to contact. 1 shows the basic structure of such a component 100 with an insulating buffer and rear side trench (here using a trench MOSFET 100). The rear side trench can also be referred to below as a rear side cavern or rear side aperture.

As illustrated in FIG. 1, the following III-V nitride semiconductor layers (GaN with the exception of the buffer) are grown epitaxially on the silicon substrate 61 or generally the carrier substrate: the insulating buffer 13, a highly doped contact semiconductor layer with n conductivity 14, the lightly doped n conductive drift layer 15, a p-conductive body layer 16 and a highly doped n-conductive source contact layer 17.

Source contact layer 17 and body layer 16 are penetrated by a trench (trench), the side walls and bottom of which are separated from gate electrode 21 by a gate dielectric 22 . Source contact layer 17 and body layer 16 are contacted by a source electrode 41 which is separated from gate electrode 21 by an insulating layer 31 . At the rear, the silicon substrate 61 and the buffer 13 are removed by a rear-side trench 51, which ends in the highly doped contact semiconductor layer with n-type conductivity 14. This is through a rear drain electrode 52 contacted. In operation, a conductive channel is formed in the body layer 16 by applying a gate voltage to the gate electrode 21, through which a current flow from the source electrode 41 to the drain electrode 52 is permitted.

1 shows a three cell transistor, i.e. three repeating structures, for the sake of simplicity. In a real transistor, there are typically a large number of such cells and are therefore effectively connected in parallel. Typical active areas are in the range of a few square millimeters, the remaining GaN layers have a thickness of a few micrometers. The drain electrode 52 can consist of several metallic layers.

FIG. FIG. 2A illustrates a schematic cross-sectional view of a vertical trench MOSFET of the related art and FIG. 2B illustrates a schematic top view of the same trench MOSFET on a native semiconductor substrate 61A along with associated assembly and connection technology. The vertical trench MOSFET can be a silicon trench MOSFET on a silicon substrate, a SiC trench MOSFET on a SiC substrate, or a GaN trench MOSFET on a GaN substrate. The native semiconductor substrate 61A is electrically conductive and no insulating layers are provided between the native semiconductor substrate 61A and the drift layer 15, as a result of which vertical current flow through the trench MOSFET is possible.

In order to use a conventional vertical trench MOSFET in electrical circuits (as a module or discrete package), the transistor electrodes must be contacted. For this purpose, the rear drain electrode 52 is usually on a circuit board 71, for example a DBC (direct bonded copper) - substrate, an AMB (active metal brazed) - substrate, a metal-core printed circuit board (insulated metal substrate (IMS)) or a printed circuit board upset. Technologies such as soft soldering or silver sintering are used for this purpose.

The source electrode 41 and the gate pad 23 on the front of the transistor, however, are mostly by wire or Ribbon bond connections 96 are realized and are thus connected to the gate 73 or source connection 72 on the circuit board 71 . The source electrode 41 is designed as a full-area electrode above the entire active transistor area. As a result, the lateral lead resistance for the transistor current can be reduced. Several wires or ribbons are typically used for the bond connection in order to keep the current load in the source pad metallization low and also to reduce the connection resistance.

The bond connection is made directly over the active transistor area (bond over active). Another advantage of this is that no additional inactive chip area is required for a separate bond pad. In other words: the source electrode 41 and the source pad overlap each other and are used interchangeably in the following. Larger lateral lead resistances are acceptable for the gate. For this reason, the individual gate electrode fingers 21 are led out to a gate pad 23 (not visible in the cross section). This can be within the active area of the transistor or at its edge. However, the gate electrode fingers 21 and the gate pad 23 do not contribute to the vertical current flow. The gate pad 23 thus increases the chip area requirement for the transistor without reducing its resistance. Fewer wires are typically required to connect to gate terminal 73 on circuit board 71 . Ultrasonic energy and pressure are applied to the transistor for the bonding process.

In order to reduce the lateral electrical resistance in the contact surfaces and to be able to bond to standard power semiconductors with copper wire, a so-called "die top system" is installed on the surface of the source electrode 41.

(DTS) used. A DTS is a copper foil cut to the surface of the source electrode 41 and electrically bonded thereto by silver sintering. The DTS and chip are connected when the chips are built in the module, i.e. a connection is only made after the processed wafer has been separated into individual chips.

In order to enable vertical conductivity of GaN-on-Si wafers, the substrate 61 and the buffer layers 13 have so far been partially removed, so that a Rear cavern 51 is formed. This process is technically demanding and the remaining stabilizing Si webs (61) on the edge of each individual transistor take up chip area and complicate further processing, for example due to the resulting topography on the underside of the chip.

Previous technical solutions for stabilizing fragile semiconductor substrates 61, for example thin wafer technology, use a temporary bonding process on a carrier substrate or a carrier film. The carrier substrate or the carrier foil is removed again after the rear side has been processed. However, the thin wafers processed in this way require sufficient inherent stability for the separation into chips.

So far, there is no technical solution to reliably remove the substrate 61 and the buffer layers 13 completely from a GaN-on-Si wafer (instead of local removal under the transistor as illustrated in FIG. 1) and thereby stabilize the wafer that it can be further processed.

Disclosure of Invention

Advantages of the Invention

The inventive method for producing a vertical semiconductor device with the features of claim 1 has the advantage of removing the substrate and the buffer layers from a GaN-on-Si wafer by clearly an additionally applied, graded metal foil, such as copper, molybdenum or Tungsten or corresponding layer combinations, is provided on the vertical semiconductor component before the singulation process. The graded metal foil is attached to the front side of the wafer, for example using silver technology or diffusion soldering, before the back side is processed. In this case, only gate electrodes and/or source electrodes and optionally auxiliary structures are contacted. Thus, the wafer can be more easily handled for subsequent backside processes. Before the singulation process, for example a wafer sawing process, the upper layer of the stepped metal foil is removed. As a result, intended separation points, such as saw lines, are uncovered. By exposing the intended separation points, the individual vertical semiconductor components can become electrically functional again.

The mechanical stability of the wafer can be stabilized during the back side processes. For example, the graded metal foil can mechanically stabilize the entire wafer and/or each individual chip before and after singulation. As a result, conventional bonding methods using temperature and pressure can be used without the vertical semiconductor component being damaged or, in the case of a diaphragm, being deformed by the pressure. Alternatively or additionally, the graded metal foil can be used as a replacement or substitute for a DTS. This saves a process step at chip level.

Developments of the aspects and advantageous configurations of the vertical semiconductor component are described in the dependent claims and the description.

drawing

Embodiments of the invention are shown in the figures and are explained in more detail below. Show it:

FIG. 1 is a schematic representation of a related art membrane transistor;

2A and 2B are schematic representations of a related art vertical field effect transistor; and

FIG. 3A to FIG.8 schematic representations of a membrane

Semiconductor device according to various aspects.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is understood that others Embodiments may be used and structural or logical changes may be made without departing from the scope of the present invention. It is understood that the features of the various exemplary embodiments described herein can be combined with one another unless specifically stated otherwise. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. In the figures, identical or similar elements are provided with identical reference symbols, insofar as this is appropriate.

In the following description, various aspects and embodiments of a vertical semiconductor component are described using a trench MOSFET as an example. It goes without saying, however, that the use of the stepped metal foil for processing the rear side of a semiconductor component is not limited to a trench MOSFET, so that in principle any vertical semiconductor components can be produced using this technology, such as Schottky diodes, pn diodes, vertical Diffusion MOSFETS (VDMOS), Current-Aperture Vertical Electron Transistors (CAVETs), vGroove Vertical High Electron Mobility Transistors (vHEMTs) or Fin Field Effect Transistors (FinFETs).

Description of the embodiments

FIG. 3A shows a schematic top view of a vertical semiconductor device wafer 100 according to various embodiments. 3B illustrates a schematic cross-sectional view of the semiconductor device wafer 100 illustrated in FIG. 3A. The solid line in FIG. 3B shown area.

A stepped metal foil 110 with a step structure 111 and a joining material 112 is arranged on the semiconductor component wafer 100 . The semiconductor device wafer 100 is arranged on a carrier material 99 on the rear side of the wafer. The step structure 111 and the joining material 112 are located on the underside of the metal foil 110 which faces the semiconductor device wafer 100 . The metal foil 110 can be applied to the semiconductor component wafer 100 by means of silver sintering technology or diffusion soldering, for example. For this purpose, the metal foil 110 can have a joining material 112, for example a silver sintering paste or electrolytic tin, which is arranged on the stepped structure 111, so that the joining material 112 is arranged between the stepped structure 111 and the semiconductor component wafer 100. For example, the step structure 111 is coated with the joining material 112 .

The metal foil 110 coated with joining material 112 and having a stepped structure 111 can be applied to the semiconductor component wafer 100 by means of pressure and/or temperature, for example joined.

During the application of the metal foil 110 on a first side of the semiconductor device wafer 100, the semiconductor device wafer 100 can be supported by a carrier material 99 on an opposite second side.

After the metal foil 110 has been applied and connected to the semiconductor component wafer 100, the fragile semiconductor component wafer 100 is mechanically stabilized. As a result, the carrier material 99 on the rear side of the semiconductor device wafer 100 can be removed. This allows the back side of the stabilized semiconductor device wafer 100 to be further processed. For example, the further processing (also referred to as the rear-side process) can include a local or full-area removal of the (silicon) substrate 61 and (optionally) the buffer layer 13 .

After the rear side process, the semiconductor device wafer 100 can be applied to a carrier component 99 and can optionally be connected to it (see FIG. 4). The semiconductor device wafer 100 can then be further processed. This carrier component 99 can, for example, be sawing tape for a sawing process. The metal foil 110 can be removed, for example reduced, to such an extent that only the step structure 111 remains on the semiconductor component wafer 100 . Desired separation points, for example saw lines, can be exposed between the steps of the step structure 111 . In this state, the semiconductor device wafer 100 can be sawed and the semiconductor devices can be singulated.

4 shows the semiconductor component wafer 100 on the carrier material 99 with the metal foil 110 removed, so that only the stepped structure 111 and the joining material 112 remain on the semiconductor component wafer 100. FIG.

Clearly, the vertical semiconductor device wafer 100 has: a gallium nitride layer system 15, 16, 17 on or over a first side of a substrate 61, 61A, a front-side contact structure 23, 41 on or over the gallium nitride layer system 15, 16, 17, where the front-side contact structure 23, 41 has at least a first electrode structure 41 and a second electrode structure 23 which are electrically insulated from one another; a backside contact structure 52 on or over a second side of the substrate 61, 61A, which is opposite the first side, and/or on or over the gallium nitride layer system 15, 16, 17 on the second side, the backside contact structure 52 having a third electrode structure 52 , which is electrically isolated from the first electrode structure 42 and the second electrode structure 23; a carrier support 101 on or above the front-side contact structure 23, 41, which is mechanically coupled to the front-side contact structure 23, 41 by means of a joining material 112, the carrier support 101 being set up in such a way that the first electrode structure 41 is coupled to the second electrode structure 23.

The carrier support 101 is a front-side support or front-side support for the semiconductor device wafer 100 and can also be referred to as a carrier element or carrier element.

The substrate 61, 61A may be a semiconductor substrate such as Si, SiC or GaN; or a non-conductive substrate, e.g. alumina, e.g. sapphire. 5A-FIG. 5B and FIG. 6A-FIG. 6B illustrate schematic cross-sectional views of various aspects of GaN membrane wafers 100 with different backside embodiments. FIG. 5A and FIG. 5B illustrate an embodiment of a method in which the substrate 61 and the buffer 13 are removed locally under the active areas by the back side processing, as a result of which a back side cavern 51 is formed (see also FIG. 7A). FIG. 6A and FIG. 6B illustrate an embodiment of a method in which the substrate 61 and the buffer 13 are removed over the entire area by the rear-side processing (see also FIG. 7B).

In various embodiments, the metal foil 110 is removed and the semiconductor component wafer 100 is singulated, for example sawed, along intended separation points. After the isolation, isolated membrane semiconductor components, for example membrane transistors, are provided in a stabilized form.

The method may further include a sintering process, for example a silver sintering process, to contact the semiconductor device wafer 100, for example by means of subsequent wire or ribbon bonding 96, as illustrated in the schematic cross-sectional views in FIG. 7A and FIG. 7B. In FIG. 7A and FIG. 7B, embodiments of GaN membrane transistors with a stabilized upper side are illustrated, which were joined onto a printed circuit board 71. FIG.

Large-area transistors can have a specific gate line, also referred to as gate runner 102, in the transistor cell array. The gate runner 102 may be covered with relatively soft organic layers as a gate runner passivation. The soft organic layers can pose a risk for pressure-sensitive sintering of a conventional DTS foil. During the sintering process, a copper foil can be applied under pressure over the gate runner 102 in the transistor cell array. A particle can be pushed through the gate runner passivation under pressure during sintering. In the metal foil 110 in the area of the gate runner 102, a recess 104 in of the step structure 111 so that a particle is not pressed into the gate runner passivation. A recess and/or separate source pads can be formed in a simple manner by means of the method described. 8A illustrates a plan view of a membrane semiconductor device wafer 100 with gate runner 102, and FIG. 8B, FIG. 8C and FIG. 8D illustrate schematic cross-sectional views of embodiments taken along the line of FIG. 8A.

In other words:

In various embodiments, the method for manufacturing a vertical semiconductor device wafer 100 includes forming a gallium nitride layer system 15, 16, 17 on or over a first side of a substrate 61, 61A. The method includes forming a front-side contact structure 23, 41 on or above the gallium nitride layer system 15, 16, 17. The front-side contact structure 23, 41 has at least a first electrode structure 41 and a second electrode structure 23, which are electrically insulated from one another. The method includes forming a backside contact structure 52 on or over a second side of the substrate 61, 61A and/or on or over the gallium nitride layer system 15, 16, 17 at the second side. The second page is opposite the first page. The rear contact structure 52 is electrically isolated from the first electrode structure 42 and the second electrode structure 23 . The method includes applying a carrier support 101 to or above the front-side contact structure 23, 41 by means of a joining material 112. The carrier support 101 is set up in such a way that the first electrode structure 41 is coupled to the second electrode structure 23 . The method further includes processing from the second side of the substrate 61, 61A at least one of the gallium nitride layer system 15, 16, 17, the substrate 61, 61A and the backside contact structure 52. The method further includes removing part of the carrier support 101 in such a way that the first electrode structure 41 and the second electrode structure 23 are at least electrically insulated from one another after removal. The first electrode structure 41 and the second electrode structure 23 can also be physically separated or isolated from one another. If the substrate 61, 61A has been completely removed, at least locally, so that the GaN layer system 15, 15, 17 is exposed on the back, there can clearly no longer be a second side of the substrate 61, 61A. The rear side of the semiconductor component wafer 100 is processed, for example forming the rear-side electrode structure, from the direction of the second side of the substrate 61, 61A (formerly possibly present) or in other words “at the second side of the substrate 61, 61A and/or on or over a side of the gallium nitride layer system 15, 16, 17 opposite the first side of the substrate 61, 61A.

The backside contact structure 52 may include a third electrode structure 52 . The third electrode structure 52 is electrically insulated from the first electrode structure 42 and the second electrode structure 23 .

Vertical semiconductor device wafer 100 may be vertical transistor 100 . In this case, the first electrode structure 41 is a source electrode 41 or a drain electrode, the second electrode structure 23 is a gate electrode 23 and the rear contact structure 52 or the third electrode structure 52 is a drain electrode 52 or a source -Electrode. The method can include electrically contacting the first electrode structure 42 , the second electrode structure 23 and the rear-side contact structure 52 or the third electrode structure 52 with a printed circuit board 71 .

The method can also include forming a desired separation point, which is set up for singulating the semiconductor component.

In various embodiments, the method alternatively or additionally forms a front-side contact structure on or above the gallium nitride layer system 15, 16, 17, wherein the

Front-side contact structure has a first electrode structure of a first vertical semiconductor component and a second electrode structure of a second vertical semiconductor component. A predetermined separation point is arranged (laterally) between the first electrode structure and the second electrode structure or is formed there. The procedure also includes Forming a rear contact structure on or over a second side of the substrate 61, 61A opposite the first side and/or on or over the gallium nitride layer system 15, 16, 17 at the second side. The backside contact structure is electrically isolated from the frontside contact structure. The rear-side contact structure has a third electrode structure of the first vertical semiconductor component and a fourth electrode structure of the second vertical semiconductor component. The intended separation point is arranged (laterally) between the third electrode structure and the fourth electrode structure. The method includes the application of the carrier support 101 on or over the front contact structure using the joining material 112 . The carrier support 101 is set up in such a way that the first electrode structure is coupled to the second electrode structure. The method comprises processing, from the second side of the substrate 61, 61A, at least one of the gallium nitride layer system 15, 16, 17, the substrate 61, 61A and the backside contact structure. The method further includes removing part of the carrier support 101 in such a way that the first electrode structure and the second electrode structure are at least electrically insulated from one another after the removal. Clearly, the method can be used to singulate a number of vertical semiconductor components that are arranged on a common semiconductor component wafer. In this case, the first vertical semiconductor component and the second vertical semiconductor component can be controlled semiconductor components, for example transistors, or uncontrolled semiconductor components, for example diodes. If the first semiconductor component and the second semiconductor component are each a diode, the first electrode structure and the second electrode structure is an anode electrode and the third electrode structure and the fourth electrode structure is a cathode electrode, or vice versa.

The method of one of the embodiments described above can include separating the desired separation point, so that the first vertical semiconductor component and the second vertical semiconductor component are singulated. A desired separation point, which is set up for separating the semiconductor component—for example a sawing line or a breaking edge, can be arranged between adjacent steps or step structures of the step structure 111 .

In one of the previously described embodiments, the processing can include, for example, at least a part of the substrate 61, 61A being removed. The removal can take place, for example, in such a way that a rear-side cavern 51 is formed below the first electrode structure and the second electrode structure. Alternatively, the processing may be such that the substrate 61, 61A is completely removed. The backside contact structure 52 is formed after removing the portion of the substrate 61, 61A in various embodiments.

The gallium nitride layer system 15, 16, 17 can have, for example, at least one drift layer 17, a p-doped gallium nitride layer 15, 16 and an n-doped gallium nitride layer 16, 15.

The rear side contact structure 52 can be in direct contact with the gallium nitride layer system 15, 16, 17 at least in one area.

The joining material 112 can be electrically conductive, for example a silver, tin or copper sinter paste, or electroplated silver, tin or copper.

The carrier support 101 can have a step structure 111 on a foil 110 . The step structure 111 can be coupled to the first electrode structure 42 by means of the joining material 112 . The step structure 111 can be set up in such a way that the second electrode structure 23 is free from physical contact with the carrier support 101. At least part of the foil 110 can be the removed part of the carrier support 101.

Alternatively, the carrier support 101 can have a step structure 111 on a foil 110 . The step structure 111 can have at least a first step structure 111 and a second step structure 111 which are mechanically connected to one another by means of the foil 110 . The first step structure 111 can be coupled to the first electrode structure by means of the joining material 112 and the second step structure 111 can be coupled by means of the joining material 112 be coupled to the second electrode structure 23 . At least part of the foil 110 can be the removed part of the carrier support 101 .

One or the desired separation point can be arranged between adjacent (partial) step structures of the step structure, for example laterally between the first step structure and the second step structure.

In various embodiments, the metal foil 110 and the stepped structure 111 are formed in one piece, for example as a structured or stepped metal foil 101.

Alternatively or additionally, the front-side contact structure can have at least one pad metallization, for example the first electrode structure and the second electrode structure, and an insulation layer 31 . The pad metallization has a first height and the insulating layer 31 has a second height that is smaller than the first height, so that the pad metallization extends further from the substrate 61, 61A than the insulating layer 31. The carrier support 101 can in this case be a planar or substantially planar foil 110 .

In various embodiments, the substrate 61, 61A is applied to a carrier material 99 before the carrier carrier 101 is applied.

The carrier material 99 is removed before the at least one of the gallium nitride layer system 15, 16, 17, the substrate 61, 61A and the rear-side contact structure 52 are processed.

In various embodiments, a vertical semiconductor device wafer 100 comprises: a gallium nitride layer system 15, 16, 17 on or over a first side of a substrate 61, 61A; a front-side contact structure 23, 41 on or above the gallium nitride layer system 15, 16, 17, the front-side contact structure 23, 41 having at least a first electrode structure 41 and a second electrode structure 23, which are electrically insulated from one another; a backside contact structure 52 on or above a second side of the substrate 61, 61A, which is opposite the first side, and / or on or above the gallium nitride layer system 15, 16, 17 at the second side, wherein the Backside contact structure 52 is electrically isolated from first electrode structure 42 and second electrode structure 23; a carrier support 101 on or above the front-side contact structure 23, 41, which is mechanically coupled to the front-side contact structure 23, 41 by means of a joining material 112, the carrier support 101 being set up in such a way that the first electrode structure 41 is coupled to the second electrode structure 23.

Alternatively or additionally, the vertical semiconductor device wafer 100 comprises: a gallium nitride layer system 15, 16, 17 on or over a first side of a substrate 61, 61A; a front-side contact structure 23, 41 on or above the gallium nitride layer system 15, 16, 17, the front-side contact structure 23, 41 having at least one source electrode 41 and one gate electrode 23 which are electrically insulated from one another; a backside contact structure 52 on or over a second side of the substrate 61, 61A, opposite the first side, and/or on or over the gallium nitride layer system 15, 16, 17 at the second side, the backside contact structure 52 being separated from the source electrode 42 and the gate electrode 23 is electrically insulated; the source electrode 42 has a first height and the gate electrode 23 has a second height different from the first height; and a compensation structure 111, which is arranged on the source electrode 42 and on the gate electrode 23 by means of a joining material 112, the compensation structure 111 being set up in such a way that the source electrode 42 is connected to the compensation structure 111 and the gate electrode 23 have the same or substantially the same third height with the balancing structure 112 .

This enables the metallization to be of the same height on the source and gate electrode structure, which can be advantageous for chips joined on both sides.

The embodiments described and shown in the figures are only chosen as examples. Different embodiments can be combined with one another completely or in relation to individual features. An embodiment can also be supplemented by features of a further embodiment. Furthermore, method steps described can be repeated and carried out in a different order than in the order described. In particular, the invention is not limited to the specified method.

Claims

Expectations

A method of manufacturing a vertical semiconductor device (100), the method comprising:

forming a gallium nitride layer system (15, 16, 17) on or over a first side of a substrate (61, 61A);

Forming a front contact structure (23, 41) on or above the gallium nitride layer system (15, 16, 17), wherein the

Front side contact structure (23, 41) has at least a first electrode structure (41) and a second electrode structure (23) which are electrically isolated from each other;

Forming a rear contact structure (52) on or over a second side of the substrate (61, 61A), which is opposite the first side, and / or on or over the gallium nitride layer system (15, 16, 17) at the second side, wherein the Backside contact structure (52) is electrically isolated from the first electrode structure (42) and the second electrode structure (23);

Application of a carrier support (101) on or above the

Front-side contact structure (23, 41) by means of a joining material (112), the carrier support (101) being set up in such a way that the first electrode structure (41) is coupled to the second electrode structure (23); and processing, from the second side of the substrate (61, 61A), at least one of the gallium nitride layer system (15, 16, 17), the substrate (61, 61A) and the backside contact structure (52); and

Removing part of the carrier support (101) in such a way that the first electrode structure (41) and the second electrode structure (23) are at least electrically insulated from one another after the removal.

2 Method according to claim 1, wherein the vertical semiconductor device (100) is a vertical transistor (100), wherein the first electrode structure (41) is a source electrode (41) and a drain electrode, respectively, the second electrode structure (23) is a gate electrode (23) and the third electrode structure (52) is a drain electrode (52) and a source electrode, respectively.

The method according to claim 2, further comprising: electrically contacting the first electrode structure (42), the second electrode structure (23) and the third electrode structure (52) with a printed circuit board (71).

4. The method according to any one of claims 1 to 3, further comprising:

forming a desired separation point, which is set up for singulating the semiconductor component.

5. A method of manufacturing a vertical semiconductor device (100), the method comprising:

Forming a front-side contact structure on or above the gallium nitride layer system (15, 16, 17), the front-side contact structure having a first electrode structure of a first vertical semiconductor component and a second electrode structure of a second vertical semiconductor component, with a desired separation point between the first electrode structure and the second electrode structure is arranged;

Forming a backside contact structure on or over a second side of the substrate (61, 61A), which is opposite the first side, and/or on or over the gallium nitride layer system (15, 16, 17) at the second side, the backside contact structure extending from the Front-side contact structure is electrically isolated, and wherein the back-side contact structure has a third electrode structure of the first vertical semiconductor component and a fourth electrode structure of the second vertical semiconductor component, the intended separation point being arranged between the third electrode structure and the fourth electrode structure;

Applying a carrier support (101) on or over the front-side contact structure by means of a joining material (112), the carrier support (101) being set up in such a way that the first electrode structure is coupled to the second electrode structure; and processing, from the second side of the substrate (61, 61A), at least one of the gallium nitride layer system (15, 16, 17), the substrate (61, 61A) and the backside contact structure; and

Removing part of the carrier support (101) in such a way that the first electrode structure and the second electrode structure are at least electrically insulated from one another after the removal.

6. The method of claim 5, further comprising:

Separating the intended separation point, so that the first vertical semiconductor component and the second vertical semiconductor component are singulated.

7. The method according to any one of claims 1 to 6, wherein the processing comprises removing at least part of the substrate (61, 61A).

8. The method according to claim 7, wherein a rear side cavern (51) is formed below the first electrode structure and the second electrode structure.

9. The method according to claim 7, wherein the substrate (61, 61A) is completely removed.

10. The method according to any one of claims 7 to 9, wherein the backside contact structure (52) is formed after removing the part of the substrate (61, 61A).

11. The method according to any one of claims 1 to 10, wherein the gallium nitride layer system (15, 16, 17) at least one drift layer (17), a p-doped gallium nitride layer (15, 16) and an n-doped gallium nitride layer (15, 16 ) having.

12. The method according to any one of claims 1 to 11, wherein the rear side contact structure (52) is in direct contact with the gallium nitride layer system (15, 16, 17) at least in one region.

13. The method according to any one of claims 1 to 12, wherein the joining material (112) is electrically conductive.

14. The method according to any one of claims 1 to 13, wherein the carrier support (101) has a step structure (111) on a film (110), the step structure (111) being coupled to the first electrode structure (42) by means of the joining material (112). and wherein the step structure (111) is set up such that the second electrode structure (23) is free from physical contact with the carrier support (101); and wherein at least part of the foil (110) is the removed part of the carrier support (101).

15. The method according to any one of claims 1 to 14, wherein the carrier support (101) has a step structure (111) on a film (110), the step structure (111) having at least a first step structure (111) and a second step structure (111) which are mechanically connected to one another by means of the foil (110), the first step structure (111) being coupled to the first electrode structure by means of the joining material (112) and the second step structure (111) being coupled to the second electrode structure by means of the joining material (112). is paired; and at least part of the foil (110) is the removed part of the carrier support (101).

16. The method according to any one of claims 14 or 15, wherein the desired separation point is arranged between adjacent step structures of the step structure (111).

17. The method according to any one of claims 1 to 16, wherein the front-side contact structure has at least one pad metallization and one insulation layer (31), the pad metallization having a first height and the insulation layer (31) having a second height that is smaller than the first height , so that the pad metallization extends further from the substrate (61, 61A) than the insulating layer (31), and wherein the carrier support (101) is a planar or substantially planar foil (110).

18. The method according to any one of claims 1 to 17, wherein the substrate (61, 61A) is applied to a carrier material (99) before the carrier support (101) is applied; and wherein the carrier material (99) is removed before processing the at least one of the gallium nitride layer system (15, 16, 17), the substrate (61, 61A) and the backside contact structure (52).

A vertical semiconductor device wafer (100) comprising: a gallium nitride layer system (15, 16, 17) on or over a first side of a substrate (61, 61A); a front-side contact structure (23, 41) on or above the gallium nitride layer system (15, 16, 17), the front-side contact structure (23, 41) having at least a first electrode structure (41) and a second electrode structure (23) which electrically insulates from one another are; a backside contact structure (52) on or over a second side of the substrate (61, 61A) opposite the first side and/or on or over the gallium nitride layer system (15, 16, 17) at the second side, the backside contact structure (52) is electrically isolated from the first electrode structure (42) and the second electrode structure (23); a carrier support (101) on or above the front-side contact structure (23, 41), which is connected to the front-side contact structure (23,

41) is mechanically coupled, the carrier support (101) being set up in such a way that the first electrode structure (41) is coupled to the second electrode structure (23).

A vertical semiconductor device wafer (100) comprising: a gallium nitride layer system (15, 16, 17) on or over a first side of a substrate (61, 61A); a front-side contact structure (23, 41) on or above the gallium nitride layer system (15, 16, 17), wherein the front-side contact structure (23, 41) has at least one source electrode (41) and one gate electrode (23) which is electrically are isolated from each other; a backside contact structure (52) on or over a second side of the substrate (61, 61A) opposite the first side, and/or on or over the gallium nitride layer system (15, 16, 17) at the second side, wherein the Backside contact structure (52) is electrically isolated from the source electrode (42) and the gate electrode (23); the source electrode (42) having a first height and the gate electrode (23) having a second height different from the first height; and a compensation structure (111) which is arranged on the source electrode (42) and on the gate electrode (23) by means of a joining material (112), the compensation structure (111) being set up in such a way that the source electrode ( 42) with the compensation structure (111) and the gate electrode (23) with the compensation structure (112) have the same or substantially the same third height.