WO2022223214A1

WO2022223214A1 - Gan semiconductor device on a silicon substrate with a back-side trench and method for producing same

Info

Publication number: WO2022223214A1
Application number: PCT/EP2022/057409
Authority: WO
Inventors: Christian Huber; Thomas Kaden
Original assignee: Robert Bosch Gmbh
Priority date: 2021-04-21
Filing date: 2022-03-22
Publication date: 2022-10-27
Also published as: DE102021203956A1

Abstract

The invention relates to a membrane semiconductor device (100) which has an outer region (81) and a membrane region (82). At least part of a substrate (61) is arranged in the outer region (81). The substrate (61) is structured in such a way that a back-side trench (51) is provided in the membrane region (82). The back-side trench (51) is free of substrate (61). The membrane comprises the active semiconductor layer and can be contacted from the back side. At least one active region is arranged in the membrane region (82), and the active region has at least one p-n junction. At least one desired contact point (98) for membrane semiconductor device-external contacting is arranged on or above the substrate (61) in the outer region (81). The desired contact point (98) has an electrically conductive structure which is coupled to the active region.

Description

description

title

GAN SEMICONDUCTOR DEVICE ON SILICON SUBSTRATE WITH BACK TRACK AND METHOD FOR MAKING THE SAME

State of the art

Transistors based on gallium nitride (GaN) offer the possibility of realizing components with lower on-resistances and at the same time higher breakdown voltages than comparable components based on silicon or silicon carbide.

GaN transistors are primarily known for what are known as high-electron mobility transistors (HEMTs), in which the current flow takes place laterally on the top side of the substrate through a two-dimensional electron gas that forms the transistor channel. Such lateral components can be produced by heteroepitaxy of the functional GaN layers on silicon wafers. However, for high breakdown voltage with small on-resistance per unit area, vertical devices, in which the current flows from the front of the substrate to the back of the substrate, are more advantageous in terms of both the size and the electric field distribution inside the device. Such a component cannot be produced directly using heteroepitaxial GaN layers on silicon (Si), since insulating intermediate layers (a so-called buffer) are required to adapt the lattice mismatch between GaN and Si and to reduce the substrate curvature.

The buffer itself is mechanically strained in such a way that it just compensates for the strain of the GaN layers at room temperature. Because the buffer one is an insulator, the current flow from the front of the substrate to the back of the substrate is prevented by the buffer.

Native GaN substrates are also known on which the required additional epitaxial GaN layers of the device can be grown without the need for an insulating buffer. However, such GaN substrates are small (typically 50 mm in diameter) and expensive.

In order to reduce the transistor price per area element, it can be advantageous to use the available heteroepitaxial GaN layers on large silicon substrates. Vertical components (trench MOSFET, pn diode) are known for this purpose, in which the silicon substrate and the insulating buffer under the component are selectively removed, whereby a backside trench (backside trench) is formed in order to directly cover the backside of the drift zone of the component to be able to contact. 1 shows the basic structure of such a component 1 with an insulating buffer and rear trench (here using a trench MOSFET). The rear side trench can also be referred to below as a rear side cavern or rear side aperture.

As illustrated in FIG. 1, the following III-V nitride semiconductor layers (GaN with the exception of the buffer) are grown epitaxially on the silicon substrate 61 or generally the carrier substrate: the insulating buffer 13, a highly doped contact semiconductor layer with n conductivity 14, the lightly doped n conductive drift layer 15, a p-conductive body layer 16 and a highly doped n-conductive source contact layer 17.

Source contact layer 17 and body layer 16 are penetrated by a trench (trench), the side walls and bottom of which are separated from gate electrode 21 by a gate dielectric 22 . Source contact layer 17 and body layer 16 are contacted by a source electrode 41 which is separated from gate electrode 21 by an insulating layer 31 . At the rear, the silicon substrate 61 and the buffer 13 are removed by a rear-side trench 51, which ends in the highly doped contact semiconductor layer with n-type conductivity 14. This is through a rear drain electrode 52 is contacted. In operation, a conductive channel is formed in the body layer 16 by applying a gate voltage to the gate electrode 21, through which a current flow from the source electrode 41 to the drain electrode 52 is permitted.

1 shows a three cell transistor, i.e. three repeating structures, for the sake of simplicity. In a real transistor, there are typically a large number of such cells and are therefore effectively connected in parallel. Typical active areas are in the range of a few square millimeters, the remaining GaN layers have a thickness of a few micrometers. The drain electrode 52 can consist of several metallic layers.

In FIG. 2A and 2B, a vertical trench MOSFET is shown in simplified form on a native semiconductor substrate 61A together with the associated assembly and connection technology of the related technology. FIG. 2A shows a cross section and FIG.2B shows a plan view. The vertical trench MOSFET can be either a silicon trench MOSFET on a silicon substrate, a SiC trench MOSFET on a SiC substrate, or a GaN trench MOSFET on a GaN substrate. In this case, native substrate 61A is conductive and there are no insulating layers between native substrate 61A and drift layer 15 . This allows a vertical current flow.

In order to use such a transistor in electrical circuits (as a module or discrete package), the transistor electrodes are contacted. For this purpose, the rear drain electrode is typically applied to a printed circuit board 71, e.g. a so-called direct bonded copper (DBC), active metal brazed (AMB) substrate, insulated metal substrate (IMS) or printed circuit board, e.g.

The source electrode 41 and the gate pad 23 on the front side of the transistor, on the other hand, are usually implemented by wire or ribbon bond connections and are thus connected to the gate 73 or source connection 72 on the printed circuit board 71 . The source electrode 41 is used as a full-area electrode over the entire active transistor area executed. As a result, the lateral lead resistance for the transistor current can be reduced. Several wires or ribbons are typically used for the bond connection in order to keep the current load in the source pad metallization low and also to reduce the connection resistance.

The bond connection is made directly over the active transistor area (bond over active). Another advantage of this is that no additional inactive chip area is required for a separate bond pad. In other words: the source electrode 41 and the source pad overlap each other and are used interchangeably in the following. Larger lateral lead resistances are acceptable for the gate. For this reason, the individual gate electrode fingers 21 are led out to a gate pad 23 (not visible in the cross section). This can be within the active area of the transistor or at its edge. However, the gate electrode fingers 21 and the gate pad 23 do not contribute to the vertical current flow. The gate pad thus increases the chip area requirement for the transistor without reducing its resistance. Fewer wires are typically required to connect to gate terminal 73 on circuit board 71 . Ultrasonic energy and pressure are applied to the transistor for the bonding process.

A direct transfer of the "bond over active" technology known from vertical transistors on native substrates in the area of thin transistor membranes would mean that a bond connection would have to be carried out on a fragile and deformable membrane under the influence of temperature and pressure. No methods are currently known for contacting a source and gate pad in a vertical membrane transistor.

Disclosure of Invention

Advantages of the Invention

The membrane semiconductor component according to the invention with the features of claim 1 has the advantage that by a support structure below the source electrode and gate pad in the membrane semiconductor component, conventional wire and ribbon bonding technologies are made possible for contacting the electrodes on the front side of the transistor. Thus, a reliable structure and connection technology for vertical GaN-on-Si membrane transistors can be made possible. Alternatively or additionally, the stability of the semiconductor component can be increased for the bonding process. As an alternative or in addition, a low lead resistance can be implemented with a simultaneously low additional area requirement for contact pads. The dependent claims and the description describe developments of the aspects and advantageous configurations of the membrane semiconductor component.

drawing

Embodiments of the invention are shown in the figures and are explained in more detail below. Show it:

FIG. 1 is a schematic representation of a related art membrane transistor;

2A and 2B are schematic representations of a related art vertical field effect transistor; and

FIG. 3A to FIG.7B are schematic representations of a membrane semiconductor component according to various aspects.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. It is understood that the features of the various exemplary embodiments described herein can be combined with one another unless specifically stated otherwise. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims. In the figures, identical or similar elements are provided with identical reference symbols, insofar as this is appropriate.

A vertical membrane power semiconductor component, for example a transistor or a diode, which has one or more bond pads on the front side, is clearly provided. The thickness of the transistor in the vertical direction, for example at least of the crystalline layers, is greater in the area of the bond pad by means of a support structure than in the remaining active area of the vertical membrane power semiconductor component. The mechanical stability of the membrane power semiconductor component can be increased in the area of the bond pad, so that conventional bonding methods using temperature and pressure can be used without the membrane power semiconductor component being damaged or deformed by the pressure.

Various aspects relate to the electrical connection of the bond pads of the membrane semiconductor component to a circuit board. In the following description, various aspects and embodiments are described using the example of a trench MOSFET. However, it goes without saying that the possibility of providing such conductive access to the back of a drift zone by means of a back trench is not limited to a trench MOSFET, so that in principle any vertical power semiconductor components can be produced using this technology, such as Schottky diodes , pn diodes, vertical diffusion MOSFETS (VDMOS), current aperture vertical electron transistors (CAVETs), vGroove vertical high electron mobility transistors (vHEMTs) or fin field effect transistors (FinFETs).

Description of the embodiments

FIG. 3A, FIG.3B and FIG.3C show an aspect of a membrane semiconductor component 100 in a schematic transverse view (FIG.3A) and two top views (FIG.3B and FIG.3C). The membrane semiconductor component 100 is contacted on a printed circuit board 71 by means of bonding wires 97, as a result of which a membrane semiconductor structure is formed. The membrane semiconductor component 100 has an outer area 81 and a membrane area 82 . A back side trench 51 is arranged in the membrane area 82 . In the plan view, the membrane semiconductor component 100 is bordered by dashed lines. The active area that overlaps the backside trench 51 is illustrated with a dash-dot line.

At least a part or portion of a substrate 61 is arranged in the outer area 81 . The substrate 61 is structured in such a way that the rear side trench 51 is set up in the membrane area 82 . The rear trench 51 is free of substrate 61. At least an active area of the Semiconductor component 100, for example at least one pn junction of a vertical diode or a vertical transistor, is arranged in membrane region 82. At least one target contact point 98 for contacting the outside of the membrane semiconductor component is arranged on or above the substrate 61 in the outer area 81 . The target pad 98 comprises an electrically conductive structure coupled to the active area. The desired contact point 98 is or has the gate pad 23 or the source electrode 41, for example.

In the aspect illustrated in FIG.3A-FIG.3C, all bonding connections of the membrane semiconductor component 100 to the circuit board 71 occur entirely within the outer area 81.

In FIG.3B, analogously to FIG. 2 the routing of the gate electrodes 21 to the gate pad 23 is shown. For the sake of simplicity, the individual transistor cells are not shown in FIG. 3C and in all of the following top views (FIG. 4B-4D, FIG. 5B, FIG. However, it is understood that there is always an electrical connection from the gate pad 23 into the active area.

Clearly, the thickness of the membrane semiconductor component in the area of the bond pads (also referred to as desired contact points 98), for example in the outer area 81, is greater than in the remaining area of the membrane semiconductor component 100, for example the membrane area 82. The gate electrode fingers 21 be routed to a gate pad 23 located outside of the rear side trench 51 . The source electrode 41 can extend over the full area to an area outside of the rear side trench 51 . In the illustrated embodiments, the source electrode 41 in the membrane region 82 may be configured as a continuous electrode.

In this aspect, a wire bond can only take place in the mechanically more stable outer area 81 instead of the membrane area 82, for example. As a result, a high level of stability of the membrane semiconductor component can be achieved during the bonding process. In addition, only a small additional lead resistance can result from the full-area source electrode 41 compared to result in a more central bonding over the active area. This embodiment is suitable, for example, for applications with low power requirements. Furthermore, a small additional area requirement for the bond pads (desired contact points 98) is required, since the bond pads can be implemented in the outer area 81 of the transistor that is present anyway.

In various embodiments, the back side trench 51 can be filled with a material (also referred to as back side trench filler material 93, see FIG. 7B). The back side trench filling material can be designed to be thermally and electrically conductive. The back trench filling material can be, for example, sintered copper powder or a sinter paste. In contrast to the substrate 61 in the outer area 81, however, the backside trench filling material does not have to be a completely crystalline material. The rear side trench filling material can also have a different mechanical stability than the substrate 61.

FIG. 4A, 4B, 4C and 4D illustrate another aspect of a membrane semiconductor device 100, which is suitable for applications with a higher current demand, for example. FIG. 4A illustrates a cross section and FIG. 4B to FIG. 4D illustrate top views of different embodiments of the membrane semiconductor device 100 according to the further aspect. In the further aspect, the membrane semiconductor component 100 has a support structure 91 in an inner region 83 . The inner area 83 is arranged laterally next to the outer area 81 and the membrane area 82 . The support structure 91 can be formed, for example, by not removing the substrate 61 in the inner area 83 when forming the rear side trench 51 .

The support structure 91 extends from the active area into the rear side trench 51. A further target contact point 99, which has an electrically conductive structure which is coupled to the active area, is on or above the active area and the further target Contact point 99 arranged. The target pad 99 may be one of a gate pad 23 or a source electrode 41, or may be electrically coupled thereto. In other words, the target Contact point 99 can be conductively connected to a gate pad 23 or a source electrode 41

The source electrode 41 can be contacted, for example by means of wire bonds 97 or ribbon bonds 97, laterally next to the mechanically stable source electrode region 41 in the outer area 81 and also in the inner area 83 on the same full-area source electrode. The bonding areas 99 are thus arranged in an area with a higher thickness. This allows a large current to be supplied to the source electrode more smoothly. As a result, an overload such as that which occurs, for example, in the case of high currents in the circuit shown in FIG. 2 illustrated component of the related art can be prevented.

The active area can have a higher surface resistivity above the inner area 83 . As a result, current intended to flow through the transistor MOS channel should spread laterally in depth to flow into the drain contact 52 within an interior region 82 . In the active region, the membrane semiconductor component can have correspondingly more heavily doped regions for current spreading, directly above or laterally encompassing the support structures 91, 92.

In the embodiment illustrated in FIG. 4C, the support structure 91 is additionally coupled laterally to the substrate 61, for example by the inner region 83 having a multiplicity of webs 84 in which the substrate 61 is not removed or is not completely removed when the rear side trench 51 is formed , is connected to the outside area 81 . As a result, the mechanical stability of the membrane semiconductor component 100 before it is applied to the printed circuit board 71 can be increased. The higher surface area of the support structure 91 with the webs 84 can lead to a higher area-specific resistance in this area. This can be taken into account by current spreading structures in the active area of the semiconductor component.

In the embodiment illustrated in FIG.4D, a plurality of support structures are formed, for example by a plurality of interior regions 83 within which the substrate 61 is supported in forming the Rear trench 51 is not removed is present. These inner areas 83 can have a regular, for example hexagonal (illustrated), or irregular shape or structure and can be arranged in a regular or irregular distribution in the active region. A bond connection can be made on or over each of these inner regions 83 . This enables an even more even current distribution. The area-specific resistance of the active area can be higher in the area 83 of the support structures 91 than in the membrane area 82. This can be taken into account by current-spreading structures in the active area of the semiconductor component.

The features illustrated in FIG.4C and FIG.4D can be combined with one another in one embodiment. In other words, a multiplicity of inner areas 83 can be connected to one another and to the substrate 61 in the outer area 81 by means of a multiplicity of webs 84 . This enables an even more stable semiconductor device with uniform source current supply.

5A and FIG. 5B show yet another aspect of a membrane semiconductor component 100. The source electrode 41 can extend over the entire area into the outer area 81 and be contacted in the outer area 81. FIG.

The gate pad 23 can be arranged in the inner area 83 . This makes it possible, for example by a (more) central arrangement of the gate pad 23, to reduce the lead resistance to the individual gate finger electrodes. As a result, fast and low-loss switching processes can be implemented. The entire source current can be supplied via the bonding pad in the outer area 81. Analogous to those in FIG. 4B to FIG. 4D, the gate pad 23 can also be arranged in one or more inner area(s) 83 and/or be connected to one another and/or to the substrate 61 in the outer area 81 by means of webs 84.

FIG. 6A and FIG. 6B show yet another aspect of a membrane semiconductor component 100. The inner region 83 can be formed from a plurality of partial inner regions 85. FIG. The partial inner areas 85 can have a similar mechanical stability as the inner area 83 of the FIG. 4A through FIG.4D illustrated embodiments. Of the However, the total area required may be less. As a result, the additional area-specific on-resistance of the membrane semiconductor component 100 can be reduced with the same stability. In other words: in various embodiments, at least one target contact point 99 can be arranged on or over two or more support structures 91 .

FIG.7A and FIG.7B show yet another aspect of a membrane semiconductor component 100. In the inner region 86, the support structure 92 can only extend to a predetermined depth in the direction of the substrate 61, for example the substrate 61 when forming the rear side trench 51 be removed only to the specified depth. As a result, greater mechanical stability for the bonding process can be made possible in the inner area 86 than in the membrane area 82 . Analogously to the embodiments illustrated in FIG. 4B to FIG. 4D, the support structure 92 can also be arranged in one or more inner area(s) 83 and/or can be connected to one another and/or to the substrate 61 in the outer area 81 by means of webs 84 .

In various embodiments of the aspects described above, the rear side trench 51 can be filled with a thermally and/or electrically conductive material 93 (rear side trench filling material 93). As a result, the drain resistance can be reduced since the current flowing off has a larger cross-section in the filling material.

In various aspects, the one or more target contact points are contacted using a top-side contacting method. The top-side contacting process has a pressure load and joining energy on the target contact point. The target contact point is supported by the support structure. The top-side contacting method can be wire bonding or ribbon bonding, for example. should that

Top contacting method, for example, be a module solution in which only partial areas on the top of the semiconductor component are to be joined, e.g. by Ag or Cu sintering or by means of nanowire connection technology (Klett welding, Klett sinter ring), support using the support structure may be necessary. With the nanowire connection technology, the joining partners are coated with the finest copper threads ("hairs"), which are joining process like a “Velcro fastener”. For this purpose, the structure is again subjected to pressure and temperature.

The embodiments described and shown in the figures are only chosen as examples. Different embodiments can be combined with one another completely or in relation to individual features. An embodiment can also be supplemented by features of a further embodiment. Furthermore, method steps described can be repeated and carried out in a different order than in the order described. In particular, the invention is not limited to the specified method.

Claims

Expectations

1. Membrane semiconductor component (100) with an outer area (81) and a membrane area (82), at least part of a substrate (61) being arranged in the outer area (81), the substrate (61) being structured in such a way that a backside trench (51) is established in the membrane region (82), the backside trench (51) being free of substrate (61); wherein at least one active area is arranged in the membrane area (82) and the active area has at least one pn junction; and wherein at least one desired contact point (98) for external contacting of the membrane semiconductor component is arranged on or above the substrate (61) in the outer region (81), the desired contact point (98) having an electrically conductive structure which is coupled to the active region.

2 membrane semiconductor device (100) according to claim 1, further comprising at least one support structure (91, 92), which extends from the active area into the back side trench (51), and a further target contact point (99), the one has electrically conductive structure which is coupled to the active area, on or above the active area and the further target contact point (99).

3. Membrane semiconductor component (100) with an outer area (81) and a membrane area (82), at least part of a substrate (61) being arranged in the outer area (81), the substrate (61) being structured in such a way that a backside trench (51) is established in the membrane region (82), the backside trench (51) being free of substrate (61); wherein at least one active area is arranged in the membrane area (82) and the active area has at least one pn junction; and at least one support structure (91, 92) extending from the active area into the backside trench (51), and a target pad (98, 99) comprising an electrically conductive structure coupled to the active area, on or over the active area and the support structure (91, 92), the support structure (91, 92) being external (81) and/or in the membrane area (82).

4. membrane semiconductor device (100) according to any one of claims 1 to 3, wherein the target pad (98, 99) is one of a gate pad (23) or a source electrode (41).

5. membrane semiconductor component (100) according to any one of claims 1 to 4, wherein the support structure (91, 92) comprises the material of the substrate (61) or is formed therefrom.

6. membrane semiconductor component (100) according to any one of claims 1 to 5, wherein the support structure (91, 92) by means of one or more webs (84) is mechanically connected to the substrate (61) in the outer region (81).

7. membrane semiconductor device (100) according to any one of claims 1 to 6, comprising: a plurality of support structures (91, 92), which are arranged side by side spaced in the same backside trench (51) and are from the active area in the backsides - Trench (51), wherein at least one desired contact point (99) is arranged on or over two or more support structures (91, 92) of the plurality of support structures (91, 92).

8. membrane semiconductor device (100) according to any one of claims 1 to 7 comprising: a plurality of support structures (91, 92), which are arranged spaced apart from each other in the same back side trench (51) and extend from the active area in the back side Trench (51), a first support structure (91, 92) of the plurality of support structures (91,92) being connected to a second support structure (91, 92) of the plurality of support structures (91,92) by means of one or more webs (84). mechanically connected.

9 membrane semiconductor device (100) according to any one of claims 1 to 8, further comprising: a backside trench fill material (93) disposed in the backside trench (51), wherein the backside trench fill material (93) electrically and thermally conductive is.

A membrane semiconductor structure (110), comprising: a membrane semiconductor device (100) according to any one of claims 1 to 9; and a printed circuit board (71), wherein the substrate (61) is arranged on or over the printed circuit board (71) such that the back side trench (51) is arranged between the printed circuit board (71) and the active area.

11. membrane semiconductor structure (110) according to claim 10, wherein the support structure (91) mechanically couples the active area with the circuit board (71).

12. membrane semiconductor structure (110) according to claim 10, wherein the substrate (61) extends further towards the circuit board (71) than the support structure (92).

13. Membrane semiconductor structure (110) according to any one of claims 10 to 12, further comprising: a surface contact (97) for contacting the membrane semiconductor device externally, the surface contact (97) being electrically coupled to the target contact point (98, 99). is, wherein preferably the surface contact (97) has at least one metallic wire or a metallic band.

The membrane semiconductor structure (110) of claim 13, wherein the active area is electrically coupled to the circuit board (71) through the surface contact (97).

15. A method for producing a membrane semiconductor component (100) with an outer area (81) and a membrane area (82), the method having:

Structuring a substrate (61) in such a way that at least part of the substrate (61) is arranged in the outer region (81), and that a rear side trench (51) is in the membrane region (82) is established, wherein the rear side trench (51) is free of substrate (61);

forming at least one active region in the membrane region (82), the active region having at least one pn junction; and forming at least one support structure (91, 92) that differs from the active

region extending into the backside trench (51), and a target pad (98, 99) having an electrically conductive structure coupled to the active region on or over the active region and the support structure (91, 92 ), wherein the support structure (91, 92) is arranged in the outer area (81) and/or in the membrane area (82).