WO2022247194A1 - 乘法器、数据处理方法、芯片、计算机设备及存储介质 - Google Patents

乘法器、数据处理方法、芯片、计算机设备及存储介质 Download PDF

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WO2022247194A1
WO2022247194A1 PCT/CN2021/134297 CN2021134297W WO2022247194A1 WO 2022247194 A1 WO2022247194 A1 WO 2022247194A1 CN 2021134297 W CN2021134297 W CN 2021134297W WO 2022247194 A1 WO2022247194 A1 WO 2022247194A1
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data
processed
circuit
control signal
multiplication
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PCT/CN2021/134297
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English (en)
French (fr)
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霍冠廷
王文强
徐宁仪
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上海阵量智能科技有限公司
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Publication of WO2022247194A1 publication Critical patent/WO2022247194A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/491—Computations with decimal numbers radix 12 or 20.
    • G06F7/4915—Multiplying; Dividing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present disclosure relates to the technical field of integrated circuits, in particular, to a multiplier, a data processing method, a chip, computer equipment, and a storage medium.
  • Neural network is an algorithmic mathematical model that imitates the behavior characteristics of animal neural networks and performs distributed parallel information processing. It is a nonlinear and adaptive information processing system composed of a large number of processing units interconnected. Research on neural networks can promote or accelerate the development of artificial intelligence.
  • Convolution calculation is one of the main functions that need to be realized in the neural network processing circuit.
  • the multiplier is the basic unit that constitutes the neural network processing circuit. A large number of convolution calculations make the power consumption of the multiplier become the work consumed by the neural network processing circuit. major part of consumption. How to reduce the power consumption of the multiplier during the multiplication process has become an urgent problem to be solved.
  • Embodiments of the present disclosure at least provide a multiplier, a data processing method, a chip, a computer device, and a storage medium.
  • an embodiment of the present disclosure provides a multiplier, including: a control circuit, and a multiplication circuit;
  • control circuit is configured to determine the input of at least two first data to be processed; in response to the absence of preset data in the at least two first data to be processed, the at least two first data to be processed Data transmission to the multiplication circuit, and receive the result data transmitted by the multiplication circuit; output the result data;
  • the multiplication operation circuit is configured to, when receiving the at least two first data to be processed transmitted by the control circuit, perform multiplication processing on the at least two first data to be processed to obtain the result data, and The resulting data is communicated to the control circuit.
  • control circuit controls whether to transmit the first data to be processed to the multiplication circuit, and the first data to be processed will be transmitted to the multiplication operation only when there is no preset data in the first data to be processed
  • the circuit performs multiplication processing; the power consumption when the multiplication operation circuit performs multiplication processing can be reduced.
  • control circuit is also used for:
  • the preset data is used as result data of multiplication of the at least two first data to be processed.
  • the preset data when there is preset data in at least two data to be processed, the preset data will be used as the result data of the multiplication process on the at least two first data to be processed, so that the data to be processed will not be transmitted to the multiplication Operation circuit, when the data input to the multiplication circuit remains unchanged, there will be no signal inversion inside the multiplication circuit. If there is no signal inversion, there will be no power consumption due to signal inversion, thereby reducing the power of multiplication processing. consumption.
  • control circuit includes: a control signal generation circuit, and a result output circuit;
  • the control signal generating circuit is configured to determine whether the preset data exists in the at least two first data to be processed after receiving the at least two first data to be processed; in response to the at least two There is the preset data in the first data to be processed, generating a first control signal, and transmitting the first control signal to the result output circuit;
  • the result output circuit is configured to, in response to receiving the first control signal, use the preset data as the result data of multiplying the at least two first data to be processed, and output the result data .
  • control signal generating circuit is further configured to generate a second control signal in response to the absence of the preset data in the at least two first data to be processed, and report to the result an output circuit transmitting the second control signal;
  • the result output circuit is further configured to output the result data transmitted by the multiplication operation circuit in response to receiving the second control signal.
  • control signal generating circuit includes: a first data selector respectively corresponding to the at least two first data to be processed, and a control signal generator; the first data selector The output terminal is connected to the input terminal of the control signal generator;
  • the first data selector is configured to send an indication signal to the control signal generator based on the corresponding first data to be processed in response to receiving the corresponding first data to be processed; the indication signal is used to indicate the Whether the corresponding first data to be processed is the preset data;
  • the control signal generator is configured to generate the first control signal in response to at least one of the received indication signals indicating that the corresponding first data to be processed is preset data.
  • control signal generator is further configured to generate the second control signal in response to the received indication signals indicating that the corresponding first data to be processed is not preset data.
  • control signal generator includes: an AND gate circuit or an OR gate circuit.
  • the result output circuit includes: a second data selector
  • the control signal input terminal of the second data selector is connected to the output terminal of the control signal generating circuit
  • the first input interface of the second data selector is connected to the output interface of the multiplication circuit
  • the second input interface of the second data selector is used for inputting the preset data.
  • control circuit further includes: a data transmission circuit
  • the control signal generation circuit is further configured to transmit the first control signal to the data transmission circuit in response to the presence of the preset data in the at least two first data to be processed;
  • the data transmission circuit is further configured to, in response to receiving the first control signal, shield the at least two pieces of first data to be processed from the multiplication circuit.
  • the data transmission circuit is further configured to, in response to receiving the first control signal, transmit the second data to be processed to the multiplication circuit, where the second data to be processed It is the at least two first data to be processed previously transmitted to the multiplication circuit.
  • control signal generating circuit is further configured to transmit the second control signal
  • the data transmission circuit is further configured to transmit the at least two first pieces of data to be processed to the multiplication circuit in response to receiving the second control signal.
  • the data transmission circuit includes: a third data selector respectively corresponding to the at least two first data to be processed;
  • the output end of the third data selector is connected to the input end of the multiplication circuit
  • the third data selector is configured to receive the first data to be processed corresponding to the third data selector; in response to receiving the second control signal transmitted by the control signal generating circuit, to the multiplication circuit and transmitting the first data to be processed corresponding to the third data selector.
  • the third data selector is further configured to transmit the second data to be processed to the multiplication circuit in response to receiving the first control signal transmitted by the control signal generating circuit.
  • the data transmission circuit further includes: a register corresponding to each of the third data selectors;
  • the register is used to store the second data to be processed
  • the third data selector is configured to read the second data to be processed from a corresponding register when transmitting the second data to be processed to the multiplication circuit, and transmit the second data to be processed to the multiplication circuit. Describe the second data to be processed.
  • the third data selector when the third data selector transmits the first data to be processed corresponding to the third data selector to the multiplication circuit, it is also used to: transmit the data to the corresponding register
  • the first to-be-processed data corresponding to the third data selector controls the second to-be-processed data stored in the corresponding register, and updates it to the first to-be-processed data corresponding to the third data selector.
  • an embodiment of the present disclosure provides a data processing method, which is applied to a multiplier, and the multiplier includes: a control circuit, and a multiplication operation circuit;
  • the data processing methods include:
  • the control circuit determines the input of at least two first data to be processed; in response to the absence of preset data in the at least two first data to be processed, transmits the at least two first data to be processed to the A multiplication circuit, and receive the result data transmitted by the multiplication circuit; output the result data;
  • the multiplication circuit When the multiplication circuit receives the at least two first data to be processed transmitted by the control circuit, it multiplies the at least two first data to be processed to obtain the result data, and converts the The resulting data is transmitted to the control circuit.
  • the data processing method further includes: the control circuit, in response to preset data in the at least two first data to be processed, using the preset data as a reference to the at least two The result data of the multiplication processing of the first data to be processed.
  • control circuit includes: a control signal generation circuit, and a result output circuit;
  • the control circuit determines whether there is preset data in the at least two input first data to be processed; if it exists, the preset data is used as the result data of the multiplication process for the at least two first data to be processed, include:
  • the control signal generation circuit After receiving the at least two first data to be processed, the control signal generation circuit determines whether the preset data exists in the at least two first data to be processed; in response to the at least two first data to be processed The preset data exists in the processing data, a first control signal is generated, and the first control signal is transmitted to the result output circuit;
  • the result output circuit uses the preset data as the result data of multiplication of the at least two first data to be processed, and outputs the result data.
  • the data processing method further includes: the control signal generating circuit generates a second control signal in response to the absence of the preset data among the at least two first data to be processed, and transmitting the second control signal to the result output circuit;
  • the result output circuit outputs the result data transmitted by the multiplication operation circuit in response to receiving the second control signal.
  • control signal generating circuit includes: a first data selector respectively corresponding to the at least two first data to be processed, and a control signal generator; the first data selector The output terminal is connected to the input terminal of the control signal generator;
  • the control signal generating circuit sends an indication signal to the control signal generator based on the corresponding first data to be processed in response to receiving the corresponding first data to be processed; the indication signal is used to indicate the corresponding first Whether the data to be processed is the preset data;
  • the control signal generator generates the first control signal in response to at least one of the received indication signals indicating that the corresponding first data to be processed is preset data.
  • the generating the second control signal includes: the control signal generator generating the second control signal in response to the received indication signals indicating that the corresponding first data to be processed is not preset data. Two control signals.
  • control signal generator includes: an AND gate circuit or an OR gate circuit.
  • the result output circuit includes: a second data selector; the control signal input terminal of the second data selector is connected to the output terminal of the control signal generating circuit; the second data The first input interface of the selector is connected to the output interface of the multiplication circuit; the second input interface of the second data selector is used to input the preset data.
  • control circuit further includes: a data transmission circuit
  • the data processing method further includes: the control signal generation circuit transmits the first control signal to the data transmission circuit in response to the presence of the preset data in the at least two first data to be processed;
  • the data transmission circuit In response to receiving the first control signal, the data transmission circuit masks the at least two first pieces of data to be processed from the multiplication circuit.
  • the data processing method further includes: the data transmission circuit transmits the second data to be processed to the multiplication circuit in response to receiving the first control signal, wherein the first The two data to be processed are the at least two first data to be processed previously transmitted to the multiplication circuit.
  • the data processing method further includes: the control signal generation circuit transmits to the data transmission circuit in response to the absence of the preset data in the at least two first data to be processed said second control signal;
  • the data transmission circuit transmits the at least two first pieces of data to be processed to the multiplication circuit in response to receiving the second control signal.
  • the data transmission circuit includes: a third data selector respectively corresponding to the at least two first data to be processed; an output terminal of the third data selector is connected to the The input terminal connection;
  • Transmitting the at least two first data to be processed to the multiplication circuit includes:
  • the third data selector receives the first data to be processed corresponding to the third data selector; in response to receiving the second control signal transmitted by the control signal generating circuit, transmits the data corresponding to the multiplication operation circuit to the multiplication operation circuit The first data to be processed corresponding to the third data selector.
  • the data processing method further includes: the third data selector transmits the first control signal to the multiplication circuit in response to receiving the first control signal transmitted by the control signal generating circuit. 2. Data to be processed.
  • the data transmission circuit further includes: a register corresponding to each of the third data selectors; the register is used to store the second data to be processed;
  • the third data selector transmitting the second data to be processed to the multiplication circuit includes: reading the second data to be processed from a corresponding register, and transmitting the second data to the multiplication circuit pending data.
  • the third data selector transmitting the first data to be processed corresponding to the third data selector to the multiplication circuit includes: transmitting the third data to a corresponding register
  • the first to-be-processed data corresponding to the selector controls the second to-be-processed data stored in the corresponding register, and updates it to the first to-be-processed data corresponding to the third data selector.
  • an embodiment of the present disclosure provides a chip, including: the multiplier according to any one of the first aspect.
  • an embodiment of the present disclosure provides a computer device, including: a processor, a memory, and the multiplier according to any one of the first aspect, or including the chip according to the third aspect.
  • an embodiment of the present disclosure provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is run by a computer device, the computer device performs any of the tasks described in the second aspect. A step of the described data processing method.
  • FIG. 1 shows a schematic structural diagram of a multiplier provided by an embodiment of the present disclosure.
  • FIG. 2 shows a schematic structural diagram of another multiplier provided by an embodiment of the present disclosure.
  • FIG. 3 shows a schematic structural diagram of another multiplier provided by an embodiment of the present disclosure.
  • Fig. 4 shows a flowchart of a data processing method provided by an embodiment of the present disclosure.
  • convolution calculation is one of the main functions that need to be realized in the neural network processing circuit, and there are a lot of multiplication processing in the convolution calculation, and the multiplier is the basic unit that constitutes the neural network processing circuit to realize convolution.
  • Multiplication processing during operation When the multiplier multiplies the first data to be processed, every time the data input to the multiplier changes, a large number of signal inversions will be generated inside the multiplier to realize the multiplication of the first data to be processed; and the signal inversion , will lead to an increase in power consumption.
  • the more convolutional layers in the neural network the more convolutional processing operations it brings.
  • a deep learning model usually contains millions or even tens of millions of parameters and dozens or even dozens of layers.
  • the network brings a huge amount of computing overhead.
  • activation functions in many network layers, such as the activation function Relu.
  • Relu activation function
  • the above situation leads to a large number of multipliers or multiplicands being 0 in the calculation of the subsequent convolutional layer, and when one input is 0 and the other input is not 0, although the result is 0, but because the input to the multiplier If the data of the multiplier changes, it will cause a large number of signal inversions inside the multiplier, resulting in a huge increase in the power consumption of the multiplier. Therefore, reducing the power consumption during the multiplication process has become an urgent problem to be solved at present.
  • the present disclosure provides a multiplier, which controls whether the first data to be processed is to be transmitted to the multiplication circuit for multiplication processing through the control circuit, and only when there is no preset data in the first data to be processed, the The first data to be processed is transmitted to the multiplication operation circuit for multiplication processing, thereby reducing power consumption when the multiplication operation circuit performs multiplication processing.
  • the multiplier provided in the embodiment of the present disclosure can be applied to a computer device, and the computer device includes, for example: a terminal device or a server or other
  • the processing device the terminal device may be user equipment (User Equipment, UE), mobile device, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (Personal Digital Assistant, PDA), handheld device, computing device, vehicle-mounted device, wearable devices etc.
  • Multipliers can also be used in chips, such as neural network processing chips, artificial intelligence chips, etc.
  • the multiplier can perform multiplication during convolution processing, and can also be used for multiplication of other data.
  • FIG. 1 it is a schematic diagram of a multiplier provided by an embodiment of the present disclosure, including: a control circuit 10 and a multiplication circuit 20;
  • control circuit 10 is configured to determine the input of at least two first data to be processed; in response to the absence of preset data in the at least two first data to be processed, the at least two first data to be processed The processed data is transmitted to the multiplication circuit, and the result data transmitted by the multiplication circuit is received; the result data is output;
  • the multiplication operation circuit 20 is configured to, when receiving at least two first data to be processed transmitted by the control circuit 10, perform multiplication processing on the at least two first data to be processed to obtain the result data, and The resulting data is transmitted to the control circuit 10 .
  • control circuit 10 is also used for:
  • the preset data is used as result data of multiplication of the at least two first data to be processed.
  • control circuit 10 controls whether to transmit the first data to be processed to the multiplication circuit 20, and the first data to be processed will be transmitted to the multiplication circuit 20 only when there is no preset data in the first data to be processed.
  • the multiplication operation circuit 20 performs multiplication processing; the power consumption when the multiplication operation circuit 20 performs the multiplication processing can be reduced.
  • the preset data when there is preset data in at least two data to be processed, the preset data will be used as the result data of multiplication of the at least two first data to be processed, so that the The at least two data to be processed are transmitted to the multiplication circuit. If the data input to the multiplication circuit 20 remains unchanged, signal inversion will not occur inside the multiplication operation circuit 20. The power consumption caused by inversion, thereby reducing the power consumption of multiplication processing.
  • the preset data is, for example: data in which multiple bits are all 0.
  • the embodiment of the present disclosure provides an example of a specific structure of a control circuit 10 , including: a control signal generation circuit 11 and a result output circuit 12 .
  • the control signal generating circuit 11 is configured to determine whether the preset data exists in the at least two first data to be processed after receiving the at least two first data to be processed; in response to the at least two The preset data exists in the first data to be processed, generate a first control signal, and transmit the first control signal to the result output circuit 12;
  • the result output circuit 12 is configured to, in response to receiving the first control signal, use the preset data as result data for multiplication of the at least two first data to be processed, and output the result data.
  • control signal generation circuit 11 is further configured to generate a second control signal in response to the absence of the preset data in the at least two first data to be processed, and transmit the second control signal to the result output circuit 12 said second control signal;
  • the result output circuit 12 is further configured to output the result data transmitted by the multiplication circuit 20 in response to receiving the second control signal.
  • the embodiment of the present disclosure also provides a specific structural example of a multiplier.
  • the control signal generation circuit 11 includes: first data respectively corresponding to the at least two first data to be processed A selector 111, and a control signal generator 112; the output end of the first data selector 111 is connected to the input end of the control signal generator 112;
  • the first data selector 111 is configured to send an indication signal to the control signal generator 112 based on the corresponding first data to be processed in response to receiving the corresponding first data to be processed; the indication signal is used for indicating whether the corresponding first data to be processed is the preset data;
  • the control signal generator 112 is configured to generate the first control signal in response to at least one of the received indication signals indicating that the corresponding first data to be processed is preset data.
  • the number of first data selectors 111 is the same as the maximum number of first data to be processed; for example, if at most 5 first data to be processed are multiplied during use of the multiplier, then The number of first data selectors 111 is 5; if at most 3 pieces of first data to be processed are multiplied, the number of first data selectors 111 is 3.
  • the number of first data to be processed may be the same or different; the number of first data to be processed input in a certain processing cycle is less than that of the first data selection
  • the number of devices 111 only the first data selector 111 of the first data to be processed input is valid, and other first data selectors 111 without the first data to be processed input can be set to an invalid state to realize Processing of the first data selector 111 with no first data to be processed input.
  • first data to be processed there are 2 first data to be processed, and the 2 first data to be processed are respectively: data_a and data_b, data_a and data_b are respectively input to two first data selectors 111, and data_a and data_b serves as control signals of the two first data selectors 111 respectively, so as to control the two first data selectors 111 to output respective corresponding indication signals.
  • the value of the indication signal can be 0 or 1.
  • the value of the indication signal output by a certain first data selector 111 is 0, it represents the first waiting data input to the first data selector 111.
  • the processing data is preset data.
  • the value of the indication signal output by the first data selector 111 is 1, it means that the first data to be processed input to the first data selector 111 is not preset data.
  • the value of the indication signal output by a certain first data selector 111 is 1, it indicates that the first data to be processed input to the first data selector 111 is preset data.
  • the value of the indication signal output by the first data selector 111 is 0, it means that the first data to be processed input to the first data selector 111 is not preset data.
  • the value is 11 or 00, and 11 and 00 are used to represent different situations of the meaning of the indication signal, which can be set according to actual needs.
  • the control signal generator 112 After the indication signal from the first data selector 111 is transmitted to the control signal generator 112, it is determined whether there is an indication signal indicating that the corresponding first data to be processed is preset data in the received indication signal. If present, a first control signal is generated.
  • control signal generator 112 is further configured to generate the second control signal in response to the received indication signals indicating that the corresponding first data to be processed is not preset data.
  • control signal generator 112 is, for example, a circuit formed by a logic gate circuit, such as an AND gate circuit or an OR gate circuit.
  • control signal generator 112 is an AND gate circuit
  • the logic of the AND gate circuit is: all input signals are high-level signals before outputting 1, if any of the input signals is low-level, then The output is 0, so when the value of the indication signal is 1, it indicates that the corresponding first data to be processed is not preset data; when the value of the indication signal is 0, it indicates that the corresponding first data to be processed is Preset data; if any first data to be processed in the first data to be processed is preset data, the value of the indication signal corresponding to the first data to be processed is 0, and the output result of the AND gate circuit is 0 , using 0 as the first control signal to indicate that the preset data is used as the result data of multiplication of the at least two first data to be processed.
  • control signal generator 112 is an OR gate circuit
  • the logic of the OR gate circuit is: as long as the input signal has a high level, it will output 1, and if the input signals are all low level signals, the output is 0, therefore, when the value of the indication signal is 0, it can be indicated that the corresponding first data to be processed is preset data, and when the value of the indication signal is 1, it can be indicated that the corresponding first data to be processed is not preset data.
  • control signal generator 112 can also be formed by other logic gate devices, and the symbolic meaning of the signal value can be determined according to the specific situation, which is not limited in this embodiment of the present disclosure.
  • control signal generator 112 After the control signal generator 112 generates the first control signal, it transmits the first control signal to the result output circuit 12 . After receiving the first control signal, the result output circuit 12 outputs the preset data as result data.
  • the result output circuit 12 includes, for example: a second data selector 121 .
  • the control signal input end of the second data selector 121 is connected to the output end of the control signal generating circuit 11;
  • the first input interface of the second data selector 121 is connected to the output interface of the multiplication circuit 20; the second input interface of the second data selector 121 is used to input the preset data.
  • the second data selector 121 connects the output path between the second input interface and the output interface of the second data selector 121, thereby providing The outside world directly transmits preset data.
  • the second data selector 121 When the signal transmitted to the result output circuit 12 is the second control signal, the second data selector 121 gates the output path between the first input interface and the output interface of the second data selector 121, thereby to the outside world The result data transferred by the multiplication operation circuit 20 is transferred.
  • control circuit 10 further includes: a data transmission circuit 13 .
  • the control signal generation circuit 11 is further configured to transmit the first control signal to the data transmission circuit 13 in response to the presence of the preset data in the at least two first data to be processed;
  • the data transmission circuit 13 is further configured to, in response to receiving the first control signal, shield the at least two pieces of first data to be processed from the multiplication circuit.
  • the data transmission circuit 13 shields the first data to be processed transmitted to the multiplication operation circuit 20, so that the multiplication operation circuit 20 does not perform multiplication processing on the first data to be processed, thereby avoiding the multiplication operation of the multiplication operation circuit 20.
  • the signal inversion that occurs when the first data to be processed is processed does not need to process the first data to be processed to generate power consumption, thus reducing the power consumption during the multiplication process.
  • the data transmission circuit 13 is further configured to transmit the second data to be processed to the multiplication circuit in response to receiving the first control signal, wherein the second data to be processed It is the at least two first data to be processed previously transmitted to the multiplication circuit.
  • the input port of the multiplication circuit 20 cannot be left floating. If the input port of the multiplication circuit 20 is empty, it may cause circuit breakdown or incorrect input caused by environmental reasons. Therefore, in the example of the present disclosure, the data transmission circuit 13 After receiving the first control signal, the second data to be processed will also be transmitted to the multiplication circuit, so that the multiplication circuit 20 performs a process corresponding to the previous multiplication process once.
  • the processing corresponding to the previous multiplication processing will not generate power consumption due to signal inversion, and can also avoid circuit breakdown caused by floating input terminals of the multiplication circuit 20 or incorrect input caused by environmental reasons.
  • control signal generating circuit 11 is further configured to transmit the second control signal
  • the data transmission circuit 13 is further configured to transmit the at least two first pieces of data to be processed to the multiplication circuit 20 after receiving the second control signal.
  • control signal generation circuit 11 transmits the second control signal to the data transmission circuit 13 when there is no preset data in the first data to be processed, and the data transmission circuit 13 transmits the second control signal to the multiplication operation after receiving the second control signal.
  • the circuit 20 transmits the first data to be processed, so that the multiplication circuit 20 can perform multiplication processing on the first data to be processed to obtain result data of the multiplication processing.
  • the embodiment of the present disclosure also provides a specific structure of the data transmission circuit 13, including: a third data selector 131 respectively corresponding to the at least two first data to be processed;
  • the output end of the third data selector 131 is connected to the input end of the multiplication circuit 20;
  • the third data selector 131 is configured to receive the first data to be processed corresponding to the third data selector 131; after receiving the second control signal transmitted by the control signal generating circuit 11, send the data to the The multiplication circuit 20 transmits the first data to be processed corresponding to the third data selector 131 .
  • the output end of the control signal generating circuit 11 is connected to the control signal input end of the third data selector 131; the first input end of the third data selector 131 is used for external input of the first data to be processed; After the third data selector 131 receives the second control signal, the data path between the first input terminal of the third data selector 131 and the data output terminal of the third data selector 131 is selected, so that the corresponding The data to be processed is transmitted to the multiplication circuit 20 .
  • the third data selector 131 is further configured to transmit the second data to be processed to the multiplication circuit 20 after receiving the first control signal transmitted by the control signal generating circuit 11 , wherein the second data to be processed is the first data to be processed previously transmitted to the multiplication circuit 20 .
  • the second input terminal of the third data selector is used to input the second data to be processed.
  • the third data selector 131 receives the first control signal, the data path between the second input terminal and the data output terminal of the third data selector 131 is selected to transmit the second data to be processed to the multiplication circuit 20.
  • the register 132 is used to store the second data to be processed
  • the third data selector 131 is configured to read the second data to be processed from the corresponding register 132 when transmitting the second data to be processed to the multiplication circuit 20, and send the data to the multiplication circuit 20 Transmit the second data to be processed.
  • the third data selector 131 transmits the first data to be processed corresponding to the third data selector 131 to the multiplication circuit 20, it is also used to: transmit the data to the corresponding register 132.
  • the first data to be processed corresponding to the third data selector 131 is controlled to update the second data to be processed corresponding to the register 132 to the first data to be processed corresponding to the third data selector 131 .
  • the data stored in the register 132 is updated so that the input of 0 appears in the next processing cycle of the current processing cycle
  • the data to be processed in the current processing cycle can be used as the input of the multiplication circuit 20 to avoid circuit breakdown caused by the input of the multiplication circuit 20 floating or incorrect input caused by environmental reasons.
  • first data to be processed there are 2 first data to be processed, and the 2 first data to be processed are respectively: data_a and data_b, and data_a and data_b are input to two third data selectors 131 respectively;
  • the third data selectors 131 are respectively connected with registers 132.
  • data_a is input to the third data selector 131; after receiving the first control signal transmitted by the control signal generating circuit, the third data selector 131 strobes connected to the register 132 The input terminal and the signal output terminal transmit the second data to be processed stored in the register 132 to the multiplier circuit as data multi_a to be multiplied in the current processing cycle.
  • the third data selector 131 After receiving the second control signal transmitted by the control signal generating circuit, the third data selector 131 is gated and connected to the input terminal of input data_a and the signal output terminal, and the first data to be processed data_a is used as the current processing cycle to be multiplied The processed data multi_a is transferred to the multiplier circuit.
  • the embodiment of the present disclosure also provides a data processing method corresponding to the multiplier. Since the problem-solving principle of the method in the embodiment of the present disclosure is similar to that of the above-mentioned multiplier in the embodiment of the present disclosure, the implementation of the method can be found in The implementation of the multiplier will not be repeated here.
  • FIG. 4 it is a flowchart of a data processing method provided by an embodiment of the present disclosure, which is applied to a multiplier, and the multiplier includes: a control circuit and a multiplication circuit;
  • the data processing methods include:
  • the control circuit determines at least two input first data to be processed; in response to the absence of preset data in the at least two first data to be processed, transmit the at least two first data to be processed to The multiplication circuit, and receives the result data transmitted by the multiplication circuit;
  • control circuit includes: a control signal generation circuit, and a result output circuit;
  • the control circuit determines whether there is preset data in the at least two input first data to be processed; if it exists, the preset data is used as the result data of the multiplication process for the at least two first data to be processed, include:
  • the control signal generation circuit After receiving the at least two first data to be processed, the control signal generation circuit determines whether the preset data exists in the at least two first data to be processed; in response to the at least two first data to be processed The preset data exists in the processing data, a first control signal is generated, and the first control signal is transmitted to the result output circuit;
  • the result output circuit uses the preset data as the result data of multiplication of the at least two first data to be processed, and outputs the result data.
  • the data processing method further includes: the control signal generating circuit generates a second control signal in response to the absence of the preset data among the at least two first data to be processed, and transmitting the second control signal to the result output circuit;
  • the result output circuit outputs the result data transmitted by the multiplication operation circuit in response to receiving the second control signal.
  • control signal generating circuit includes: a first data selector respectively corresponding to the at least two first data to be processed, and a control signal generator; the first data selector The output terminal is connected to the input terminal of the control signal generator;
  • the control signal generating circuit sends an indication signal to the control signal generator based on the corresponding first data to be processed in response to receiving the corresponding first data to be processed; the indication signal is used to indicate the corresponding first Whether the data to be processed is the preset data;
  • the control signal generator generates the first control signal in response to at least one of the received indication signals indicating that the corresponding first data to be processed is preset data.
  • the generating the second control signal includes: the control signal generator generating the second control signal in response to the received indication signals indicating that the corresponding first data to be processed is not preset data. Two control signals.
  • control signal generator includes: an AND gate circuit or an OR gate circuit.
  • the result output circuit includes: a second data selector; the control signal input terminal of the second data selector is connected to the output terminal of the control signal generating circuit; the second data The first input interface of the selector is connected to the output interface of the multiplication circuit; the second input interface of the second data selector is used to input the preset data.
  • control circuit further includes: a data transmission circuit
  • the data processing method further includes: the control signal generation circuit transmits the first control signal to the data transmission circuit in response to the presence of the preset data in the at least two first data to be processed;
  • the data transmission circuit In response to receiving the first control signal, the data transmission circuit masks the at least two first pieces of data to be processed from the multiplication circuit.
  • the data processing method further includes: the data transmission circuit transmits the second data to be processed to the multiplication circuit in response to receiving the first control signal, wherein the first The two data to be processed are the at least two first data to be processed previously transmitted to the multiplication circuit.
  • the data processing method further includes: the control signal generation circuit transmits to the data transmission circuit in response to the absence of the preset data in the at least two first data to be processed said second control signal;
  • the data transmission circuit transmits the at least two first pieces of data to be processed to the multiplication circuit in response to receiving the second control signal.
  • the data transmission circuit includes: a third data selector respectively corresponding to the at least two first data to be processed; an output terminal of the third data selector is connected to the The input terminal connection;
  • Transmitting the at least two first data to be processed to the multiplication circuit includes:
  • the third data selector receives the first data to be processed corresponding to the third data selector; in response to receiving the second control signal transmitted by the control signal generating circuit, transmits the data corresponding to the multiplication operation circuit to the multiplication operation circuit The first data to be processed corresponding to the third data selector.
  • the data processing method further includes: the third data selector transmits the first control signal to the multiplication circuit in response to receiving the first control signal transmitted by the control signal generating circuit. 2. Data to be processed.
  • the data transmission circuit further includes: a register corresponding to each of the third data selectors; the register is used to store the second data to be processed;
  • the third data selector transmitting the second data to be processed to the multiplication circuit includes: reading the second data to be processed from a corresponding register, and transmitting the second data to the multiplication circuit pending data.
  • the third data selector transmitting the first data to be processed corresponding to the third data selector to the multiplication circuit includes: transmitting the third data to a corresponding register
  • the first to-be-processed data corresponding to the selector controls the second to-be-processed data stored in the corresponding register, and updates it to the first to-be-processed data corresponding to the third data selector.
  • An embodiment of the present disclosure further provides a chip, including the multiplier according to any one of the first aspect.
  • An embodiment of the present disclosure further provides a computer device, including: a processor, a memory, and the multiplier according to any embodiment of the present disclosure, or including the chip provided by the embodiment of the present disclosure.
  • An embodiment of the present disclosure also provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium.
  • a computer program is stored on the computer-readable storage medium.
  • the computer device executes the method provided by any embodiment of the present disclosure. The steps of the data processing method.
  • the embodiment of the present disclosure also provides a computer program product, the computer program product carries a program code, and the instructions included in the program code can be used to execute the steps of data processing described in the above method embodiment, for details, please refer to the above method implementation example, which will not be repeated here.
  • the above-mentioned computer program product may be specifically implemented by means of hardware, software or a combination thereof.
  • the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK) etc. Wait.
  • the units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.
  • each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit.
  • the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium executable by a processor.
  • the technical solution of the present disclosure is essentially or the part that contributes to the prior art or the part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including Several instructions are used to make a computer device (which may be a personal computer, a server, or a network device, etc.) execute all or part of the steps of the methods described in various embodiments of the present disclosure.
  • the aforementioned storage media include: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disc and other media that can store program codes. .

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Abstract

本公开提供了一种乘法器、数据处理方法、芯片、计算机设备及存储介质，其中乘法器，包括：控制电路、以及乘法运算电路；其中，所述控制电路，用于确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；输出所述结果数据；所述乘法运算电路，用于接收到所述控制电路传输的所述至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路传输。

Description

乘法器、数据处理方法、芯片、计算机设备及存储介质
相关申请的交叉引用
本申请要求于2021年5月22日提交中国专利局的申请号为202110561400.X的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本公开涉及集成电路技术领域，具体而言，涉及一种乘法器、数据处理方法、芯片、计算机设备及存储介质。
背景技术
人工智能作为新一轮科技革命和产业变革的核心驱动力，正快速催生新产品、新服务、新业态，重塑着经济社会运行模式，改变人类生产和生活方式。神经网络是一种模仿动物神经网络行为特征，进行分布式并行信息处理的算法数学模型，是由大量处理单元互联组成的非线性、自适应信息处理系统。神经网络的研究能促进或者加快人工智能的发展。
卷积计算是神经网络处理电路中需要实现的主要功能之一，乘法器是构成神经网络处理电路的基础单元，大量的卷积计算使得乘法器消耗的功耗成为神经网络处理电路所消耗的功耗的主要部分。如何减少乘法器在进行乘法处理时的功耗成为当前亟待解决的问题。
发明内容
本公开实施例至少提供一种乘法器、数据处理方法、芯片、计算机设备及存储介质。
第一方面，本公开实施例提供了一种乘法器，包括：控制电路、以及乘法运算电路；
其中，所述控制电路，用于确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；输出所述结果数据；
所述乘法运算电路，用于接收到所述控制电路传输的所述至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路传输。
本公开实施例通过控制电路对是否要将第一待处理数据传输给乘法运算电路进行控制，在第一待处理数据中不存在预设数据时，才会将第一待处理数据传输给乘法运算电路进行乘法处理；能够减少乘法运算电路执行乘法处理时的功耗。
一种可能的实施方式中，所述控制电路，还用于：
响应于所述至少两个第一待处理数据中存在预设数据，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据。
这样，在至少两个待处理数据中存在预设数据时，会将预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，从而不会将待处理数据传输给乘法运算电路，输入至乘法运算电路的数据不变的情况下，乘法运算电路内部便不会发生信号翻转，信号无翻转，则不会产生由于信号翻转带来的功耗，进而降低乘法处理的功耗。
一种可能的实施方式中，所述控制电路包括：控制信号生成电路、以及结果输出电路；
所述控制信号生成电路，用于在接收所述至少两个第一待处理数据后，确定所述至少两个第一待处理数据中是否存在所述预设数据；响应于所述至少两个第一待处理数据中存在所述预设数据，生成第一控制信号，并向所述结果输出电路传输所述第一控制信号；
所述结果输出电路，用于响应于接收到所述第一控制信号，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，并输出所述结果数据。
一种可能的实施方式中，所述控制信号生成电路，还用于响应于所述至少两个第一待处理数据中不存在所述预设数据，生成第二控制信号，并向所述结果输出电路传输所述第二控制信号；
所述结果输出电路，还用于响应于接收到所述第二控制信号，输出所述乘法运算电路传输的结果数据。
一种可能的实施方式中，所述控制信号生成电路，包括：与所述至少两个第一待处理数据分别对应的第一数据选择器、以及控制信号生成器；所述第一数据选择器的输出端与所述控制信号生成器的输入端连接；
所述第一数据选择器，用于响应于接收到对应第一待处理数据，基于所述对应第一待处理数据，向所述控制信号生成器发送指示信号；所述指示信号用于指示所述对应第一待处理数据是否为所述预设数据；
所述控制信号生成器，用于响应于接收到的指示信号中有至少一个指示信号指示所述对应第一待处理数据为预设数据，生成所述第一控制信号。
一种可能的实施方式中，所述控制信号生成器，还用于响应于接收到的所述指示信号均指示对应第一待处理数据并非预设数据，生成所述第二控制信号。
一种可能的实施方式中，所述控制信号生成器包括：与门电路、或者或门电路。
一种可能的实施方式中，所述结果输出电路包括：第二数据选择器；
所述第二数据选择器的控制信号输入端与所述控制信号生成电路的输出端连接；
所述第二数据选择器的第一输入接口与所述乘法运算电路的输出接口连接；
所述第二数据选择器的第二输入接口用于输入所述预设数据。
一种可能的实施方式中，所述控制电路，还包括：数据传输电路；
所述控制信号生成电路，还用于响应于在所述至少两个第一待处理数据中存在所述预设数据，向所述数据传输电路传输所述第一控制信号；
所述数据传输电路，还用于响应于接收到所述第一控制信号，向所述乘法运算电路屏蔽所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据传输电路，还用于响应于接收到所述第一控制信号，向所述乘法运算电路传输第二待处理数据，其中，所述第二待处理数据为前一次向所述乘法运算电路传输的所述至少两个第一待处理数据。
一种可能的实施方式中，所述控制信号生成电路，还用于响应于所述至少两个第一待处理数据中不存在所述预设数据，向所述数据传输电路传输所述第二控制信号；
所述数据传输电路，还用于响应于接收到所述第二控制信号，向所述乘法运算电路 传输所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据传输电路，包括：与所述至少两个第一待处理数据分别对应的第三数据选择器；
所述第三数据选择器的输出端与所述乘法运算电路的输入端连接；
所述第三数据选择器，用于接收与所述第三数据选择器对应的第一待处理数据；响应于接收到所述控制信号生成电路传输的第二控制信号，向所述乘法运算电路传输与所述第三数据选择器对应的第一待处理数据。
一种可能的实施方式中，所述第三数据选择器，还用于响应于接收到所述控制信号生成电路传输的第一控制信号，向所述乘法运算电路传输所述第二待处理数据。
一种可能的实施方式中，所述数据传输电路中还包括：与各所述第三数据选择器对应的寄存器；
所述寄存器用于存储所述第二待处理数据；
所述第三数据选择器，在向所述乘法运算电路传输所述第二待处理数据时，用于从对应寄存器中读取所述第二待处理数据，并向所述乘法运算电路传输所述第二待处理数据。
一种可能的实施方式中，所述第三数据选择器，在向所述乘法运算电路传输与所述第三数据选择器对应的第一待处理数据时，还用于：向对应的寄存器传输所述第三数据选择器对应的第一待处理数据，控制对应寄存器中存储的所述第二待处理数据，更新为所述第三数据选择器对应的第一待处理数据。
第二方面，本公开实施例提供一种数据处理方法，应用于乘法器，所述乘法器包括：控制电路、以及乘法运算电路；
所述数据处理方法包括：
所述控制电路确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；输出所述结果数据；
所述乘法运算电路接收到所述控制电路传输的所述至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路传输。
一种可能的实施方式中，所述数据处理方法还包括：所述控制电路响应于所述至少两个第一待处理数据中存在预设数据，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据。
一种可能的实施方式中，所述控制电路包括：控制信号生成电路、以及结果输出电路；
所述控制电路确定输入的至少两个第一待处理数据中是否存在预设数据；若存在，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，包括：
所述控制信号生成电路在接收所述至少两个第一待处理数据后，确定所述至少两个第一待处理数据中是否存在所述预设数据；响应于所述至少两个第一待处理数据中存在所述预设数据，生成第一控制信号，并向所述结果输出电路传输所述第一控制信号；
所述结果输出电路响应于接收到所述第一控制信号，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，并输出所述结果数据。
一种可能的实施方式中，所述数据处理方法还包括：所述控制信号生成电路响应于所述至少两个第一待处理数据中不存在所述预设数据，生成第二控制信号，并向所述结果输出电路传输所述第二控制信号；
所述结果输出电路响应于接收到所述第二控制信号，输出所述乘法运算电路传输的结果数据。
一种可能的实施方式中，所述控制信号生成电路，包括：与所述至少两个第一待处理数据分别对应的第一数据选择器、以及控制信号生成器；所述第一数据选择器的输出端与所述控制信号生成器的输入端连接；
所述控制信号生成电路响应于接收到对应第一待处理数据，基于所述对应第一待处理数据，向所述控制信号生成器发送指示信号；所述指示信号用于指示所述对应第一待处理数据是否为所述预设数据；
所述控制信号生成器响应于接收到的指示信号中有至少一个指示信号指示所述对应第一待处理数据为预设数据，生成所述第一控制信号。
一种可能的实施方式中，所述生成第二控制信号，包括：所述控制信号生成器响应于接收到的所述指示信号均指示对应第一待处理数据并非预设数据，生成所述第二控制信号。
一种可能的实施方式中，所述控制信号生成器包括：与门电路、或者或门电路。
一种可能的实施方式中，所述结果输出电路包括：第二数据选择器；所述第二数据选择器的控制信号输入端与所述控制信号生成电路的输出端连接；所述第二数据选择器的第一输入接口与所述乘法运算电路的输出接口连接；所述第二数据选择器的第二输入接口用于输入所述预设数据。
一种可能的实施方式中，所述控制电路，还包括：数据传输电路；
所述数据处理方法还包括：所述控制信号生成电路响应于在所述至少两个第一待处理数据中存在所述预设数据，向所述数据传输电路传输所述第一控制信号；
所述数据传输电路响应于接收到所述第一控制信号，向所述乘法运算电路屏蔽所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据处理方法还包括：所述数据传输电路响应于接收到所述第一控制信号，向所述乘法运算电路传输第二待处理数据，其中，所述第二待处理数据为前一次向所述乘法运算电路传输的所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据处理方法还包括：所述控制信号生成电路响应于所述至少两个第一待处理数据中不存在所述预设数据，向所述数据传输电路传输所述第二控制信号；
所述数据传输电路响应于接收到所述第二控制信号，向所述乘法运算电路传输所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据传输电路，包括：与所述至少两个第一待处理数据分别对应的第三数据选择器；第三数据选择器的输出端与所述乘法运算电路的输入端连接；
将所述至少两个第一待处理数据传输给所述乘法运算电路，包括：
所述第三数据选择器接收与所述第三数据选择器对应的第一待处理数据；响应于接收到所述控制信号生成电路传输的第二控制信号，向所述乘法运算电路传输与所述第三 数据选择器对应的第一待处理数据。
一种可能的实施方式中，所述数据处理方法还包括：所述第三数据选择器响应于接收到所述控制信号生成电路传输的第一控制信号，向所述乘法运算电路传输所述第二待处理数据。
一种可能的实施方式中，数据传输电路中还包括：与各所述第三数据选择器对应的寄存器；所述寄存器用于存储所述第二待处理数据；
所述第三数据选择器向所述乘法运算电路传输所述第二待处理数据，包括：从对应寄存器中读取所述第二待处理数据，并向所述乘法运算电路传输所述第二待处理数据。
一种可能的实施方式中，所述第三数据选择器向所述乘法运算电路传输与所述第三数据选择器对应的第一待处理数据，包括：向对应的寄存器传输所述第三数据选择器对应的第一待处理数据，控制对应寄存器中存储的所述第二待处理数据，更新为所述第三数据选择器对应的第一待处理数据。
第三方面，本公开实施例提供一种芯片，包括：如第一方面任一项所述的乘法器。
第四方面，本公开实施例提供一种计算机设备，包括：处理器、存储器，及如第一方面任一项所述的乘法器，或者包括如第三方面所述的芯片。
第四方面，本公开实施例提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时，所述计算机设备执行如第二方面任一项所述的数据处理方法的步骤。
为使本公开的上述目的、特征和优点能更明显易懂，下文给出实施例，并配合所附附图，作详细说明如下。
附图说明
为了更清楚地说明本公开实施例的技术方案，下面将对实施例中所需要使用的附图作简单地介绍，此处的附图被并入说明书中并构成本说明书中的一部分，这些附图示出了符合本公开的实施例，并与说明书一起用于说明本公开的技术方案。应当理解，以下附图仅示出了本公开的某些实施例，因此不应被看作是对范围的限定，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他相关的附图。
图1示出了本公开实施例所提供的一种乘法器的结构示意图。
图2示出了本公开实施例所提供的另一种乘法器的结构示意图。
图3示出了本公开实施例所提供的另一种乘法器的结构示意图。
图4示出了本公开实施例所提供的一种数据处理方法的流程图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例中附图，对本公开实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本公开一部分实施例，而不是全部的实施例。通常在此处描述和示出的本公开实施例的组件可以以各种不同的配置来布置和设计。因此，以下对本公开的实施例的详细描述并非旨在限制要求保护的本公开的范围，而是仅仅表示本公开的选定实施例。基于本公开的实施例，本领域技术人员在没有做出创造性劳动的前提下所获得的所有其他实施 例，都属于本公开保护的范围。
经研究发现，卷积计算是神经网络处理电路中需要实现的主要功能之一，而卷积计算中存在大量的乘法处理，乘法器则是构成神经网络处理电路的基础单元，用以实现卷积运算过程中的乘法处理。乘法器在对第一待处理数据进行乘法处理的时候，输入至乘法器的数据每变化一次，乘法器内部都会产生大量的信号翻转，以实现对第一待处理数据的乘法处理；而信号翻转，则会带来功耗的增加。神经网络中卷积层的数量越多，所带来的卷积处理运算量也越多，一个深度学习模型通常包含数以百万计甚至千万计的参数和十几层甚至几十层的网络，带来了巨量的计算开销。例如在当前神经网络中，很多网络层中存在有激活函数，如激活函数Relu，在利用Relu对特征图进行处理后，导致网络层输出的结果中会存在大量特征点的特征值为0的情况；上述情况导致后续卷积层的计算中，出现大量的乘数或者被乘数为0，而当一个输入为0，另一个输入不为0时，虽然结果为0，但由于输入给乘法器的数据发生了变化，就会导致乘法器内部出现大量信号翻转，造成乘法器功耗的巨增。因此，降低乘法处理过程中的功耗已经成为当前亟待解决的问题。
基于上述研究，本公开提供了一种乘法器，通过控制电路控制第一待处理数据是否要传输给乘法运算电路进行乘法处理，在第一待处理数据中不存在预设数据时，才会将第一待处理数据传输给乘法运算电路进行乘法处理，从而能够减少乘法运算电路执行乘法处理时的功耗。
针对以上问题以及本公开提供的解决方案，均是发明人在经过实践并仔细研究后得出的结果，因此，上述问题的发现过程以及本公开针对上述问题所提出的解决方案，都应该是发明人在本公开过程中对本公开做出的贡献。
应注意到：相似的标号和字母在下面的附图中表示类似项，因此，一旦某一项在一个附图中被定义，则在随后的附图中不需要对其进行进一步定义和解释。
为便于对本实施例进行理解，首先对本公开实施例所公开的一种乘法器进行详细介绍，本公开实施例提供的乘法器可以应用于计算机设备中，计算机设备例如包括：终端设备或服务器或其它处理设备，终端设备可以为用户设备(User Equipment，UE)、移动设备、用户终端、终端、蜂窝电话、无绳电话、个人数字助理(Personal Digital Assistant，PDA)、手持设备、计算设备、车载设备、可穿戴设备等。乘法器还可以用于芯片中，如神经网络处理芯片、人工智能芯片等。该乘法器能够在卷积处理过程中进行乘法处理，也能够用于其他数据的乘法处理。
下面本公开实施例提供的乘法器加以说明。
参见图1所示，为本公开实施例提供的乘法器的示意图，包括：控制电路10、以及乘法运算电路20；
其中，所述控制电路10，用于确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；输出所述结果数据；
所述乘法运算电路20，用于接收到所述控制电路10传输的至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路10传输。
在本公开另一实施例中，所述控制电路10，还用于：
响应于所述至少两个第一待处理数据中存在预设数据，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据。
本公开实施例通过控制电路10对是否要将第一待处理数据传输给乘法运算电路20进行控制，在第一待处理数据中不存在预设数据时，才会将第一待处理数据传输给乘法运算电路20进行乘法处理；能够减少乘法运算电路20执行乘法处理时的功耗。
本公开另一实施例中，在至少两个待处理数据中存在预设数据时，会将预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，从而不会将所述至少两个待处理数据传输给乘法运算电路，输入至乘法运算电路20的数据不变的情况下，乘法运算电路20内部便不会发生信号翻转，信号无翻转，则不会产生由于信号翻转带来的功耗，进而降低乘法处理的功耗。
下面对本公开实施例提供的乘法器加以详细说明。
本公开各实施例中，预设数据例如为：多个比特位均为0的数据。由于输入至乘法器中的第一待处理数据一旦发生变化，就会造成乘法运算电路20内部发生信号翻转，但当至少两个第一待处理数据中的任一第一待处理数据为0时，乘法器所输出的结果均为0，因此，可以在所述至少两个第一待处理数据中存在0数据的情况下，通过控制电路10屏蔽所述至少两个第一待处理数据，并能够通过控制电路10输出正确的乘法处理结果，以使得在所述至少两个第一待处理数据存在0数据的情况下，乘法运算电路20的内部不会发生信号翻转，从而降低乘法运算电路20在执行乘法处理过程中的功耗。
参见图2所示，本公开实施例提供一种控制电路10的具体结构的示例，包括：控制信号生成电路11以及结果输出电路12。
所述控制信号生成电路11，用于在接收所述至少两个第一待处理数据后，确定所述至少两个第一待处理数据中是否存在所述预设数据；响应于所述至少两个第一待处理数据中存在所述预设数据，生成第一控制信号，并向所述结果输出电路12传输所述第一控制信号；
所述结果输出电路12，用于响应于接收到所述第一控制信号，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，并输出所述结果数据。
在具体实施中，控制信号生成电路11，还用于响应于所述至少两个第一待处理数据中不存在所述预设数据，生成第二控制信号，并向所述结果输出电路12传输所述第二控制信号；
所述结果输出电路12，还用于响应于接收到所述第二控制信号，输出所述乘法运算电路20传输的结果数据。
参见图3所示，本公开实施例还提供一种乘法器的具体结构示例，在该实例中，控制信号生成电路11包括：与所述至少两个第一待处理数据分别对应的第一数据选择器111、以及控制信号生成器112；所述第一数据选择器111的输出端与所述控制信号生成器112的输入端连接；
所述第一数据选择器111，用于响应于接收到对应第一待处理数据，基于所述对应第一待处理数据，向所述控制信号生成器112发送指示信号；所述指示信号用于指示所述对应第一待处理数据是否为所述预设数据；
所述控制信号生成器112，用于响应于接收到的指示信号中有至少一个指示信号指示所述对应第一待处理数据为预设数据，生成所述第一控制信号。
此处，第一数据选择器111的数量与要处理的第一待处理数据的最大数量相同；例如，若在乘法器使用过程中，最多将5个第一待处理数据进行相乘处理，则第一数据选择器111的数量为5个；若最多将3个第一待处理数据进行相乘处理，则第一数据选择器111的数量为3个。而在实际使用的过程中，在不同处理周期，所输入的第一待处理 数据的数量可以相同，也可以不同；在某个处理周期输入的第一待处理数据的数量少于第一数据选择器111的数量的情况下，则仅有第一待处理数据输入的第一数据选择器111有效，其他无第一待处理数据输入的第一数据选择器111可以被置为无效状态，以实现无第一待处理数据输入的第一数据选择器111的处理。
在图3对应的示例中，以第一待处理数据有2个，2个第一待处理数据分别为：data_a以及data_b，data_a以及data_b分别输入至两个第一数据选择器111，且data_a以及data_b分别作为两个第一数据选择器111的控制信号，以控制两个第一数据选择器111能够输出各自对应的指示信号。
示例性的，指示信号的取值可以为0或者为1，当某个第一数据选择器111输出的指示信号的取值为0时，表征输入至该第一数据选择器111的第一待处理数据为预设数据。当该第一数据选择器111输出的指示信号的取值为1时，表征输入至该第一数据选择器111的第一待处理数据并非预设数据。或者，当某个第一数据选择器111输出的指示信号的取值为1时，表征输入至该第一数据选择器111的第一待处理数据为预设数据。当该第一数据选择器111输出的指示信号的取值为0时，表征输入至该第一数据选择器111的第一待处理数据并非预设数据。在另一实施例中，也可以为指示信号设置其他的取值，例如取值为11或00，通过11和00来表征指示信号表征含义的不同情况，具体的可以根据实际的需要来进行设定，本公开实施例中不做限定。
第一数据选择器111的指示信号传输给控制信号生成器112后，判断接收到的指示信号中是否存在指示对应第一待处理数据为预设数据的指示信号。若存在，则生成第一控制信号。
在本公开另一实施例中，控制信号生成器112，还用于响应于收到的所述指示信号均指示对应第一待处理数据并非预设数据，生成所述第二控制信号。
此处，控制信号生成器112例如是通过逻辑门电路构成的一电路，例如与门电路、或者或门电路。
其中，在控制信号生成器112为与门电路的情况下，由于与门电路的逻辑为：输入信号所有均为高电平信号才输出1，若输入信号中有任一为低电平，则输出为0，因此可以在指示信号的取值为1的时候，指示对应的第一待处理数据并非预设数据；在指示信号的取值为0的时候，指示对应的第一待处理数据为预设数据；若第一待处理数据中有任一第一待处理数据为预设数据，则与该第一待处理数据对应的指示信号的取值为0，与门电路的输出结果为0，将0作为第一控制信号，用于指示将预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据。反之，若第一待处理数据中不存在预设数据，则与第一待处理数据对应的指示信号取值均为1，与门电路的输出结果为1，将1作为第二控制信号，用于指示将第一待处理数据传输给乘法运算电路20进行乘法处理，得到结果数据。
另外，在控制信号生成器112为或门电路的情况下，由于或门电路的逻辑为：输入信号只要存在高电平，则会输出1，若输入信号均为低电平信号，则输出为0，因此，可以在指示信号的取值为0的时候，指示对应的第一待处理数据为预设数据，在指示信号的取值为1的时候，指示对应的第一待处理数据并非预设数据；若第一待处理数据中有任一第一待处理数据为预设数据，则与该第一待处理数据对应的指示信号的取值为1，或门电路的输出结果为1，将1作为第一控制信号，用于指示将预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据。反之，若第一待处理数据中不存在预设数据，则与第一待处理数据对应的指示信号取值均为0，或门电路的输出结果为0，将0作为第二控制信号，用于指示将第一待处理数据传输给乘法运算电路20进行乘法处理，得到结果数据。
另外，控制信号生成器112还可以通过其他的逻辑门器件构成，信号取值的表征含义可以根据具体的情况来确定，本公开实施例中不做限定。
控制信号生成器112在生成第一控制信号后，向结果输出电路12传输第一控制信号。结果输出电路12在接收到第一控制信号后，将预设数据作为结果数据输出。
其中，参见图3所示，结果输出电路12例如包括：第二数据选择器121。该第二数据选择器121的控制信号输入端与控制信号生成电路11的输出端连接；
所述第二数据选择器121的第一输入接口与所述乘法运算电路20的输出接口连接；所述第二数据选择器121的第二输入接口用于输入所述预设数据。
这样，当传输给结果输出电路12的信号为第一控制信号的情况下，第二数据选择器121连通第二输入接口、和第二数据选择器121的输出接口之间的输出通路，从而向外界直接传输预设数据。
当传输给结果输出电路12的信号为第二控制信号的情况下，第二数据选择器121选通第一输入接口、和第二数据选择器121的输出接口之间的输出通路，从而向外界传输由乘法运算电路20传输的结果数据。
本公开另一实施例中，参见图2所示，控制电路10中还包括：数据传输电路13。
所述控制信号生成电路11，还用于响应于所述至少两个第一待处理数据中存在所述预设数据，向所述数据传输电路13传输所述第一控制信号；
所述数据传输电路13，还用于响应于接收到所述第一控制信号，向所述乘法运算电路屏蔽所述至少两个第一待处理数据。
在该种情况下，数据传输电路13将传输给乘法运算电路20的第一待处理数据屏蔽掉，从而使得乘法运算电路20不对第一待处理数据进行乘法处理，也就避免了乘法运算电路20对第一待处理数据进行处理而发生的信号翻转，也就不需要对第一待处理数据进行处理而产生功耗，因而降低了乘法处理过程中的功耗。
在另一实施例中，所述数据传输电路13，还用于响应于接收到所述第一控制信号，向所述乘法运算电路传输第二待处理数据，其中，所述第二待处理数据为前一次向所述乘法运算电路传输的所述至少两个第一待处理数据。
在具体实施中，乘法运算电路20的输入端口不能悬空，若乘法运算电路20的输入端口为空，则可能导致电路击穿或者环境原因导致的错误输入，因此本公开示例中，数据传输电路13在接收到第一控制信号后，还会向乘法运算电路传输第二待处理数据，使得乘法运算电路20执行一次前一次乘法处理对应的处理。此处，由于当前处理周期和前一次输入至乘法运算电路20中的数据未发生变化，因而也就不会造成乘法运算电路20中发生信号翻转，因此即使乘法运算电路20在本周期执行了与前一次乘法处理对应的处理，也不会产生由于信号翻转而造成的功耗，同时也能够避免由于乘法运算电路20的输入端悬空导致的电路击穿或者环境原因导致的错误输入。
本公开另一实施例中，控制信号生成电路11，还用于响应于所述至少两个第一待处理数据中不存在所述预设数据，向所述数据传输电路13传输所述第二控制信号；
所述数据传输电路13，还用于在接收到所述第二控制信号后，向所述乘法运算电路20传输所述至少两个第一待处理数据。
这样，控制信号生成电路11在第一待处理数据中不存在预设数据的情况下，向数据传输电路13传输第二控制信号，数据传输电路13在接收到第二控制信号后，向乘法运算电路20传输第一待处理数据，以使得乘法运算电路20能够对第一待处理数据进行乘 法处理，得到乘法处理的结果数据。
参见图3所示，本公开实施例还提供了一种数据传输电路13的具体结构，包括：与所述至少两个第一待处理数据分别对应的第三数据选择器131；
所述第三数据选择器131的输出端与所述乘法运算电路20的输入端连接；
所述第三数据选择器131，用于接收与所述第三数据选择器131对应的第一待处理数据；在接收到所述控制信号生成电路11传输的第二控制信号后，向所述乘法运算电路20传输与所述第三数据选择器131对应的第一待处理数据。
在该实施例中，控制信号生成电路11的输出端与第三数据选择器131的控制信号输入端连接；第三数据选择器131的第一输入端用于外界输入第一待处理数据；第三数据选择器131在接收到第二控制信号后，选通第三数据选择器131的第一输入端和第三数据选择器131的数据输出端之间的数据通路，以将外界输入的对应待第一处理数据传输给乘法运算电路20。
在另一实施例中，所述第三数据选择器131，还用于在接收到所述控制信号生成电路11传输的第一控制信号后，向所述乘法运算电路20传输第二待处理数据，其中，所述第二待处理数据为前一次向乘法运算电路20传输的第一待处理数据。
在该种情况下，第三数据选择器的第二输入端用于输入第二待处理数据。当第三数据选择器131接收到第一控制信号后，选通第二输入端和第三数据选择器131的数据输出端之间的数据通路，以将第二待处理数据传输给乘法运算电路20。
在另一实施例中，与各所述第三数据选择器131对应的寄存器132；
所述寄存器132用于存储所述第二待处理数据；
所述第三数据选择器131，在向所述乘法运算电路20传输第二待处理数据时，用于从对应寄存器132中读取所述第二待处理数据，并向所述乘法运算电路20传输所述第二待处理数据。
另外，所述第三数据选择器131，在向所述乘法运算电路20传输与所述第三数据选择器131对应的第一待处理数据时，还用于：向对应的寄存器132传输所述第三数据选择器131对应的第一待处理数据，控制对应寄存器132中存储的所述第二待处理数据，更新为所述第三数据选择器131对应的第一待处理数据。
这样，在多个处理周期中，若当前处理周期对应的待处理数据中不存在为0的数据，则更新寄存器132中存储的数据，以在当前处理周期的下一处理周期出现为0的输入时，能够利用当前处理周期的待处理数据作为乘法运算电路20的输入，避免乘法运算电路20的输入悬空导致的电路击穿或者环境原因导致的错误输入。
在图3对应的示例中，以第一待处理数据有2个，2个第一待处理数据分别为：data_a以及data_b，data_a以及data_b分别输入至两个第三数据选择器131；其中，两个第三数据选择器131分别连接有寄存器132。
以其中一个第三数据选择器131为例，data_a输入至第三数据选择器131；当接收到控制信号生成电路传输的第一控制信号后，第三数据选择器131选通连接有寄存器132的输入端、和信号输出端，将寄存器132中存储的第二待处理数据作为当前处理周期要进行乘法运算的数据multi_a，传输给乘法器电路。
当接收到控制信号生成电路传输的第二控制信号后，第三数据选择器131选通连用于输入data_a的输入端、和信号输出端，将第一待处理数据data_a作为当前处理周期要进行乘法处理的数据multi_a，传输给乘法器电路。
本领域技术人员可以理解，在具体实施方式的上述乘法器中，各部件的连接关系和各自的功能并不对本公开实施例提供的乘法器的结构构成任何限定，乘法器的具体电路结构应当以其功能和可能的内在逻辑确定。
基于同一发明构思，本公开实施例中还提供了与乘法器对应的数据处理方法，由于本公开实施例中的方法解决问题的原理与本公开实施例上述乘法器相似，因此方法的实施可以参见乘法器的实施，重复之处不再赘述。
参照图4所示，为本公开实施例提供的一种数据处理方法的流程图，应用于乘法器，所述乘法器包括：控制电路、以及乘法运算电路；
所述数据处理方法包括：
S401：所述控制电路确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；
S402：所述乘法运算电路接收到所述控制电路传输的至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路传输；
S403：输出所述结果数据。
一种可能的实施方式中，所述控制电路包括：控制信号生成电路、以及结果输出电路；
所述控制电路确定输入的至少两个第一待处理数据中是否存在预设数据；若存在，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，包括：
所述控制信号生成电路在接收所述至少两个第一待处理数据后，确定所述至少两个第一待处理数据中是否存在所述预设数据；响应于所述至少两个第一待处理数据中存在所述预设数据，生成第一控制信号，并向所述结果输出电路传输所述第一控制信号；
所述结果输出电路响应于接收到所述第一控制信号，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，并输出所述结果数据。
一种可能的实施方式中，所述数据处理方法还包括：所述控制信号生成电路响应于所述至少两个第一待处理数据中不存在所述预设数据，生成第二控制信号，并向所述结果输出电路传输所述第二控制信号；
所述结果输出电路响应于接收到所述第二控制信号，输出所述乘法运算电路传输的结果数据。
一种可能的实施方式中，所述控制信号生成电路，包括：与所述至少两个第一待处理数据分别对应的第一数据选择器、以及控制信号生成器；所述第一数据选择器的输出端与所述控制信号生成器的输入端连接；
所述控制信号生成电路响应于接收到对应第一待处理数据，基于所述对应第一待处理数据，向所述控制信号生成器发送指示信号；所述指示信号用于指示所述对应第一待处理数据是否为所述预设数据；
所述控制信号生成器响应于接收到的指示信号中有至少一个指示信号指示所述对应第一待处理数据为预设数据，生成所述第一控制信号。
一种可能的实施方式中，所述生成第二控制信号，包括：所述控制信号生成器响应于接收到的所述指示信号均指示对应第一待处理数据并非预设数据，生成所述第二控制 信号。
一种可能的实施方式中，所述控制信号生成器包括：与门电路、或者或门电路。
一种可能的实施方式中，所述结果输出电路包括：第二数据选择器；所述第二数据选择器的控制信号输入端与所述控制信号生成电路的输出端连接；所述第二数据选择器的第一输入接口与所述乘法运算电路的输出接口连接；所述第二数据选择器的第二输入接口用于输入所述预设数据。
一种可能的实施方式中，所述控制电路，还包括：数据传输电路；
所述数据处理方法还包括：所述控制信号生成电路响应于在所述至少两个第一待处理数据中存在所述预设数据，向所述数据传输电路传输所述第一控制信号；
所述数据传输电路响应于接收到所述第一控制信号，向所述乘法运算电路屏蔽所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据处理方法还包括：所述数据传输电路响应于接收到所述第一控制信号，向所述乘法运算电路传输第二待处理数据，其中，所述第二待处理数据为前一次向所述乘法运算电路传输的所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据处理方法还包括：所述控制信号生成电路响应于所述至少两个第一待处理数据中不存在所述预设数据，向所述数据传输电路传输所述第二控制信号；
所述数据传输电路响应于接收到所述第二控制信号，向所述乘法运算电路传输所述至少两个第一待处理数据。
一种可能的实施方式中，所述数据传输电路，包括：与所述至少两个第一待处理数据分别对应的第三数据选择器；第三数据选择器的输出端与所述乘法运算电路的输入端连接；
将所述至少两个第一待处理数据传输给所述乘法运算电路，包括：
所述第三数据选择器接收与所述第三数据选择器对应的第一待处理数据；响应于接收到所述控制信号生成电路传输的第二控制信号，向所述乘法运算电路传输与所述第三数据选择器对应的第一待处理数据。
一种可能的实施方式中，所述数据处理方法还包括：所述第三数据选择器响应于接收到所述控制信号生成电路传输的第一控制信号，向所述乘法运算电路传输所述第二待处理数据。
一种可能的实施方式中，数据传输电路中还包括：与各所述第三数据选择器对应的寄存器；所述寄存器用于存储所述第二待处理数据；
所述第三数据选择器向所述乘法运算电路传输所述第二待处理数据，包括：从对应寄存器中读取所述第二待处理数据，并向所述乘法运算电路传输所述第二待处理数据。
一种可能的实施方式中，所述第三数据选择器向所述乘法运算电路传输与所述第三数据选择器对应的第一待处理数据，包括：向对应的寄存器传输所述第三数据选择器对应的第一待处理数据，控制对应寄存器中存储的所述第二待处理数据，更新为所述第三数据选择器对应的第一待处理数据。
本公开实施例还提供一种芯片，包括如第一方面任一项所述的乘法器。
本公开实施例还提供一种计算机设备，包括：处理器、存储器，及如本公开任一实施例所述的乘法器，或者包括如本公开实施例提供的芯片。
本公开实施例还提供一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时，所述计算机设备执行本公开任一实施例提供的数据处理方法的步骤。
本公开实施例还提供一种计算机程序产品，该计算机程序产品承载有程序代码，所述程序代码包括的指令可用于执行上述方法实施例中所述的数据处理的步骤，具体可参见上述方法实施例，在此不再赘述。
其中，上述计算机程序产品可以具体通过硬件、软件或其结合的方式实现。在一个可选实施例中，所述计算机程序产品具体体现为计算机存储介质，在另一个可选实施例中，计算机程序产品具体体现为软件产品，例如软件开发包(Software Development Kit，SDK)等等。
所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，上述描述的系统和装置的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。在本公开所提供的几个实施例中，应该理解到，所揭露的系统、装置和方法，可以通过其它的方式实现。以上所描述的装置实施例仅仅是示意性的，例如，所述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，又例如，多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些通信接口，装置或单元的间接耦合或通信连接，可以是电性，机械或其它的形式。
所述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本公开各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。
所述功能如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个处理器可执行的非易失的计算机可读取存储介质中。基于这样的理解，本公开的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)执行本公开各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：U盘、移动硬盘、只读存储器(Read-Only Memory，ROM)、随机存取存储器(Random Access Memory，RAM)、磁碟或者光盘等各种可以存储程序代码的介质。
最后应说明的是：以上所述实施例，仅为本公开的具体实施方式，用以说明本公开的技术方案，而非对其限制，本公开的保护范围并不局限于此，尽管参照前述实施例对本公开进行了详细的说明，本领域的普通技术人员应当理解：任何熟悉本技术领域的技术人员在本公开揭露的技术范围内，其依然可以对前述实施例所记载的技术方案进行修改或可轻易想到变化，或者对其中部分技术特征进行等同替换；而这些修改、变化或者替换，并不使相应技术方案的本质脱离本公开实施例技术方案的精神和范围，都应涵盖在本公开的保护范围之内。因此，本公开的保护范围应所述以权利要求的保护范围为准。

Claims (19)

  1. 一种乘法器，其特征在于，包括：控制电路、以及乘法运算电路；
    其中，所述控制电路，用于确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；输出所述结果数据；
    所述乘法运算电路，用于接收到所述控制电路传输的所述至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路传输。
  2. 根据权利要求1所述的乘法器，其特征在于，所述控制电路，还用于：
    响应于所述至少两个第一待处理数据中存在预设数据，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据。
  3. 根据权利要求1或2所述的乘法器，其特征在于，所述控制电路包括：控制信号生成电路、以及结果输出电路；
    所述控制信号生成电路，用于在接收所述至少两个第一待处理数据后，确定所述至少两个第一待处理数据中是否存在所述预设数据；响应于所述至少两个第一待处理数据中存在所述预设数据，生成第一控制信号，并向所述结果输出电路传输所述第一控制信号；
    所述结果输出电路，用于响应于接收到所述第一控制信号，将所述预设数据作为对所述至少两个第一待处理数据进行乘法处理的结果数据，并输出所述结果数据。
  4. 根据权利要求3所述的乘法器，其特征在于，所述控制信号生成电路，还用于响应于所述至少两个第一待处理数据中不存在所述预设数据，生成第二控制信号，并向所述结果输出电路传输所述第二控制信号；
    所述结果输出电路，还用于响应于接收到所述第二控制信号，输出所述乘法运算电路传输的结果数据。
  5. 根据权利要求3或4所述的乘法器，其特征在于，所述控制信号生成电路，包括：与所述至少两个第一待处理数据分别对应的第一数据选择器、以及控制信号生成器；所述第一数据选择器的输出端与所述控制信号生成器的输入端连接；
    所述第一数据选择器，用于响应于接收到对应第一待处理数据，基于所述对应第一待处理数据，向所述控制信号生成器发送指示信号；所述指示信号用于指示所述对应第一待处理数据是否为所述预设数据；
    所述控制信号生成器，用于响应于接收到的指示信号中有至少一个指示信号指示所述对应第一待处理数据为预设数据，生成所述第一控制信号。
  6. 根据权利要求5所数据的乘法器，其特征在于，所述控制信号生成器，还用于响应于接收到的所述指示信号均指示对应第一待处理数据并非预设数据，生成所述第二控制信号。
  7. 根据权利要求5或6所述的乘法器，其特征在于，所述控制信号生成器包括：与门电路、或者或门电路。
  8. 根据权利要求3-7任一项所述的乘法器，其特征在于，所述结果输出电路包括：第二数据选择器；
    所述第二数据选择器的控制信号输入端与所述控制信号生成电路的输出端连接；
    所述第二数据选择器的第一输入接口与所述乘法运算电路的输出接口连接；
    所述第二数据选择器的第二输入接口用于输入所述预设数据。
  9. 根据权利要求3-8任一项所述的乘法器，其特征在于，所述控制电路，还包括：数据传输电路；
    所述控制信号生成电路，还用于响应于在所述至少两个第一待处理数据中存在所述预设数据，向所述数据传输电路传输所述第一控制信号；
    所述数据传输电路，还用于响应于接收到所述第一控制信号，向所述乘法运算电路屏蔽所述至少两个第一待处理数据。
  10. 根据权利要求9所述的乘法器，其特征在于，所述数据传输电路，还用于响应于接收到所述第一控制信号，向所述乘法运算电路传输第二待处理数据，其中，所述第二待处理数据为前一次向所述乘法运算电路传输的所述至少两个第一待处理数据。
  11. 根据权利要求9或10所述的乘法器，其特征在于，所述控制信号生成电路，还用于响应于所述至少两个第一待处理数据中不存在所述预设数据，向所述数据传输电路传输所述第二控制信号；
    所述数据传输电路，还用于响应于接收到所述第二控制信号，向所述乘法运算电路传输所述至少两个第一待处理数据。
  12. 根据权利要求9-11任一项所述的乘法器，其特征在于，所述数据传输电路，包括：与所述至少两个第一待处理数据分别对应的第三数据选择器；
    所述第三数据选择器的输出端与所述乘法运算电路的输入端连接；
    所述第三数据选择器，用于接收与所述第三数据选择器对应的第一待处理数据；响应于接收到所述控制信号生成电路传输的第二控制信号，向所述乘法运算电路传输与所述第三数据选择器对应的第一待处理数据。
  13. 根据权利要求12所述的乘法器，其特征在与，所述第三数据选择器，还用于响应于接收到所述控制信号生成电路传输的第一控制信号，向所述乘法运算电路传输所述第二待处理数据。
  14. 根据权利要求13所述的乘法器，其特征在于，所述数据传输电路中还包括：与各所述第三数据选择器对应的寄存器；
    所述寄存器用于存储所述第二待处理数据；
    所述第三数据选择器，在向所述乘法运算电路传输所述第二待处理数据时，用于从对应寄存器中读取所述第二待处理数据，并向所述乘法运算电路传输所述第二待处理数据。
  15. 根据权利要求13所述的乘法器，其特征在于，所述第三数据选择器，在向所述乘法运算电路传输与所述第三数据选择器对应的第一待处理数据时，还用于：向对应的寄存器传输所述第三数据选择器对应的第一待处理数据，控制对应寄存器中存储的所述第二待处理数据，更新为所述第三数据选择器对应的第一待处理数据。
  16. 一种数据处理方法，其特征在于，应用于乘法器，所述乘法器包括：控制电路、以及乘法运算电路；
    所述数据处理方法包括：
    所述控制电路确定输入的至少两个第一待处理数据；响应于所述至少两个第一待处 理数据中不存在预设数据，将所述至少两个第一待处理数据传输给所述乘法运算电路，并接收所述乘法运算电路传输的结果数据；输出所述结果数据；
    所述乘法运算电路接收到所述控制电路传输的所述至少两个第一待处理数据时，对所述至少两个第一待处理数据进行乘法处理，得到所述结果数据，并将所述结果数据向所述控制电路传输。
  17. 一种芯片，其特征在于，包括：如权利要求1-15任一项所述的乘法器。
  18. 一种计算机设备，其特征在于，包括：处理器、存储器，及如权利要求1-15任一项所述的乘法器，或者包括如权利要求17所述的芯片。
  19. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被计算机设备运行时，所述计算机设备执行如权利要求16所述的数据处理方法的步骤。
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