WO2022246610A1 - 一种显示基板及其驱动方法、显示装置 - Google Patents

一种显示基板及其驱动方法、显示装置 Download PDF

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Publication number
WO2022246610A1
WO2022246610A1 PCT/CN2021/095575 CN2021095575W WO2022246610A1 WO 2022246610 A1 WO2022246610 A1 WO 2022246610A1 CN 2021095575 W CN2021095575 W CN 2021095575W WO 2022246610 A1 WO2022246610 A1 WO 2022246610A1
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Prior art keywords
pixel
initialization voltage
transistor
electrically connected
sub
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PCT/CN2021/095575
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English (en)
French (fr)
Inventor
王本莲
程羽雕
张振华
张玉欣
Original Assignee
京东方科技集团股份有限公司
成都京东方光电科技有限公司
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Application filed by 京东方科技集团股份有限公司, 成都京东方光电科技有限公司 filed Critical 京东方科技集团股份有限公司
Priority to US18/563,556 priority Critical patent/US20240221590A1/en
Priority to PCT/CN2021/095575 priority patent/WO2022246610A1/zh
Priority to CN202180001239.9A priority patent/CN115699148A/zh
Publication of WO2022246610A1 publication Critical patent/WO2022246610A1/zh

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
    • G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0421—Structural details of the set of electrodes
    • G09G2300/0426—Layout of electrodes and connections
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/04—Structural and physical details of display devices
    • G09G2300/0439—Pixel structures
    • G09G2300/0452—Details of colour pixel setup, e.g. pixel composed of a red, a blue and two green components
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor

Definitions

  • the present disclosure relates to the field of display technology, and in particular to a display substrate, a driving method thereof, and a display device.
  • a display substrate provided by an embodiment of the present disclosure has a display area and a frame area, and the display area includes: a first display area and a second display area; the light transmittance of the first display area is greater than that of the second display area The light transmittance of the area;
  • the first display area includes a plurality of pixel units distributed in an array, and each pixel unit includes a first sub-pixel and a second sub-pixel with different light emitting colors;
  • the first display area includes a first initialization voltage line and a second initialization voltage line, the first initialization voltage line is electrically connected to the first sub-pixel, and the second initialization voltage line is connected to the second sub-pixel electrically connected, the first initialization voltage line and the second initialization voltage line are configured to receive different initialization voltages.
  • each of the pixel units further includes a third sub-pixel, and the light emission color of the third sub-pixel is the same as the light emission color of the first sub-pixel, the light emission color of the first sub-pixel, the The light emitting colors of the second sub-pixels are all different, and the third sub-pixel is electrically connected to the second initialization voltage line.
  • the above-mentioned display substrate includes a base substrate, a first gate metal layer, a second gate metal layer, and a source-drain metal layer that are sequentially stacked;
  • the first initialization voltage line and the second initialization voltage line are arranged on the same layer as the first gate metal layer; or,
  • the first initialization voltage line, the second initialization voltage line and the second gate metal layer are arranged in the same layer; or,
  • One of the first initialization voltage line and the second initialization voltage line is set on the same layer as the first gate metal layer, and the other is set on the same layer as the second gate metal layer.
  • the first sub-pixel, the second sub-pixel and the third sub-pixel each include a light emitting device and a driving circuit, and the driving circuit is located in the the frame area or the second display area;
  • the drive circuit includes a first initialization transistor, a second initialization transistor, a drive transistor, a data write transistor, a threshold compensation transistor, a first light emission control transistor, a second light emission control transistor and a storage capacitor;
  • the gate of the first initialization transistor is electrically connected to the reset signal line
  • the first electrode of the first initialization transistor in the driving circuit corresponding to the first sub-pixel is electrically connected to the first initialization voltage line
  • the first initialization transistor is electrically connected to the first initialization voltage line.
  • the first poles of the first initialization transistors in the drive circuits corresponding to the second sub-pixel and the third sub-pixel are electrically connected to the second initialization voltage line
  • the second poles of the first initialization transistor are connected to the drive circuit.
  • the gate of the second initialization transistor is electrically connected to the scanning signal line
  • the first pole of the second initialization transistor in the driving circuit corresponding to the first sub-pixel is electrically connected to the first initialization voltage line
  • the first electrode is electrically connected to the first initialization voltage line.
  • the first poles of the second initialization transistors in the drive circuits corresponding to the second subpixel and the third subpixel are electrically connected to the second initialization voltage line
  • the second poles of the second initialization transistor are connected to the light emitting Anode electrical connection of the device;
  • the gate of the first light emission control transistor is electrically connected to the light emission control line
  • the first pole of the first light emission control transistor is electrically connected to the first power supply line
  • the second pole of the first light emission control transistor is connected to the light emission control line.
  • the first electrode of the driving transistor is electrically connected;
  • the gate of the second light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the second light emission control transistor is electrically connected to the second electrode of the driving transistor
  • the second electrode of the second light emission control transistor is electrically connected to the light emission control line.
  • the second pole is electrically connected to the anode of the light emitting device; the cathode of the light emitting device is electrically connected to the second power line;
  • the gate of the threshold compensation transistor is electrically connected to the scanning signal line, the first pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor, and the second pole of the threshold compensation transistor is connected to the driving transistor.
  • the second pole is electrically connected;
  • the gate of the data writing transistor is electrically connected to the scanning signal line, the first pole of the data writing transistor is electrically connected to the data signal line, and the second pole of the data writing transistor is connected to the driving transistor.
  • the first pole is electrically connected;
  • a first pole of the storage capacitor is electrically connected to the first power line, and a second pole of the storage capacitor is electrically connected to the gate of the driving transistor.
  • each of the pixel units further includes a third sub-pixel, and the light emission color of the third sub-pixel is the same as the light emission color of the first sub-pixel, the light emission color of the first sub-pixel, the The light emitting colors of the second sub-pixels are all different;
  • the first display area further includes a third initialization voltage line, the third sub-pixel is electrically connected to the third initialization voltage line, and the third initialization voltage line is configured to receive a voltage different from the first initialization voltage. line, the initialization voltage received by the second initialization voltage line.
  • the above-mentioned display substrate includes a base substrate, a first gate metal layer, a second gate metal layer, and a source-drain metal layer that are sequentially stacked;
  • the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line are arranged on the same layer as the first gate metal layer; or,
  • the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line are arranged on the same layer as the second gate metal layer; or,
  • Two of the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line are arranged on the same layer as the first gate metal layer, and the other is arranged on the same layer as the second gate metal layer. Layer same layer settings.
  • the first sub-pixel, the second sub-pixel and the third sub-pixel each include a light emitting device and a driving circuit, and the driving circuit is located in the the frame area or the second display area;
  • the drive circuit includes a first initialization transistor, a second initialization transistor, a drive transistor, a data write transistor, a threshold compensation transistor, a first light emission control transistor, a second light emission control transistor and a storage capacitor;
  • the gate of the first initialization transistor is electrically connected to the reset signal line
  • the first electrode of the first initialization transistor in the driving circuit corresponding to the first sub-pixel is electrically connected to the first initialization voltage line
  • the first initialization transistor is electrically connected to the first initialization voltage line.
  • the first electrode of the first initialization transistor in the drive circuit corresponding to the second sub-pixel is electrically connected to the second initialization voltage line
  • the first electrode of the first initialization transistor in the drive circuit corresponding to the third sub-pixel is connected to the second initialization voltage line.
  • the third initialization voltage line is electrically connected, and the second pole of the first initialization transistor is electrically connected to the gate of the driving transistor;
  • the gate of the second initialization transistor is electrically connected to the scanning signal line, the first pole of the second initialization transistor in the driving circuit corresponding to the first sub-pixel is electrically connected to the first initialization voltage line, and the first electrode is electrically connected to the first initialization voltage line.
  • the first electrode of the second initialization transistor in the drive circuit corresponding to the second sub-pixel is electrically connected to the second initialization voltage line, and the first electrode of the second initialization transistor in the drive circuit corresponding to the third sub-pixel is connected to the second initialization voltage line.
  • the third initialization voltage line is electrically connected, and the second pole of the second initialization transistor is electrically connected to the anode of the light emitting device;
  • the gate of the first light emission control transistor is electrically connected to the light emission control line
  • the first pole of the first light emission control transistor is electrically connected to the first power supply line
  • the second pole of the first light emission control transistor is connected to the light emission control line.
  • the first electrode of the driving transistor is electrically connected;
  • the gate of the second light emission control transistor is electrically connected to the light emission control line
  • the first electrode of the second light emission control transistor is electrically connected to the second electrode of the driving transistor
  • the second electrode of the second light emission control transistor is electrically connected to the light emission control line.
  • the second pole is electrically connected to the anode of the light emitting device; the cathode of the light emitting device is electrically connected to the second power line;
  • the gate of the threshold compensation transistor is electrically connected to the scanning signal line, the first pole of the threshold compensation transistor is electrically connected to the gate of the driving transistor, and the second pole of the threshold compensation transistor is connected to the driving transistor.
  • the second pole is electrically connected;
  • the gate of the data writing transistor is electrically connected to the scanning signal line, the first pole of the data writing transistor is electrically connected to the data signal line, and the second pole of the data writing transistor is connected to the driving transistor.
  • the first pole is electrically connected;
  • a first pole of the storage capacitor is electrically connected to the first power line, and a second pole of the storage capacitor is electrically connected to the gate of the driving transistor.
  • the plurality of driving circuits are located in the frame area adjacent to the first display area; or,
  • the second display area has a transition area adjacent to the first display area, and the plurality of driving circuits are located in the transition area.
  • the first sub-pixel is a green sub-pixel
  • the second sub-pixel is a red sub-pixel
  • the third sub-pixel is a blue sub-pixel.
  • the above-mentioned display substrate provided by an embodiment of the present disclosure further includes at least one transparent wiring layer located between the driving circuit and the anode of the light emitting device, the driving circuit and the anode pass through The transparent wiring on the transparent wiring layer is electrically connected.
  • the resolution of the first display area is smaller than the resolution of the second display area, or the resolution of the first display area is different from that of the second display area.
  • the resolutions of the two display areas are roughly the same.
  • the shape of the first display area is at least one of circle, ellipse, rectangle or polygon.
  • an embodiment of the present disclosure further provides a display device, including a photosensitive device, and any one of the display substrates described above; wherein, the photosensitive device is disposed in a first display area of the display substrate.
  • an embodiment of the present disclosure also provides a method for driving a display substrate described in any one of the above, including:
  • a first initialization voltage is applied to the first subpixel through the first initialization voltage line, and a second initialization voltage is applied to the second subpixel through the second initialization voltage line;
  • the first initialization voltage is greater than the second initialization voltage.
  • the second initialization voltage is applied to the third sub-pixel through the second initialization voltage line.
  • the first initialization voltage is approximately 0.5V greater than the second initialization voltage.
  • each of the pixel units in the first display area further includes a third sub-pixel, and the emission color of the third sub-pixel is the same as that of the first sub-pixel.
  • the emission color of the pixel and the emission color of the second sub-pixel are different;
  • the display area of the display substrate further includes a third initialization voltage line, and the third sub-pixel is electrically connected to the third initialization voltage line, so
  • the third initialization voltage line is configured to receive an initialization voltage different from that received by the first initialization voltage line and the second initialization voltage line;
  • the driving method also includes:
  • a third initialization voltage is applied to the third subpixel through the third initialization voltage line;
  • the third initialization voltage is smaller than the second initialization voltage.
  • the first initialization voltage is approximately 0.2V greater than the second initialization voltage
  • the second initialization voltage is approximately 0.3V greater than the third initialization voltage
  • FIG. 1 is a schematic top view of a display substrate provided by an embodiment of the present disclosure
  • FIG. 2 is a schematic diagram of a simulation of the turn-on time of three sub-pixels provided by an embodiment of the present disclosure
  • FIG. 3 is a schematic structural diagram of a driving circuit in a red sub-pixel provided by an embodiment of the present disclosure
  • FIG. 4 is a schematic structural diagram of a driving circuit in a green sub-pixel provided by an embodiment of the present disclosure
  • FIG. 5 is a schematic structural diagram of a driving circuit in a blue sub-pixel provided by an embodiment of the present disclosure
  • Figure 6 is a schematic diagram of the layout corresponding to Figure 3- Figure 5;
  • FIG. 7A is a schematic layout diagram corresponding to FIG. 3;
  • FIG. 7B is a schematic diagram of the layout corresponding to FIG. 4.
  • FIG. 7C is a schematic layout diagram corresponding to FIG. 5;
  • FIG. 8 is a schematic structural diagram of another driving circuit in a blue sub-pixel provided by an embodiment of the present disclosure.
  • FIG. 9 is a schematic top view of another display substrate provided by an embodiment of the present disclosure.
  • the under-screen camera technology generally sets the first display area AA1 and the second display area AA2 in the display area AA, wherein the second display area AA2 occupies most of the display area, and the first display area AA1 occupies the display area In the smaller part, the first display area AA1 is where the camera under the screen is placed.
  • the under-screen camera means that the front camera is located at the bottom of the screen but does not affect the display function of the screen. When the front camera is not used, the screen above the camera can still display images normally. So from the appearance point of view, the camera under the screen will not have any camera holes, which truly achieves a full-screen display effect.
  • the pixel circuit of the first display area AA1 is arranged in the frame area BB above the first display area AA1 or in the second display area AA2 adjacent to the first display area AA1, so as to The pixel circuit is set in the frame area BB above the first display area AA1 as an example.
  • the pixel circuit is connected to the light-emitting device in the first display area AA1 through the ITO wiring 100, so as to transmit the surrounding pixel signals to the under-screen camera area.
  • the ITO wiring 100 is too long, the turn-on time of the R/G/B sub-pixels in the first display area AA1 is prolonged, and the turn-on time of the R/G/B sub-pixels (corresponding to a, b, c) There are differences, as shown in FIG. 2 , sub-pixel B is turned on first, followed by sub-pixel R, and sub-pixel G is turned on last. Because the lighting time of the pixel G is too long, the human eyes perceive purple when displaying, which means that the display in the first display area AA1 is defective in purple.
  • an embodiment of the present disclosure provides a display substrate. As shown in FIG. 1 , it has a display area AA and a frame area BB. The light transmittance of the display area AA1 is greater than the light transmittance of the second display area AA2;
  • the first display area AA1 includes a plurality of pixel units (not shown) distributed in an array, and each pixel unit includes a first sub-pixel (not shown) and a second sub-pixel (not shown) that emit light with different colors;
  • the first display area AA1 includes a first initialization voltage line (not shown) and a second initialization voltage line (not shown), the first initialization voltage line is electrically connected to the first sub-pixel, and the second initialization voltage line is connected to the second sub-pixel
  • the pixels are electrically connected, and the first initialization voltage line and the second initialization voltage line are configured to receive different initialization voltages.
  • the turn-on time (that is, the charging time) of the sub-pixel has a great relationship with the potential of the anode of the light-emitting device (described later), the potential of the anode of the light-emitting device is strongly related to the initialization voltage.
  • the charging time that is, the lighting time
  • the embodiment of the present disclosure transmits the initialization voltage to the first sub-pixel and the second sub-pixel respectively through the first initialization voltage line and the second initialization line arranged on the display substrate, so as to realize the reception of the first sub-pixel and the second sub-pixel.
  • the first sub-pixel in the first display area AA1 can be sent to the first sub-pixel through the first initialization voltage line.
  • the pixel input initialization voltage is greater than the initialization voltage input to the second sub-pixel through the second initialization voltage line, so that the charging time of the first sub-pixel and the second sub-pixel are consistent, thereby solving the problem of bad purple in the first display area AA1 question.
  • the first sub-pixel is a green sub-pixel G
  • the second sub-pixel is a red sub-pixel R.
  • the initialization voltage input to the green sub-pixel G can be set to be higher than the initialization voltage input to the red sub-pixel R, thereby The charging time of the first sub-pixel and the second sub-pixel is kept consistent, so as to solve the problem of bad purple in the first display area AA1.
  • each pixel unit in the first display area AA1 further includes a third sub-pixel (blue sub-pixel B), and the third The emission color of the pixel is different from the emission color of the first sub-pixel (green sub-pixel G) and the emission color of the second sub-pixel (red sub-pixel R), and the third sub-pixel (blue sub-pixel B) is different from the second initialization color Voltage wire electrical connection.
  • the turn-on time of the green sub-pixel G is longer than the turn-on time of the red sub-pixel R
  • the turn-on time of the red sub-pixel R is longer than the turn-on time of the blue sub-pixel B
  • the red sub-pixel R and The turn-on time of the blue sub-pixel B has little difference
  • the third sub-pixel (blue sub-pixel B) can be electrically connected to the second initialization voltage line, that is, the initialization voltage of the input green sub-pixel G can be set to be higher than the input
  • the initialization voltage of the red sub-pixel R, and the initialization voltage input to the red sub-pixel R and the blue sub-pixel B are set to be the same, so that the charging time of the first sub-pixel, the second sub-pixel and the third sub-pixel are consistent, Therefore, the problem of bad purple in the first display area AA1 is solved.
  • the base substrate, the first gate metal layer, the second gate metal layer, and the source-drain metal layer are sequentially stacked. Mutual insulation;
  • the first initialization voltage line and the second initialization voltage line are arranged on the same layer as the first gate metal layer; or,
  • the first initialization voltage line, the second initialization voltage line and the second gate metal layer are arranged in the same layer; or,
  • One of the first initialization voltage line and the second initialization voltage line is set on the same layer as the first gate metal layer, and the other is set on the same layer as the second gate metal layer.
  • the first initialization voltage line and the second initialization voltage line are set on the same layer as the first gate metal layer and/or the second gate metal layer And set with the same material, so as to realize the synchronous production of the first initialization voltage line and the second initialization voltage line while setting the first gate metal layer and the second gate metal layer; wherein, the first initialization voltage line, the second initialization voltage line
  • the second initialization voltage line can be set on the first gate metal layer or on the second gate metal layer at the same time, or one on the first gate metal layer and one on the second gate metal layer, because the second gate
  • the metal layer is generally provided with the electrode plate of the capacitor, and the second gate metal layer has a large space, so it is a preferred arrangement method to arrange the first initialization voltage line and the second initialization voltage line on the second gate metal layer at the same time.
  • the first sub-pixel (green sub-pixel G), the second sub-pixel (red sub-pixel R ) and the third sub-pixel (blue sub-pixel B) both include a light emitting device and a driving circuit, and the driving circuit is located in the frame area BB or the second display area AA2;
  • Figure 3 is a schematic diagram of the driving circuit of the second sub-pixel (red sub-pixel R)
  • Figure 4 is a schematic diagram of the driving circuit of the first sub-pixel (green sub-pixel G)
  • Figure 5 is a schematic diagram of the third sub-pixel Schematic diagram of the driving circuit of the sub-pixel (blue sub-pixel B)
  • the driving circuit includes the first initialization transistor T1, the second initialization transistor T7, the driving transistor T3, the data writing transistor T4, the threshold compensation transistor T2, and the first light emission control transistor T5 , the second light emission control transistor T6 and the storage capacitor C1;
  • the gate of the first initialization transistor T1 is electrically connected to the reset signal line RES, and the first electrode of the first initialization transistor T1 in the driving circuit corresponding to the first sub-pixel (green sub-pixel G) is electrically connected to the first initialization voltage line VIN1 , the first poles of the first initialization transistor T1 in the drive circuits corresponding to the second subpixel (red subpixel R) and the third subpixel (blue subpixel B) are electrically connected to the second initialization voltage line VIN2, and the second A second pole of the initialization transistor T1 is electrically connected to the gate of the driving transistor T3;
  • the gate of the second initialization transistor T7 is electrically connected to the scanning signal line GA, and the first electrode of the second initialization transistor T7 in the driving circuit corresponding to the first sub-pixel (green sub-pixel G) is electrically connected to the first initialization voltage line VIN1 , the first poles of the second initialization transistor T7 in the drive circuits corresponding to the second subpixel (red subpixel R) and the third subpixel (blue subpixel B) are electrically connected to the second initialization voltage line VIN2, and the second 2.
  • the second pole of the initialization transistor T7 is electrically connected to the anode of the light emitting device L;
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line EM, the first pole of the first light emission control transistor T5 is electrically connected to the first power supply line VDD, and the second pole of the first light emission control transistor T5 is connected to the driving transistor T3.
  • the first pole is electrically connected;
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line EM, the first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3, and the second pole of the second light emission control transistor T6 is connected to the light emission control line EM.
  • the anode of the device L is electrically connected; the cathode of the light emitting device L is electrically connected to the second power line VSS;
  • the gate of the threshold compensation transistor T2 is electrically connected to the scanning signal line GA, the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3. connect;
  • the gate of the data writing transistor T4 is electrically connected to the scanning signal line GA, the first pole of the data writing transistor T4 is electrically connected to the data signal line DA, and the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor T3. electrical connection;
  • a first pole of the storage capacitor C1 is electrically connected to the first power line VDD, and a second pole of the storage capacitor C1 is electrically connected to the gate of the driving transistor T3.
  • FIG. 6 is a schematic diagram of the layout (layout) of the driving circuit corresponding to the three sub-pixels in FIG. 3-FIG.
  • the second display area AA2 is adjacent to the first display area AA1, and may also be distributed in the second display area AA2.
  • the first poles of the two initialization transistors T7 are electrically connected to the first initialization voltage line VIN1, and the first initialization in the drive circuit corresponding to the second sub-pixel (red sub-pixel R) and the third sub-pixel (blue sub-pixel B)
  • Both the first electrode of the transistor T1 and the first electrode of the second initialization transistor T7 are electrically connected to the second initialization voltage line VIN2.
  • the third sub-pixel (blue sub-pixel B) and the second sub-pixel (red sub-pixel R) can both be electrically connected to the second initialization voltage line VIN2, so that the initialization voltage of the input green sub-pixel G can be set higher than that of the input red sub-pixel R
  • the initialization voltage of the input red sub-pixel R and the blue sub-pixel B are set to be the same, so that the charging time of the first sub-pixel, the second sub-pixel and the third sub-pixel are consistent, thereby solving the first The problem of bad purple in the display area AA1.
  • Figure 7A- Figure 7C are respectively the layout of the driving circuit shown in Figure 3- Figure 5 (Layout) schematic diagram
  • the second sub-pixel (red sub-pixel R) corresponding to FIG. 7A and the third sub-pixel (blue sub-pixel B) corresponding to FIG. 7C are both electrically connected to the second initialization voltage line VIN2, and the corresponding to FIG. 7B
  • the first sub-pixel (green sub-pixel G) is electrically connected to the first initialization voltage line VIN1.
  • each pixel unit in the first display area AA1 further includes a third sub-pixel (blue sub-pixel B), and the third The emission color of the pixel (blue sub-pixel B) is different from the emission color of the first sub-pixel (green sub-pixel G) and the emission color of the second sub-pixel (red sub-pixel R);
  • the first display area AA1 further includes a third initialization voltage line (not shown), the third sub-pixel (blue sub-pixel B) is electrically connected to the third initialization voltage line, and the third initialization voltage line is configured to receive The initialization voltage received by the first initialization voltage line and the second initialization voltage line.
  • the three sub-pixels are different from each other.
  • the initialization voltage lines are electrically connected, so the corresponding initialization voltages can be respectively input through different corresponding initialization voltage lines, that is, the initialization voltage input to the green sub-pixel G can be set to be higher than the initialization voltage input to the red sub-pixel R, and the The initialization voltage input to the red sub-pixel R is set higher than the initialization voltage input to the blue sub-pixel B. Therefore, the charging time of the first sub-pixel, the second sub-pixel and the third sub-pixel is kept consistent, thereby solving the problem of bad purple in the first display area AA1.
  • the base substrate, the first gate metal layer, the second gate metal layer, and the source-drain metal layer are sequentially stacked. Mutual insulation;
  • the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line are arranged on the same layer as the first gate metal layer; or,
  • the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line are arranged on the same layer as the second gate metal layer; or,
  • Two of the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line are arranged on the same layer as the first gate metal layer, and the other is arranged on the same layer as the second gate metal layer.
  • the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line are set to be connected with the first gate metal layer and/or the second
  • the gate metal layer is set on the same layer and material, so that the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line can be completed while setting the first gate metal layer and the second gate metal layer.
  • the first initialization voltage line, the second initialization voltage line, and the third initialization voltage line can be set on the first gate metal layer or on the second gate metal layer at the same time, or both can be set on the first gate metal layer
  • One of the gate metal layers is arranged on the second gate metal layer.
  • the second gate metal layer is generally provided with the plate of the capacitor, the space of the second gate metal layer is larger, so the first initialization voltage line, the second initialization voltage line It is a preferred way to arrange both the line and the third initialization voltage line on the second gate metal layer.
  • the first sub-pixel (green sub-pixel G), the second sub-pixel (red sub-pixel R ) and the third sub-pixel (blue sub-pixel B) both include a light emitting device and a driving circuit, and the driving circuit is located in the frame area BB or the second display area AA2;
  • Figure 8 is a schematic diagram of another drive circuit for the third sub-pixel (blue sub-pixel B), the drive circuit includes a first initialization transistor T1, a second initialization transistor T7, a drive Transistor T3, data writing transistor T4, threshold compensation transistor T2, first light emission control transistor T5, second light emission control transistor T6 and storage capacitor C1;
  • the gate of the first initialization transistor T1 is electrically connected to the reset signal line RES, and the first electrode of the first initialization transistor T1 in the driving circuit corresponding to the first sub-pixel (green sub-pixel G) is electrically connected to the first initialization voltage line VIN1 , the first electrode of the first initialization transistor T1 in the driving circuit corresponding to the second subpixel (red subpixel R) is electrically connected to the second initialization voltage line VIN2, and the driving circuit corresponding to the third subpixel (blue subpixel B)
  • the first pole of the first initialization transistor T1 in the circuit is electrically connected to the third initialization voltage line VIN3, and the second pole of the first initialization transistor T1 is electrically connected to the gate of the driving transistor T3;
  • the gate of the second initialization transistor T7 is electrically connected to the scanning signal line GA, and the first electrode of the second initialization transistor T7 in the driving circuit corresponding to the first sub-pixel (green sub-pixel G) is electrically connected to the first initialization voltage line VIN1 , the first electrode of the second initialization transistor T7 in the driving circuit corresponding to the second subpixel (red subpixel R) is electrically connected to the second initialization voltage line VIN2, and the driving circuit corresponding to the third subpixel (blue subpixel B)
  • the first pole of the second initialization transistor T7 in the circuit is electrically connected to the third initialization voltage line VIN3, and the second pole of the second initialization transistor T7 is electrically connected to the anode of the light emitting device L;
  • the gate of the first light emission control transistor T5 is electrically connected to the light emission control line EM, the first pole of the first light emission control transistor T5 is electrically connected to the first power supply line VDD, and the second pole of the first light emission control transistor T5 is connected to the driving transistor T3.
  • the first pole is electrically connected;
  • the gate of the second light emission control transistor T6 is electrically connected to the light emission control line EM, the first pole of the second light emission control transistor T6 is electrically connected to the second pole of the driving transistor T3, and the second pole of the second light emission control transistor T6 is connected to the light emission control line EM.
  • the anode of the device L is electrically connected; the cathode of the light emitting device L is electrically connected to the second power line VSS;
  • the gate of the threshold compensation transistor T2 is electrically connected to the scanning signal line GA, the first pole of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the second pole of the threshold compensation transistor T2 is electrically connected to the second pole of the driving transistor T3. connect;
  • the gate of the data writing transistor T4 is electrically connected to the scanning signal line GA, the first pole of the data writing transistor T4 is electrically connected to the data signal line DA, and the second pole of the data writing transistor T4 is connected to the first pole of the driving transistor T3. electrical connection;
  • a first pole of the storage capacitor C1 is electrically connected to the first power line VDD, and a second pole of the storage capacitor C1 is electrically connected to the gate of the driving transistor T3.
  • the driving circuits corresponding to the three sub-pixels in FIG. 3 , FIG. 4 and FIG. 8 may be located in the frame area BB in FIG. It may be distributed in the second display area AA2, the first electrode of the first initialization transistor T1 in the driving circuit corresponding to the first sub-pixel (green sub-pixel G) is electrically connected to the first initialization voltage line VIN1, and the second sub-pixel ( The first pole of the first initialization transistor T1 in the driving circuit corresponding to the red sub-pixel R) is electrically connected to the second initialization voltage line VIN2, and the first initialization voltage in the driving circuit corresponding to the third sub-pixel (blue sub-pixel B) The first pole of the transistor T1 is electrically connected to the third initialization voltage line VIN3.
  • the turn-on time of the blue sub-pixel B, so the first sub-pixel, the second sub-pixel and the third sub-pixel can be electrically connected to different initialization voltage lines, so that the initialization voltage input to the green sub-pixel G can be set to high
  • the initialization voltage input to the red sub-pixel R is set to be higher than the initialization voltage input to the blue sub-pixel B, so that the first sub-pixel, the second sub-pixel and the third sub-pixel
  • the charging time is kept consistent, thereby solving the problem of bad purple in the first display area AA1.
  • a plurality of driving circuits are located in the frame area adjacent to the first display area AA1; or,
  • the second display area AA2 has a transition area CC adjacent to the first display area AA1 , and multiple driving circuits are located in the transition area CC, or multiple driving circuits can also be distributed in the second display area AA2 .
  • the above-mentioned display substrate provided by the embodiments of the present disclosure further includes at least one transparent wiring layer located between the driving circuit and the anode of the light-emitting device, and the driving circuit and the anode pass through the transparent wiring layer located on the transparent wiring layer. Trace electrical connections.
  • the transparent wiring layer may be multi-layered, each layer is insulated, and each transparent wiring layer includes a plurality of transparent wiring layers.
  • the multiple transparent wirings contained in each transparent wiring layer do not overlap each other, and the multiple transparent wirings contained in different transparent wiring layers
  • the orthographic projections on the base substrate do not overlap each other.
  • the orthographic projections of the multiple transparent wiring layers contained in different transparent wiring layers on the substrate can also be partially overlapped or completely overlapped during actual implementation. , is not limited here.
  • the material of the transparent wiring layer may be ITO.
  • the resolution of the first display area AA1 can be smaller than the resolution of the second display area AA2, so that the first The transmittance of the display area A1 is greater than the transmittance of the second display area AA2 to realize the under-screen camera technology; or, the resolution of the first display area AA1 is roughly the same as that of the second display area AA2, which can enhance the screen
  • the luminance of the lower camera display area (first display area AA1 ) reduces the brightness difference between the main display area (ie the second display area AA2 ) and the under-screen camera display area (ie the first display area AA1 ).
  • the shape of the first display area AA1 may be a circle as shown in FIG. 1 and FIG. 9 , or other shapes such as rectangle, ellipse, or polygon, which may be specifically designed according to actual needs. It is not limited here.
  • the second display area AA2 can surround the periphery of the first display area AA1 as shown in FIG. 1 and FIG.
  • the upper border of the first display area AA1 coincides with the upper border of the second display area AA2 .
  • the first display area AA1 is configured to install a photosensitive device, such as a camera module. Since there are only light-emitting devices in the first display area AA1 in the present disclosure, a larger light-transmitting area can be provided, which is helpful for adapting a larger-sized camera module.
  • an embodiment of the present disclosure further provides a display device, including a photosensitive device, and the above-mentioned display substrate; wherein the photosensitive device is disposed in the first display area of the display substrate.
  • the photosensitive device may be a camera module.
  • an embodiment of the present disclosure also provides a driving method for the above-mentioned display substrate, including:
  • the first initialization voltage is applied to the first sub-pixel (green sub-pixel G) through the first initialization voltage line VIN1
  • the second initialization voltage is applied to the second sub-pixel (red sub-pixel G) through the second initialization voltage line VIN2.
  • the first initialization voltage is greater than the second initialization voltage.
  • the first initialization voltage is applied to the first sub-pixel through the first initialization voltage line
  • the second initialization voltage is applied to the second sub-pixel through the second initialization voltage line
  • the first The initialization voltage is greater than the second initialization voltage, which can keep the charging time of the first sub-pixel and the second sub-pixel consistent, thereby solving the problem of bad purple in the first display area.
  • the above-mentioned display substrate provided by the embodiment of the present disclosure, as shown in FIG. 6 , it also includes:
  • a second initialization voltage is applied to the third sub-pixel (blue sub-pixel B) through the second initialization voltage line VIN2.
  • the turn-on time of the green sub-pixel G is longer than the turn-on time of the red sub-pixel R
  • the turn-on time of the red sub-pixel R is longer than the turn-on time of the blue sub-pixel B
  • the red sub-pixel R and The turn-on time of the blue sub-pixel B has little difference, so the same initialization voltage as that of the second sub-pixel can be input to the third sub-pixel (blue sub-pixel B) through the second initialization voltage line at the same time, that is, the input green
  • the initialization voltage of the sub-pixel G is set to be higher than the initialization voltage of the input red sub-pixel R
  • the initialization voltages of the input red sub-pixel R and the blue sub-pixel B are set to be the same, so that the first sub-pixel, the second sub-pixel It is consistent with the charging time of the third sub-
  • the first initialization voltage may be approximately 0.5V greater than the second initialization voltage.
  • the first initialization voltage may be -2.0 ⁇ 0.2V
  • the second initialization voltage may be -2.5 ⁇ 0.2V.
  • each pixel unit in the first display area AA1 further includes a third sub-pixel (blue sub-pixel B), and the third The emission color of the pixel (blue sub-pixel B) is different from the emission color of the first sub-pixel (green sub-pixel G) and the emission color of the second sub-pixel (red sub-pixel R);
  • the first display area AA1 further includes a third initialization voltage line (not shown), the third sub-pixel (blue sub-pixel B) is electrically connected to the third initialization voltage line, and the third initialization voltage line is configured to receive an initialization voltage line, an initialization voltage received by the second initialization voltage line;
  • the driving method may also include:
  • a third initialization voltage is applied to the third subpixel (blue subpixel B) through the third initialization voltage line VIN3;
  • the third initialization voltage is less than the second initialization voltage, because the turn-on time of the green sub-pixel G is longer than the turn-on time of the red sub-pixel R, and the turn-on time of the red sub-pixel R is longer than the turn-on time of the blue sub-pixel B, so the first One sub-pixel, the second sub-pixel and the third sub-pixel can be electrically connected to different initialization voltage lines respectively, so that the first initialization voltage input to the green sub-pixel G can be set to be higher than the initialization voltage input to the red sub-pixel R, And the initialization voltage input to the red sub-pixel R is set to be higher than the initialization voltage input to the blue sub-pixel B, so that the charging time of the first sub-pixel, the second sub-pixel and the third sub-pixel are consistent, thereby solving the first The problem of bad purple in the display area AA1.
  • the first initialization voltage is approximately 0.2V greater than the second initialization voltage
  • the second initialization voltage is approximately 0.3V greater than the third initialization voltage.
  • the first initialization voltage may be -2.0 ⁇ 0.2V
  • the second initialization voltage may be -2.2 ⁇ 0.2V
  • the third initialization voltage may be -2.5 ⁇ 0.2V.
  • the turn-on time (that is, the charging time) of the sub-pixel since the turn-on time (that is, the charging time) of the sub-pixel has a large relationship with the potential of the anode of the light-emitting device, the potential of the anode of the light-emitting device is strongly related to the initialization voltage. , when the initialization voltage is increased, the charging time (that is, the lighting time) can be reduced. Therefore, the embodiment of the present disclosure transmits the initialization voltage to the first sub-pixel and the second sub-pixel respectively through the first initialization voltage line and the second initialization line arranged on the display substrate, so as to realize the reception of the first sub-pixel and the second sub-pixel.
  • Different initialization voltages so that, for example, when the first sub-pixel in the first display area is turned on for too long and causes poor purple in the first display area, it can be input to the first sub-pixel through the first initialization voltage line
  • the initialization voltage is greater than the initialization voltage input to the second sub-pixel through the second initialization voltage line, so that the charging time of the first sub-pixel and the second sub-pixel are consistent, thereby solving the problem of bad purple in the first display area.

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Abstract

本公开实施例提供的一种显示基板及其驱动方法、显示装置，该显示基板具有显示区和边框区，显示区包括：第一显示区和第二显示区；第一显示区的透光率大于第二显示区的透光率；第一显示区包括阵列分布的多个像素单元，各像素单元包括发光颜色不同的第一子像素和第二子像素；第一显示区包括第一初始化电压线和第二初始化电压线，第一初始化电压线与第一子像素电连接，第二初始化电压线与第二子像素电连接，第一初始化电压线和第二初始化电压线被配置为接收不同的初始化电压。

Description

一种显示基板及其驱动方法、显示装置 技术领域
本公开涉及显示技术领域，尤其涉及一种显示基板及其驱动方法、显示装置。
背景技术
随着智能手机的高速发展，不仅要求手机的外形美观，还需兼顾给手机使用者带来更出色的视觉体验。各大厂商开始在智能手机上提高屏占比，使得全面屏成为智能手机的一个新竞争点。随着全面屏的发展，在性能和功能上的提升需求也与日俱增，屏下摄像头在不影响高屏占比的前提下，在一定程度上可以带来视觉和使用体验上的冲击感。
发明内容
本公开实施例提供的一种显示基板，具有显示区和边框区，所述显示区包括：第一显示区和第二显示区；所述第一显示区的透光率大于所述第二显示区的透光率；
所述第一显示区包括阵列分布的多个像素单元，各所述像素单元包括发光颜色不同的第一子像素和第二子像素；
所述第一显示区包括第一初始化电压线和第二初始化电压线，所述第一初始化电压线与所述第一子像素电连接，所述第二初始化电压线与所述第二子像素电连接，所述第一初始化电压线和所述第二初始化电压线被配置为接收不同的初始化电压。
可选地，在本公开实施例提供的上述显示基板中，各所述像素单元还包括第三子像素，所述第三子像素的发光颜色与所述第一子像素的发光颜色、所述第二子像素的发光颜色均不同，所述第三子像素与所述第二初始化电压线电连接。
可选地，在本公开实施例提供的上述显示基板中，包括依次层叠设置的衬底基板、第一栅极金属层、第二栅极金属层和源漏金属层；
所述第一初始化电压线、所述第二初始化电压线与所述第一栅极金属层同层设置；或者，
所述第一初始化电压线、所述第二初始化电压线与所述第二栅极金属层同层设置；或者，
所述第一初始化电压线、所述第二初始化电压线中的一个与所述第一栅极金属层同层设置，另一个与所述第二栅极金属层同层设置。
可选地，在本公开实施例提供的上述显示基板中，所述第一子像素、所述第二子像素和所述第三子像素均包括发光器件和驱动电路，所述驱动电路位于所述边框区或所述第二显示区；
所述驱动电路包括第一初始化晶体管、第二初始化晶体管、驱动晶体管、数据写入晶体管、阈值补偿晶体管、第一发光控制晶体管、第二发光控制晶体管和存储电容；
所述第一初始化晶体管的栅极与复位信号线电连接，所述第一子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素和所述第三子像素对应的驱动电路中的第一初始化晶体管的第一极均与所述第二初始化电压线电连接，所述第一初始化晶体管的第二极与所述驱动晶体管的栅极电连接；
所述第二初始化晶体管的栅极与扫描信号线电连接，所述第一子像素对应的驱动电路中的第二初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素和所述第三子像素对应的驱动电路中的第二初始化晶体管的第一极均与所述第二初始化电压线电连接，所述第二初始化晶体管的第二极与所述发光器件的阳极电连接；
所述第一发光控制晶体管的栅极与发光控制线电连接，所述第一发光控制晶体管的第一极与第一电源线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件的阳极电连接；所述发光器件的阴极与第二电源线电连接；
所述阈值补偿晶体管的栅极与所述扫描信号线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所阈值补偿晶体管的第二极与所述驱动晶体管的第二极电连接；
所述数据写入晶体管的栅极与所述扫描信号线电连接，所述数据写入晶体管的第一极与数据信号线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连接；
所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接。
可选地，在本公开实施例提供的上述显示基板中，各所述像素单元还包括第三子像素，所述第三子像素的发光颜色与所述第一子像素的发光颜色、所述第二子像素的发光颜色均不同；
所述第一显示区还包括第三初始化电压线，所述第三子像素与所述第三初始化电压线电连接，所述第三初始化电压线被配置为接收不同于所述第一初始化电压线、所述第二初始化电压线接收的初始化电压。
可选地，在本公开实施例提供的上述显示基板中，包括依次层叠设置的衬底基板、第一栅极金属层、第二栅极金属层和源漏金属层；
所述第一初始化电压线、所述第二初始化电压线、所述第三初始化电压线与所述第一栅极金属层同层设置；或者，
所述第一初始化电压线、所述第二初始化电压线、所述第三初始化电压线与所述第二栅极金属层同层设置；或者，
所述第一初始化电压线、所述第二初始化电压线、所述第三初始化电压线中的两个与所述第一栅极金属层同层设置，另一个与所述第二栅极金属层同层设置。
可选地，在本公开实施例提供的上述显示基板中，所述第一子像素、所述第二子像素和所述第三子像素均包括发光器件和驱动电路，所述驱动电路位于所述边框区或所述第二显示区；
所述驱动电路包括第一初始化晶体管、第二初始化晶体管、驱动晶体管、数据写入晶体管、阈值补偿晶体管、第一发光控制晶体管、第二发光控制晶体管和存储电容；
所述第一初始化晶体管的栅极与复位信号线电连接，所述第一子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第二初始化电压线电连接，所述第三子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第三初始化电压线电连接，所述第一初始化晶体管的第二极与所述驱动晶体管的栅极电连接；
所述第二初始化晶体管的栅极与扫描信号线电连接，所述第一子像素对应的驱动电路中的第二初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素对应的驱动电路中的第二初始化晶体管的第一极与所述第二初始化电压线电连接，所述第三子像素对应的驱动电路中的第二初始化晶体管的第一极与所述第三初始化电压线电连接，所述第二初始化晶体管的第二极与所述发光器件的阳极电连接；
所述第一发光控制晶体管的栅极与发光控制线电连接，所述第一发光控制晶体管的第一极与第一电源线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件的阳极电连接；所述发光器件的阴极与第二电源线电连接；
所述阈值补偿晶体管的栅极与所述扫描信号线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所阈值补偿晶体管的第二极 与所述驱动晶体管的第二极电连接；
所述数据写入晶体管的栅极与所述扫描信号线电连接，所述数据写入晶体管的第一极与数据信号线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连接；
所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接。
可选地，在本公开实施例提供的上述显示基板中，所述多个驱动电路位于与所述第一显示区邻近的所述边框区内；或者，
所述第二显示区具有邻近所述第一显示区的过渡区，所述多个驱动电路位于所述过渡区内。
可选地，在本公开实施例提供的上述显示基板中，所述第一子像素为绿色子像素，所述第二子像素为红色子像素，所述第三子像素为蓝色子像素。
可选地，在本公开实施例提供的上述显示基板中，还包括位于所述驱动电路和所述发光器件的阳极之间的至少一层透明走线层，所述驱动电路和所述阳极通过位于所述透明走线层的透明走线电连接。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区的分辨率小于所述第二显示区的分辨率，或所述第一显示区的分辨率与所述第二显示区的分辨率大致相同。
可选地，在本公开实施例提供的上述显示基板中，所述第一显示区的形状为圆形、椭圆形、矩形或多边形中的至少一种。
相应地，本公开实施例还提供了一种显示装置，包括感光器件，以及上述任一项所述的显示基板；其中，所述感光器件被设置在所述显示基板的第一显示区。
相应地，本公开实施例还提供了一种上述任一项所述的显示基板的驱动方法，包括：
在初始化阶段，通过所述第一初始化电压线向所述第一子像素加载第一初始化电压，通过所述第二初始化电压线向所述第二子像素加载第二初始化 电压；其中，
所述第一初始化电压大于所述第二初始化电压。
可选地，在本公开实施例提供的上述驱动方法中，还包括：
在初始化阶段，通过所述第二初始化电压线向所述第三子像素加载所述第二初始化电压。
可选地，在本公开实施例提供的上述驱动方法中，所述第一初始化电压大于所述第二初始化电压大致0.5V。
可选地，在本公开实施例提供的上述驱动方法中，所述第一显示区的各所述像素单元还包括第三子像素，所述第三子像素的发光颜色与所述第一子像素的发光颜色、所述第二子像素的发光颜色均不同；所述显示基板的显示区还包括第三初始化电压线，所述第三子像素与所述第三初始化电压线电连接，所述第三初始化电压线被配置为接收不同于所述第一初始化电压线、所述第二初始化电压线接收的初始化电压；
所述驱动方法还包括：
在初始化阶段，通过所述第三初始化电压线向所述第三子像素加载第三初始化电压；其中，
所述第三初始化电压小于所述第二初始化电压。
可选地，在本公开实施例提供的上述驱动方法中，所述第一初始化电压大于所述第二初始化电压大致0.2V，所述第二初始化电压大于所述第三初始化电压大致0.3V。
附图说明
为了更清楚地说明本公开实施例中的技术方案，下面将对实施例描述中所需要使用的附图作简要介绍，显而易见地，下面描述中的附图仅仅是本公开的一些实施例，对于本领域的普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本公开实施例提供的一种显示基板的俯视示意图；
图2为本公开实施例提供的三种子像素的启亮时间模拟示意图；
图3为本公开实施例提供的红色子像素中驱动电路的结构示意图；
图4为本公开实施例提供的绿色子像素中驱动电路的结构示意图；
图5为本公开实施例提供的蓝色子像素中驱动电路的结构示意图；
图6为图3-图5对应的layout示意图；
图7A为图3对应的layout示意图；
图7B为图4对应的layout示意图；
图7C为图5对应的layout示意图；
图8为本公开实施例提供的另一种蓝色子像素中驱动电路的结构示意图；
图9为本公开实施例提供的又一种显示基板的俯视示意图。
具体实施方式
为使本公开实施例的目的、技术方案和优点更加清楚，下面将结合本公开实施例的附图，对本公开实施例的技术方案进行清楚、完整地描述。显然，所描述的实施例是本公开的一部分实施例，而不是全部的实施例。并且在不冲突的情况下，本公开中的实施例及实施例中的特征可以相互组合。基于所描述的本公开的实施例，本领域普通技术人员在无需创造性劳动的前提下所获得的所有其他实施例，都属于本公开保护的范围。
除非另外定义，本公开使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性，而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同，而不排除其他元件或者物件。“连接”或者“相连”等类似的词语并非限定于物理的或者机械的连接，而是可以包括电性的连接，不管是直接的还是间接的。
需要注意的是，附图中各图形的尺寸和形状不反映真实比例，目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元 件或具有相同或类似功能的元件。
如图1所示，屏下摄像头技术一般在显示区AA内设置第一显示区AA1和第二显示区AA2，其中第二显示区AA2占显示区绝大部分，第一显示区AA1占据显示区较小部分，第一显示区AA1是屏下摄像头放置的位置。屏下摄像头就是指前置摄像头位于屏幕下方但并不影响屏幕显示功能，不使用前置摄像头的时候，摄像头上方的屏幕仍可以正常显示图像。所以从外观上看，屏下摄像头不会有任何相机孔，真正的达到了全面屏显示效果。但是，目前在屏下摄像头设计方案中，是将第一显示区AA1的像素电路设置在第一显示区AA1上方的边框区BB或设置在邻近第一显示区AA1的第二显示区AA2，以像素电路设置在第一显示区AA1上方的边框区BB为例，像素电路与第一显示区AA1内的发光器件通过ITO走线100连接，以此将周边的像素信号传递到屏下摄像头区域。然而，由于ITO走线100过长，造成第一显示区AA1内R/G/B子像素的启亮时间延长，且R/G/B子像素的启亮时间(对应a、b、c)存在差异，如图2所示，子像素B最先启亮，紧接着是子像素R启亮，而子像素G最后启亮。因子像素G启亮时间过长，显示时人眼感知到紫色，即为第一显示区AA1内显示出现发紫不良的问题。
为了解决上述问题，本公开实施例提供了一种显示基板，如图1所示，具有显示区AA和边框区BB，显示区AA包括：第一显示区AA1和第二显示区AA2；第一显示区AA1的透光率大于第二显示区AA2的透光率；
第一显示区AA1包括阵列分布的多个像素单元(未示出)，各像素单元包括发光颜色不同的第一子像素(未示出)和第二子像素(未示出)；
第一显示区AA1包括第一初始化电压线(未示出)和第二初始化电压线(未示出)，第一初始化电压线与第一子像素电连接，第二初始化电压线与第二子像素电连接，第一初始化电压线和第二初始化电压线被配置为接收不同的初始化电压。
本公开实施例提供的上述显示基板，由于子像素的启亮时间(即充电时间)与发光器件阳极(后续介绍)的电位有较大关系，发光器件阳极的电位 与初始化电压强相关，当初始化电压提升时可减小充电时间(即启亮时间)。因此本公开实施例通过设置在显示基板上的第一初始化电压线和第二初始化线分别对第一子像素和第二子像素进行初始化电压的传输，实现第一子像素和第二子像素接收不同的初始化电压，这样例如当第一显示区AA1内的第一子像素启亮时间过长导致第一显示区AA1内出现发紫不良的问题时，可以通过第一初始化电压线向第一子像素输入初始化电压大于通过第二初始化电压线向第二子像素输入的初始化电压，从而使得第一子像素和第二子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，第一子像素为绿色子像素G，第二子像素为红色子像素R。如图2所示，由于绿色子像素G的启亮时间大于红色子像素R的启亮时间，因此可以将输入绿色子像素G的初始化电压设置成高于输入红色子像素R的初始化电压，从而使得第一子像素和第二子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1所示，第一显示区AA1内的各像素单元还包括第三子像素(蓝色子像素B)，第三子像素的发光颜色与第一子像素(绿色子像素G)的发光颜色、第二子像素(红色子像素R)的发光颜色均不同，第三子像素(蓝色子像素B)与第二初始化电压线电连接。如图2所示，由于绿色子像素G的启亮时间大于红色子像素R的启亮时间，红色子像素R的启亮时间大于蓝色子像素B的启亮时间，并且红色子像素R和蓝色子像素B的启亮时间差异不大，第三子像素(蓝色子像素B)可以与第二初始化电压线电连接，即可以将输入绿色子像素G的初始化电压设置成高于输入红色子像素R的初始化电压，且将输入红色子像素R和蓝色子像素B的初始化电压设置成相同，从而使得第一子像素、第二子像素和第三子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，包括依次层叠 设置的衬底基板、第一栅极金属层、第二栅极金属层和源漏金属层，各金属层之间相互绝缘；
第一初始化电压线、第二初始化电压线与第一栅极金属层同层设置；或者，
第一初始化电压线、第二初始化电压线与第二栅极金属层同层设置；或者，
第一初始化电压线、第二初始化电压线中的一个与第一栅极金属层同层设置，另一个与第二栅极金属层同层设置。
具体的，为了简化制作工艺且保证显示基板的厚度，本实施例中将第一初始化电压线、第二初始化电压线设置为与第一栅极金属层和/或第二栅极金属层同层且同材料设置，进而实现在设置第一栅极金属层和第二栅极金属层的同时既能够完成第一初始化电压线、第二初始化电压线的同步制作；其中，第一初始化电压线、第二初始化电压线可以同时设置在第一栅极金属层或同时设置在第二栅极金属层或一个设置在第一栅极金属层一个设置在第二栅极金属层，由于第二栅极金属层一般设置电容的极板，第二栅极金属层空间较大，因而将第一初始化电压线、第二初始化电压线同时设置在第二栅极金属层是优选的设置方式。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1所示，第一显示区AA1内的第一子像素(绿色子像素G)、第二子像素(红色子像素R)和第三子像素(蓝色子像素B)均包括发光器件和驱动电路，驱动电路位于边框区BB或第二显示区AA2；
如图3-图5所示，图3为第二子像素(红色子像素R)的驱动电路示意图，图4为第一子像素(绿色子像素G)的驱动电路示意图，图5为第三子像素(蓝色子像素B)的驱动电路示意图，驱动电路包括第一初始化晶体管T1、第二初始化晶体管T7、驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6和存储电容C1；
第一初始化晶体管T1的栅极与复位信号线RES电连接，第一子像素(绿 色子像素G)对应的驱动电路中的第一初始化晶体管T1的第一极与第一初始化电压线VIN1电连接，第二子像素(红色子像素R)和第三子像素(蓝色子像素B)对应的驱动电路中的第一初始化晶体管T1的第一极均与第二初始化电压线VIN2电连接，第一初始化晶体管T1的第二极与驱动晶体管T3的栅极电连接；
第二初始化晶体管T7的栅极与扫描信号线GA电连接，第一子像素(绿色子像素G)对应的驱动电路中的第二初始化晶体管T7的第一极与第一初始化电压线VIN1电连接，第二子像素(红色子像素R)和第三子像素(蓝色子像素B)对应的驱动电路中的第二初始化晶体管T7的第一极均与第二初始化电压线VIN2电连接，第二初始化晶体管T7的第二极与发光器件L的阳极电连接；
第一发光控制晶体管T5的栅极与发光控制线EM电连接，第一发光控制晶体管T5的第一极与第一电源线VDD电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接；
第二发光控制晶体管T6的栅极与发光控制线EM电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光器件L的阳极电连接；发光器件L的阴极与第二电源线VSS电连接；
阈值补偿晶体管T2的栅极与扫描信号线GA电连接，阈值补偿晶体管T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接；
数据写入晶体管T4的栅极与扫描信号线GA电连接，数据写入晶体管T4的第一极与数据信号线DA电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接；
存储电容C1的第一极与第一电源线VDD电连接，存储电容C1的第二极与驱动晶体管T3的栅极电连接。
如图6所示，图6为图3-图5三个子像素对应的驱动电路的layout(版图) 示意图，该驱动电路可以位于图1中的边框区BB内，也可以位于图1中的第二显示区AA2邻近第一显示区AA1内，也可以分布于第二显示区AA2内，第一子像素(绿色子像素G)对应的驱动电路中的第一初始化晶体管T1的第一极、第二初始化晶体管T7的第一极均与第一初始化电压线VIN1电连接，第二子像素(红色子像素R)和第三子像素(蓝色子像素B)对应的驱动电路中的第一初始化晶体管T1的第一极、第二初始化晶体管T7的第一极均与第二初始化电压线VIN2电连接，由于红色子像素R和蓝色子像素B的启亮时间差异不大，第三子像素(蓝色子像素B)和第二子像素(红色子像素R)可以均与第二初始化电压线VIN2电连接，从而可以将输入绿色子像素G的初始化电压设置成高于输入红色子像素R的初始化电压，且将输入红色子像素R和蓝色子像素B的初始化电压设置成相同，从而使得第一子像素、第二子像素和第三子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
为了清楚的示意图3-图5三个子像素对应的驱动电路的layout(版图)示意图，如图7A-图7C所示，图7A-图7C分别为图3-图5所示的驱动电路的layout(版图)示意图，图7A对应的第二子像素(红色子像素R)和图7C对应的第三子像素(蓝色子像素B)均与第二初始化电压线VIN2电连接，图7B对应的第一子像素(绿色子像素G)与第一初始化电压线VIN1电连接。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1所示，第一显示区AA1内的各像素单元还包括第三子像素(蓝色子像素B)，第三子像素(蓝色子像素B)的发光颜色与第一子像素(绿色子像素G)的发光颜色、第二子像素(红色子像素R)的发光颜色均不同；
第一显示区AA1还包括第三初始化电压线(未示出)，第三子像素(蓝色子像素B)与第三初始化电压线电连接，第三初始化电压线被配置为接收不同于第一初始化电压线、第二初始化电压线接收的初始化电压。如图2所示，由于绿色子像素G的启亮时间大于红色子像素R的启亮时间，红色子像素R的启亮时间大于蓝色子像素B的启亮时间，三种子像素与不同的初始化 电压线电连接，因此可以通过各自对应的不同的初始化电压线分别输入对应的初始化电压，即可以将输入绿色子像素G的初始化电压设置成高于输入红色子像素R的初始化电压，且将输入红色子像素R的初始化电压设置成高于输入蓝色子像素B的初始化电压。从而使得第一子像素、第二子像素和第三子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，包括依次层叠设置的衬底基板、第一栅极金属层、第二栅极金属层和源漏金属层，各金属层之间相互绝缘；
第一初始化电压线、第二初始化电压线、第三初始化电压线与第一栅极金属层同层设置；或者，
第一初始化电压线、第二初始化电压线、第三初始化电压线与第二栅极金属层同层设置；或者，
第一初始化电压线、第二初始化电压线、第三初始化电压线中的两个与第一栅极金属层同层设置，另一个与第二栅极金属层同层设置。
具体的，为了简化制作工艺且保证显示基板的厚度，本实施例中将第一初始化电压线、第二初始化电压线、第三初始化电压线设置为与第一栅极金属层和/或第二栅极金属层同层且同材料设置，进而实现在设置第一栅极金属层和第二栅极金属层的同时既能够完成第一初始化电压线、第二初始化电压线、第三初始化电压线的同步制作；其中，第一初始化电压线、第二初始化电压线、第三初始化电压线可以同时设置在第一栅极金属层或同时设置在第二栅极金属层或两个设置在第一栅极金属层一个设置在第二栅极金属层，由于第二栅极金属层一般设置电容的极板，第二栅极金属层空间较大，因而将第一初始化电压线、第二初始化电压线、第三初始化电压线同时设置在第二栅极金属层是优选的设置方式。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1所示，第一显示区AA1内的第一子像素(绿色子像素G)、第二子像素(红色子像素R)和第三子像素(蓝色子像素B)均包括发光器件和驱动电路，驱动电路 位于边框区BB或第二显示区AA2；
如图3、图4和图8所示，图8为第三子像素(蓝色子像素B)的另一种驱动电路示意图，驱动电路包括第一初始化晶体管T1、第二初始化晶体管T7、驱动晶体管T3、数据写入晶体管T4、阈值补偿晶体管T2、第一发光控制晶体管T5、第二发光控制晶体管T6和存储电容C1；
第一初始化晶体管T1的栅极与复位信号线RES电连接，第一子像素(绿色子像素G)对应的驱动电路中的第一初始化晶体管T1的第一极与第一初始化电压线VIN1电连接，第二子像素(红色子像素R)对应的驱动电路中的第一初始化晶体管T1的第一极与第二初始化电压线VIN2电连接，第三子像素(蓝色子像素B)对应的驱动电路中的第一初始化晶体管T1的第一极与第三初始化电压线VIN3电连接，第一初始化晶体管T1的第二极与驱动晶体管T3的栅极电连接；
第二初始化晶体管T7的栅极与扫描信号线GA电连接，第一子像素(绿色子像素G)对应的驱动电路中的第二初始化晶体管T7的第一极与第一初始化电压线VIN1电连接，第二子像素(红色子像素R)对应的驱动电路中的第二初始化晶体管T7的第一极与第二初始化电压线VIN2电连接，第三子像素(蓝色子像素B)对应的驱动电路中的第二初始化晶体管T7的第一极与第三初始化电压线VIN3电连接，第二初始化晶体管T7的第二极与发光器件L的阳极电连接；
第一发光控制晶体管T5的栅极与发光控制线EM电连接，第一发光控制晶体管T5的第一极与第一电源线VDD电连接，第一发光控制晶体管T5的第二极与驱动晶体管T3的第一极电连接；
第二发光控制晶体管T6的栅极与发光控制线EM电连接，第二发光控制晶体管T6的第一极与驱动晶体管T3的第二极电连接，第二发光控制晶体管T6的第二极与发光器件L的阳极电连接；发光器件L的阴极与第二电源线VSS电连接；
阈值补偿晶体管T2的栅极与扫描信号线GA电连接，阈值补偿晶体管 T2的第一极与驱动晶体管T3的栅极电连接，阈值补偿晶体管T2的第二极与驱动晶体管T3的第二极电连接；
数据写入晶体管T4的栅极与扫描信号线GA电连接，数据写入晶体管T4的第一极与数据信号线DA电连接，数据写入晶体管T4的第二极与驱动晶体管T3的第一极电连接；
存储电容C1的第一极与第一电源线VDD电连接，存储电容C1的第二极与驱动晶体管T3的栅极电连接。
具体地，图3、图4和图8三个子像素对应的驱动电路可以位于图1中的边框区BB内，也可以位于图1中的第二显示区AA2邻近第一显示区AA1内，也可以分布于第二显示区AA2内，第一子像素(绿色子像素G)对应的驱动电路中的第一初始化晶体管T1的第一极与第一初始化电压线VIN1电连接，第二子像素(红色子像素R)对应的驱动电路中的第一初始化晶体管T1的第一极与第二初始化电压线VIN2电连接，第三子像素(蓝色子像素B)对应的驱动电路中的第一初始化晶体管T1的第一极与第三初始化电压线VIN3电连接，如图2所示，由于绿色子像素G的启亮时间大于红色子像素R的启亮时间，红色子像素R的启亮时间大于蓝色子像素B的启亮时间，因此第一子像素、第二子像素和第三子像素可以分别与不同的初始化电压线电连接，从而可以将输入绿色子像素G的初始化电压设置成高于输入红色子像素R的初始化电压，且将输入红色子像素R的初始化电压设置成高于输入蓝色子像素B的初始化电压，从而使得第一子像素、第二子像素和第三子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1所示，多个驱动电路位于与第一显示区AA1邻近的边框区内；或者，
如图9所示，第二显示区AA2具有邻近第一显示区AA1的过渡区CC，多个驱动电路位于过渡区CC内，或者多个驱动电路也可以分布于第二显示区AA2内。
在具体实施时，在本公开实施例提供的上述显示基板中，还包括位于驱 动电路和发光器件的阳极之间的至少一层透明走线层，驱动电路和阳极通过位于透明走线层的透明走线电连接。具体地，透明走线层可以为多层，各层绝缘设置，每一透明走线层均包括多条透明走线。
可选地，在本公开实施例提供的上述显示面板中，每一透明走线层所含的多条透明走线互不交叠，不同透明走线层所含的多条透明走线在衬底基板上的正投影互不交叠。当然，由于不同透明走线层之间是相互绝缘的，因此在具体实施时，不同透明走线层所含的多条透明走线在基底上的正投影也可以部分交叠，也可以完全重合，在此不做限定。
可选地，在本公开实施例提供的上述显示面板中，透明走线层的材料可以为ITO。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1和图9所示，第一显示区AA1的分辨率可以小于第二显示区AA2的分辨率，这样可以实现第一显示区A1的透过率大于第二显示区AA2的透过率，以实现屏下摄像头技术；或者，第一显示区AA1的分辨率与第二显示区AA2的分辨率大致相同，可以提升屏下摄像头显示区(第一显示区AA1)发光亮度，降低主要显示区(即第二显示区AA2)和屏下摄像头显示区(即第一显示区AA1)的亮度差异。
需要说明的是，在本公开中第一显示区AA1的形状可以为图1和图9所示的圆形，也可以为矩形、椭圆形或多边形等其他形状，具体可根据实际需要进行设计，在此不做限定。第二显示区AA2可以如图1和图9所示环绕第一显示区AA1的周边；也可以包围部分第一显示区AA1，例如包围第一显示区AA1的左侧、下侧和右侧，而第一显示区AA1的上侧边界与第二显示区AA2的上侧边界重合。
可选地，在本公开实施例提供的上述显示基板中，如图1和图9所示，第一显示区AA1被配置为安装感光器件，例如摄像头模组。由于在本公开中第一显示区AA1内仅存在发光器件，因此能够提供更大面积的透光区域，有助于适配更大尺寸的摄像头模组。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括感光器件，以及上述显示基板；其中，感光器件被设置在显示基板的第一显示区。可选地，感光器件可以为摄像头模组。
基于同一发明构思，本公开实施例还提供了一种上述显示基板的驱动方法，包括：
如图6所示，在初始化阶段，通过第一初始化电压线VIN1向第一子像素(绿色子像素G)加载第一初始化电压，通过第二初始化电压线VIN2向第二子像素(红色子像素R)加载第二初始化电压；其中，
第一初始化电压大于第二初始化电压。
本公开实施例提供的上述显示基板的驱动方法，通过第一初始化电压线向第一子像素加载第一初始化电压，通过第二初始化电压线向第二子像素加载第二初始化电压，且第一初始化电压大于第二初始化电压，可以使得第一子像素和第二子像素的充电时间保持一致，从而解决第一显示区内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，如图6所示，还包括：
在初始化阶段，通过第二初始化电压线VIN2向第三子像素(蓝色子像素B)加载第二初始化电压。如图2所示，由于绿色子像素G的启亮时间大于红色子像素R的启亮时间，红色子像素R的启亮时间大于蓝色子像素B的启亮时间，并且红色子像素R和蓝色子像素B的启亮时间差异不大，因此可以通过第二初始化电压线同时向第三子像素(蓝色子像素B)输入与第二子像素相同的初始化电压，即可以将输入绿色子像素G的初始化电压设置成高于输入红色子像素R的初始化电压，且将输入红色子像素R和蓝色子像素B的初始化电压设置成相同，从而使得第一子像素、第二子像素和第三子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，第一初始化电压可以大于第二初始化电压大致0.5V。优地，第一初始化电压可以为-2.0± 0.2V，第二初始化电压可以为-2.5±0.2V。
在具体实施时，在本公开实施例提供的上述显示基板中，如图1所示，第一显示区AA1内的各像素单元还包括第三子像素(蓝色子像素B)，第三子像素(蓝色子像素B)的发光颜色与第一子像素(绿色子像素G)的发光颜色、第二子像素(红色子像素R)的发光颜色均不同；
第一显示区AA1还包括第三初始化电压线(未示出)，第三子像素(蓝色子像素B)与第三初始化电压线电连接，第三初始化电压线被配置为接收不同于第一初始化电压线、第二初始化电压线接收的初始化电压；
所述驱动方法还可以包括：
在初始化阶段，通过第三初始化电压线VIN3向第三子像素(蓝色子像素B)加载第三初始化电压；其中，
第三初始化电压小于第二初始化电压，由于绿色子像素G的启亮时间大于红色子像素R的启亮时间，红色子像素R的启亮时间大于蓝色子像素B的启亮时间，因此第一子像素、第二子像素和第三子像素可以分别与不同的初始化电压线电连接，从而可以将输入绿色子像素G的第一初始化电压设置成高于输入红色子像素R的初始化电压，且将输入红色子像素R的初始化电压设置成高于输入蓝色子像素B的初始化电压，从而使得第一子像素、第二子像素和第三子像素的充电时间保持一致，从而解决第一显示区AA1内发紫不良的问题。
在具体实施时，在本公开实施例提供的上述显示基板中，第一初始化电压大于第二初始化电压大致0.2V，第二初始化电压大于第三初始化电压大致0.3V。优地，第一初始化电压可以为-2.0±0.2V，第二初始化电压可以为-2.2±0.2V，第三初始化电压可以为-2.5±0.2V。
本公开实施例提供的上述显示基板及其驱动方法、显示装置，由于子像素的启亮时间(即充电时间)与发光器件阳极的电位有较大关系，发光器件阳极的电位与初始化电压强相关，当初始化电压提升时可减小充电时间(即启亮时间)。因此本公开实施例通过设置在显示基板上的第一初始化电压线和 第二初始化线分别对第一子像素和第二子像素进行初始化电压的传输，实现第一子像素和第二子像素接收不同的初始化电压，这样例如当第一显示区内的第一子像素启亮时间过长导致第一显示区内出现发紫不良的问题时，可以通过第一初始化电压线向第一子像素输入初始化电压大于通过第二初始化电压线向第二子像素输入的初始化电压，从而使得第一子像素和第二子像素的充电时间保持一致，从而解决第一显示区内发紫不良的问题。
尽管已描述了本公开的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本公开范围的所有变更和修改。
显然，本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样，倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (18)

  1. 一种显示基板，其中，具有显示区和边框区，所述显示区包括：第一显示区和第二显示区；所述第一显示区的透光率大于所述第二显示区的透光率；
    所述第一显示区包括阵列分布的多个像素单元，各所述像素单元包括发光颜色不同的第一子像素和第二子像素；
    所述第一显示区包括第一初始化电压线和第二初始化电压线，所述第一初始化电压线与所述第一子像素电连接，所述第二初始化电压线与所述第二子像素电连接，所述第一初始化电压线和所述第二初始化电压线被配置为接收不同的初始化电压。
  2. 如权利要求1所述的显示基板，其中，各所述像素单元还包括第三子像素，所述第三子像素的发光颜色与所述第一子像素的发光颜色、所述第二子像素的发光颜色均不同，所述第三子像素与所述第二初始化电压线电连接。
  3. 如权利要求2所述的显示基板，其中，包括依次层叠设置的衬底基板、第一栅极金属层、第二栅极金属层和源漏金属层；
    所述第一初始化电压线、所述第二初始化电压线与所述第一栅极金属层同层设置；或者，
    所述第一初始化电压线、所述第二初始化电压线与所述第二栅极金属层同层设置；或者，
    所述第一初始化电压线、所述第二初始化电压线中的一个与所述第一栅极金属层同层设置，另一个与所述第二栅极金属层同层设置。
  4. 如权利要求2所述的显示基板，其中，所述第一子像素、所述第二子像素和所述第三子像素均包括发光器件和驱动电路，所述驱动电路位于所述边框区或所述第二显示区；
    所述驱动电路包括第一初始化晶体管、第二初始化晶体管、驱动晶体管、数据写入晶体管、阈值补偿晶体管、第一发光控制晶体管、第二发光控制晶 体管和存储电容；
    所述第一初始化晶体管的栅极与复位信号线电连接，所述第一子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素和所述第三子像素对应的驱动电路中的第一初始化晶体管的第一极均与所述第二初始化电压线电连接，所述第一初始化晶体管的第二极与所述驱动晶体管的栅极电连接；
    所述第二初始化晶体管的栅极与扫描信号线电连接，所述第一子像素对应的驱动电路中的第二初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素和所述第三子像素对应的驱动电路中的第二初始化晶体管的第一极均与所述第二初始化电压线电连接，所述第二初始化晶体管的第二极与所述发光器件的阳极电连接；
    所述第一发光控制晶体管的栅极与发光控制线电连接，所述第一发光控制晶体管的第一极与第一电源线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件的阳极电连接；所述发光器件的阴极与第二电源线电连接；
    所述阈值补偿晶体管的栅极与所述扫描信号线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所阈值补偿晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述数据写入晶体管的栅极与所述扫描信号线电连接，所述数据写入晶体管的第一极与数据信号线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接。
  5. 如权利要求1所述的显示基板，其中，各所述像素单元还包括第三子 像素，所述第三子像素的发光颜色与所述第一子像素的发光颜色、所述第二子像素的发光颜色均不同；
    所述第一显示区还包括第三初始化电压线，所述第三子像素与所述第三初始化电压线电连接，所述第三初始化电压线被配置为接收不同于所述第一初始化电压线、所述第二初始化电压线接收的初始化电压。
  6. 如权利要求5所述的显示基板，其中，包括依次层叠设置的衬底基板、第一栅极金属层、第二栅极金属层和源漏金属层；
    所述第一初始化电压线、所述第二初始化电压线、所述第三初始化电压线与所述第一栅极金属层同层设置；或者，
    所述第一初始化电压线、所述第二初始化电压线、所述第三初始化电压线与所述第二栅极金属层同层设置；或者，
    所述第一初始化电压线、所述第二初始化电压线、所述第三初始化电压线中的两个与所述第一栅极金属层同层设置，另一个与所述第二栅极金属层同层设置。
  7. 如权利要求5所述的显示基板，其中，所述第一子像素、所述第二子像素和所述第三子像素均包括发光器件和驱动电路，所述驱动电路位于所述边框区或所述第二显示区；
    所述驱动电路包括第一初始化晶体管、第二初始化晶体管、驱动晶体管、数据写入晶体管、阈值补偿晶体管、第一发光控制晶体管、第二发光控制晶体管和存储电容；
    所述第一初始化晶体管的栅极与复位信号线电连接，所述第一子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第二初始化电压线电连接，所述第三子像素对应的驱动电路中的第一初始化晶体管的第一极与所述第三初始化电压线电连接，所述第一初始化晶体管的第二极与所述驱动晶体管的栅极电连接；
    所述第二初始化晶体管的栅极与扫描信号线电连接，所述第一子像素对 应的驱动电路中的第二初始化晶体管的第一极与所述第一初始化电压线电连接，所述第二子像素对应的驱动电路中的第二初始化晶体管的第一极与所述第二初始化电压线电连接，所述第三子像素对应的驱动电路中的第二初始化晶体管的第一极与所述第三初始化电压线电连接，所述第二初始化晶体管的第二极与所述发光器件的阳极电连接；
    所述第一发光控制晶体管的栅极与发光控制线电连接，所述第一发光控制晶体管的第一极与第一电源线电连接，所述第一发光控制晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述第二发光控制晶体管的栅极与所述发光控制线电连接，所述第二发光控制晶体管的第一极与所述驱动晶体管的第二极电连接，所述第二发光控制晶体管的第二极与所述发光器件的阳极电连接；所述发光器件的阴极与第二电源线电连接；
    所述阈值补偿晶体管的栅极与所述扫描信号线电连接，所述阈值补偿晶体管的第一极与所述驱动晶体管的栅极电连接，所阈值补偿晶体管的第二极与所述驱动晶体管的第二极电连接；
    所述数据写入晶体管的栅极与所述扫描信号线电连接，所述数据写入晶体管的第一极与数据信号线电连接，所述数据写入晶体管的第二极与所述驱动晶体管的第一极电连接；
    所述存储电容的第一极与所述第一电源线电连接，所述存储电容的第二极与所述驱动晶体管的栅极电连接。
  8. 如权利要求4或7所述的显示基板，其中，所述多个驱动电路位于与所述第一显示区邻近的所述边框区内；或者，
    所述第二显示区具有邻近所述第一显示区的过渡区，所述多个驱动电路位于所述过渡区内。
  9. 如权利要求2或5所述的显示基板，其中，所述第一子像素为绿色子像素，所述第二子像素为红色子像素，所述第三子像素为蓝色子像素。
  10. 如权利要求4或7所述的显示基板，其中，还包括位于所述驱动电 路和所述发光器件的阳极之间的至少一层透明走线层，所述驱动电路和所述阳极通过位于所述透明走线层的透明走线电连接。
  11. 如权利要求1所述的显示基板，其中，所述第一显示区的分辨率小于所述第二显示区的分辨率，或所述第一显示区的分辨率与所述第二显示区的分辨率大致相同。
  12. 如权利要求1所述的显示基板，其中，所述第一显示区的形状为圆形、椭圆形、矩形或多边形中的至少一种。
  13. 一种显示装置，其中，包括感光器件，以及如权利要求1-12任一项所述的显示基板；其中，所述感光器件被设置在所述显示基板的第一显示区。
  14. 一种如权利要求1-12任一项所述的显示基板的驱动方法，其中，包括：
    在初始化阶段，通过所述第一初始化电压线向所述第一子像素加载第一初始化电压，通过所述第二初始化电压线向所述第二子像素加载第二初始化电压；其中，
    所述第一初始化电压大于所述第二初始化电压。
  15. 如权利要求14所述的驱动方法，其中，还包括：
    在初始化阶段，通过所述第二初始化电压线向所述第三子像素加载所述第二初始化电压。
  16. 如权利要求15所述的驱动方法，其中，所述第一初始化电压大于所述第二初始化电压大致0.5V。
  17. 如权利要求14所述的驱动方法，其中，所述第一显示区的各所述像素单元还包括第三子像素，所述第三子像素的发光颜色与所述第一子像素的发光颜色、所述第二子像素的发光颜色均不同；所述显示基板的显示区还包括第三初始化电压线，所述第三子像素与所述第三初始化电压线电连接，所述第三初始化电压线被配置为接收不同于所述第一初始化电压线、所述第二初始化电压线接收的初始化电压；
    所述驱动方法还包括：
    在初始化阶段，通过所述第三初始化电压线向所述第三子像素加载第三初始化电压；其中，
    所述第三初始化电压小于所述第二初始化电压。
  18. 如权利要求17所述的驱动方法，其中，所述第一初始化电压大于所述第二初始化电压大致0.2V，所述第二初始化电压大于所述第三初始化电压大致0.3V。
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