WO2022228315A1 - 一种服务器系统mmioh基地址的设置方法、装置 - Google Patents

一种服务器系统mmioh基地址的设置方法、装置 Download PDF

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WO2022228315A1
WO2022228315A1 PCT/CN2022/088576 CN2022088576W WO2022228315A1 WO 2022228315 A1 WO2022228315 A1 WO 2022228315A1 CN 2022088576 W CN2022088576 W CN 2022088576W WO 2022228315 A1 WO2022228315 A1 WO 2022228315A1
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mmioh
base address
server system
minimum
target
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PCT/CN2022/088576
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English (en)
French (fr)
Inventor
王兵
钱慧娟
杨少俊
姚藩益
罗鹏芳
李道童
张炳会
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山东英信计算机技术有限公司
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Priority to US18/039,482 priority Critical patent/US11847086B2/en
Publication of WO2022228315A1 publication Critical patent/WO2022228315A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L61/00—Network arrangements, protocols or services for addressing or naming
    • H04L61/50—Address allocation
    • H04L61/5046—Resolving address allocation conflicts; Testing of addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/27—Built-in tests
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G06F9/4411—Configuring for operating with peripheral devices; Loading of device drivers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/16—Memory access
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2101/00—Indexing scheme associated with group H04L61/00
    • H04L2101/60—Types of network addresses
    • H04L2101/695—Types of network addresses using masks or ranges of addresses
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the field of computer technologies, and in particular, to a method, apparatus, device, and medium for setting an MMIOH base address of a server system.
  • the peripheral devices of the server system can be mapped into the memory space of the server system, which will make it easier for the CPU (Central Processing Unit, central processing unit) to monitor the peripheral devices. Access. Therefore, the MMIO specification has been widely used in the field of server technology.
  • the server manufacturer when setting the MMIOH (Memory Mapping I/O High, IO device information is mapped to the high-end memory space of the memory address) base address of the server system, the server manufacturer will pre-set a reasonable default for the server system according to the configuration of the server.
  • the MMIOH base address to ensure the normal operation of the server system.
  • PCIE Peripheral Component Interconnect Express, high-speed serial computer expansion bus standard
  • the purpose of the present application is to provide a method, apparatus, device and medium for setting the MMIOH base address of a server system, so as to improve the efficiency and accuracy of setting the MMIOH base address of the server system. Its specific plan is as follows:
  • a method for setting an MMIOH base address of a server system comprising:
  • the total capacity of all memories in the server system is detected, and the minimum MMIOH base address of the server system is determined according to the MMIO specification and the total capacity;
  • the minimum MMIOH base address is compared with the target MMIOH base address range; wherein the whitelist is based on the target MMIOH base address range.
  • the minimum MMIOH base address is within the target MMIOH base address range, determine the minimum MMIOH base address as the MMIOH base address of the server system, and store the minimum MMIOH base address in the server System's BIOS.
  • the whitelist is written to the BIOS in advance.
  • the target MMIOH base address range corresponding to the target PCIE device cannot be calculated according to the whitelist, a first warning message is prompted, and the minimum MMIOH base address is set as the MMIOH base address of the server system .
  • the process of determining the minimum MMIOH base address of the server system according to the MMIO specification and the total capacity includes:
  • a first calculated value of X+2MB is determined, and the first calculated value is rounded in units of 0.5TB to obtain a second calculated value;
  • X is the total capacity, and MB is Megabyte, TB is terabyte;
  • the second calculated value is set to the minimum MMIOH base address of the server system.
  • the process of comparing the minimum MMIOH base address with the target MMIOH base address range it further includes:
  • the minimum MMIOH base address is not within the target MMIOH base address range, a second warning message is prompted, and the minimum MMIOH base address is set as the MMIOH base address of the server system.
  • the target PCIE device is adjusted according to the second early warning information.
  • the present application also discloses a device for setting the MMIOH base address of a server system, including:
  • a memory detection module configured to detect the total capacity of all memories in the server system during the power-on self-check of the server system, and determine the minimum MMIOH base address of the server system according to the MMIO specification and the total capacity;
  • a device detection module configured to detect the PCIE device configured in the server system to obtain the target PCIE device
  • the address calculation module is configured to compare the minimum MMIOH base address with the target MMIOH base address range if the target MMIOH base address range corresponding to the target PCIE device can be calculated according to the whitelist; Described white list is according to described MMIO specification and the list that the PCIE device that has setting requirement to MMIOH base address is set up;
  • An address determining module configured to determine the minimum MMIOH base address as the MMIOH base address of the server system if the minimum MMIOH base address is within the target MMIOH base address range, and determine the minimum MMIOH base address as the MMIOH base address of the server system.
  • the address is stored in the BIOS of the server system.
  • the present application also discloses a device for setting the MMIOH base address of a server system, including:
  • the processor is configured to implement the steps of the method for setting an MMIOH base address of a server system as disclosed above when executing the computer program.
  • the present application also discloses a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, implements the MMIOH-based server system as disclosed above. The steps of how to set the address.
  • a whitelist is set in advance according to the MMIO specification and the PCIE devices that have setting requirements for the MMIOH base address; when the server system performs a power-on self-check, the total capacity of all memory in the server system is detected, and according to the MMIO
  • the specification and the total capacity of the physical memory of the server system determine the minimum MMIOH base address of the server system; then, detect the PCIE device configured in the server system to obtain the target PCIE device; if the target PCIE device corresponding to the target PCIE device can be calculated according to the whitelist
  • the minimum MMIOH base address is compared with the target MMIOH base address range; if the minimum MMIOH base address is within the target MMIOH base address range, the minimum MMIOH base address is determined as the MMIOH base address of the server system.
  • the method can significantly improve the performance of the MMIOH base address of the server system. Efficiency and accuracy in setting.
  • the device, device and medium for setting the MMIOH base address of a server system provided by the present application also have the above beneficial effects.
  • FIG. 1 is a flowchart of a method for setting an MMIOH base address of a server system provided by an embodiment of the application;
  • FIG. 2 is a structural diagram of a device for setting an MMIOH base address of a server system provided by an embodiment of the application;
  • FIG. 3 is a structural diagram of a device for setting an MMIOH base address of a server system according to an embodiment of the present application.
  • FIG. 1 is a flowchart of a method for setting an MMIOH base address of a server system provided by an embodiment of the application.
  • the setting method includes:
  • Step S11 in the process of the server system performing the power-on self-check, the total capacity of all memories in the server system is detected, and the minimum MMIOH base address of the server system is determined according to the MMIO specification and the total capacity;
  • Step S12 Detect the PCIE device configured in the server system, and obtain the target PCIE device;
  • Step S13 if the target MMIOH base address range corresponding to the target PCIE device can be calculated according to the whitelist, then compare the minimum MMIOH base address with the target MMIOH base address range;
  • the white list is a list set according to the MMIO specification and the PCIE devices that have setting requirements for the MMIOH base address;
  • Step S14 If the minimum MMIOH base address is within the target MMIOH base address range, determine the minimum MMIOH base address as the MMIOH base address of the server system, and store the minimum MMIOH base address in the BIOS of the server system.
  • a method for setting the MMIOH base address of a server system is provided, and the setting method can significantly improve the efficiency and accuracy of setting the MMIOH base address of the server system.
  • the MMIOH base address of the server system is related to the memory capacity of the server system. There are also corresponding settings. Therefore, in this embodiment, it is necessary to set a whitelist in advance according to the provisions of the MMIO specification that have special setting requirements for the MMIOH base address of the PCIE device and the PCIE devices that have special setting requirements for the MMIOH base address.
  • the PCIE devices that have special setting requirements for the MMIOH base address of the PCIE device and the PCIE devices that have special setting requirements for the MMIOH base address are sorted into a white list.
  • the MMIOH base address of the server system is firstly set according to the memory capacity of the server system, that is, in the process of the server performing the power-on self-check, the total capacity of all physical memories in the server system is detected. , and determine the minimum MMIOH base address of the server system according to the MMIO specification and the total capacity of all memory in the server system.
  • the PCIE device configured in the server system is detected to obtain the target PCIE device.
  • the target PCIE device may be either all configured PCIE devices in the server system, or may be a PCIE device that has special setting requirements for the MMIOH base address in the server system. Then, the target PCIE device is compared with the whitelist, and the target MMIOH base address range corresponding to the target PCIE device in the server system is calculated according to the whitelist.
  • the minimum MMIOH base address is compared with the target MMIOH base address range to determine the minimum MMIOH base address and the target MMIOH base address. Whether the MMIOH base address range collides. Assuming that the minimum MMIOH base address is Y, and the target MMIOH base address range corresponding to the target PCIE device in the server system is (A, B), if the minimum MMIOH base address Y is within the target MMIOH base address range (A, B), then It means that the minimum MMIOH base address does not conflict with the target MMIOH base address range. In this case, the minimum MMIOH base address Y can be determined as the MMIOH base address of the server system, and the minimum MMIOH base address Y can be stored in the BIOS of the server system. among.
  • the method for setting the MMIOH base address of the server system can avoid the tedious process of manually setting the MMIOH base address of the server system.
  • This method can be used in different application scenarios.
  • the MMIOH base address of the server system is adaptively set according to the memory capacity of the server system and the PCIE device configured in the server system, which can not only greatly save the R&D personnel in the process of R&D, testing and production of the server.
  • the time required for server production can be saved, and at the same time, the method can also ensure the accuracy and reliability of the MMIOH base address of the server system during the setting process.
  • a whitelist is set in advance according to the MMIO specification and the PCIE devices that have setting requirements for the MMIOH base address;
  • the MMIO specification and the total capacity of the physical memory of the server system determine the minimum MMIOH base address of the server system; then, detect the PCIE devices configured in the server system to obtain the target PCIE device; if the target PCIE device can be calculated according to the whitelist
  • the minimum MMIOH base address is compared with the target MMIOH base address range; if the minimum MMIOH base address is within the target MMIOH base address range, the minimum MMIOH base address is determined as the MMIOH base address of the server system , and store the minimum MMIOH base address in the BIOS of the server system.
  • the foregoing method for setting the MMIOH base address of the server system further includes:
  • the sorted whitelist may be written into the BIOS of the server system in advance. It is conceivable that when the whitelist is written into the BIOS of the server system, the tedious process of calling the whitelist from the remote server can be avoided. In this case, the server system can directly call the whitelist from the BIOS. list, and calculate the target MMIOH base address range corresponding to the target PCIE device in the server system according to the white list.
  • the foregoing method for setting the MMIOH base address of the server system further includes:
  • the target MMIOH base address range corresponding to the target PCIE device cannot be calculated according to the whitelist, a first warning message is prompted, and the minimum MMIOH base address is set as the MMIOH base address of the server system.
  • the target MMIOH base address range corresponding to the target PCIE device cannot be calculated according to the whitelist. That is, the MMIOH base addresses corresponding to different PCIE devices in the server system conflict. In this case, the target MMIOH base address range corresponding to the target PCIE device cannot be calculated according to the whitelist.
  • the server system will prompt the first warning message, and in the BIOS The first warning information is printed and displayed in the middle for the user's analysis and reference.
  • the server system will set the minimum MMIOH base address calculated based on the maximum physical memory capacity of the server system as the MMIOH base address of the server system.
  • this embodiment further describes and optimizes the technical solution.
  • the above steps the process of determining the minimum MMIOH base address of the server system according to the MMIO specification and the total capacity, including:
  • the first calculated value of X+2MB is determined, and the first calculated value is rounded in units of 0.5TB to obtain the second calculated value; where X is the total capacity, MB is megabytes, and TB is terabyte;
  • the second calculated value is set to the minimum MMIOH base address of the server system.
  • the MMIOH base address of the server system is larger than the total capacity of all contents in the server system by more than 2MB. Therefore, in this embodiment, in order to make the minimum MMIOH base address of the server system meet the above-mentioned requirements.
  • the requirement is to first determine the first calculated value of X+2MB, then round the first calculated value in units of 0.5TB to obtain the second calculated value, and set the second calculated value to the minimum value of the server system MMIOH base address.
  • this embodiment further illustrates and optimizes the technical solution.
  • the minimum MMIOH base address is not within the target MMIOH base address range, a second warning message is prompted, and the minimum MMIOH base address is set as the MMIOH base address of the server system.
  • the minimum MMIOH base address Y of the server system is not within the target MMIOH base address range (A, B), that is, the minimum MMIOH base address Y is greater than the maximum MMIOH base address B in the target MMIOH base address range (A, B), Or, if the minimum MMIOH base address Y is smaller than the minimum MMIOH base address A in the target MMIOH base address range (A, B), it means that the minimum MMIOH base address conflicts with the target MMIOH base address range, so that the server system cannot determine the MMIOH base address. address.
  • the server system will prompt the second warning information, and print and display the second warning information in the BIOS for the user's analysis and reference.
  • the server system will set the minimum MMIOH base address calculated based on the maximum physical memory capacity of the server system as the MMIOH base address of the server system.
  • the above-mentioned method for setting the MMIOH base address of the server system further includes:
  • the second early warning information contains the specific reasons why the server system cannot normally determine the MMIOH base address of the server system
  • the staff when they obtains the second early warning information, they can The second warning information is to adjust the target PCIE device in the server system. That is, according to the second warning information, some PCIE devices in the server system are removed or some PCIE devices in the server system are replaced with other types of PCIE devices. Based on the same principle, the staff can also adjust the target PCIE device in the server system according to the information content contained in the first warning information, which will not be described in detail here.
  • FIG. 2 is a structural diagram of a device for setting an MMIOH base address of a server system provided by an embodiment of the application.
  • the setting device includes:
  • the memory detection module 21 is used to detect the total capacity of all the memory in the server system during the process of the server system POST, and determine the minimum MMIOH base address of the server system according to the MMIO specification and the total capacity;
  • the device detection module 22 is used to detect the PCIE device configured in the server system to obtain the target PCIE device;
  • the address calculation module 23 is configured to compare the minimum MMIOH base address with the target MMIOH base address range if the target MMIOH base address range corresponding to the target PCIE device can be calculated according to the whitelist; wherein, the whitelist is based on the MMIO specification and the list of PCIE devices that require MMIOH base address settings;
  • the address determination module 24 is configured to determine the minimum MMIOH base address as the MMIOH base address of the server system if the minimum MMIOH base address is within the target MMIOH base address range, and store the minimum MMIOH base address in the BIOS of the server system.
  • the device for setting an MMIOH base address of a server system provided by the embodiment of the present application has the beneficial effects of the aforementioned method for setting an MMIOH base address of a server system.
  • FIG. 3 is a structural diagram of a device for setting an MMIOH base address of a server system provided by an embodiment of the application.
  • the setting device includes:
  • memory 31 for storing computer programs
  • the processor 32 is configured to implement the steps of the method for setting the MMIOH base address of the server system as disclosed above when executing the computer program.
  • the device for setting an MMIOH base address of a server system provided by an embodiment of the present application has the beneficial effects of the aforementioned method for setting an MMIOH base address of a server system.
  • an embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the MMIOH base address of a server system as disclosed above is implemented. Steps to set up a method.
  • the computer-readable storage medium provided by the embodiments of the present application has the beneficial effects of the aforementioned method for setting an MMIOH base address of a server system.

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Abstract

本申请公开了一种服务器系统MMIOH基地址的设置方法，包括：在服务器系统进行开机自检的过程中，检测服务器系统中所有内存的总容量，并根据MMIO规范和总容量确定服务器系统的最小MMIOH基地址；若根据白名单能够计算出服务器系统中所配置目标PCIE设备所对应的目标MMIOH基地址范围，同时，最小MMIOH基地址在目标MMIOH基地址范围之内，则将该基地址判定为服务器系统的MMIOH基地址，并将该基地址存储至服务器系统的BIOS。由于该方法可以免去人工手动对服务器系统MMIOH基地址进行设定时的繁琐过程，所以，通过该方法就可以提高在对服务器系统MMIOH基地址进行设定时的效率与准确性。

Description

一种服务器系统MMIOH基地址的设置方法、装置
本申请要求在2021年04月26日提交中国专利局、申请号为202110452757.4、发明名称为“一种服务器系统MMIOH基地址的设置方法、装置”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及一种服务器系统MMIOH基地址的设置方法、装置、设备及介质。
背景技术
通过MMIO(Memory Mapping I/O，内存映射I/O)规范能够将服务器系统的外围设备映射到服务器系统的内存空间中，这样就会更加便于CPU(Central Processing Unit，中央处理器)对外围设备的访问。因此，MMIO规范在服务器技术领域得到了十分广泛的应用。
目前，在设定服务器系统的MMIOH(Memory Mapping I/O High，IO设备的信息映射到内存地址的高端内存空间)基地址时，服务器厂商会预先根据服务器的配置情况给服务器系统默认设置一个合理的MMIOH基地址，从而保证服务器系统的正常运行。当服务器系统的内存更换之后，或者是服务器系统更换了对MMIOH基地址有不同设置要求的PCIE(Peripheral Component Interconnect Express，高速串行计算机扩展总线标准)设备时，就需要重新设定服务器系统的MMIOH基地址。在现有技术中，通常是有两种方法来对服务器系统的MMIOH基地址进行重新设定，也即，一种方法是人工手动进入BIOS界面利用工具或命令将服务器系统的MMIOH基地址修改为合适的值，另一种方法是通过修改BIOS代码将服务器系统的MMIOH基地址修改为合适的值。但是，这两种服务器系统MMIOH基地址的设定方法不仅效率低下，而且，也容易出错。针对这一技术问题，现在还没有较为有效的解决办法。
发明内容
有鉴于此，本申请的目的在于提供一种服务器系统MMIOH基地址的设定方法、装置、设备及介质，以提高在对服务器系统MMIOH基地址进行设定时的效率与准确性。其具体方案如下：
一种服务器系统MMIOH基地址的设置方法，包括：
在服务器系统进行开机自检的过程中，检测所述服务器系统中所有内存的总容量，并根据MMIO规范和所述总容量确定所述服务器系统的最小MMIOH基地址；
检测所述服务器系统中所配置的PCIE设备，得到目标PCIE设备；
若根据白名单能够计算出所述目标PCIE设备所对应的目标MMIOH基地址范围时，则将所述最小MMIOH基地址与所述目标MMIOH基地址范围进行对比；其中，所述白名单为根据所述MMIO规范和对MMIOH基地址有设置要求的PCIE设备所设置的名单；
若所述最小MMIOH基地址在所述目标MMIOH基地址范围之内，则将所述最小MMIOH基地址判定为所述服务器系统的MMIOH基地址，并将所述最小MMIOH基地址存储至所述服务器系统的BIOS。
可选的，还包括：
预先将所述白名单写入至所述BIOS。
可选的，还包括：
若根据所述白名单无法计算出所述目标PCIE设备所对应的目标MMIOH基地址范围时，则提示第一预警信息，并将所述最小MMIOH基地址设定为所述服务器系统的MMIOH基地址。
可选的，所述根据MMIO规范和所述总容量确定所述服务器系统的最小MMIOH基地址的过程，包括：
基于所述MMIO规范，确定X+2MB的第一计算值，并以0.5TB为单位对所述第一计算值进行取整，得到第二计算值；其中，X为所述总容量，MB为兆字节，TB为太字节；
将所述第二计算值设定为所述服务器系统的最小MMIOH基地址。
可选的，所述将所述最小MMIOH基地址与所述目标MMIOH基地址范围进行对比的过程之后，还包括：
若所述最小MMIOH基地址不在所述目标MMIOH基地址范围之内，则提示第二预警信息，并将所述最小MMIOH基地址设定为所述服务器系统的MMIOH基地址。
可选的，还包括：
根据所述第二预警信息对所述目标PCIE设备进行调整。
相应的，本申请还公开了一种服务器系统MMIOH基地址的设置装置，包括：
内存检测模块，用于在服务器系统进行开机自检的过程中，检测所述服务器系统中所有内存的总容量，并根据MMIO规范和所述总容量确定所述服务器系统的最小MMIOH基地址；
设备检测模块，用于检测所述服务器系统中所配置的PCIE设备，得到目标PCIE设备；
地址计算模块，用于若根据白名单能够计算出所述目标PCIE设备所对应的目标MMIOH基地址范围时，则将所述最小MMIOH基地址与所述目标MMIOH基地址范围进行对比；其中，所述白名单为根据所述MMIO规范和对MMIOH基地址有设置要求的PCIE设备所设置的名单；
地址确定模块，用于若所述最小MMIOH基地址在所述目标MMIOH基地址范围之内，则将所述最小MMIOH基地址判定为所述服务器系统的MMIOH基地址，并将所述最小MMIOH基地址存储至所述服务器系统的BIOS。
相应的，本申请还公开了一种服务器系统MMIOH基地址的设置设备，包括：
存储器，用于存储计算机程序；
处理器，用于执行所述计算机程序时实现如前述所公开的一种服务器系统MMIOH基地址的设置方法的步骤。
相应的，本申请还公开了一种计算机可读存储介质，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如前述所公开的一种服务器系统MMIOH基地址的设置方法的步骤。
可见，在本申请中，是预先根据MMIO规范和对MMIOH基地址有设置要求的PCIE设备设置白名单；当服务器系统进行开机自检时，则检测服务器系统中所有内存的总容量，并根据MMIO规范和服务器系统物理内存的总容量确定服务器系统的最小MMIOH基地址；然后，再检测服务器系统中所配置的PCIE设备，得到目标PCIE设备；如果根据白名单能够计算出目标PCIE设备所对应的目标MMIOH基地址范围时，则将最小MMIOH基地址与目标MMIOH基地址范围进行对比；如果最小MMIOH基地址在目标MMIOH基地址范围之内，则将最小MMIOH基地址判定为服务器系统的MMIOH基地址，并将最小MMIOH基地址存储至服务器系统的BIOS中。显然，相较于现有技术而言，由于该方法可以免去人工手动对服务器系统MMIOH基地址进行设定时的繁琐过程，所以，通过该方法就可以显著提高在对服务器系统MMIOH基地址进行设定时的效率与准确性。相应的，本申请所提供的一种服务器系统MMIOH基地址的设定装置、设备及介质，同样具有上述有益效果。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据提供的附图获得其他的附图。
图1为本申请实施例所提供的一种服务器系统MMIOH基地址的设置方法的流程图；
图2为本申请实施例所提供的一种服务器系统MMIOH基地址的设置装置的结构图；
图3为本申请实施例所提供的一种服务器系统MMIOH基地址的设置设备的结构图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而 不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
请参见图1，图1为本申请实施例所提供的一种服务器系统MMIOH基地址的设置方法的流程图，该设置方法包括：
步骤S11：在服务器系统进行开机自检的过程中，检测服务器系统中所有内存的总容量，并根据MMIO规范和总容量确定服务器系统的最小MMIOH基地址；
步骤S12：检测服务器系统中所配置的PCIE设备，得到目标PCIE设备；
步骤S13：若根据白名单能够计算出目标PCIE设备所对应的目标MMIOH基地址范围时，则将最小MMIOH基地址与目标MMIOH基地址范围进行对比；
其中，白名单为根据MMIO规范和对MMIOH基地址有设置要求的PCIE设备所设置的名单；
步骤S14：若最小MMIOH基地址在目标MMIOH基地址范围之内，则将最小MMIOH基地址判定为服务器系统的MMIOH基地址，并将最小MMIOH基地址存储至服务器系统的BIOS。
在本实施例中，是提供了一种服务器系统MMIOH基地址的设置方法，通过该设置方法可以显著提高在对服务器系统MMIOH基地址进行设定时的效率与准确性。
可以理解的是，因为服务器中有一部分GPU、网卡等PCIE设备对于MMIOH基地址是有一定设置要求、不能随意进行设定，并且，根据MMIO规范，服务器系统的MMIOH基地址与服务器系统的内存容量也有相应的设定关系。因此，在本实施例中，需要预先根据MMIO规范中对PCIE设备MMIOH基地址有特殊设置要求的规定以及对MMIOH基地址有特殊设置要求的PCIE设备来设置白名单，也即，预先将MMIO规范中对PCIE设备MMIOH基地址有特殊设置要求的PCIE设备以及对MMIOH基地址有特殊设置要求的PCIE设备整理成白名单。
具体的，在本实施例中，首先是根据服务器系统的内存容量来设定服务器系统的MMIOH基地址，也即，在服务器进行开机自检的过程中，检测服 务器系统中所有物理内存的总容量，并根据MMIO规范和服务器系统中所有内存的总容量来确定服务器系统的最小MMIOH基地址。
当确定出服务器系统的最小MMIOH基地址时，则检测服务器系统中所配置的PCIE设备，得到目标PCIE设备。需要说明的是，在本实施例中，目标PCIE设备既可以是服务器系统中所有配置的PCIE设备，也可以是服务器系统中对MMIOH基地址有特殊设置要求的PCIE设备。然后，将目标PCIE设备与白名单进行对比，并根据白名单来计算服务器系统中目标PCIE设备所对应的目标MMIOH基地址范围。
如果根据预先所设置的白名单能够计算出服务器系统中目标PCIE设备所对应的目标MMIOH基地址范围时，则将最小MMIOH基地址与目标MMIOH基地址范围进行对比，以判断最小MMIOH基地址与目标MMIOH基地址范围是否发生冲突。假设最小MMIOH基地址为Y，服务器系统中目标PCIE设备所对应的目标MMIOH基地址范围为(A,B)，如果最小MMIOH基地址Y在目标MMIOH基地址范围(A,B)之内，则说明最小MMIOH基地址与目标MMIOH基地址范围没有发生冲突，在此情况下，就可以将最小MMIOH基地址Y判定为服务器系统的MMIOH基地址，并将最小MMIOH基地址Y存储到服务器系统的BIOS当中。
相较于现有技术而言，通过本实施例所提供的服务器系统MMIOH基地址的设置方法，由于可以避免人工手动对服务器系统MMIOH基地址进行设置的繁琐过程，利用该方法可以在不同应用场景中根据服务器系统的内存容量和服务器系统中所配置的PCIE设备来自适应的对服务器系统的MMIOH基地址进行设定，这样不仅可以大大节省研发人员在对服务器进行研发、测试和生产过程中所需要投入的人力成本，而且，也可以节省服务器在生产时所需要的时间，同时，利用该方法也可以保证服务器系统MMIOH基地址在设置过程中的准确性与可靠性。
此外，在现有技术中，如果是通过修改BIOS代码来编译生成新的BIOS版本，则需要研发人员在每一次变更服务器系统MMIOH基地址时重新开发一个BIOS版本，这样不仅会增加研发人员的开发成本，而且，也会增加服务器的测试成本和生产成本，同时，也会造成BIOS代码版本的混乱以及增加在对BIOS版本进行管理时的管控难度。而通过本实施例所提供的服务器系统 MMIOH基地址的设置方法，由于不会产生多余的BIOS版本，因此，通过该方法就可以显著减少BIOS代码版本的数量以及对BIOS代码版本进行管理时的管控难度，并且，也可以显著提高服务器的生产效率。
可见，在本实施例中，是预先根据MMIO规范和对MMIOH基地址有设置要求的PCIE设备设置白名单；当服务器系统进行开机自检时，则检测服务器系统中所有内存的总容量，并根据MMIO规范和服务器系统物理内存的总容量确定服务器系统的最小MMIOH基地址；然后，再检测服务器系统中所配置的PCIE设备，得到目标PCIE设备；如果根据白名单能够计算出目标PCIE设备所对应的目标MMIOH基地址范围时，则将最小MMIOH基地址与目标MMIOH基地址范围进行对比；如果最小MMIOH基地址在目标MMIOH基地址范围之内，则将最小MMIOH基地址判定为服务器系统的MMIOH基地址，并将最小MMIOH基地址存储至服务器系统的BIOS中。显然，相较于现有技术而言，由于该方法可以免去人工手动对服务器系统MMIOH基地址进行设定时的繁琐过程，所以，通过该方法就可以显著提高在对服务器系统MMIOH基地址进行设定时的效率与准确性。
基于上述实施例，本实施例对技术方案作进一步的说明与优化，作为一种优选的实施方式，上述服务器系统MMIOH基地址的设置方法还包括：
预先将白名单写入至BIOS。
在实际应用中，可以预先将整理好的白名单写入到服务器系统的BIOS中。能够想到的是，当将白名单写入到服务器系统的BIOS当中时，就可以免去从远程服务器端调用白名单的繁琐过程，在此情况下，服务器系统就可以直接从BIOS中调取白名单，并根据白名单来计算服务器系统中目标PCIE设备所对应的目标MMIOH基地址范围。
显然，通过本实施例所提供的技术方案，就可以进一步提高在对服务器系统MMIOH基地址进行设置时的速度与效率。
基于上述实施例，本实施例对技术方案作进一步的说明与优化，作为一种优选的实施方式，上述服务器系统MMIOH基地址的设置方法还包括：
若根据白名单无法计算出目标PCIE设备所对应的目标MMIOH基地址范围时，则提示第一预警信息，并将最小MMIOH基地址设定为服务器系统的MMIOH基地址。
可以理解的是，在实际操作过程中，还可能会遇到根据白名单无法计算出目标PCIE设备所对应的目标MMIOH基地址范围的情况。也即，服务器系统中不同PCIE设备所对应的MMIOH基地址出现了冲突，在此情况下，就无法根据白名单计算出目标PCIE设备所对应的目标MMIOH基地址范围。
当出现上述情况时，为了使得工作人员可以及时知悉到服务器系统无法根据白名单计算出目标PCIE设备所对应的目标MMIOH基地址范围，此时，服务器系统就会提示第一预警信息，并在BIOS中打印显示第一预警信息，以供用户进行分析与参考。与此同时，服务器系统会将基于服务器系统物理内存最大容量所计算得到的最小MMIOH基地址设置为服务器系统的MMIOH基地址。
显然，通过本实施例所提供的技术方案，可以保证本申请所提供服务器系统MMIOH基地址在设置过程中的全面性与完整性。
基于上述实施例，本实施例对技术方案作进一步的说明与优化，作为一种优选的实施方式，上述步骤：根据MMIO规范和总容量确定服务器系统的最小MMIOH基地址的过程，包括：
基于MMIO规范，确定X+2MB的第一计算值，并以0.5TB为单位对第一计算值进行取整，得到第二计算值；其中，X为总容量，MB为兆字节，TB为太字节；
将第二计算值设定为服务器系统的最小MMIOH基地址。
可以理解的是，根据MMIO规范的规定，服务器系统的MMIOH基地址要比服务器系统中所有内容的总容量大2MB以上，因此，在本实施例中，为了使得服务器系统的最小MMIOH基地址满足上述要求，首先是确定X+2MB的第一计算值，然后，再以0.5TB为单位对第一计算值进行取整，得到第二计算值，并将第二计算值设定为服务器系统的最小MMIOH基地址。
比如：如果根据X+2MB计算得到的值为3.02TB，那么，以0.5TB为单位对3.02TB进行取整，就会得到3.5TB，也即，此时会将服务器系统的最小MMIOH 基地址设置为3.5TB；如果根据X+2MB计算得到的值为3.6TB，那么，以0.5TB为单位对3.6TB进行取整，就会得到4TB，也即，此时会将服务器系统的最小MMIOH基地址设置为4TB。
可见，通过本实施例所提供的技术方案，可以保证服务器系统最小MMIOH基地址在设置过程中的可靠性。
基于上述实施例，本实施例对技术方案作进一步的说明与优化，作为一种优选的实施方式，上述步骤：将最小MMIOH基地址与目标MMIOH基地址范围进行对比的过程之后，还包括：
若最小MMIOH基地址不在目标MMIOH基地址范围之内，则提示第二预警信息，并将最小MMIOH基地址设定为服务器系统的MMIOH基地址。
如果服务器系统的最小MMIOH基地址Y不在目标MMIOH基地址范围(A,B)之内，也即，最小MMIOH基地址Y大于目标MMIOH基地址范围(A,B)中的最大MMIOH基地址B，或者，最小MMIOH基地址Y小于目标MMIOH基地址范围(A,B)的最小MMIOH基地址A，则说明最小MMIOH基地址与目标MMIOH基地址范围发生了冲突，从而导致服务器系统无法确定出MMIOH基地址。
在此情况下，服务器系统就会提示第二预警信息，并在BIOS中打印显示第二预警信息，以供用户分析与参考。与此同时，服务器系统会将基于服务器系统物理内存最大容量所计算得到的最小MMIOH基地址设置为服务器系统的MMIOH基地址。
作为一种优选的实施方式，上述服务器系统MMIOH基地址的设置方法还包括：
根据第二预警信息对目标PCIE设备进行调整。
可以理解的是，由于第二预警信息中蕴含着服务器系统无法正常确定出服务器系统MMIOH基地址的具体原因，所以，在实际应用中，当工作人员获取得到第二预警信息时，就可以根据第二预警信息对服务器系统中的目标PCIE设备进行调整。也即，根据第二预警信息将服务器系统中的某些PCIE设备去除或者是将服务器系统中的某些PCIE设备替换为其它类型的PCIE设 备。基于同样的原理，工作人员也可以根据第一预警信息中所蕴含的信息内容来对服务器系统中的目标PCIE设备进行调整，此处不作具体赘述。
显然，通过本实施例所提供的技术方案，就可以相对保证服务器系统在后续使用过程中的安全性。
请参见图2，图2为本申请实施例所提供的一种服务器系统MMIOH基地址的设置装置的结构图，该设置装置包括：
内存检测模块21，用于在服务器系统进行开机自检的过程中，检测服务器系统中所有内存的总容量，并根据MMIO规范和总容量确定服务器系统的最小MMIOH基地址；
设备检测模块22，用于检测服务器系统中所配置的PCIE设备，得到目标PCIE设备；
地址计算模块23，用于若根据白名单能够计算出目标PCIE设备所对应的目标MMIOH基地址范围时，则将最小MMIOH基地址与目标MMIOH基地址范围进行对比；其中，白名单为根据MMIO规范和对MMIOH基地址有设置要求的PCIE设备所设置的名单；
地址确定模块24，用于若最小MMIOH基地址在目标MMIOH基地址范围之内，则将最小MMIOH基地址判定为服务器系统的MMIOH基地址，并将最小MMIOH基地址存储至服务器系统的BIOS。
本申请实施例所提供的一种服务器系统MMIOH基地址的设置装置，具有前述所公开的一种服务器系统MMIOH基地址的设置方法所具有的有益效果。
请参见图3，图3为本申请实施例所提供的一种服务器系统MMIOH基地址的设置设备的结构图，该设置设备包括：
存储器31，用于存储计算机程序；
处理器32，用于执行计算机程序时实现如前述所公开的一种服务器系统MMIOH基地址的设置方法的步骤。
本申请实施例所提供的一种服务器系统MMIOH基地址的设置设备，具有前述所公开的一种服务器系统MMIOH基地址的设置方法所具有的有益效果。
相应的，本申请实施例还提供了一种计算机可读存储介质，计算机可读存储介质上存储有计算机程序，计算机程序被处理器执行时实现如前述所公开的一种服务器系统MMIOH基地址的设置方法的步骤。
本申请实施例所提供的一种计算机可读存储介质，具有前述所公开的一种服务器系统MMIOH基地址的设置方法所具有的有益效果。
本说明书中各个实施例采用递进的方式描述，每个实施例重点说明的都是与其它实施例的不同之处，各个实施例之间相同或相似部分互相参见即可。对于实施例公开的装置而言，由于其与实施例公开的方法相对应，所以描述的比较简单，相关之处参见方法部分说明即可。
最后，还需要说明的是，在本文中，诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来，而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且，术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含，从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上对本申请所提供的一种服务器系统MMIOH基地址的设置方法、装置、设备及介质进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (9)

  1. 一种服务器系统MMIOH基地址的设置方法，其特征在于，包括：
    在服务器系统进行开机自检的过程中，检测所述服务器系统中所有内存的总容量，并根据MMIO规范和所述总容量确定所述服务器系统的最小MMIOH基地址；
    检测所述服务器系统中所配置的PCIE设备，得到目标PCIE设备；
    若根据白名单能够计算出所述目标PCIE设备所对应的目标MMIOH基地址范围时，则将所述最小MMIOH基地址与所述目标MMIOH基地址范围进行对比；其中，所述白名单为根据所述MMIO规范和对MMIOH基地址有设置要求的PCIE设备所设置的名单；
    若所述最小MMIOH基地址在所述目标MMIOH基地址范围之内，则将所述最小MMIOH基地址判定为所述服务器系统的MMIOH基地址，并将所述最小MMIOH基地址存储至所述服务器系统的BIOS。
  2. 根据权利要求1所述的设置方法，其特征在于，还包括：
    预先将所述白名单写入至所述BIOS。
  3. 根据权利要求1所述的设置方法，其特征在于，还包括：
    若根据所述白名单无法计算出所述目标PCIE设备所对应的目标MMIOH基地址范围时，则提示第一预警信息，并将所述最小MMIOH基地址设定为所述服务器系统的MMIOH基地址。
  4. 根据权利要求1所述的设置方法，其特征在于，所述根据MMIO规范和所述总容量确定所述服务器系统的最小MMIOH基地址的过程，包括：
    基于所述MMIO规范，确定X+2MB的第一计算值，并以0.5TB为单位对所述第一计算值进行取整，得到第二计算值；其中，X为所述总容量，MB为兆字节，TB为太字节；
    将所述第二计算值设定为所述服务器系统的最小MMIOH基地址。
  5. 根据权利要求1至4任一项所述的设置方法，其特征在于，所述将所述最小MMIOH基地址与所述目标MMIOH基地址范围进行对比的过程之后，还包括：
    若所述最小MMIOH基地址不在所述目标MMIOH基地址范围之内，则提示第二预警信息，并将所述最小MMIOH基地址设定为所述服务器系统的MMIOH基地址。
  6. 根据权利要求5所述的设置方法，其特征在于，还包括：
    根据所述第二预警信息对所述目标PCIE设备进行调整。
  7. 一种服务器系统MMIOH基地址的设置装置，其特征在于，包括：
    内存检测模块，用于在服务器系统进行开机自检的过程中，检测所述服务器系统中所有内存的总容量，并根据MMIO规范和所述总容量确定所述服务器系统的最小MMIOH基地址；
    设备检测模块，用于检测所述服务器系统中所配置的PCIE设备，得到目标PCIE设备；
    地址计算模块，用于若根据白名单能够计算出所述目标PCIE设备所对应的目标MMIOH基地址范围时，则将所述最小MMIOH基地址与所述目标MMIOH基地址范围进行对比；其中，所述白名单为根据所述MMIO规范和对MMIOH基地址有设置要求的PCIE设备所设置的名单；
    地址确定模块，用于若所述最小MMIOH基地址在所述目标MMIOH基地址范围之内，则将所述最小MMIOH基地址判定为所述服务器系统的MMIOH基地址，并将所述最小MMIOH基地址存储至所述服务器系统的BIOS。
  8. 一种服务器系统MMIOH基地址的设置设备，其特征在于，包括：
    存储器，用于存储计算机程序；
    处理器，用于执行所述计算机程序时实现如权利要求1至6任一项所述的一种服务器系统MMIOH基地址的设置方法的步骤。
  9. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质上存储有计算机程序，所述计算机程序被处理器执行时实现如权利要求1至6任一项所述的一种服务器系统MMIOH基地址的设置方法的步骤。
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