WO2022227564A1

WO2022227564A1 - Circuit layout generation method and apparatus, computer device, and storage medium

Info

Publication number: WO2022227564A1
Application number: PCT/CN2021/134622
Authority: WO
Inventors: 陈文杰; 徐宁仪
Original assignee: 上海阵量智能科技有限公司
Priority date: 2021-04-29
Filing date: 2021-11-30
Publication date: 2022-11-03
Also published as: CN113111622A; CN113111622B

Abstract

The present disclosure provides a circuit layout generation method and apparatus, a computer device, and a storage medium. The method comprises: generating a target circuit diagram by using register transfer level (RTL) design information corresponding to a target circuit; and generating a target layout of the target circuit using position constraint information and the target circuit diagram, the position constraint information being used for constraining the wiring distances between output ends of multiple target registers connected to a same target logic gate device and the target logic gate device to be equal in the target circuit. In embodiments of the present disclosure, the number of invalid flips of the target logic gate device is reduced, thereby effectively reducing power consumed by the target circuit and improving operation stability of the target circuit in a chip.

Description

A circuit layout generation method, device, computer equipment and storage medium

Cross-references to relevant publications

The present disclosure claims priority to Chinese Patent Publication No. 2021104766166 filed on April 29, 2021, the entire contents of which are incorporated herein by reference.

technical field

The present disclosure relates to the technical field of integrated circuits, and in particular, to a method, apparatus, computer equipment, and storage medium for generating a circuit layout.

Background technique

For chips with high computing performance, because the signal delay information of each register array in the chip reaching the logic gate device is different, there will be invalid flipping of the logic gate device when running a large number of calculations, resulting in serious power consumption. The stability of the overall operation of the chip circuit is adversely affected.

SUMMARY OF THE INVENTION

Embodiments of the present disclosure provide at least a method, apparatus, computer device, and storage medium for generating a circuit layout.

In a first aspect, an embodiment of the present disclosure provides a method for generating a circuit layout, including: generating a target circuit diagram using register transfer level RTL design information corresponding to a target circuit; generating the target circuit diagram using position constraint information and the target circuit diagram The target layout of the circuit; the position constraint information is used to constrain the wiring distance between the output ends of multiple target registers connected to the same target logic gate device and the target logic gate device in the target circuit, so that all The time when the output signals of the plurality of target registers reach the target logic gate device is within a preset range.

In this way, in the obtained target layout, the wiring distances between the output terminals of multiple target registers connected to the same target logic gate device and the target logic gate device are basically the same, that is, the same target logic gate device is connected to The time required for multiple target registers to transmit signals to the target logic gate device is basically the same, so that the signals transmitted from different target registers to the same target logic gate device arrive at almost the same time, reducing the target logic gate device due to the input signal. The number of invalid flips caused by reaching at different times, thereby effectively reducing the power consumption value of the target circuit and improving the stability of the target circuit operation in the chip.

In a possible implementation manner, the location constraint information is used to constrain the routing distances between the output terminals of the plurality of target registers and the target logic gate device to be substantially equal.

In a possible implementation manner, generating the target layout of the target circuit using the position constraint information and the target circuit diagram includes: performing at least one iteration, and in each iteration: using the current iteration and the target circuit diagram, generate layout information of the plurality of target registers and the target logic gate device in the target circuit; in response to satisfying a preset iteration stop condition, based on the layout information , to generate the target layout.

In a possible implementation manner, the position constraint information of the current iteration is determined based on the position constraint information of the previous iteration, or determined based on the initial position constraint information corresponding to the first iteration.

In this way, after many iterations, the appropriate position constraint information can be determined, and based on the appropriate position constraint information, the target circuit can be constrained, the output terminals of multiple target registers connected to the same target logic gate device and the target logic gate The wiring distance between the devices is equal, and the target circuit can be implemented in the chip, which effectively reduces the power consumption value of the target circuit.

In a possible implementation manner, the layout information includes: position information and size information respectively corresponding to the target register and the target logic gate device; the method further includes: in the layout information generated based on the current iteration, the The position information and size information corresponding to the plurality of target registers and the target logic gate device respectively, determine the chip space size occupied by the target circuit; compare the chip space size with a preset chip space size threshold; The generating the target layout based on the layout information in response to satisfying an iteration stop condition includes: generating the target layout based on the layout information in response to the chip space size being less than or equal to the chip space size threshold target layout.

In a possible implementation manner, the method further includes: in response to the chip space size being greater than the chip space size threshold, generating new position constraint information based on the position constraint information of the current iteration; using the new position constraint information as The position constraint information of the current iteration is returned to the step of generating the layout information of the multiple target registers and the target logic gate device in the target circuit by using the position constraint information of the current iteration and the target circuit diagram.

In this way, it can be determined whether the current position constraint information is appropriate position constraint information based on whether the chip space size occupied by the target circuit is greater than the preset chip space size threshold, that is, through each device in the target circuit (such as the target register, target logic Whether the gate device, etc.) can be normally arranged in the chip to determine whether the current position constraint information is appropriate position constraint information, so that the final position constraint information can ensure that the target circuit can be normally arranged in the chip, and the same target can be guaranteed. The multiple target registers connected to the logic gate device transmit signals to the target logic gate device at substantially the same time, thereby reducing the number of invalid flips of the target logic gate device, thereby effectively reducing the power consumption value of the target circuit in the chip.

In a possible implementation manner, the method further includes: in response to the chip space size being smaller than or equal to the chip space size threshold and the difference between each target register and the target logic gate device in the position constraint information of the current iteration If the distance value between them does not reach the minimum value, reduce the distance value between the target register and the target logic gate device in the position constraint information, obtain new position constraint information, and return the position constraint using the current iteration. information, and the target circuit diagram, the step of generating the layout information of the plurality of target registers and the target logic gate device in the target circuit; the step of generating the layout information based on the layout information in response to satisfying the iteration stop condition The target layout includes: in response to the chip space size being less than or equal to the chip space size threshold, and the distance value between each target register and the target logic gate device in the position constraint information reaches The minimum value in the at least one iteration, based on the layout information, generates the target layout.

In a possible implementation manner, the layout information includes: routing relationship information between the multiple target registers and the target logic gate device; the method further includes: the generated data based on the current iteration In the layout information, the routing relationship information between the multiple target registers and the target logic gate device determines whether the target circuit can be deployed in the chip; the response is satisfying the iteration stop condition, based on the layout information, generating the target layout includes: in response to determining that the target circuit can be deployed in a chip, generating the target layout based on the layout information.

In this way, based on the routing relationship information between the target register and the target logic gate device, it can be determined whether the target circuit can be deployed in the chip, and then it can be determined whether the current position constraint information is suitable position constraint information. The finally determined position constraint information can ensure that the target circuit can be deployed in the chip.

In a possible implementation manner, the method further includes: in response to determining that the target circuit cannot be deployed in the chip, generating new position constraint information based on the position constraint information of the current iteration; using the new position constraint information as the current iteration The step of generating the layout information of the multiple target registers and the target logic gate device in the target circuit by using the position constraint information of the current iteration and the target circuit diagram is returned.

In a possible implementation manner, the method further includes: based on the layout information generated by the current iteration, performing circuit power consumption simulation analysis to obtain a power consumption value of the target circuit; The condition, generating the target layout based on the layout information includes: in response to determining that the power consumption value of the target circuit is less than a preset power consumption value, generating the target layout based on the layout information.

In a possible implementation manner, the method further includes: in response to determining that the power consumption value of the target circuit is greater than or equal to the preset power consumption value, generating new position constraint information based on the position constraint information of the current iteration; The new position constraint information is used as the position constraint information of the current iteration, the position constraint information using the current iteration and the target circuit diagram are returned, and the plurality of target registers and the target logic gate in the target circuit are generated. Steps for placement information of the device.

In this way, it can be judged whether the current position constraint information is appropriate position constraint information according to the power consumption value of the circuit determined based on the position constraint information of the current iteration, so that the finally determined position constraint information can ensure that the power consumption value of the target circuit is less than the predetermined value. Set the power consumption value to effectively reduce the power consumption of the target circuit.

In a second aspect, an embodiment of the present disclosure further provides a circuit layout generation device, including: a first generation module for generating a target circuit diagram using register transfer level RTL design information corresponding to the target circuit; a second generation module for using The position constraint information and the target circuit diagram are used to generate the target layout of the target circuit; the position constraint information is used to constrain the target circuit, the output terminals of the multiple target registers connected to the same target logic gate device are connected to the target circuit. The wiring distance between the target logic gate devices makes the time for the output signals of the plurality of target registers to reach the target logic gate device within a preset range.

In a possible implementation manner, when generating the target layout of the target circuit by using the position constraint information and the target circuit diagram, the second generation module is specifically configured to perform at least one iteration, in each In the iteration: using the position constraint information of the current iteration and the target circuit diagram to generate layout information of the multiple target registers and the target logic gate device in the target circuit; in response to satisfying a preset iteration A stop condition generates the target layout based on the layout information.

In a possible implementation manner, the layout information includes: position information and size information respectively corresponding to the target register and the target logic gate device; the second generation module is specifically configured to generate the layout based on the current iteration In the information, the position information and size information corresponding to the multiple target registers and the target logic gate device respectively, determine the chip space size occupied by the target circuit; the chip space size and the preset chip space size threshold performing a comparison; when generating the target layout based on the layout information in response to satisfying the iteration stop condition, the second generation module is specifically configured to respond that the chip space size is less than or equal to the chip space A size threshold, and based on the layout information, the target layout is generated.

In a possible implementation manner, the second generation module is further configured to, in response to the chip space size being greater than the chip space size threshold, generate new position constraint information based on the position constraint information of the current iteration; The new position constraint information is used as the position constraint information of the current iteration, the position constraint information using the current iteration and the target circuit diagram are returned, and the plurality of target registers and the target logic gate in the target circuit are generated. Steps for placement information of the device.

In a possible implementation manner, the second generation module is further configured to respond that the chip space size is less than or equal to the chip space size threshold, and the target registers and the target registers in the position constraint information of the current iteration are The distance value between the target logic gate devices does not reach the minimum value, reduce the distance value between the target register and the target logic gate device in the position constraint information, obtain new position constraint information, and return the Describe the step of using the position constraint information of the current iteration and the target circuit diagram to generate the layout information of the plurality of target registers and the target logic gate device in the target circuit; in response to satisfying the iteration stop condition, based on For the layout information, when the target layout is generated, the second generation module is specifically configured to respond that the chip space size is less than or equal to the chip space size threshold, and each of the position constraint information The distance value between the target register and the target logic gate device reaches the minimum value in the at least one iteration, and the target layout is generated based on the layout information.

In a possible implementation manner, the layout information includes: routing relationship information between the multiple target registers and the target logic gate device; the second generation module is further configured to generate data based on the current iteration In the generated layout information, the routing relationship information between the multiple target registers and the target logic gate device determines whether the target circuit can be deployed in the chip; in response to satisfying the iteration stop condition, based on For the layout information, when the target layout is generated, the second generation module is specifically configured to, in response to determining that the target circuit can be deployed in the chip, generate the target layout based on the layout information.

In a possible implementation manner, the second generation module is further configured to, in response to determining that the target circuit cannot be deployed in the chip, generate new position constraint information based on the position constraint information of the current iteration; The position constraint information of the current iteration is used as the position constraint information of the current iteration, and the position constraint information of the current iteration and the target circuit diagram are returned, and the relationship between the plurality of target registers in the target circuit and the target logic gate device is generated. Steps for laying out information.

In a possible implementation manner, the second generation module is further configured to perform circuit power consumption simulation analysis based on the layout information generated by the current iteration to obtain a power consumption value of the target circuit; When the iteration stop condition is satisfied, and the target layout is generated based on the layout information, the second generation module is specifically configured to, in response to determining that the power consumption value of the target circuit is less than a preset power consumption value, generate the target layout based on the layout information to generate the target layout.

In a possible implementation manner, the second generating module is further configured to: in response to determining that the power consumption value of the target circuit is greater than or equal to the preset power consumption value, generate the position constraint information based on the current iteration new position constraint information; use the new position constraint information as the position constraint information of the current iteration, return the position constraint information using the current iteration and the target circuit diagram, and generate the plurality of target circuits The steps of the target register and the layout information of the target logic gate device.

In a third aspect, an optional implementation manner of the present disclosure further provides a computer device, a processor, and a memory, where the memory stores machine-readable instructions executable by the processor, and the processor is configured to execute the instructions stored in the memory. machine-readable instructions, when the machine-readable instructions are executed by the processor, when the machine-readable instructions are executed by the processor, the above-mentioned first aspect, or any possible implementation of the first aspect, is executed steps in the method.

In a fourth aspect, an optional implementation manner of the present disclosure further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and the computer program executes the first aspect, or any of the first aspect, when the computer program is run. steps in one possible implementation.

For a description of the effects of the above-mentioned circuit layout generating apparatus, computer equipment, and computer-readable storage medium, reference may be made to the description of the above-mentioned circuit layout generating method, which will not be repeated here.

In order to make the above-mentioned objects, features and advantages of the present disclosure more obvious and easy to understand, the preferred embodiments are exemplified below, and are described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present disclosure more clearly, the accompanying drawings required in the embodiments will be briefly introduced below. These drawings illustrate embodiments consistent with the present disclosure, and together with the description, serve to explain the technical solutions of the present disclosure. It should be understood that the following drawings only show some embodiments of the present disclosure, and therefore should not be regarded as limiting the scope. Other related figures are obtained from these figures.

FIG. 1 shows a flowchart of a method for generating a circuit layout provided by an embodiment of the present disclosure;

Figures 2a and 2b show an example diagram of determining initial position constraint information provided by an embodiment of the present disclosure;

3 shows a flowchart of a method for generating a target layout of a target circuit by using current position constraint information and a target circuit diagram provided by an embodiment of the present disclosure;

FIG. 4 shows a specific implementation flowchart of a method for generating a circuit layout provided by an embodiment of the present disclosure;

FIG. 5 shows a specific example of a method for generating a circuit layout provided by an embodiment of the present disclosure;

FIG. 6 shows a schematic diagram of an apparatus for generating a circuit layout provided by an embodiment of the present disclosure;

FIG. 7 shows a schematic diagram of a computer device provided by an embodiment of the present disclosure.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only These are some, but not all, embodiments of the present disclosure. The components of the disclosed embodiments generally described and illustrated herein may be arranged and designed in a variety of different configurations. Thus, the following detailed description of the embodiments of the present disclosure is not intended to limit the scope of the disclosure as claimed, but is merely representative of selected embodiments of the disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present disclosure.

After research, it is found that in the implementation process of the chip, because of the wiring distance between the output terminals of a plurality of registers connected to a logic gate device in the chip and the logic gate device (specifically, the input terminal of the logic gate device) Different, resulting in different signal transmission time between each register in the multiple registers and the corresponding logic gate device, which may lead to invalid flipping of the corresponding logic gate device in some cases, resulting in unnecessary power consumption, which adversely affects the stability of the overall operation of the circuit.

For example, for a logic gate device whose function is a NAND relationship, hereinafter referred to as a NAND logic gate device, when both inputs are high, the output is low; when either input is not When it is high, the output is high; assuming that the two inputs of the NAND logic gate device correspond to register 1 and register 2 respectively, and the transmission time for register 1 to send a level signal to the NAND logic gate device is 3 picometres Second, the transmission time of register 2 to send the level signal to the NAND logic gate device is 5 picoseconds. If register 1 inputs a low level to the NAND logic gate device, and register 2 inputs a high level to the NAND logic gate device, the NAND logic gate device outputs a high level. After that, register 1 inputs a high level to the NAND logic gate device, and register 2 inputs a low level to the NAND logic gate device. In this case, because the transmission time for register 1 to send a level signal to the NAND gate device is less than the transmission time for register 2 to send a level signal to the NAND gate device, the low level transmitted in register 2 It does not reach the NAND logic gate device, and the high level transmitted by register 1 has reached the NAND logic gate device within 2 picoseconds, and the two input signals received by the NAND logic gate device are both high level, Then the output signal of the NAND logic gate device flips to a low level, until the NAND logic gate device receives the low level transmitted by the register 2, and then flips to a high level again. In fact, the output of the NAND logic gate device should always remain high, but because there is a 2 picosecond time difference between register 1 and register 2 transmitting signals to the NAND logic gate device, the NAND logic in these 2 picoseconds The output of the gate device has two invalid toggles.

Based on the above research, the present disclosure provides a method, device, computer equipment and storage medium for generating a circuit layout. When generating a target layout of a target circuit in a chip, a register transfer level (RTL) corresponding to the target circuit is used. ) design information to generate a target circuit diagram, and then generate a target layout of the target circuit based on the current position constraint information and the target circuit diagram. In this way, in the obtained target layout, the wiring distance between the output ends of the multiple target registers connected to the same target logic gate device and the target logic gate device (can be specifically the input end of the logic gate device) is Basically the same, that is, the time required for multiple target registers connected to the same target logic gate device to transmit signals to the target logic gate device is basically the same, so that the signals transmitted from different target registers to the same target logic gate device are almost the same. Reaching at the same time, reducing the number of invalid flips of the target logic gate device due to the arrival of input signals at different times, thereby effectively reducing the power consumption value of the target circuit and improving the stability of the target circuit in the chip.

The above are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above-mentioned problems and the solutions to the above-mentioned problems proposed by the present disclosure below should be the results of the inventors' understanding of the present disclosure in the process of the present disclosure. contribution made.

It should be noted that like numerals and letters refer to like items in the following figures, so once an item is defined in one figure, it does not require further definition and explanation in subsequent figures.

In order to facilitate the understanding of this embodiment, a method for generating a circuit layout disclosed by an embodiment of the present disclosure is first introduced in detail. The execution body of the method for generating a circuit layout provided by an embodiment of the present disclosure is generally a computer with a certain computing capability. equipment, the computer equipment for example includes: terminal equipment, server or other processing equipment, the terminal equipment can be user equipment (User Equipment, UE), mobile equipment, user terminal, terminal, cellular phone, cordless phone, personal digital assistant (Personal Digital Assistant) Assistant, PDA), handheld devices, computing devices, in-vehicle devices, wearable devices, personal computers, notebook computers, etc. In some possible implementations, the circuit layout generation method may be implemented by a processor in a computer device calling computer-readable instructions stored in a memory.

Some terms in the embodiments of the present disclosure are explained below:

The chip described in the embodiment of the present disclosure is an integrated circuit including a plurality of circuit modules, and the target circuit described in the embodiment of the present disclosure may include any circuit module in the chip. For example, the target circuit is in the chip. A circuit block whose power consumption value exceeds the preset power consumption value.

The preset power consumption value is determined based on the product to which the chip is applied, and different products have different requirements for the chip power consumption value. Therefore, the preset power consumption value can be set to different values for different chips or different application scenarios, which is not limited in the embodiments of the present disclosure.

The RTL design information described in the embodiments of the present disclosure is an algorithm written in a high-level programming language (eg, C language, C++, Java, assembly language, C#, etc.) and capable of realizing specific computing processing functions.

The target layout described in the embodiments of the present disclosure is the circuit structure layout that the target circuit can finally implement in the chip, and includes, for example, the model, size, arrangement position of each device in the target circuit, and the arrangement position of each device in the target circuit. At least one of the routing conditions between them.

The following describes the circuit layout generation method provided by the embodiments of the present disclosure.

Referring to FIG. 1, which is a flowchart of a method for generating a circuit layout provided by an embodiment of the present disclosure, the method includes steps S101-S102, wherein:

S101: Generate a target circuit diagram by using the RTL design information of the register transfer level corresponding to the target circuit.

The target circuit diagram is a circuit schematic diagram generated according to the RTL design information corresponding to the target circuit, for example, including at least one of the models, attribute values, and connection relationships between the devices in the target circuit.

Specifically, for example, any integrated circuit design tool such as Design Compiler (design compiler), Fusion Compiler (fusion compiler), Genus (genus) can be used to generate the target circuit diagram based on the RTL design information corresponding to the target circuit.

S102: Use the position constraint information and the target circuit diagram to generate a target layout of the target circuit; the position constraint information is used to constrain the target circuit, the output ends of the multiple target registers connected to the same target logic gate device and the target logic gate device The routing distance between them makes the time for the output signals of the multiple target registers to reach the target logic gate device within a preset range.

Here, the routing distance between the output ends of multiple target registers connected to the same target logic gate device in the target circuit and the target logic gate device is constrained, so that the time for the output signals of the multiple target registers to reach the target logic gate device Within a preset range, for example, in the target circuit, the routing distances between the output ends of multiple target registers connected to the same target logic gate device and the target logic gate device can be constrained to be substantially equal, so that It can make the time for the signals output by multiple target registers to reach the target logic gate device within a preset range, and even enable the signals output from multiple target registers to reach the target logic gate device within a reasonable time range, so that the target logic gate device can be used by the target. The logic gate device is handled correctly. In the embodiment of the present disclosure, the preset range may be represented as a range of the time difference between the signals output by the multiple target registers reaching the target logic gate device. The preset range can be very small, for example: 0, thereby achieving the effect that the signals output by multiple target registers reach the target logic gate device at the same time.

In a specific implementation, when the target layout of the target circuit is generated by using the position constraint information and the target circuit diagram, for example, at least one iteration of the initial position constraint information may be performed to obtain a solution that can both satisfy the position constraint requirements and meet the position constraint requirements. The position constraint information of the integrated circuit can be deployed in the chip, and based on the obtained position constraint information and the target circuit diagram, the target layout of the target circuit is generated.

Wherein, in the first iteration, the position constraint information is determined based on the initial position constraint information.

In iterations other than the first iteration, the position constraint information is determined based on the position constraint information used in the previous iteration.

The initial position constraint information is the position constraint information of the first iteration. Before generating the target layout of the target circuit by using the position constraint information and the target circuit diagram, it may further include: performing circuit power consumption simulation analysis based on the target circuit diagram to obtain the target The electronic pulse power consumption corresponding to each logic gate device in the circuit; based on the electronic pulse power consumption corresponding to each logic gate device, the target logic gate device is determined from the target circuit; and the register connecting the output end and the target logic gate device is determined as The target register, and the target register, and the target logic gate device as the optimization target.

The initial position constraint information may be obtained by setting initial position constraint information for the target logic gate device and its corresponding target register.

Among them, when the circuit power consumption simulation analysis is performed based on the target circuit diagram, since the routing distance between the target logic gate device and the corresponding target register can be determined, the target logic gate device determined by the circuit power consumption simulation analysis can be used. The routing distance with the corresponding target register determines the initial position constraint information. For example, the maximum distance between the wiring and the target logic gate device is used as the initial position constraint information, or the minimum distance between the wiring and the target logic gate device is used as the initial position constraint information, or, when the maximum wiring distance is A value is randomly determined between the value and the minimum line distance as the initial position constraint information.

In addition, the initial position constraint information may also be determined according to the historical experience value of the routing distance.

Exemplarily, as shown in Figure 2a, when the circuit power consumption simulation analysis is performed based on the target circuit diagram, the distances between the target register 1 and the target register 2 and the target logic gate device are respectively 5 microns and 3 microns; The initial position constraint information determined by the circuit power consumption simulation analysis result is, for example, the trace distance values between target register 2 and target register 1 and the target logic gate device are both 3 microns (as shown in Figure 2b), or both are 4 microns or 5 microns (neither shown in Figure 2b).

Referring to FIG. 3 , an embodiment of the present disclosure provides a specific method for generating a target layout of a target circuit by using location constraint information and a target circuit diagram, including:

S301: perform at least one iteration, in each iteration: use the position constraint information of the current iteration and the target circuit diagram to generate the layout information of multiple target registers and target logic gate devices in the target circuit;

S302: In response to satisfying a preset iteration stop condition, generate a target layout based on the layout information.

In a specific implementation, the layout information includes, for example: position information and size information corresponding to the target register and the target logic gate device respectively; when generating the target layout based on the layout information, for example, based on the position information corresponding to the target register and the target logic gate device respectively and size information to determine the chip space size occupied by the target circuit; compare the chip space size with the preset chip space size threshold; when the chip space size is less than or equal to the chip space size threshold, generate the target layout based on the layout information picture.

The iteration stop condition includes, for example, at least one of the following: the size of the chip space occupied by the target circuit is less than or equal to the chip space size threshold; or when the size of the chip space occupied by the target circuit is less than or equal to the chip space size threshold, the current iteration The routing distance value between the target register and the corresponding target logic gate device in the location constraint information of the target circuit reaches the minimum value, the target circuit can be deployed in the chip, and the power consumption value of the target circuit is less than the preset power consumption value.

For the case where the chip space size occupied by the target circuit is less than or equal to the chip space size threshold as the iteration stop condition, the position information corresponding to the target register and the target logic gate device respectively includes, for example, the target register and the target logic gate device respectively in the simulation space of the chip The position occupied in the Floorplan; the size information corresponding to the target register and the target logic gate device respectively includes, for example, the volume and shape corresponding to the target register and the target logic gate device respectively.

For the case where the chip space size is larger than the chip space size threshold, generate new position constraint information based on the position constraint information of the current iteration; use the new position constraint information as the position constraint information of the current iteration, return the position constraint information using the current iteration, and The target circuit diagram includes the steps of generating layout information of multiple target registers and target logic gate devices in the target circuit.

In this way, it can be determined whether the current position constraint information is appropriate position constraint information based on whether the space size occupied by the target circuit is greater than the preset chip space size threshold; , when it is less than or equal to the preset chip space size threshold, that is, under the position constraint information of the current iteration, each device in the target circuit (such as target register, target logic gate device, etc.) can be determined in the chip for the target circuit. When normally arranged in the deployment area, the location constraint information is appropriate location constraint information. When the chip space size occupied by the target circuit determined based on the position constraint information of the current iteration is larger than the preset chip space size threshold, that is, under the position constraint information, each device in the target circuit cannot be the target circuit in the chip When it is normally arranged in the determined deployment area, the current location constraint information is not suitable location constraint information, and the next iteration needs to be performed. At this time, the position constraint information of the current iteration can be updated as the position constraint information of the next iteration, and then return to use the position constraint information of the current iteration and the target circuit diagram to generate multiple target registers and target logic gates in the target circuit The step of device layout information, ie, perform the next iteration until suitable position constraint information is determined, ie, when the chip space size is less than or equal to the chip space size threshold, generate a target layout based on the layout information.

Here, when the chip space size is greater than the chip space size threshold, when new position constraint information is generated based on the position constraint information of the current iteration, for example, the target register and the corresponding target logic gate device in the position constraint information of the current iteration can be reduced. The distance value between the traces to get the new position constraint information.

In addition, since the power consumption of the target circuit is also related to the routing distance between the target register and the target logic gate device, that is, the greater the routing distance, the greater the power consumption of the target circuit; therefore, in order to further reduce the target circuit In another embodiment, when the chip space size is less than or equal to the chip space size threshold, the power consumption between the target register and the corresponding target logic gate device in the position constraint information of the current iteration can also be further reduced. Get the new position constraint information, and enter the next round of iteration; until the routing distance value between the target register and the corresponding target logic gate device in the position constraint information of the current iteration reaches the minimum value in at least one iteration, In addition, the target circuit can be deployed in the chip. Here, the target circuit cannot be deployed in the chip, for example, the devices with the connection relationship in the target circuit cannot be routed normally.

For the iterative stop condition that the target circuit can be deployed in the chip, in another embodiment of the present disclosure, the layout information further includes, for example, the routing relationship information between the target register and the target logic gate device; based on the layout information, when the target layout is generated , for example: determine whether the target circuit can be deployed in the chip based on the routing relationship information between the target register and the target logic gate device; if it is determined that the target circuit can be deployed in the chip, generate the target layout based on the layout information .

Wherein, the routing relationship information includes, for example, at least one of the line connection distance, connection position, and connection method between each target register in the plurality of target registers and the target logic gate device; based on the target register and the target logic gate device When determining whether the target circuit can be deployed in the chip, for example, determining the line connection between each target register and the target logic gate device (such as line connection distance, connection position, and connection method, etc.) Is it achievable.

In addition, when it is determined that the target circuit cannot be deployed in the chip, new position constraint information is generated based on the position constraint information of the current iteration; the new position constraint information is used as the position constraint information of the current iteration, and the position constraint using the current iteration is returned. information, and a target circuit diagram, and a step of generating layout information of a plurality of target registers and target logic gate devices in the target circuit.

In this way, based on the routing relationship information between the target register and the target logic gate device, it can be determined whether the target circuit can be deployed in the chip, and then it can be determined whether the current position constraint information is suitable position constraint information. When it is determined that the target circuit cannot be deployed in the chip, it means that under the position constraint information of the current iteration, each device in the target circuit (such as target registers, target logic gate devices, etc.) The wiring relationship between the devices, that is, the target circuit cannot be implemented in the chip, the current position constraint information is not suitable position constraint information, and the next iteration needs to be performed. At this time, the position constraint information of the current iteration can be updated as the position constraint information of the next iteration, and then return to use the position constraint information of the current iteration and the target circuit diagram to generate multiple target registers and target logic gates in the target circuit The step of layout information of the device, ie, performing the next iteration until suitable location constraint information is determined, ie, generating a target layout based on the layout information when it is determined that the target circuit can be deployed in the chip.

For the stop iteration condition that the power consumption value of the target circuit is less than the preset power consumption value, after the layout information generated based on the current position constraint information can implement the target circuit in the chip, the layout information generated based on the current position constraint information can also correspond to Therefore, in another embodiment of the present disclosure, circuit power consumption simulation analysis is performed based on the layout information generated by the current iteration to obtain the power consumption of the target circuit. power consumption value; in the case that the power consumption value of the target circuit is determined to be less than the preset power consumption value, the target layout is generated based on the layout information.

In addition, when it is determined that the power consumption value of the target circuit is greater than or equal to the preset power consumption value, new position constraint information is generated based on the position constraint information of the current iteration; the new position constraint information is used as the position constraint information of the current iteration, Returns to the step of generating layout information of a plurality of target registers and target logic gate devices in the target circuit by using the position constraint information of the current iteration and the target circuit diagram.

In this way, when it is determined that the power consumption value of the target circuit is greater than or equal to the preset power consumption value, it means that under the current position constraint information, even if the target circuit can be implemented in the chip, the target circuit in the chip is still in the process of using the chip. If the power consumption of the circuit is too large, the stability of the operation of the chip will be affected, so the current position constraint information is not suitable position constraint information, and the next iteration needs to be performed. At this time, the position constraint information of the current iteration can be updated as the position constraint information of the next iteration, and then return to use the position constraint information of the current iteration and the target circuit diagram to generate the target register in the target circuit and the target logic gate device. The step of laying out information, that is, executing the next iteration until the appropriate position constraint information is determined, that is, when it is determined that the power consumption value of the target circuit is less than the preset power consumption value, generating a target layout based on the layout information.

As shown in FIG. 4 , a specific implementation flowchart of a method for generating a circuit layout provided by an embodiment of the present disclosure includes:

S401: Generate a target circuit diagram using RTL (register transfer level) design information corresponding to the target circuit.

S402: Using the position constraint information and the target circuit diagram, generate layout information of the target register and the target logic gate device in the target circuit, where the layout information includes: position information and size information corresponding to the target register and the target logic gate device respectively, and the target register The trace relationship information to the target logic gate device.

S403: Determine the chip space size occupied by the target circuit based on the position information and size information respectively corresponding to the target register and the target logic gate device; determine whether the chip space size is less than or equal to a preset chip space size threshold; if yes, then jump to Step S404; if no, jump to step S405.

S404: Based on the routing relationship information between the target register and the target logic gate device, determine whether the target circuit can be deployed in the chip, if so, jump to step S406; if not, jump to step S405.

S405: Generate new location constraint information based on the current location constraint information, use the new location constraint information as the current location constraint information, and jump to step S402.

S406: Based on the layout information, perform circuit power consumption simulation analysis to obtain the power consumption value of the target circuit, and determine whether the power consumption value of the target circuit is less than the preset power consumption value, and if so, jump to step S407; if not, then Jump to step S405.

S407: Based on the layout information, generate a target layout.

Through the above process, the power consumption of the integrated circuit manufactured based on the generated target layout is reduced.

As shown in FIG. 5 , a specific example of a method for generating a circuit layout provided by an embodiment of the present disclosure includes:

S501: Use the integrated circuit design tool Design Compiler (design compiler) to read in the RTL (register transfer level) design information of the target circuit.

S502: Define a relative placement (relative position) constraint file of the target circuit in Design Compiler to set position constraint information.

Among them, the relative placement constraint file is used to constrain the position of the target register, so as to constrain the routing distance between the output terminals of multiple target registers connected to the same target logic gate device and the target logic gate device to be equal.

S503: Read in the simulation space Floorplan (floor plan) information of the chip.

Among them, the Floorplan information is the simulation space of the chip space size threshold size.

S504: Perform physical synthesis: generate a target circuit diagram based on the RTL design information, and determine whether each device in the target circuit diagram (for example, target registers and target logic gate devices) can meet the requirements placed on the chip based on the Floorplan information and the position constraint information. Simulate the requirements in the space Floorplan, if no, go to step S502, if yes, go to step S505.

S505: Set the tcl (tool command language, tool command language) file of the ICCQ (Integrated Circuit Design Tool) based on the relative placement constraint file.

Among them, the integrated circuit design tool ICCQ is the software used to realize the simulation of integrated circuit traces, and the tcl file is the constraint file used in ICCQ to constrain the position of each device in the target circuit. During trace simulation, the placement position of each device in the target circuit is the same as the placement position in the chip's simulation space Floorplan.

S506: Complete the routing simulation of the target circuit based on the tcl file, and determine whether the routing simulation can be implemented based on the constraints of the tcl file, if yes, skip to step S507, and if not, skip to step S502.

S507: Extract the delay information of the virtual integrated circuit corresponding to the target circuit that has completed the layout and wiring, use PrimePower (motive force) to analyze the power consumption of the delay information, and determine whether the electronic pulse power consumption of the virtual integrated circuit of the target circuit is less than the preset power consumption. consumption value; if yes, go to step S508, if no, go to step S502.

S508: Generate a target layout of the target circuit based on the virtual integrated circuit corresponding to the target circuit that has completed layout and wiring.

In this embodiment of the present disclosure, when the target layout of the target circuit in the chip is generated, the target circuit diagram is generated by using the RTL design information corresponding to the target circuit, and then the target layout of the target circuit is generated based on the position constraint information and the target circuit diagram. In this way, the obtained In the target layout, the routing distances between the output terminals of multiple target registers connected to the same target logic gate device and the target logic gate device are basically the same, that is, multiple targets connected to the same target logic gate device The time required for the register to transmit signals to the target logic gate device is basically the same, so that the signals transmitted from different target registers to the same target logic gate device can arrive at almost the same time, reducing the target logic gate device because the input signal arrives at different times The number of invalid flips caused, thereby effectively reducing the power consumption value of the target circuit and improving the stability of the operation of the target circuit in the chip.

Those skilled in the art can understand that in the above method of the specific implementation, the writing order of each step does not mean a strict execution order but constitutes any limitation on the implementation process, and the specific execution order of each step should be based on its function and possible Internal logic is determined.

Based on the same inventive concept, the embodiment of the present disclosure also provides a circuit layout generation device corresponding to the circuit layout generation method, because the principle of solving the problem of the device in the embodiment of the present disclosure is the same as the above-mentioned circuit layout generation method of the embodiment of the present disclosure. Similar, therefore, the implementation of the apparatus may refer to the implementation of the method, and repeated descriptions will not be repeated.

Referring to FIG. 6 , which is a schematic diagram of an apparatus for generating a circuit layout provided by an embodiment of the present disclosure, the apparatus includes: a first generating module 601 and a second generating module 602 ; wherein,

The first generation module 601 is used to generate a target circuit diagram by using the register transfer level RTL design information corresponding to the target circuit;

The second generation module 602 is configured to generate a target layout of the target circuit by using the position constraint information and the target circuit diagram; the position constraint information is used to constrain the target circuit, the same target logic gate device is connected The wiring distance between the output ends of the multiple target registers and the target logic gate device makes the time when the output signals of the multiple target registers reach the target logic gate device within a preset range.

For the description of the processing flow of each module in the apparatus and the interaction flow between the modules, reference may be made to the relevant descriptions in the foregoing method embodiments, which will not be described in detail here.

An embodiment of the present disclosure further provides a computer device. As shown in FIG. 7 , the schematic structural diagram of the computer device provided by the embodiment of the present disclosure includes:

A processor 71 and a memory 72; the memory 72 stores machine-readable instructions executable by the processor 71, the processor 71 is configured to execute the machine-readable instructions stored in the memory 72, and the machine-readable instructions are executed by the processor 71 When executed, the processor 71 performs the following steps:

Generate the target circuit diagram using the register transfer level RTL design information corresponding to the target circuit;

generating a target layout of the target circuit using the position constraint information and the target circuit diagram;

The position constraint information is used to constrain the wiring distance between the output ends of multiple target registers connected to the same target logic gate device in the target circuit and the target logic gate device, so that the multiple target registers output signals The time to reach the target logic gate device is within a preset range.

The above-mentioned memory 72 includes a memory 721 and an external memory 722; the memory 721 here is also called an internal memory, which is used to temporarily store the operation data in the processor 71 and the data exchanged with the external memory 722 such as the hard disk. The external memory 722 performs data exchange.

For the specific execution process of the above-mentioned instructions, reference may be made to the steps of the circuit layout generation method described in the embodiments of the present disclosure, and details are not described herein again.

Embodiments of the present disclosure further provide a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is run by a processor, the steps of the circuit layout generation method described in the foregoing method embodiments are executed. . Wherein, the storage medium may be a volatile or non-volatile computer-readable storage medium.

Embodiments of the present disclosure further provide a computer program product, where the computer program product carries program codes, and the instructions included in the program codes can be used to execute the steps of the circuit layout generation method described in the above method embodiments. For details, please refer to The foregoing method embodiments are not repeated here.

Wherein, the above-mentioned computer program product can be specifically implemented by means of hardware, software or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium, and in another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (Software Development Kit, SDK), etc. Wait.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, for the specific working process of the system and device described above, reference may be made to the corresponding process in the foregoing method embodiments, which will not be repeated here. In the several embodiments provided by the present disclosure, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. The apparatus embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the shown or discussed mutual coupling or direct coupling or communication connection may be through some communication interfaces, indirect coupling or communication connection of devices or units, which may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.

The functions, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a processor-executable non-volatile computer-readable storage medium. Based on such understanding, the technical solutions of the present disclosure can be embodied in the form of software products in essence, or the parts that contribute to the prior art or the parts of the technical solutions. The computer software products are stored in a storage medium, including Several instructions are used to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of the present disclosure. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), magnetic disk or optical disk and other media that can store program codes .

Finally, it should be noted that the above-mentioned embodiments are only specific implementations of the present disclosure, and are used to illustrate the technical solutions of the present disclosure, but not to limit them. The protection scope of the present disclosure is not limited to this, although the aforementioned The embodiments describe the present disclosure in detail, and those skilled in the art should understand that: any person skilled in the art can still modify the technical solutions described in the foregoing embodiments within the technical scope disclosed by the present disclosure. Or can easily think of changes, or equivalently replace some of the technical features; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be covered in the present disclosure. within the scope of protection. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

A method for generating a circuit layout, comprising:

Generate the target circuit diagram using the register transfer level RTL design information corresponding to the target circuit;

generating a target layout of the target circuit using the position constraint information and the target circuit diagram;

Wherein, the position constraint information is used to constrain the wiring distance between the output terminals of multiple target registers connected to the target logic gate device in the target circuit and the target logic gate device, so that the multiple target registers output The time for the signal to reach the target logic gate device is within a preset range.
The circuit layout generation method according to claim 1, wherein the position constraint information is used to constrain the wiring distance between the output terminals of the plurality of target registers and the target logic gate device to be substantially equal.
The method for generating a circuit layout according to claim 1 or 2, wherein the generating the target layout of the target circuit by using the position constraint information and the target circuit diagram comprises:

Execute at least one iteration, and in each iteration, use the position constraint information of the current iteration and the target circuit diagram to generate layout information of the plurality of target registers and the target logic gate device in the target circuit ;

The target layout is generated based on the layout information in response to satisfying a preset iteration stop condition.
The circuit layout generation method according to claim 3, wherein the position constraint information of the current iteration is determined based on the position constraint information of the previous iteration, or determined based on the initial position constraint information corresponding to the first iteration .
The method for generating a circuit layout according to claim 3, wherein the method further comprises:

Determine the chip space size occupied by the target circuit based on the position information and size information respectively corresponding to the target registers and the target logic gate device in the layout information generated by the current iteration;

comparing the chip space size with a preset chip space size threshold;

Wherein, the iteration stop condition includes: the chip space size is less than or equal to the chip space size threshold.
The method for generating a circuit layout according to claim 5, wherein the method further comprises:

In response to the chip space size being greater than the chip space size threshold, generating new position constraint information based on the position constraint information of the current iteration;

Using the new position constraint information as the position constraint information of the current iteration, returning the position constraint information using the current iteration and the target circuit diagram, and generating the plurality of target registers in the target circuit and the target Steps for placement information of logic gate devices.
The method for generating a circuit layout according to claim 6, wherein the generating new position constraint information based on the position constraint information of the current iteration comprises:

In the case that the distance value between each target register and the target logic gate device in the position constraint information does not reach the minimum value, reduce the target register and the target logic gate in the position constraint information The distance value between the devices, get the new position constraint information;

Wherein, the iteration stop condition further includes: the distance value between each of the target registers and the target logic gate device in the position constraint information reaches the minimum value in the at least one iteration.
The method for generating a circuit layout according to any one of claims 3 to 6, wherein the method further comprises:

Determine whether the target circuit can be deployed in the chip based on the routing relationship information between the multiple target registers and the target logic gate device in the layout information generated by the current iteration;

Wherein, the iterative stop condition further includes: determining that the target circuit can be deployed in a chip.
The method for generating a circuit layout according to claim 8, wherein the method further comprises:

In response to determining that the target circuit cannot be deployed in the chip, generating new position constraint information based on the position constraint information of the current iteration;

Using the new position constraint information as the position constraint information of the current iteration, returning the position constraint information using the current iteration and the target circuit diagram, and generating the plurality of target registers in the target circuit and the target Steps for placement information of logic gate devices.
The method for generating a circuit layout according to any one of claims 3 to 9, wherein the method further comprises:

Based on the layout information generated by the current iteration, a circuit power consumption simulation analysis is performed to obtain a power consumption value of the target circuit;

Wherein, the iteration stop condition further includes: the power consumption value of the target circuit is less than the preset power consumption value.
The method for generating a circuit layout according to claim 10, wherein the method further comprises:

In response to determining that the power consumption value of the target circuit is greater than or equal to the preset power consumption value, generating new position constraint information based on the position constraint information of the current iteration;

Using the new position constraint information as the position constraint information of the current iteration, returning the position constraint information using the current iteration and the target circuit diagram, and generating the plurality of target registers in the target circuit and the target Steps for placement information of logic gate devices.
A circuit layout generation device, characterized in that it includes:

The first generation module is used for generating the target circuit diagram by using the register transfer stage RTL design information corresponding to the target circuit;

The second generation module is configured to generate a target layout of the target circuit by using the position constraint information and the target circuit diagram; wherein the position constraint information is used to constrain the target logic gate devices in the target circuit connected to the target circuit. The wiring distance between the output ends of the multiple target registers and the target logic gate device enables the time when the output signals of the multiple target registers reach the target logic gate device within a preset range.
A computer device, comprising: a processor and a memory, wherein the memory stores machine-readable instructions executable by the processor, and the processor is configured to execute the machine-readable instructions stored in the memory, When the machine-readable instructions are executed by the processor, the processor performs the steps of the method for generating a circuit layout according to any one of claims 1 to 11.
A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, and when the computer program is run by a computer device, the computer device executes any one of claims 1 to 11. The steps of the circuit layout generation method described above.