WO2022227234A1 - 满足不同负载下自适应线性稳压器的相位补偿电路与方法 - Google Patents

满足不同负载下自适应线性稳压器的相位补偿电路与方法 Download PDF

Info

Publication number
WO2022227234A1
WO2022227234A1 PCT/CN2021/099226 CN2021099226W WO2022227234A1 WO 2022227234 A1 WO2022227234 A1 WO 2022227234A1 CN 2021099226 W CN2021099226 W CN 2021099226W WO 2022227234 A1 WO2022227234 A1 WO 2022227234A1
Authority
WO
WIPO (PCT)
Prior art keywords
electrically connected
circuit
tube
transistor
nmos transistor
Prior art date
Application number
PCT/CN2021/099226
Other languages
English (en)
French (fr)
Inventor
刘晓敏
袁广睿
彭豪
许哲鸣
Original Assignee
无锡力芯微电子股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 无锡力芯微电子股份有限公司 filed Critical 无锡力芯微电子股份有限公司
Priority to KR1020227008314A priority Critical patent/KR20220148794A/ko
Publication of WO2022227234A1 publication Critical patent/WO2022227234A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is dc
    • G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/26—Current mirrors
    • G05F3/262—Current mirrors using field-effect transistors only

Definitions

  • the invention belongs to the technical field of integrated circuits, and in particular relates to a phase compensation circuit and method for adaptive linear voltage regulators under different loads.
  • the stability of the linear regulator circuit will have a small or insufficient phase margin under different load currents, which affects the dynamic response of the loop and stability.
  • the present invention provides a phase compensation circuit and method for adapting an adaptive linear regulator under different loads, which can solve the phase stability problem of the linear regulator circuit under different loads.
  • the present invention adopts the following technical scheme to realize: a phase compensation circuit satisfying the adaptive linear voltage stabilizer under different loads, including a linear voltage stabilizer circuit and a power tube grid driving signal tracking circuit, and the linear voltage stabilizer circuit is electrically connected with a The first NMOS transistor; the power transistor gate drive signal tracking circuit is electrically connected to the first NMOS transistor, and is used for adjusting the on-resistance of the first NMOS transistor according to different loads.
  • the power transistor gate drive signal tracking circuit turns the GATE DRIVER into the control signal R_Dynamic_Con of the dynamic regulator, and then the control signal R_Dynamic_Con controls the change of the first NMOS transistor, and then changes the access to the linear regulator.
  • the resistance of the circuit thus changes the output voltage. After the resistance of the first NMOS tube changes, the zero point is moved, which in turn cancels the output pole and stabilizes the output.
  • the power transistor gate drive signal tracking circuit includes a second NMOS transistor, a first resistor and a first PMOS transistor, the first PMOS transistor is electrically connected to an external power supply, and the first PMOS transistor is electrically connected to the first resistor
  • the first resistor is electrically connected to the second NMOS transistor, the second NMOS transistor is grounded, and the first PMOS transistor is electrically connected to the first NMOS transistor.
  • the first PMOS tube is used to sample the signal change of the GATE DRIVER, and the first resistor acts as a DC bias, turning the GATE DRIVER into the control signal R_Dynamic_Con of the dynamic adjustment tube, and then the control signal R_Dynamic_Con controls The first NMOS transistor changes, and then the equivalent resistance of the access circuit is changed to change the output voltage.
  • the linear regulator circuit includes a first current mirror, a second current mirror, a bias current source, an adjusting tube, a zero-adjusting resistor, a Miller capacitor, a load periphery, a first differential input pair tube,
  • the second difference input pair is in charge of the tube, the capacitive inductance circuit, the first feedback network and the second feedback network.
  • the bias current source is electrically connected to the first difference input pair tube, and the first difference input pair tube is electrically connected to the first current mirror.
  • the first current mirror is electrically connected with the second current mirror, the first current mirror is grounded, the second differential input pair tube is electrically connected with ferrite beads, and the second current mirror is sequentially connected to the adjustment tube, the second resistor, the first An NMOS transistor is electrically connected to the second differential input pair, the first NMOS transistor is electrically connected to the Miller capacitor, the zero-adjusting resistor is electrically connected to the Miller capacitor, the Miller capacitor is electrically connected to a power transistor, and the power transistors are in turn It is electrically connected to the first feedback network, the capacitive inductance circuit and the load periphery, the first feedback network is electrically connected to the second feedback network, the second feedback network is grounded, the load peripheral is grounded, the capacitive inductance circuit is grounded, and the first NMOS The tube is connected in parallel with the zero-adjusting resistor.
  • P OUT will dynamically change with the load periphery, and the first PMOS tube accepts the GATE DRIVER signal.
  • R_Dynamic_Con the equivalent resistance size of the first NMOS tube and the zero-adjusting resistor is controlled by R_Dynamic_Con to make P OUT a suitable size.
  • the bias current source includes a second PMOS transistor and a third PMOS transistor, the drain of the second PMOS transistor is connected to an external power supply, and the drain of the third PMOS transistor is connected to the external power supply.
  • the drain of the second PMOS transistor is electrically connected to the source of the first differential input pair of transistors, and the source of the third PMOS transistor is electrically connected to the drain of the power transistor.
  • Phase compensation methods for adaptive linear regulators under different loads including:
  • the first PMOS tube samples the signal change in the linear regulator circuit, the second NMOS tube and the first resistor play the role of DC bias, and the sampled signal change in the linear regulator circuit is converted into the second Control signal R_Dynamic_Con of NMOS tube;
  • control signal R_Dynamic_Con controls the resistance value change of the first NMOS tube, thereby changing the resistance value of the parallel zero-adjusting resistor composed of the first NMOS tube and the zero-adjusting resistor;
  • the zero point C C 1/22 ⁇ (RN4R1/(RN4+R1))C1 changes, which in turn cancels P OUT , thereby generating a stable output.
  • FIG. 1 is a circuit diagram of a linear voltage regulator circuit and a first NMOS tube being electrically connected in the present invention
  • FIG. 2 is a circuit diagram of a power tube grid drive signal tracking circuit
  • FIG. 3 is a circuit diagram of the prior art.
  • P1-the first differential input pair is in charge
  • P2-the second differential input pair is in charge
  • P3-the second PMOS tube P4-the third PMOS tube
  • P5-power tube P6-the first PMOS tube
  • R3-the first PMOS tube A feedback network, R2-second feedback network, R1-zeroing resistor, R4-first resistor, RL-load peripheral, N1-first current mirror, N2-second current mirror, N3-adjustment tube, N4-th One NMOS tube, N5- the second NMOS tube, C1- Miller capacitor, CL-capacitance circuit.
  • a phase compensation method and circuit for an adaptive linear regulator under different loads including a linear regulator circuit and a power tube grid drive signal tracking circuit, the linear regulator circuit has a power-on property
  • a first NMOS transistor N4 is connected; the power transistor gate drive signal tracking circuit is electrically connected to the first NMOS transistor N4 for adjusting the on-resistance of the first NMOS transistor N4 according to different loads.
  • the power transistor gate drive signal tracking circuit converts the GATE DRIVER to the control signal R_Dynamic_Con of the dynamic regulator, and then the control signal R_Dynamic_Con controls the first NMOS transistor N4 to change, and then changes the access linear regulator.
  • the resistance of the circuit is changed to change the output voltage. After the resistance of the first NMOS transistor N4 changes, the zero point is moved, thereby offsetting the output pole, so as to stabilize the output.
  • the power transistor gate drive signal tracking circuit includes a second NMOS transistor N5, a first resistor R4, and a first PMOS transistor P6.
  • the first PMOS transistor P6 is electrically connected to an external power supply, and the first PMOS transistor P6 is electrically connected to the first resistor R4.
  • the first resistor R4 is electrically connected to the second NMOS transistor N5, the second NMOS transistor N5 is grounded, and the first PMOS transistor P6 is electrically connected to the first NMOS transistor N4.
  • the first PMOS tube P6 is used to sample the signal change of the GATE DRIVER, and the first resistor R4 acts as a DC bias, turning the GATE DRIVER into a dynamic adjustment tube, that is, the first NMOS tube N4.
  • the control signal R_Dynamic_Con, and then the control signal R_Dynamic_Con controls the first NMOS transistor N4 to change, and then changes the equivalent resistance of the access circuit to change the output voltage.
  • the linear regulator circuit includes a first current mirror N1, a second current mirror N2, a bias current source, an adjustment tube N3, a zero-adjusting resistor R1, a Miller capacitor C1, a load peripheral RL, a first differential input pair tube P1, and a first differential input pair tube P1.
  • the two-difference input pair divides the tube P2, the capacitive inductance circuit CL, the first feedback network R3 and the second feedback network R2, the bias current source is electrically connected to the first difference input pair tube P1, and the first difference input pair tube P1 is connected to the first differential input pair tube P1.
  • the current mirror N1 is electrically connected, the first current mirror N1 is electrically connected to the second current mirror N2, the first current mirror N1 is grounded, the second differential input pair tube P2 is electrically connected with a ferrite bead FB, and the second current mirror N1 is electrically connected to
  • the mirror N2 is electrically connected to the adjusting tube N3, the second resistor R1, the first NMOS tube N4 and the second differential input pair tube P2 in turn, the first NMOS tube N4 is electrically connected to the Miller capacitor C1, and the zero-adjusting resistor R1 is connected to the
  • the Miller capacitor C1 is electrically connected, the Miller capacitor C1 is electrically connected with a power tube (P5), the power tube P5 is electrically connected with the first feedback network R3, the capacitance-inductance circuit CL and the load peripheral R L are electrically connected in sequence, and the first The feedback network R3 is electrically connected to the second feedback network R2, the second feedback network R2 is grounded, the load periphery RL is grounded,
  • Phase compensation methods for adaptive linear regulators under different loads including:
  • the first PMOS transistor P6 samples the signal change in the linear regulator circuit, and the second NMOS transistor and the first resistor R4 act as a DC bias to convert the sampled signal change in the linear regulator circuit into The control signal R_Dynamic_Con of the second NMOS transistor N5;
  • control signal R_Dynamic_Con controls the change of the resistance value of the first NMOS transistor N4, thereby changing the resistance value of the parallel zero-adjustment resistor composed of the first NMOS transistor N4 and the zero-adjustment resistor R1;
  • the zero point C C 1/22 ⁇ (RN4R1/(RN4+R1))C1 changes, which in turn cancels P OUT , thereby generating a stable output
  • P OUT will dynamically change with the load periphery.
  • the equivalent resistance of the first NMOS transistor P6 and the zero-adjusting resistor R1 is controlled by R_Dynamic_Con to make P OUT a suitable size.
  • the main operational amplifier part of the traditional linear regulator circuit is composed of a first current mirror N1, a second current mirror N2, a first differential input pair tube P1, a second differential input pair tube P2, a bias current source, and a regulating tube N3. .
  • the power output tube P5/the first feedback network R3 and the second feedback network R2 provide a stable output voltage and load current.
  • the load current is determined by the load peripheral RL used by the user.
  • the main op amp is used for phase compensation.
  • the zero-point position because the resistance and capacitance of the Miller capacitor C1 and the zero-adjusting resistor R1 are fixed, so the frequency point position within the system bandwidth is fixed, and the linearity is stable.
  • POUT When CL is fixed, POUT will dynamically change with RL.
  • the internal compensation zero can track the output pole, and the stability of the entire linear regulator circuit will not have a small or insufficient phase margin, so as to avoid affecting the dynamic response and stability of the loop. .
  • the bias current source includes a second PMOS transistor P3 and a third PMOS transistor P4, the drain of the second PMOS transistor P3 is connected to an external power supply, and the drain of the third PMOS transistor P4 is connected to the external power supply.
  • the source of the first differential input pair tube P1 is electrically connected to the drain of the first current mirror N1, the gate of the first current mirror N1 is electrically connected to the gate of the second current mirror N2, and the gate of the second current mirror N2 is electrically connected.
  • the drain is electrically connected to the source of the first NMOS transistor N4, the gate of the adjustment transistor N3 and the source of the second differential input pair transistor P2 in turn, and the drain of the first NMOS transistor N4 is electrically connected to the Miller capacitor C1.
  • the drain of the second PMOS transistor P3 is electrically connected to the source of the first differential input pair of branch transistors P1, the source of the third PMOS transistor P4 is electrically connected to the drain of the power transistor P5, and the source of the power transistor P5 is electrically connected.
  • the poles are electrically connected to the first feedback network R3, the load periphery RL and the capacitive inductance circuit CL in sequence.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)

Abstract

一种满足不同负载需求下的自适应线性稳压器的相位补偿电路及方法，相位补偿电路包括线性稳压器电路和功率管栅驱动信号追踪电路。线性稳压器电路上电性连接有第一NMOS管（N4）；功率管栅驱动信号追踪电路与第一NMOS管（N4）电性连接，用于根据不同负载调节第一NMOS管（N4）的导通电阻，从而具有在不同负载下相位稳定、动态响应良好的优点。

Description

满足不同负载下自适应线性稳压器的相位补偿电路与方法 技术领域
本发明属于集成电路技术领域，特别涉及一种满足不同负载下自适应线性稳压器的相位补偿电路与方法。
背景技术
目前，线性稳压器技术发展已经接近于成熟，如图3所示。
但是，由于线性稳压器电路的补偿零点基本固定，所以在不同的负载电流下线性稳压器电路的稳定性就会出现相位裕量较小或不够的情况，影响了环路的动态响应和稳定性。
发明内容
本发明提出一种满足不同负载下自适应线性稳压器的相位补偿电路与方法，能够解决线性稳压器电路在不同负载下的相位稳定性问题。
本发明采用以下技术方案实现：一种满足不同负载下自适应线性稳压器的相位补偿电路，包括线性稳压器电路和功率管栅驱动信号追踪电路，线性稳压器电路上电性连接有第一NMOS管；功率管栅驱动信号追踪电路与第一NMOS管电性连接，用于根据不同负载调节第一NMOS管的导通电阻。
线性稳压器电路的不同负载下，功率管栅驱动信号追踪电路将GATE DRIVER转为动态调整管的控制信号R_Dynamic_Con，然后控制信号R_Dynamic_Con控制第一NMOS管变化，然后改变了接入线性稳压器电路的电阻从而改变输出电压，第一NMOS管电阻变化之后，进而使得零点移动，进而抵消输出极点，使得稳定输出。
作为一种优选的实施方式，功率管栅驱动信号追踪电路包括第二NMOS管、第一电阻和第一PMOS管，第一PMOS管与外部电源电性连接，第一PMOS管与第一电阻电性连接，第一电阻与第二NMOS管电性连接，第二NMOS管接地，第一PMOS管与第一NMOS管电性连接。线性稳压器电路的不同负载下，第一PMOS管 用于采样GATE DRIVER的信号变化，和第一电阻起直流偏置作用，将GATE DRIVER转为动态调整管的控制信号R_Dynamic_Con，然后控制信号R_Dynamic_Con控制第一NMOS管变化，然后改变了接入电路的等效电阻从而改变输出电压。
作为一种优选的实施方式，线性稳压器电路包括第一电流镜、第二电流镜、偏置电流源、调整管、调零电阻、密勒电容、负载外围、第一差输入对分管、第二差输入对分管、容感电路、第一反馈网络和第二反馈网络，偏置电流源与第一差输入对分管电性连接，第一差输入对分管与第一电流镜电性连接，第一电流镜与第二电流镜电性连接，第一电流镜接地，第二差输入对分管电性连接有铁氧体磁珠，第二电流镜依次与调整管、第二电阻、第一NMOS管和第二差输入对分管电性连接，第一NMOS管与密勒电容电性连接，调零电阻与密勒电容电性连接，密勒电容电性连接有功率管，功率管依次与第一反馈网络电性连接、容感电路和负载外围电性连接，第一反馈网络与第二反馈网络电性连接，第二反馈网络接地，负载外围接地，容感电路接地，第一NMOS管与调零电阻并联。
密勒电容和调零电阻组成相位补偿，对应的补偿零点为C C＝1/2ΠR1C1,在容感电路固定的情况下，P OUT将随负载外围动态变化，在第一PMOS管接受GATE DRIVER信号并且处理后通过R_Dynamic_Con控制第一NMOS管与调零电阻的等效电阻大小使得P OUT为合适大小，此时零点为C C＝1/22Π(RN4R1/(RN4+R1))C1，其中RN4为R_Dynamic_Con栅信号控制NMOS管(N4)的等效导通电阻,第二NMOS管和第一NMOS管起直流偏置作用，将GATE DRIVER转为第一NMOS管即调整管的控制信号R_Dynamic_Con。增大负载时，随着GATE DRIVER降低，R_Dynamic_Con升高，第一NMOS管和调零电阻组成的并联调零电阻阻值减小，零点C C＝1/2Π(R N4R1/(R N4+R1))C1位置往高频移动，追踪抵消高频下的输出极点P OUT，在小负载下，调整趋势相反，零点C C位置往低频移动，追踪抵消低频下的输出极点P OUT，即补偿零点基本固定，此时在不同的负载电流下，系统稳定性就不会出现相位裕量较小或不够的情况，避免对环路的动态响应和稳定性的影响。
作为一种优选的实施方式，偏置电流源包括第二PMOS管和第三PMOS管，第二PMOS管的漏极连接外部电源，第三PMOS管的漏极连接外部电源。
作为一种优选的实施方式，第二PMOS管的漏极与第一差输入对分管的源极电性连接，第三PMOS管的源极与功率管的漏极电性连接。
满足不同负载下自适应线性稳压器的相位补偿方法，包括：
第一步，接入负载外围，线性稳压器电路根据负载外围产生一个输出极点P OUT＝1/22ΠRLCL；
第二步，第一PMOS管采样线性稳压器电路中的信号变化，第二NMOS管和第一电阻起直流偏置作用，将采样到的线性稳压器电路中的信号变化转为第二NMOS管的控制信号R_Dynamic_Con；
第三步，控制信号R_Dynamic_Con控制第一NMOS管的阻值变化，从而改变第一NMOS管和调零电阻组成的并联调零电阻的阻值；
第四步，由于第三步中并联调零电阻阻值的改变，使得零点C C＝1/22Π(RN4R1/(RN4+R1))C1改变，进而抵消P OUT，从而产生稳定输出。
采用了上述技术方案后，本发明的有益效果是：
增大负载时，随着GATE DRIVER降低，R_Dynamic_Con升高，第一NMOS管和调零电阻组成的并联调零电阻阻值减小，零点C C＝1/2Π(R N4R1/(R N4+R1))C1位置往高频移动，追踪抵消高频下的输出极点P OUT，在小负载下，调整趋势相反，零点C C位置往低频移动，追踪抵消低频下的输出极点P OUT，即内部的补偿零点能够跟踪输出极点，此时在不同的负载电流下，系统稳定性就不会出现相位裕量较小或不够的情况，避免对环路的动态响应和稳定性的影响。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动性的前提下，还可以根据这些附图获得其他的附图。
图1为本发明中线性稳压器电路与第一NMOS管电性连接的电路图；
图2为功率管栅驱动信号追踪电路的电路图；
图3为现有技术的电路图。
图中，P1-第一差输入对分管，P2-第二差输入对分管，P3-第二PMOS管，P4-第三PMOS管，P5-功率管，P6-第一PMOS管，R3-第一反馈网络，R2-第二反馈网络，R1-调零电阻，R4-第一电阻，RL-负载外围，N1-第一电流镜，N2-第二电流镜，N3-调整管，N4-第一NMOS管，N5-第二NMOS管，C1-密勒电容，CL-容感电路。
具体实施方式
下面将结合本发明实施例中的附图，对本发明实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本发明一部分实施例，而不是全部的实施例。基于本发明中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本发明保护的范围。
根据图1～2所示，一种满足不同负载下自适应线性稳压器的相位补偿方法与电路，包括线性稳压器电路和功率管栅驱动信号追踪电路，线性稳压器电路上电性连接有第一NMOS管N4；功率管栅驱动信号追踪电路与第一NMOS管N4电性连接，用于根据不同负载调节第一NMOS管N4的导通电阻。
线性稳压器电路的不同负载下，功率管栅驱动信号追踪电路将GATE DRIVER转为动态调整管的控制信号R_Dynamic_Con，然后控制信号R_Dynamic_Con控制第一NMOS管N4变化，然后改变了接入线性稳压器电路的电阻从而改变输出电压，第一NMOS管N4的电阻变化之后，进而使得零点移动，进而抵消输出极点，使得稳定输出。
功率管栅驱动信号追踪电路包括第二NMOS管N5、第一电阻R4和第一PMOS管P6，第一PMOS管P6与外部电源电性连接，第一PMOS管P6与第一电阻R4电性连接，第一电阻R4与第二NMOS管N5电性连接，第二NMOS管N5接地，第一PMOS管P6与第一NMOS管N4电性连接。线性稳压器电路的不同负载下，第一PMOS管P6用于采样GATE DRIVER的信号变化，和第一电阻R4起直流偏置作用，将GATE DRIVER转为动态调整管即第一NMOS管N4的控制信号R_Dynamic_Con，然 后控制信号R_Dynamic_Con控制第一NMOS管N4变化，然后改变了接入电路的等效电阻从而改变输出电压。
线性稳压器电路包括第一电流镜N1、第二电流镜N2、偏置电流源、调整管N3、调零电阻R1、密勒电容C1、负载外围RL、第一差输入对分管P1、第二差输入对分管P2、容感电路CL、第一反馈网络R3和第二反馈网络R2，偏置电流源与第一差输入对分管P1电性连接，第一差输入对分管P1与第一电流镜N1电性连接，第一电流镜N1与第二电流镜N2电性连接，第一电流镜N1接地，第二差输入对分管P2电性连接有铁氧体磁珠FB，第二电流镜N2依次与调整管N3、第二电阻R1、第一NMOS管N4和第二差输入对分管P2电性连接，第一NMOS管N4与密勒电容C1电性连接，调零电阻R1与密勒电容C1电性连接，密勒电容C1电性连接有功率管(P5)，功率管P5依次与第一反馈网络R3电性连接、容感电路CL和负载外围R L电性连接，第一反馈网络R3与第二反馈网络R2电性连接，第二反馈网络R2接地，负载外围R L接地，容感电路CL接地。第一NMOS管N4与调零电阻R1并联。
满足不同负载下自适应线性稳压器的相位补偿方法，包括：
第一步，接入负载外围RL，线性稳压器电路根据负载外围RL产生一个输出极点P OUT＝1/22ΠRLCL；
第二步，第一PMOS管P6采样线性稳压器电路中的信号变化，第二NMOS管和第一电阻R4起直流偏置作用，将采样到的线性稳压器电路中的信号变化转为第二NMOS管N5的控制信号R_Dynamic_Con；
第三步，控制信号R_Dynamic_Con控制第一NMOS管N4的阻值变化，从而改变第一NMOS管N4和调零电阻R1组成的并联调零电阻的阻值；
第四步，由于第三步中并联调零电阻阻值的改变，使得零点C C＝1/22Π(RN4R1/(RN4+R1))C1改变，进而抵消P OUT，从而产生稳定输出
密勒电容C1和调零电阻R1组成相位补偿，对应的补偿零点为C C＝1/2ΠR1C1,在容感电路CL固定的情况下，P OUT将随负载外围动态变化，在第一PMOS管P6接受GATE DRIVER信号并且处理后通过R_Dynamic_Con控制第一NMOS管P6与调零电阻R1的等效电阻大小使得P OUT为合适大小，此时零点为C C＝1/22Π (RN4R1/(RN4+R1))C1，其中RN4为R_Dynamic_Con栅信号控制NMOS管(N4)的等效导通电阻,第二NMOS管N5和第一NMOS管N4起直流偏置作用，将GATE DRIVER转为第一NMOS管N4即调整管的控制信号R_Dynamic_Con。增大负载时，随着GATE DRIVER降低，R_Dynamic_Con升高，第一NMOS管N4和调零电阻R1组成的并联调零电阻阻值减小，零点C C＝1/2Π(R N4R1/(R N4+R1))C1位置往高频移动，追踪抵消高频下的输出极点P OUT，在小负载下，调整趋势相反，零点C C位置往低频移动，追踪抵消低频下的输出极点P OUT，
传统的线性稳压器电路的主运放部分由第一电流镜N1,第二电流镜N2，第一差输入对分管P1,第二差输入对分管P2，偏置电流源，调整管N3构成。功率输出管P5/第一反馈网络R3与第二反馈网络R2提供稳定的输出电压负载电流，其中负载电流由用户使用的负载外围RL决定，主运放用于相位补偿的是密勒电容C1和调零电阻R1，组成补偿零点C C＝1/2ΠR1C1，该零点位置，因为密勒电容C1和调零电阻R1的阻值和容值固定，所以在系统带宽内的频率点位置固定，线性稳压器电路使用范围需要适应不同的负载电流，所以就会产生个动态的输出极点P OUT＝1/22ΠRLCL，在CL固定的情况下，POUT将随RL动态变化。此时在不同的负载电流下，内部的补偿零点能够跟踪输出极点，整个线性稳压器电路稳定性就不会出现相位裕量较小或不够的情况，避免影响环路的动态响应和稳定性。
偏置电流源包括第二PMOS管P3和第三PMOS管P4，第二PMOS管P3的漏极连接外部电源，第三PMOS管P4的漏极连接外部电源。第一差输入对分管P1的源极与第一电流镜N1的漏极电性连接，第一电流镜N1的栅极与第二电流镜N2的栅极电性连接，第二电流镜N2的漏极依次与第一NMOS管N4的源极电性、调整管N3的栅极和第二差输入对分管P2的源极电性连接，第一NMOS管N4的漏极与密勒电容C1电性连接，第二PMOS管P3的漏极与第一差输入对分管P1的源极电性连接，第三PMOS管P4的源极与功率管P5的漏极电性连接，功率管P5的源极依次与第一反馈网络R3、负载外围RL和容感电路CL电性连接。
以上仅为本发明的较佳实施例而已，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (7)

  1. 满足不同负载下自适应线性稳压器的相位补偿电路，其特征在于，包括线性稳压器电路和功率管栅驱动信号追踪电路，所述线性稳压器电路上电性连接有第一NMOS管(N4)；
    功率管栅驱动信号追踪电路与第一NMOS管(N4)电性连接，用于根据不同负载调节第一NMOS管(N4)的导通电阻。
  2. 根据权利要求1所述的满足不同负载下自适应线性稳压器的相位补偿电路，其特征在于，所述功率管栅驱动信号追踪电路包括第二NMOS管(N5)、第一电阻(R4)和第一PMOS管(P6)，所述第一PMOS管(P6)与外部电源电性连接，所述第一PMOS管(P6)与第一电阻(R4)电性连接，所述第一电阻(R4)与第二NMOS管(N5)电性连接，所述第二NMOS管(N5)接地，所述第一PMOS管(P6)与第一NMOS管(N4)电性连接。
  3. 根据权利要求1所述的满足不同负载下自适应线性稳压器的相位补偿电路，其特征在于，所述线性稳压器电路包括第一电流镜(N1)、第二电流镜(N2)、偏置电流源、调整管(N3)、调零电阻(R1)、密勒电容(C1)、负载外围(RL)、第一差输入对分管(P1)、第二差输入对分管(P2)、容感电路(CL)、第一反馈网络(R3)和第二反馈网络(R2)，所述偏置电流源与第一差输入对分管(P1)电性连接，所述第一差输入对分管(P1)与第一电流镜(N1)电性连接，所述第一电流镜(N1)与第二电流镜(N2)电性连接，所述第一电流镜(N1)接地，所述第二差输入对分管(P2)电性连接有铁氧体磁珠(FB)，所述第二电流镜(N2)依次与调整管(N3)、第二电阻(R1)、第一NMOS管(N4)和第二差输入对分管(P2)电性连接，所述第一NMOS管(N4)与密勒电容(C1)电性连接，所述调零电阻(R1)与密勒电容(C1)电性连接，所述密勒电容(C1)电性连接有功率管(P5)，所述功率管(P5)依次与第一反馈网络(R3)电性连接、容感电路(CL)和负载外围(R L)电性连接，所述第一反馈网络(R3)与第二反馈网络(R2)电性连接，所述第二反馈网络(R2)接地，所述负载外围(R L)接地，所述容感电路(CL)接地。
  4. 根据权利要求3所述的满足不同负载下自适应线性稳压器的相位补偿电路，其特征在于，所述第一NMOS管(N4)与调零电阻(R1)并联。
  5. 根据权利要求3所述的满足不同负载下自适应线性稳压器的相位补偿电路，其特征在于，所述偏置电流源包括第二PMOS管(P3)和第三PMOS管(P4)，所述第二PMOS管(P3)的漏极连接外部电源，所述第三PMOS管(P4)的漏极连接外部电源。
  6. 根据权利要求5所述的满足不同负载下自适应线性稳压器的相位补偿电路，其特征在于，所述第二PMOS管(P3)的漏极与第一差输入对分管(P1)的源极电性连接，所述第三PMOS管(P4)的源极与功率管(P5)的漏极电性连接。
  7. 满足不同负载下自适应线性稳压器的相位补偿方法，包括如权利要求1～6任一项所述的满足不同负载下自适应线性稳压器的相位补偿电路，其特征在于，包括：
    第一步，接入负载外围(RL)，线性稳压器电路根据负载外围(RL)产生一个输出极点P OUT＝1/22ΠRLCL；
    第二步，第一PMOS管(P6)采样线性稳压器电路中的信号变化，第二NMOS管和第一电阻(R4)起直流偏置作用，将采样到的线性稳压器电路中的信号变化转为第二NMOS管(N5)的控制信号R_Dynamic_Con；
    第三步，控制信号R_Dynamic_Con控制第一NMOS管(N4)的阻值变化，从而改变第一NMOS管(N4)和调零电阻(R1)组成的并联调零电阻的阻值；
    第四步，由于第三步中并联调零电阻阻值的改变，使得零点C C＝1/22Π(RN4R1/(RN4+R1))C1改变，进而抵消P OUT，从而产生稳定输出。
PCT/CN2021/099226 2021-04-27 2021-06-09 满足不同负载下自适应线性稳压器的相位补偿电路与方法 WO2022227234A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020227008314A KR20220148794A (ko) 2021-04-27 2021-06-09 상이한 부하 요건을 충족시키는 자가적응 선형 레귤레이터의 위상 보상 회로 및 방법

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110460816.2A CN113190076A (zh) 2021-04-27 2021-04-27 满足不同负载下自适应线性稳压器的相位补偿电路与方法
CN202110460816.2 2021-04-27

Publications (1)

Publication Number Publication Date
WO2022227234A1 true WO2022227234A1 (zh) 2022-11-03

Family

ID=76979464

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/099226 WO2022227234A1 (zh) 2021-04-27 2021-06-09 满足不同负载下自适应线性稳压器的相位补偿电路与方法

Country Status (3)

Country Link
KR (1) KR20220148794A (zh)
CN (1) CN113190076A (zh)
WO (1) WO2022227234A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114253340B (zh) * 2021-12-20 2023-05-02 深圳飞骧科技股份有限公司 一种零点动态调整的频率补偿线性稳压电路

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101059702A (zh) * 2006-04-14 2007-10-24 半导体元件工业有限责任公司 线性稳压器及其制造方法
CN101847028A (zh) * 2010-04-14 2010-09-29 广州市广晟微电子有限公司 一种超低功耗的动态补偿电路及应用该电路的线性调节器
CN101957628A (zh) * 2009-07-17 2011-01-26 上海沙丘微电子有限公司 低压差线性稳压器中的自适应零点频率补偿电路
CN102541134A (zh) * 2011-05-11 2012-07-04 电子科技大学 一种基于动态零极点跟踪技术的ldo
CN102830741A (zh) * 2012-09-03 2012-12-19 电子科技大学 双环路低压差线性稳压器
CN103064455A (zh) * 2012-12-07 2013-04-24 广州慧智微电子有限公司 一种基于调零电阻的动态零点米勒补偿线性电压调整电路
CN104777871A (zh) * 2015-05-08 2015-07-15 苏州大学 一种低压差线性稳压器
CN109116906A (zh) * 2018-10-31 2019-01-01 上海海栎创微电子有限公司 一种基于自适应零点补偿的低压差线性稳压器
CN112346508A (zh) * 2020-10-22 2021-02-09 无锡艾为集成电路技术有限公司 线性稳压器及电子设备

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8547077B1 (en) * 2012-03-16 2013-10-01 Skymedi Corporation Voltage regulator with adaptive miller compensation
CN109164861A (zh) * 2018-10-31 2019-01-08 上海海栎创微电子有限公司 一种快速瞬态响应的低压差线性稳压器
CN111367345B (zh) * 2020-05-26 2021-04-20 江苏长晶科技有限公司 改善低压差线性稳压器全负载稳定性的补偿方法及其电路

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101059702A (zh) * 2006-04-14 2007-10-24 半导体元件工业有限责任公司 线性稳压器及其制造方法
CN101957628A (zh) * 2009-07-17 2011-01-26 上海沙丘微电子有限公司 低压差线性稳压器中的自适应零点频率补偿电路
CN101847028A (zh) * 2010-04-14 2010-09-29 广州市广晟微电子有限公司 一种超低功耗的动态补偿电路及应用该电路的线性调节器
CN102541134A (zh) * 2011-05-11 2012-07-04 电子科技大学 一种基于动态零极点跟踪技术的ldo
CN102830741A (zh) * 2012-09-03 2012-12-19 电子科技大学 双环路低压差线性稳压器
CN103064455A (zh) * 2012-12-07 2013-04-24 广州慧智微电子有限公司 一种基于调零电阻的动态零点米勒补偿线性电压调整电路
CN104777871A (zh) * 2015-05-08 2015-07-15 苏州大学 一种低压差线性稳压器
CN109116906A (zh) * 2018-10-31 2019-01-01 上海海栎创微电子有限公司 一种基于自适应零点补偿的低压差线性稳压器
CN112346508A (zh) * 2020-10-22 2021-02-09 无锡艾为集成电路技术有限公司 线性稳压器及电子设备

Also Published As

Publication number Publication date
KR20220148794A (ko) 2022-11-07
CN113190076A (zh) 2021-07-30

Similar Documents

Publication Publication Date Title
CN109976424B (zh) 一种无电容型低压差线性稳压器
CN111367345B (zh) 改善低压差线性稳压器全负载稳定性的补偿方法及其电路
CN105005351A (zh) 一种共源共栅全集成低漏失线性稳压器电路
CN108508951B (zh) 一种无片外电容的ldo稳压器电路
US20110193540A1 (en) Enhancement of Power Supply Rejection for Operational Amplifiers and Voltage Regulators
CN113467559B (zh) 一种应用于ldo的自适应动态零点补偿电路
US11693441B2 (en) Dual loop voltage regulator utilizing gain and phase shaping
WO2014131311A1 (zh) 一种电流源产生器
US8698556B2 (en) Low switching error, small capacitors, auto-zero offset buffer amplifier
CN111176358A (zh) 一种低功耗低压差线性稳压器
TW201939190A (zh) 電壓調節器
WO2022227234A1 (zh) 满足不同负载下自适应线性稳压器的相位补偿电路与方法
US20230006536A1 (en) Improving psrr across load and supply variances
CN114265460B (zh) 一种片内集成式频率补偿可调的低压差线性稳压器
US20010020865A1 (en) Transconductor and filter circuit
CN208351365U (zh) 一种可选接片外电容的低压差线性稳压器
JPH08274550A (ja) 広い駆動範囲を有するカスコード段を含むｍｏｓ技術の電流ミラー
WO2023116297A1 (zh) 一种零点动态调整的频率补偿线性稳压电路
CN216721300U (zh) 一种带有自适应负载变化的频率补偿电路的稳定电路
CN117111665A (zh) 一种高电源抑制比ldo电路及其应用
CN105867504B (zh) 一种高电源抑制比基准电压源
US20150249430A1 (en) Compensating A Two Stage Amplifier
CN114006610A (zh) 一种带有自适应负载变化的频率补偿电路的稳定电路
CN209265310U (zh) 一种电压缓冲器电路
CN109101069A (zh) 一种电压缓冲器电路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21938703

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21938703

Country of ref document: EP

Kind code of ref document: A1