WO2022227150A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

Info

Publication number
WO2022227150A1
WO2022227150A1 PCT/CN2021/095452 CN2021095452W WO2022227150A1 WO 2022227150 A1 WO2022227150 A1 WO 2022227150A1 CN 2021095452 W CN2021095452 W CN 2021095452W WO 2022227150 A1 WO2022227150 A1 WO 2022227150A1
Authority
WO
WIPO (PCT)
Prior art keywords
sub
source
source wiring
light
data signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
PCT/CN2021/095452
Other languages
English (en)
French (fr)
Inventor
胡道兵
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TCL China Star Optoelectronics Technology Co Ltd
Original Assignee
TCL China Star Optoelectronics Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TCL China Star Optoelectronics Technology Co Ltd filed Critical TCL China Star Optoelectronics Technology Co Ltd
Priority to US17/423,956 priority Critical patent/US12009369B2/en
Publication of WO2022227150A1 publication Critical patent/WO2022227150A1/zh
Anticipated expiration legal-status Critical
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/33—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being semiconductor devices, e.g. diodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G09F9/35—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements being liquid crystals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/121—Active-matrix OLED [AMOLED] displays characterised by the geometry or disposition of pixel elements

Definitions

  • the present application relates to the field of display technology, and in particular, to a display panel and a display device.
  • TFT Thin The number of Film Transistor
  • the present application provides a display panel and a display device to alleviate the technical problem of the low aperture ratio of the backplane existing in the existing display products.
  • An embodiment of the present application provides a display panel, which includes a gate scan line extending along a first direction; a data signal line extending along a second direction, and the data signal line and the gate scan line intersect to define a plurality of sub-sections a pixel unit; the sub-pixel unit includes at least one light-transmitting region, each of the light-transmitting regions is provided with at least one driving transistor, and the driving transistor includes a source wiring and a drain wiring; wherein, the driving transistor At least a part of the source wirings of the light-transmitting area are arranged on the boundary of the light-transmitting area and parallel to the extending direction of the data signal lines; the drain wirings are arranged in the light-transmitting area.
  • the drain wiring is parallel to the second direction, and the two drain wirings are coincident with the center line of the light-transmitting region.
  • the source wiring includes two first sub-source wirings disposed on the boundary of the light-transmitting area and parallel to the extending direction of the data signal line, and A second sub-source trace connecting the two first sub-source traces, wherein the two first sub-source traces are symmetrical with respect to the drain trace.
  • the second sub-source wiring is parallel to the first direction, and the second sub-source wiring is separated from two adjacent light-transmitting regions. Boundaries overlap.
  • one of the two first sub-source lines is electrically connected to the adjacent data signal line.
  • the interval between the first sub-source wiring and the adjacent data signal line is less than or equal to 1.5 microns.
  • the source wiring includes a first sub-source wiring and a second sub-source wiring, and the first sub-source wiring is arranged on the transparent
  • the boundary of the optical area is parallel to the extending direction of the data signal line, one end of the second sub-source line is connected to the first sub-source line, and the other end of the second sub-source line is connected. One end is connected to the data signal line away from the first sub-source wiring.
  • the line width of the source wiring and/or the drain wiring is greater than or equal to 1.5 ⁇ m.
  • the driving transistor further includes a gate electrode disposed in the same layer as the gate scanning line and connected to each other, and the gate electrode corresponds to the light-transmitting region.
  • the material of the gate electrode includes indium tin oxide.
  • the driving transistor further includes an active layer disposed opposite to the gate.
  • the active layer includes a channel region and a doped region, and a portion of the active layer corresponding to the channel region and the gate overlap in a vertical direction It is provided that a portion of the active layer corresponding to the doped region is connected to the source wire and the drain wire.
  • the material of the active layer includes silicon carbide and gallium nitride.
  • Embodiments of the present application further provide a display device, which includes a display panel, and the display panel includes:
  • the sub-pixel unit includes at least one light-transmitting region, each of the light-transmitting regions is provided with at least one driving transistor, and the driving transistor includes a source wire and a drain wire;
  • the source wiring of the driving transistor is arranged on the boundary of the light-transmitting region and is parallel to the extending direction of the data signal line; the drain wiring is arranged in the light-transmitting region.
  • the drain wiring is parallel to the second direction, and the drain wiring is coincident with the center line of the light-transmitting region.
  • the source line includes two first sub-source lines disposed on the boundary of the light-transmitting area and parallel to the extending direction of the data signal line, and A second sub-source trace connecting the two first sub-source traces, wherein the two first sub-source traces are symmetrical with respect to the drain trace.
  • the second sub-source wiring is parallel to the first direction, and the second sub-source wiring is separated from two adjacent light-transmitting regions. Boundaries overlap.
  • one of the two first sub-source wirings is electrically connected to the adjacent data signal line.
  • the interval between the first sub-source wiring and the adjacent data signal line is less than or equal to 1.5 microns.
  • the source wiring includes a first sub-source wiring and a second sub-source wiring, and the first sub-source wiring is disposed on the transparent
  • the boundary of the optical area is parallel to the extending direction of the data signal line, one end of the second sub-source line is connected to the first sub-source line, and the other end of the second sub-source line is connected. One end is connected to the data signal line away from the first sub-source wiring.
  • the source wirings of the driving transistors in the sub-pixel units in the display panel and the display device provided by the present application include two first sub-source wirings arranged in the boundary area of the sub-pixel unit and parallel to the second direction and two first sub-source wirings parallel to the second direction.
  • the second sub-source wiring is arranged in one direction, and the two first sub-source wirings are connected through the second sub-source wiring; the drain wiring of the driving transistor is arranged in the light-transmitting area of the sub-pixel unit, so that the The entire driving transistor is designed in a harpoon shape; the boundary area of the sub-pixel unit is not used for display, and the source wiring of the driving transistor is designed in the boundary area, which does not affect the display of the sub-pixel unit, and there is no need to set up a separate driving transistor setting area. Therefore, the area of the light-transmitting area of the pixel unit occupied by the driving transistor is reduced, the area of the light-transmitting area of the pixel unit is increased, and the aperture ratio of the back panel of the display product is improved.
  • FIG. 1 is a schematic top-view structure diagram of a display panel provided by an embodiment of the present application.
  • FIG. 2 is a schematic top-view structure diagram of the sub-pixel unit in FIG. 1 .
  • FIG. 3 is another schematic top-view structure diagram of a sub-pixel unit provided by an embodiment of the present application.
  • FIG. 4 is another schematic top-view structure diagram of a sub-pixel unit provided by an embodiment of the present application.
  • FIG. 5 is a schematic cross-sectional structure diagram of a driving transistor provided by an embodiment of the present application.
  • FIG. 6 is a schematic top-view structure diagram of still another sub-pixel unit according to an embodiment of the present application.
  • FIG. 1 is a schematic top-view structure diagram of a display panel provided by an embodiment of the present application
  • FIG. 2 is a top-view structure schematic diagram of a sub-pixel unit in FIG. 1
  • the display panel 1 includes gate scan lines SL extending along the first direction X and data signal lines DL extending along the second direction Y, the data signal lines DL and the gate scan lines SL are insulated from each other, and The intersection of the data signal line DL and the gate scan line SL defines a plurality of sub-pixel units 100 .
  • At least three sub-pixel units 100 form one pixel unit, for example, the three sub-pixel units 100 are respectively a red sub-pixel, a green sub-pixel, and a blue sub-pixel, and three primary colors of red, green, and blue are used to achieve color. show.
  • the data signal line DL is located above the gate scan line SL, and the data signal line DL and the gate scan line SL are separated by an insulating layer, but the present application is not limited thereto, The present application does not limit the vertical positional relationship between the data signal line DL and the gate scan line SL, and the embodiment of the present application only takes the data signal line DL located above the gate scan line SL as an example for description.
  • the projections of the data signal lines DL and the gate scanning lines SL in the vertical direction are arranged at a certain angle, and correspondingly, the first direction X and the second direction Y are also formed at a certain angle.
  • the first direction X is a horizontal direction
  • the second direction Y is a vertical direction.
  • the angle between the first direction X and the second direction Y is 90 degrees, which can simplify The manufacturing process of the display panel 1 .
  • the intersection of the data signal line DL and the gate scan line SL defines a plurality of sub-pixel units 100, the sub-pixel unit 100 includes at least one light-transmitting area LD, and each of the light-transmitting areas LD is provided with at least one driver
  • the transistor 10 includes a source wire 11 and a drain wire 12 . At least part of the source wiring 11 of the driving transistor 10 is arranged on the boundary of the light-transmitting area LD and is parallel to the extending direction of the data signal line DL; the drain wiring 12 is arranged in the light-transmitting area within LD.
  • the embodiment of the present application will take the sub-pixel unit 100 including two light-transmitting regions LD as an example, and each of the light-transmitting regions LD is provided with one of the driving transistors 10 as an example:
  • the source wirings 11 of the driving transistors 10 in the two light-transmitting regions LD are integrally provided.
  • the source wiring 11 includes two first sub-source wirings 111 arranged on the boundary of the light-transmitting area LD and parallel to the second direction Y, and a second sub-source wiring 111 arranged parallel to the first direction X.
  • Two sub-source wirings 112 , and the two first sub-source wirings 111 are connected through the second sub-source wiring 112 .
  • the two first sub-source traces 111 are disposed on the border of the light-transmitting area LD.
  • Signal shielding lines are usually disposed on the border of the light-transmitting area LD, so the border area is not used for display. Arranging the first sub-source wiring 111 in the boundary area does not affect the display of the sub-pixel unit 100 .
  • the two first sub-source wirings 111 are parallel to each other, and are respectively close to the corresponding data signal lines DL, and the corresponding data signal lines DL refer to the first sub-source wirings
  • the adjacent data signal lines DL 111 are the data signal lines DL closest to each of the first sub-source lines 111 .
  • the size of the interval is related to the adopted process conditions. Considering the process capability and the coupling between different signals, the interval distance It may be around 1.5 microns, optionally the separation distance is less than or equal to 1.5 microns.
  • the separation distance When the separation distance is small, the pixel space occupied by the first sub-source wiring 111 and the data signal line DL can be reduced, thereby increasing the area of the light-transmitting area of the sub-pixel unit 100 .
  • the separation distance cannot be too small, for example, the two first sub-source wirings 111 and the corresponding The spacing distances between the data signal lines DL are all about 1.5 microns.
  • the driving transistor 10 includes the two first sub-source wirings 111 , and one of the two first sub-source wirings 111 is connected to the adjacent data signal line DL is electrically connected, and the other first sub-source wiring 111 is not electrically connected to its adjacent data signal line DL.
  • the disconnected first sub-source wiring 111 and the adjacent data signal line DL When the separation distance between them is short, signal coupling may occur.
  • the data signal line DL that provides the driving signal to the driving transistor 10 is electrically connected to the data signal line DL.
  • the first sub-source wiring 111 and the second sub-source wiring 112 transmit the driving signal to the other first sub-source wiring 111, and provide the driving transistor 10 with the data signal of the driving signal.
  • the driving signal provided by the line DL and the adjacent data signal line DL may be different, and the signal lines of different signals may be coupled when the distance is close, so that the disconnected first sub-source wiring 111 and Coupling may occur between adjacent data signal lines DL.
  • FIG. 3 is another schematic top-view structure diagram of a sub-pixel unit provided by an embodiment of the present application.
  • the two first sub-source lines 111 of the sub-pixel unit 101 and the corresponding data signal lines DL are connected between The separation distance can be different.
  • the spacing distance L1 between the first sub-source wiring 111 and the data signal line DL that are electrically connected to each other is smaller than the distance L1 between the first sub-source wiring 111 and the data signal line DL that are not electrically connected to each other The separation distance L2 between them.
  • the distance L1 between the first sub-source wiring 111 that is electrically connected to each other and the data signal line DL is less than 1.5 microns, and the first sub-source wiring 111 that is not electrically connected to each other is The separation distance L2 from the data signal line DL is greater than 1.5 microns.
  • the two first sub-source traces 111 and the second sub-source traces 112 form a mouth-shaped structure with an opening at one end, and the drain traces 12 are arranged in the opening, so that all The driving transistor 10 is designed in a harpoon shape as a whole.
  • the second sub-source wiring 112 is arranged parallel to the first direction X, that is, the second sub-source wiring 112 is arranged parallel to the gate scan line SL.
  • the second sub-source wiring 112 overlaps with the boundary line A of the two adjacent light-transmitting regions LD, and the areas of the two adjacent light-transmitting regions LD may be equal or unequal.
  • the two light-transmitting regions LD are symmetrical with respect to the second sub-source wiring 112 .
  • the boundary line A of the two light-transmitting regions LD refers to an area where the two light-transmitting regions LD are bounded, and is not a line that actually exists.
  • FIG. 4 is another schematic top-view structure diagram of a sub-pixel unit provided by an embodiment of the present application.
  • the second sub-source wiring 112 of the sub-pixel unit 102 is disposed at another boundary of the light-transmitting area LD, and the other boundary refers to the boundary formed by the gate scanning line SL, as described above
  • the second sub-source wiring 112 is close to the gate scan line SL.
  • the projections of the second sub-source wiring 112 and the gate scan line SL in the vertical direction at least partially overlap, so that when the boundary area also needs to be set with shielded signal lines that cannot be used for display, Disposing the second sub-source wiring 112 in this area can further reduce the pixel space occupied by the driving transistor 10 .
  • the drain trace 12 is disposed in the opening formed by the source trace 11, the drain trace 12 is parallel to the second direction Y, and the drain trace 12 is parallel to the second direction Y.
  • the pole line 12 is coincident with the center line B of the light-transmitting area LD, so when the distance between the two first sub-source lines 111 and the adjacent data signal lines DL is the same, the two The first sub-source traces 111 are symmetrical with respect to the drain traces 12 .
  • the center line B of the light-transmitting area LD refers to a virtual line that divides the light-transmitting area LD into two halves parallel to the second direction Y.
  • the pixel structure in each light-transmitting area LD is It will be divided into multiple domains.
  • the pixel structure can be divided into two domains by a main electrode. The two domains are symmetrical about the main electrode, and the display effect of the area corresponding to the main electrode is generally not good. Dark lines, etc., the drain wiring 12 is arranged in the area corresponding to the main electrode, which can reduce the influence on the display effect of the display product.
  • the present application is not limited to this, and the drain wiring 12 of the present application may also be arranged at a certain angle with the second direction Y or the drain wiring 12 may be parallel to the second direction Y , but not between the two first sub-source traces 111 .
  • the line widths of the source traces 11 and the drain traces 12 are both equal to the trace widths of the data signal lines DL, which can simplify the manufacturing process.
  • the line widths of the source wiring 11, the drain wiring 12 and the data signal line DL can be set at 1.5 About micrometers, optionally, the line widths thereof are all greater than or equal to 1.5 micrometers.
  • the present application is not limited thereto, and the line widths of the source wiring 11 , the drain wiring 12 , and the data signal line DL in the embodiment of the present application may also be unequal.
  • the wiring connected to the data signal line DL in the present application is not limited to the source wiring, and the wiring connected to the data signal line DL may also be a drain wiring. In this application, only the source wiring is used.
  • the wiring 11 is connected to the data signal line DL as a schematic illustration. Because the polarity of the source wiring 11 and the drain wiring 12 is related to the high and low potential of the voltage, it has nothing to do with whether it is connected to the data signal line DL. When the end connected to the data signal line DL is at a high potential, it is the drain. The wiring, when one end connected to the data signal line DL is at a low potential, is the source wiring.
  • the other structures of the driving transistor 10, such as gate, active layer, etc., will be described below.
  • FIG. 5 is a schematic cross-sectional structure diagram of a driving transistor provided by an embodiment of the present application.
  • the driving transistor 10 further includes a gate electrode 13 disposed in the same layer as the gate scan line SL and connected to each other, and the gate electrode 13 corresponds to the light-transmitting region LD.
  • the gate 13 is connected to the corresponding gate scan line SL.
  • the gate 13 and the corresponding gate scan line SL are integrally provided.
  • the material of the gate 13 includes transparent conductive materials such as indium tin oxide (Indium Tin Oxide, ITO).
  • the gate 13 corresponds to the light-transmitting area LD, and is made of a transparent conductive material, which does not affect the light-transmitting property of the light-transmitting area LD, that is, does not occupy the area of the light-transmitting area of the sub-pixel unit 100 . .
  • the driving transistor 10 further includes an active layer 14, and the active layer 14 is located under the gate 13, but the present application is not limited to this.
  • the active layer 14 may also be located above the gate 13 , and the present application takes the active layer 14 located below the gate 13 as an example for illustration.
  • the active layer 14 includes a channel region 141 and a doping region. The portion of the active layer 14 corresponding to the channel region 141 and the gate 13 are vertically overlapped. The portion of the layer 14 corresponding to the doped region is connected to the source wiring 11 and the drain wiring 12 .
  • the channel region 141 of the active layer 14 is disposed opposite to the gate electrode 13 .
  • the coverage area of the gate electrode 13 may also be slightly larger than the coverage area of the channel region 141 .
  • the doped regions include source doped regions 142 and drain doped regions 143 located on both sides of the channel region 141 .
  • the portion of the source trace 11 connected to the source doped region 142 forms the source electrode 113 of the driving transistor 10
  • the portion of the drain trace 12 connected to the drain doped region 143 forms The drain 123 of the driving transistor 10 .
  • the material of the active layer 14 includes wide bandgap semiconductor materials such as silicon carbide (SiC) and gallium nitride (GaN).
  • Wide-bandgap semiconductor materials such as silicon carbide and gallium nitride have light transmittance and are not affected by visible light irradiation, so the channel region 141 corresponding to the active layer 14 does not need to be provided with a light shielding layer, so the active layer 14 The light transmittance of the light-transmitting region LD is also not affected.
  • the driving transistor 10 is disposed on the first substrate 20, and the layer where the data signal line DL of the driving transistor 10 is located, the layer where the gate electrode 13 is located, and the layer where the active layer 14 is located are also Insulating layers such as the gate insulating layer 15, the interlayer insulating layer 16, and the like are provided.
  • the first substrate 20 may be a rigid substrate or a flexible substrate; when the first substrate 20 is a rigid substrate, it may include a rigid substrate such as a glass substrate; when the first substrate 20 is a flexible substrate, it may include a poly Flexible substrates such as polyimide (PI) films and ultra-thin glass films.
  • PI polyimide
  • a buffer layer 30 is further disposed between the first substrate 20 and the driving transistor 10, and the buffer layer 30 can prevent unwanted impurities or contaminants (such as moisture, oxygen, etc.) from The first substrate 20 diffuses into devices that may be damaged by these impurities or contaminants, while also providing a flat top surface.
  • the active layer 14 of the driving transistor 10 is disposed on the buffer layer 30 , the gate insulating layer 15 covers the active layer 14 and the buffer layer 30 , the gate 13 and the
  • the gate scanning line SL is disposed in the same layer, and the gate electrode 13 and the gate scanning line SL are both located on the gate insulating layer 15 , wherein the gate electrode 13 and the channel of the active layer 14
  • the area 141 is arranged oppositely.
  • the interlayer insulating layer 16 covers the gate electrode 13 and the gate scan line SL, the data signal line DL, the source electrode 113 and the drain electrode 123 are arranged in the same layer, and the data The signal line DL is located on the interlayer insulating layer 16 , and the source electrode 113 and the drain electrode 123 are connected to the active layer through the via holes of the interlayer insulating layer 16 and the gate insulating layer 15 14 doped regions.
  • the "same layer arrangement" in this application means that in the preparation process, the film layers formed of the same material are patterned to obtain at least two different features, then the at least two different features are the same as Layer settings.
  • the gate electrode 13 and the gate scan line SL in this embodiment are obtained by patterning the same conductive film layer, and the gate electrode 13 and the gate scan line SL are provided in the same layer.
  • a planarization layer 17 may be further provided on the side of the driving transistor 10 away from the first substrate 20 , and the planarization layer 17 covers the data signal line DL, the source electrode 113 and the drain electrode. pole 123 etc. to provide a flat top surface.
  • the driving transistor 10 of the sub-pixel unit 100 is designed in a harpoon shape, so that at least part of the source wiring 11 of the driving transistor 10 is arranged in the boundary area of the sub-pixel unit 100 and parallel to the data signal In the extending direction of the line DL, the drain wiring 12 is disposed in the light-transmitting area LD of the sub-pixel unit 100 and coincides with the center line B of the light-transmitting area LD.
  • the boundary area of the sub-pixel unit 100 is not used for display, and the source wiring 11 of the driving transistor 10 is designed in the boundary area, which does not affect the display of the sub-pixel unit 100, and there is no need to set up a separate driving transistor setting area, so that the driving transistor
  • the area of the light-transmitting area occupied by the sub-pixel unit 100 is reduced, the area of the light-transmitting area of the sub-pixel unit 100 is increased, and the aperture ratio of the back panel of the display product is further improved.
  • the source wiring 11 of the driving transistor 10 in the sub-pixel unit 103 includes a first sub-source wiring 111 and a second sub-source wiring 112.
  • the first sub-source wiring 112 The source wiring 111 is disposed on the boundary of the light-transmitting area LD and is parallel to the extending direction of the data signal line DL, and one end of the second sub-source wiring 112 is connected to the first sub-source wiring 111 is connected, and the other end of the second sub-source wiring 112 is connected to the data signal line DL away from the first sub-source wiring 111 .
  • the data signal line DL far away from the first sub-source line 111 refers to the data signal line DL located at the boundary of the light-transmitting area LD and far from the first sub-source line 111 .
  • the second sub-source wiring 112 connects the data signal line DL and the first sub-source wiring 111, that is, the first sub-source wiring 111 passes through the second sub-source wiring 111.
  • the source wiring 112 is connected to the data signal line DL.
  • the source wiring 11 includes a first sub-source wiring 111 and a second sub-source wiring 112, so that one less first sub-source wiring 111 can be provided, which can further reduce the driving
  • the pixel space occupied by the transistor 10 increases the area of the light-transmitting area of the sub-pixel unit 100, thereby increasing the aperture ratio of the backplane of the display product.
  • the display panel of the present application includes a liquid crystal display panel, an OLED display panel, etc.
  • the liquid crystal display panel includes a pixel electrode disposed on a driving transistor, and the pixel electrode The electrode is connected to the source or drain of the driving transistor, and the pixel electrode and the driving transistor are disposed on the first substrate together to form an array substrate of the liquid crystal display panel.
  • the liquid crystal display panel further includes a color filter substrate disposed opposite to the array substrate, and liquid crystal molecules disposed between the array substrate and the color filter substrate.
  • the drain wiring of the driving transistor is arranged on In the light-transmitting area of the sub-pixel unit, correspondingly, the gate electrode and the active layer of the driving transistor are also arranged corresponding to the light-transmitting area, and the gate electrode and the active layer are made of light-transmitting materials.
  • the OLED display panel adopts bottom emission
  • the OLED display panel includes a light-emitting functional layer provided on the driving transistor and an encapsulation provided on the light-emitting functional layer Floor.
  • the light-emitting functional layer includes a pixel electrode, a pixel definition layer, a light-emitting material layer, and a cathode layer.
  • the pixel electrode is connected to the source electrode or the drain electrode of the driving transistor, the pixel defining layer covers the pixel electrode and the driving transistor, and the pixel defining layer is patterned to form a pixel opening, and the pixel opening is formed on the pixel defining layer.
  • the pixel opening exposes a part of the pixel electrode, so as to define an arrangement area of the luminescent material.
  • the luminescent material layer is formed of luminescent material printed in the pixel opening of the pixel definition layer, and the cathode layer covers the luminescent material layer and the pixel definition layer.
  • the light-emitting material layer emits light under the combined action of the pixel electrode and the cathode layer, thereby realizing pixel display of the OLED display panel.
  • the pixel electrode adopts a transparent electrode, for example, the pixel electrode can be made of indium tin oxide (ITO), indium zinc oxide (IZO), ZnO or In 2 O 3 is formed.
  • the cathode layer adopts a reflective electrode, for example, can be formed of metals with low work function such as Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, etc.
  • the light-emitting functional layer may further include a hole injection layer (HIL) and a hole transport layer (HTL) disposed between the light-emitting material layer and the pixel electrode; and a hole-injection layer (HTL) disposed between the light-emitting material Electron injection layer (EIL), electron transport layer (ETL) between the layer and the cathode layer.
  • HIL hole injection layer
  • HTL hole transport layer
  • ETL electron transport layer
  • the encapsulation layer may adopt thin film encapsulation
  • the thin film encapsulation may be a laminated structure or more layers formed by successively stacking three-layer films of the first inorganic encapsulation layer, the organic encapsulation layer, and the second inorganic encapsulation layer.
  • the laminated structure is used for protecting the light-emitting material layer of the light-emitting functional layer to avoid the failure of the light-emitting material layer caused by the invasion of water and oxygen.
  • the drain wiring of the driving transistor is arranged at In the light-transmitting area of the sub-pixel unit, correspondingly, the gate electrode and the active layer of the driving transistor are also arranged corresponding to the light-transmitting area, and the gate electrode and the active layer are made of light-transmitting materials.
  • the driving transistor region instead of arranging an opaque driving transistor region in the sub-pixel unit, the driving transistor region can be placed under the light emitting unit, and a larger pixel opening can be provided, thereby improving the aperture ratio of the OLED display panel.
  • the ability of the driving transistor to transmit light will help to increase the amount of light transmitted to the functional elements under the OLED screen, where the functional elements can be cameras, fingerprint recognition sensors, and the like.
  • An embodiment of the present application further provides a display device, which includes the display panel of one of the foregoing embodiments, a device such as a circuit board bound to the display panel, and a cover plate covering the display panel.
  • the present application provides a display panel and a display device, wherein gate scan lines extending along a first direction and data signal lines extending along a second direction of the display panel intersect to define a plurality of sub-pixel units; At least one drive transistor, the drive transistor includes a source wire and a drain wire; at least part of the source wire of the drive transistor is arranged on the boundary of the light-transmitting area and is parallel to the extension direction of the data signal wire, and the drain wire is arranged on the In the light-transmitting area, the entire driving transistor is designed in a harpoon shape.
  • the boundary area of the sub-pixel unit is not used for display, and the source wiring of the driving transistor is designed in the boundary area, which does not affect the display of the sub-pixel unit, and there is no need to set up a separate driving transistor setting area, so that the driving transistor occupies the sub-pixel unit.
  • the area of the light-transmitting area is reduced, the area of the light-transmitting area of the sub-pixel unit is increased, and the aperture ratio of the back panel of the display product is improved.

Landscapes

  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Mathematical Physics (AREA)
  • Optics & Photonics (AREA)
  • Theoretical Computer Science (AREA)
  • Geometry (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)
  • Liquid Crystal (AREA)

Abstract

本申请提供一种显示面板和显示装置；该显示面板的子像素单元包括至少一个透光区，每个透光区设置有至少一个驱动晶体管，驱动晶体管的至少部分源极走线设置于透光区的边界且平行于数据信号线的延伸方向，漏极走线设置于透光区内，使驱动晶体管占用子像素单元的透光区面积减小，以缓解现有显示产品背板开口率低的问题。

Description

显示面板和显示装置 技术领域
本申请涉及显示技术领域，尤其涉及一种显示面板和显示装置。
 背景技术
随着显示技术的不断发展，新型显示产品对显示技术的要求越来越高，特别是在大尺寸8K等高端显示产品中，分辨率越做越高，像素（pixel）的数量随之增多且像素的尺寸越做越小，而像素内的驱动晶体管（Thin Film Transistor，TFT）数量也随之增多。目前传统的TFT设计，需在像素内留出特定的TFT区来制备TFT，该TFT区不透光，如此设计随着显示产品分辨率的不断提升，TFT的数量越来越多，势必会导致TFT在背板上占的空间越来越大，造成背板开口率降低，满足不了高分辨率显示的需求。
因此，现有显示产品存在的背板开口率低的技术问题需要解决。
 技术问题
本申请提供一种显示面板和显示装置，以缓解现有显示产品存在的背板开口率低的技术问题。
 技术解决方案
为解决上述问题，本申请提供的技术方案如下：
本申请实施例提供一种显示面板，其包括沿第一方向延伸的栅极扫描线；沿第二方向延伸的数据信号线，且所述数据信号线与所述栅极扫描线交叉限定多个子像素单元；所述子像素单元包括至少一个透光区，每个所述透光区设置有至少一个驱动晶体管，所述驱动晶体管包括源极走线和漏极走线；其中，所述驱动晶体管的至少部分源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向；所述漏极走线设置于所述透光区内。
在本申请实施例提供的显示面板中，所述漏极走线与所述第二方向平行，且两条所述漏极走线与所述透光区的中心线重合。
在本申请实施例提供的显示面板中，所述源极走线包括设置于所述透光区的边界且平行于所述数据信号线的延伸方向的两条第一子源极走线，以及连接两条所述第一子源极走线的第二子源极走线，其中两条所述第一子源极走线关于所述漏极走线对称。
在本申请实施例提供的显示面板中，所述第二子源极走线与所述第一方向平行，且所述第二子源极走线与相邻两个所述透光区的分界线重合。
在本申请实施例提供的显示面板中，两条所述第一子源极走线的其中之一与相邻的所述数据信号线电连接。
在本申请实施例提供的显示面板中，所述第一子源极走线与相邻的所述数据信号线之间的间隔小于或等于1.5微米。
在本申请实施例提供的显示面板中，所述源极走线包括一条第一子源极走线和一条第二子源极走线，所述第一子源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向，所述第二子源极走线的一端与所述第一子源极走线连接，所述第二子源极走线的另一端与远离所述第一子源极走线的所述数据信号线连接。
在本申请实施例提供的显示面板中，所述源极走线和/或所述漏极走线的线宽大于或等于1.5微米。
在本申请实施例提供的显示面板中，所述驱动晶体管还包括与所述栅极扫描线同层设置且彼此连接的栅极，所述栅极对应于所述透光区。
在本申请实施例提供的显示面板中，所述栅极的材料包括氧化铟锡。
在本申请实施例提供的显示面板中，所述驱动晶体管还包括与所述栅极相对设置的有源层。
在本申请实施例提供的显示面板中，所述有源层包括沟道区和掺杂区，所述有源层与所述沟道区对应的部分与所述栅极在竖直方向上重叠设置，所述有源层与所述掺杂区对应的部分与所述源极走线和所述漏极走线连接。
在本申请实施例提供的显示面板中，所述有源层的材料包括碳化硅、氮化镓。
本申请实施例还提供一种显示装置，其包括显示面板，所述显示面板包括：
沿第一方向延伸的栅极扫描线；
沿第二方向延伸的数据信号线，且所述数据信号线与所述栅极扫描线交叉限定多个子像素单元；
所述子像素单元包括至少一个透光区，每个所述透光区设置有至少一个驱动晶体管，所述驱动晶体管包括源极走线和漏极走线；
其中，所述驱动晶体管的至少部分源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向；所述漏极走线设置于所述透光区内。
在本申请实施例提供的显示装置中，所述漏极走线与所述第二方向平行，且所述漏极走线与所述透光区的中心线重合。
在本申请实施例提供的显示装置中，所述源极走线包括设置于所述透光区的边界且平行于所述数据信号线的延伸方向的两条第一子源极走线，以及连接两条所述第一子源极走线的第二子源极走线，其中两条所述第一子源极走线关于所述漏极走线对称。
在本申请实施例提供的显示装置中，所述第二子源极走线与所述第一方向平行，且所述第二子源极走线与相邻两个所述透光区的分界线重合。
在本申请实施例提供的显示装置中，两条所述第一子源极走线的其中之一与相邻的所述数据信号线电连接。
在本申请实施例提供的显示装置中，所述第一子源极走线与相邻的所述数据信号线之间的间隔小于或等于1.5微米。
在本申请实施例提供的显示装置中，所述源极走线包括一条第一子源极走线和一条第二子源极走线，所述第一子源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向，所述第二子源极走线的一端与所述第一子源极走线连接，所述第二子源极走线的另一端与远离所述第一子源极走线的所述数据信号线连接。
 有益效果
本申请提供的显示面板和显示装置中子像素单元内的驱动晶体管的源极走线包括设置于子像素单元边界区域且平行于第二方向的两条第一子源极走线和平行于第一方向设置的第二子源极走线，两条第一子源极走线通过第二子源极走线连接；驱动晶体管的漏极走线设置于子像素单元的透光区内，使整个驱动晶体管呈鱼叉状设计；子像素单元的边界区域不用于显示，把驱动晶体管的源极走线设计在边界区域，不影响子像素单元的显示，而且无需再设置单独的驱动晶体管设置区，使驱动晶体管占用像素单元的透光区的面积减小，增大了像素单元透光区的面积，进而提高了显示产品的背板开口率。
 附图说明
为了更清楚地说明实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单介绍，显而易见地，下面描述中的附图仅仅是发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的显示面板的一种俯视结构示意图。
图2为图1中子像素单元的一种俯视结构示意图。
图3为本申请实施例提供的子像素单元的又一种俯视结构示意图。
图4为本申请实施例提供的子像素单元的另一种俯视结构示意图。
图5为本申请实施例提供的驱动晶体管的剖面结构示意图。
图6为本申请实施例提供的子像素单元的再一种俯视结构示意图。
 本发明的实施方式
以下各实施例的说明是参考附加的图示，用以例示本申请可用以实施的特定实施例。本申请所提到的方向用语，例如[上]、[下]、[前]、[后]、[左]、[右]、[内]、[外]、[侧面]等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本申请，而非用以限制本申请。在图中，结构相似的单元是用以相同标号表示。在附图中，为了清晰理解和便于描述，夸大了一些层和区域的厚度。即附图中示出的每个组件的尺寸和厚度是任意示出的，但是本申请不限于此。
请结合参照图1和图2，图1为本申请实施例提供的显示面板的一种俯视结构示意图，图2为图1中子像素单元的一种俯视结构示意图。所述显示面板1包括沿第一方向X延伸的栅极扫描线SL以及沿第二方向Y延伸的数据信号线DL，所述数据信号线DL与所述栅极扫描线SL彼此绝缘，且所述数据信号线DL与所述栅极扫描线SL交叉限定多个子像素单元100。可选地，至少三个子像素单元100组成一个像素单元，比如所述三个子像素单元100分别为红色子像度、绿色子像素、蓝色子像素，采用红、绿、蓝三基色以实现彩色显示。
可选地，所述数据信号线DL位于所述栅极扫描线SL上方，且所述数据信号线DL和所述栅极扫描线SL之间通过绝缘层隔开，但本申请不限于此，本申请不限制所述数据信号线DL和所述栅极扫描线SL的上下位置关系，本申请实施例仅以所述数据信号线DL位于所述栅极扫描线SL上方为例说明。
进一步地，所述数据信号线DL和所述栅极扫描线SL在竖直方向上的投影呈一定夹角设置，相应地，所述第一方向X和所述第二方向Y也呈一定夹角。可选地，所述第一方向X为水平方向，所述第二方向Y为竖直方向，此时所述第一方向X和所述第二方向Y的夹角为90度，如此能够简化所述显示面板1的制备工艺。
所述数据信号线DL和所述栅极扫描线SL交叉限定出多个子像素单元100，所述子像素单元100包括至少一个透光区LD，每个所述透光区LD设置有至少一个驱动晶体管10，所述驱动晶体管10包括源极走线11和漏极走线12。所述驱动晶体管10的至少部分源极走线11设置于所述透光区LD的边界且平行于所述数据信号线DL的延伸方向；所述漏极走线12设置于所述透光区LD内。
本申请实施例将以所述子像素单元100包括两个透光区LD，每个所述透光区LD设置一个所述驱动晶体管10为例说明：
具体地，两个所述透光区LD内的驱动晶体管10的源极走线11一体式设置。所述源极走线11包括设置于所述透光区LD的边界且平行于所述第二方向Y的两条第一子源极走线111和平行于所述第一方向X设置的第二子源极走线112，两条所述第一子源极走线111通过所述第二子源极走线112连接。两条所述第一子源极走线111设置于所述透光区LD的边界，所述透光区LD的边界通常设置有信号屏蔽线，故该边界区域不用于显示。把所述第一子源极走线111设置在该边界区域，不影响子像素单元100的显示。
进一步地，两条所述第一子源极走线111彼此平行，且分别靠近对应的所述数据信号线DL，对应的所述数据信号线DL是指与所述第一子源极走线111相邻的数据信号线DL，也即距离每一所述第一子源极走线111最近的数据信号线DL。所述第一子源极走线111与对应的所述数据信号线DL之间具有间隔，该间隔距离的大小与采用工艺条件有关，考虑到制程能力和不同信号之间的耦合，该间隔距离可以在1.5微米左右，可选地，该间隔距离小于或等于1.5微米。该间隔距离较小时，能够减小所述第一子源极走线111和所述数据信号线DL占用的像素空间，进而增大子像素单元100的透光区面积。但为避免所述第一子源极走线111与相邻的所述数据信号线DL之间的耦合，该间隔距离不能太小，比如两条所述第一子源极走线111与对应的所述数据信号线DL之间的间隔距离均在1.5微米左右。
需要说明的是，所述驱动晶体管10包括两条所述第一子源极走线111，两条所述第一子源极走线111的其中之一与相邻的所述数据信号线DL电连接，而另外一条所述第一子源极走线111不与其相邻的数据信号线DL电连接，当互不连接的第一子源极走线111和相邻的数据信号线DL之间的间隔距离较近时，可能会产生信号耦合。
因为两条所述第一子源极走线111之间通过所述第二子源极走线112电连接，给所述驱动晶体管10提供驱动信号的数据信号线DL通过与其电连接的所述第一子源极走线111以及所述第二子源极走线112把驱动信号传递给另外一条所述第一子源极走线111，而给所述驱动晶体管10提供驱动信号的数据信号线DL与与其相邻的数据信号线DL提供的驱动信号可能不同，不同信号的信号线之间在距离较近时可能产生耦合，如此会使得互不连接的第一子源极走线111和相邻的数据信号线DL之间可能产生耦合。
可选地，请参照图3，图3为本申请实施例提供的子像素单元的又一种俯视结构示意图。为了既不占用过多的像素空间，又可以避免信号线之间产生耦合，所述子像素单元101的两条所述第一子源极走线111与对应的所述数据信号线DL之间的间隔距离可以不同。相互电连接的所述第一子源极走线111和所述数据信号线DL之间的间隔距离L1小于互不电连接的所述第一子源极走线111和所述数据信号线DL之间的间隔距离L2。可选地，相互电连接的所述第一子源极走线111和所述数据信号线DL之间的间隔距离L1小于1.5微米，互不电连接的所述第一子源极走线111和所述数据信号线DL之间的间隔距离L2大于1.5微米。
两条所述第一子源极走线111和所述第二子源极走线112一块围成一个一端开口的口字型结构，所述漏极走线12设置在该开口内，使所述驱动晶体管10整体呈鱼叉状设计。其中所述第二子源极走线112平行于所述第一方向X设置，也即所述第二子源极走线112平行于所述栅极扫描线SL设置。
具体地，所述第二子源极走线112与相邻两个所述透光区LD的分界线A重合，相邻的两个所述透光区LD的面积可以相等或不等，当两个所述透光区LD的面积相等时，两个所述透光区LD关于所述第二子源极走线112对称。其中两个所述透光区LD的分界线A是指两个所述透光区LD交界的区域，并非实际存在的一条线。
可选地，请参照图4，图4为本申请实施例提供的子像素单元的另一种俯视结构示意图。所述子像素单元102的所述第二子源极走线112设置在所述透光区LD的另一边界，另一边界是指由所述栅极扫描线SL形成的边界，如此所述第二子源极走线112靠近所述栅极扫描线SL。
可选地，所述第二子源极走线112和所述栅极扫描线SL在竖直方向上的投影至少部分重叠，如此当该边界区域也需设置屏蔽信号线不能用于显示时，把所述第二子源极走线112设置在该区域能够进一步减小驱动晶体管10占用的像素空间。
继续结合参照图1和图2，所述漏极走线12设置在所述源极走线11形成的开口内，所述漏极走线12与所述第二方向Y平行，且所述漏极走线12与所述透光区LD的中心线B重合，如此当两条所述第一子源极走线111与其相邻的所述数据信号线DL之间的间隔距离相同时，两条所述第一子源极走线111关于所述漏极走线12对称。
需要说明的是，所述透光区LD的中心线B是指沿平行于第二方向Y把透光区LD均分成两半的虚拟线，通常每个所述透光区LD内的像素结构会分成多个畴区（domain），比如可以通过一条主干电极把像素结构均分成两个畴区，两个畴区关于主干电极对称，而主干电极对应的区域显示效果一般不好，可能会出现暗纹等，把所述漏极走线12对应该主干电极的区域设置，能够降低对显示产品的显示效果的影响。
当然地，本申请不限于此，本申请的所述漏极走线12也可以是与所述第二方向Y呈一定夹角设置或者所述漏极走线12与所述第二方向Y平行，但不位于两条所述第一子源极走线111中间。
可选地，所述源极走线11和所述漏极走线12的线宽均等于所述数据信号线DL的线宽，如此能够简化制备工艺。同时为了避免线宽过小导致断线以及线宽过大导致遮光面积增大，所述源极走线11、所述漏极走线12以及所述数据信号线DL的线宽可以设置在1.5微米左右，可选地，其线宽均大于或等于1.5微米。当然地，本申请不限于此，本申请实施例的所述源极走线11、所述漏极走线12以及所述数据信号线DL的线宽也可以不相等。
需要说明的是，本申请与所述数据信号线DL连接的走线不限于源极走线，与所述数据信号线DL连接的走线也可以为漏极走线，本申请仅以源极走线11与数据信号线DL连接作为示意性说明。因为源极走线11与漏极走线12的极性与电压的高低电位有关，与是否和数据信号线DL相连无关，当与数据信号线DL相连的一端为高电位时，即为漏极走线，当与数据信号线DL相连的一端为低电位时，即为源极走线。
下面将阐述所述驱动晶体管10的其他结构，如栅极、有源层等。
请结合参照图2和图5，图5为本申请实施例提供的驱动晶体管的剖面结构示意图。具体地，所述驱动晶体管10还包括与所述栅极扫描线SL同层设置且彼此连接的栅极13，且所述栅极13对应于所述透光区LD。所述栅极13与对应的所述栅极扫描线SL连接，可选地，所述栅极13与对应的所述栅极扫描线SL一体式设置。
可选地，所述栅极13的材料包括氧化铟锡（Indium Tin Oxide，ITO）等透明导电材料。所述栅极13对应于所述透光区LD，且采用透明导电材料制备，不影响所述透光区LD的透光性，也即不会占用所述子像素单元100的透光区面积。
进一步地，所述驱动晶体管10还包括有源层14，所述有源层14位于所述栅极13下方，但本申请不限于此，本申请在采用底栅结构时，所述有源层14也可以位于所述栅极13的上方，本申请以所述有源层14位于所述栅极13下方为例说明。所述有源层14包括沟道区141和掺杂区，所述有源层14与所述沟道区141对应的部分与所述栅极13在竖直方向上重叠设置，所述有源层14与所述掺杂区对应的部分与所述源极走线11和所述漏极走线12连接。
具体地，所述有源层14的沟道区141与所述栅极13相对设置，当然地，所述栅极13的覆盖面积也可以稍大于所述沟道区141的覆盖面积。所述掺杂区包括位于所述沟道区141两侧的源极掺杂区142和漏极掺杂区143。所述源极走线11与所述源极掺杂区142连接的部分形成所述驱动晶体管10的源极113，所述漏极走线12与所述漏极掺杂区143连接的部分形成所述驱动晶体管10的漏极123。
可选地，所述有源层14的材料包括碳化硅（SiC）、氮化镓（GaN）等宽禁带半导体材料。碳化硅、氮化镓等宽禁带半导体材料具有透光性，且不受可见光照射的影响，故对应所述有源层14的沟道区141无需设置遮光层，如此所述有源层14也不会影响所述透光区LD的透光性。
当然地，继续参照图5，所述驱动晶体管10设置在第一基板20上，且所述驱动晶体管10的数据信号线DL所在层、栅极13所在层、有源层14所在层之间还设置有绝缘层，比如栅极绝缘层15、层间绝缘层16等。
具体地，所述第一基板20可以为刚性基板或柔性基板；所述第一基板20为刚性基板时，可包括玻璃基板等硬性基板；所述第一基板20为柔性基板时，可包括聚酰亚胺（Polyimide，PI）薄膜、超薄玻璃薄膜等柔性基板。
可选地，所述第一基板20与所述驱动晶体管10之间还设置有缓冲层30，所述缓冲层30可以防止不期望的杂质或污染物（例如湿气、氧气等）从所述第一基板20扩散至可能因这些杂质或污染物而受损的器件中，同时还可以提供平坦的顶表面。
所述驱动晶体管10的有源层14设置于所述缓冲层30上，所述栅极绝缘层15覆盖在所述有源层14以及所述缓冲层30上，所述栅极13和所述栅极扫描线SL同层设置，且所述栅极13和所述栅极扫描线SL均位于所述栅极绝缘层15上，其中所述栅极13与所述有源层14的沟道区141相对设置。
所述层间绝缘层16覆盖在所述栅极13和所述栅极扫描线SL上，所述数据信号线DL、所述源极113、所述漏极123同层设置，且所述数据信号线DL位于所述层间绝缘层16上，所述源极113、所述漏极123通过所述层间绝缘层16和所述栅极绝缘层15的过孔连接到所述有源层14的掺杂区。
需要说明的是，本申请中的“同层设置”是指在制备工艺中，将相同材料形成的膜层进行图案化处理得到至少两个不同的特征，则所述至少两个不同的特征同层设置。比如，本实施例的所述栅极13与所述栅极扫描线SL由同一导电膜层进行图案化处理后得到，则所述栅极13与所述栅极扫描线SL同层设置。
可选地，所述驱动晶体管10远离所述第一基板20的一侧还可设置平坦化层17，所述平坦化层17覆盖所述数据信号线DL、所述源极113、所述漏极123等，以提供平坦的顶表面。
在本实施例中，所述子像素单元100的驱动晶体管10设计成鱼叉状，使驱动晶体管10的至少部分源极走线11设置在子像素单元100的边界区域且平行于所述数据信号线DL的延伸方向，所述漏极走线12设置于子像素单元100的透光区LD内，且与所述透光区LD的中心线B重合。而子像素单元100的边界区域不用于显示，把驱动晶体管10的源极走线11设计在边界区域，不影响子像素单元100的显示，而且无需再设置单独的驱动晶体管设置区，使驱动晶体管10占用子像素单元100的透光区面积减小，增大了子像素单元100透光区面积，进而提高了显示产品的背板开口率。
在一种实施例中，请参照图6，图6为本申请实施例提供的子像素单元的再一种俯视结构示意图。与上述实施例不同的是，所述子像素单元103中驱动晶体管10的源极走线11包括一条第一子源极走线111和一条第二子源极走线112，所述第一子源极走线111设置于所述透光区LD的边界且平行于所述数据信号线DL的延伸方向，所述第二子源极走线112的一端与所述第一子源极走线111连接，所述第二子源极走线112的另一端与远离所述第一子源极走线111的所述数据信号线DL连接。其中远离所述第一子源极走线111的所述数据信号线DL是指位于所述透光区LD边界且距离所述第一子源极走线111较远的所述数据信号线DL。
具体地，所述第二子源极走线112连接所述数据信号线DL和所述第一子源极走线111，也即所述第一子源极走线111通过所述第二子源极走线112所述数据信号线DL连接。
本实施例通过源极走线11包括一条所述第一子源极走线111和一条第二子源极走线112，如此可以少设置一条第一子源极走线111，能够进一步减少驱动晶体管10占用的像素空间，从而增大子像素单元100的透光区面积，进而提高了显示产品的背板开口率。其他说明请参照上述实施例，在此不再赘述。
可选地，本申请的所述显示面板包括液晶显示面板、OLED显示面板等，当所述显示面板为液晶显示面板时，所述液晶显示面板包括设置于驱动晶体管上的像素电极，所述像素电极与所述驱动晶体管的源极或漏极连接，所述像素电极和所述驱动晶体管一块设置在第一基板上，形成液晶显示面板的阵列基板。所述液晶显示面板还包括与所述阵列基板相对设置的彩膜基板，以及设置在所述阵列基板和所述彩膜基板之间的液晶分子。
由于液晶显示面板的所述驱动晶体管的至少部分源极走线设置在子像素单元透光区的边界区域且平行于所述数据信号线的延伸方向，所述驱动晶体管的漏极走线设置在子像素单元的透光区，相对应地，驱动晶体管的栅极、有源层也对应透光区设置，且所述栅极和所述有源层均采用透光材料制备。如此不用单独在子像素单元内设置不透光的驱动晶体管区，使驱动晶体管在子像素单元内占用的透光区面积减小，从而增大了子像素单元的透光区面积，提高了液晶显示面板的开口率。
可选地，当所述显示面板为OLED显示面板时，所述OLED显示面板采用底发射，所述OLED显示面板包括设置于驱动晶体管上的发光功能层以及设置在所述发光功能层上的封装层。
具体地，所述发光功能层包括像素电极、像素定义层、发光材料层、阴极层。所述像素电极与所述驱动晶体管的源极或漏极连接，所述像素定义层覆于所述像素电极以及所述驱动晶体管上，且所述像素定义层图案化形成有像素开口，所述像素开口裸露出部分所述像素电极，以定义出发光材料的设置区域。所述发光材料层是由打印在所述像素定义层的像素开口内的发光材料形成，所述阴极层覆盖所述发光材料层以及所述像素定义层。所述发光材料层在所述像素电极和所述阴极层的共同作用下发光，进而实现OLED显示面板的像素显示。
由于所述OLED显示面板采用底发射，为了提高光线的利用率，所述像素电极采用透明电极，比如所述像素电极可以由氧化铟锡(ITO)、氧化铟锌(IZO)、ZnO或In 2O 3形成。所述阴极层采用反射电极，比如可以由Li、Ca、LiF/Ca、LiF/Al、 Al、Ag、Mg等逸出功低的金属形成。
可选地，所述发光功能层还可包括设置于所述发光材料层与所述像素电极之间的空穴注入层(HIL)、空穴传输层(HTL)；以及设置于所述发光材料层与所述阴极层之间的电子注入层(EIL)、电子传输层(ETL)。
可选地，所述封装层可以采用薄膜封装，所述薄膜封装可以为由第一无机封装层、有机封装层、第二无机封装层三层薄膜依次层叠形成的叠层结构或更多层的叠层结构，用于保护所述发光功能层的发光材料层，避免水氧入侵导致发光材料层失效。
同样地，由于OLED显示面板的所述驱动晶体管的至少部分源极走线设置在子像素单元的边界区域且平行于所述数据信号线的延伸方向，所述驱动晶体管的漏极走线设置在子像素单元的透光区，相对应地，驱动晶体管的栅极、有源层也对应透光区设置，且所述栅极和所述有源层均采用透光材料制备。如此不用单独在子像素单元内设置不透光的驱动晶体管区，可以把驱动晶体管区置于发光单元下面，能够设置更大的像素开口，提高了OLED显示面板的开口率。而且驱动晶体管能够透光将有利于增大透射到OLED屏下功能元件的光线的量，其中功能元件可以为摄像头、指纹识别传感器等。
本申请实施例还提供一种显示装置，其包括前述实施例其中之一的显示面板、绑定于所述显示面板的电路板等器件以及覆盖在所述显示面板上的盖板等。
根据上述实施例可知：
本申请提供一种显示面板和显示装置，该显示面板沿第一方向延伸的栅极扫描线和沿第二方向延伸的数据信号线交叉限定多个子像素单元；子像素单元的透光区设置有至少一个驱动晶体管，驱动晶体管包括源极走线和漏极走线；驱动晶体管的至少部分源极走线设置于透光区的边界且平行于数据信号线的延伸方向，漏极走线设置于透光区内，使整个驱动晶体管呈鱼叉状设计。而子像素单元的边界区域不用于显示，把驱动晶体管的源极走线设计在边界区域，不影响子像素单元的显示，而且无需再设置单独的驱动晶体管设置区，使驱动晶体管占用子像素单元的透光区的面积减小，增大了子像素单元透光区的面积，进而提高了显示产品的背板开口率。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的技术方案及其核心思想；本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例的技术方案的范围。

Claims (20)

  1. 一种显示面板，其包括：
    沿第一方向延伸的栅极扫描线；
    沿第二方向延伸的数据信号线，且所述数据信号线与所述栅极扫描线交叉限定多个子像素单元；
    所述子像素单元包括至少一个透光区，每个所述透光区设置有至少一个驱动晶体管，所述驱动晶体管包括源极走线和漏极走线；
    其中，所述驱动晶体管的至少部分源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向；所述漏极走线设置于所述透光区内。
  2. 根据权利要求1所述的显示面板，其中，所述漏极走线与所述第二方向平行，且所述漏极走线与所述透光区的中心线重合。
  3. 根据权利要求2所述的显示面板，其中，所述源极走线包括设置于所述透光区的边界且平行于所述数据信号线的延伸方向的两条第一子源极走线，以及连接两条所述第一子源极走线的第二子源极走线，其中两条所述第一子源极走线关于所述漏极走线对称。
  4. 根据权利要求3所述的显示面板，其中，所述第二子源极走线与所述第一方向平行，且所述第二子源极走线与相邻两个所述透光区的分界线重合。
  5. 根据权利要求3所述的显示面板，其中，两条所述第一子源极走线的其中之一与相邻的所述数据信号线电连接。
  6. 根据权利要求5所述的显示面板，其中，所述第一子源极走线与相邻的所述数据信号线之间的间隔小于或等于1.5微米。
  7. 根据权利要求2所述的显示面板，其中，所述源极走线包括一条第一子源极走线和一条第二子源极走线，所述第一子源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向，所述第二子源极走线的一端与所述第一子源极走线连接，所述第二子源极走线的另一端与远离所述第一子源极走线的所述数据信号线连接。
  8. 根据权利要求1所述的显示面板，其中，所述源极走线和/或所述漏极走线的线宽大于或等于1.5微米。
  9. 根据权利要求1所述的显示面板，其中，所述驱动晶体管还包括与所述栅极扫描线同层设置且彼此连接的栅极，所述栅极对应于所述透光区。
  10. 根据权利要求9所述的显示面板，其中，所述栅极的材料包括氧化铟锡。
  11. 根据权利要求9所述的显示面板，其中，所述驱动晶体管还包括与所述栅极相对设置的有源层。
  12. 根据权利要求11所述的显示面板，其中，所述有源层包括沟道区和掺杂区，所述有源层与所述沟道区对应的部分与所述栅极在竖直方向上重叠设置，所述有源层与所述掺杂区对应的部分与所述源极走线和所述漏极走线连接。
  13. 根据权利要求12所述的显示面板，其中，所述有源层的材料包括碳化硅、氮化镓。
  14. 一种显示装置，其包括显示面板，所述显示面板包括：
    沿第一方向延伸的栅极扫描线；
    沿第二方向延伸的数据信号线，且所述数据信号线与所述栅极扫描线交叉限定多个子像素单元；
    所述子像素单元包括至少一个透光区，每个所述透光区设置有至少一个驱动晶体管，所述驱动晶体管包括源极走线和漏极走线；
    其中，所述驱动晶体管的至少部分源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向；所述漏极走线设置于所述透光区内。
  15. 根据权利要求14所述的显示装置，其中，所述漏极走线与所述第二方向平行，且所述漏极走线与所述透光区的中心线重合。
  16. 根据权利要求15所述的显示装置，其中，所述源极走线包括设置于所述透光区的边界且平行于所述数据信号线的延伸方向的两条第一子源极走线，以及连接两条所述第一子源极走线的第二子源极走线，其中两条所述第一子源极走线关于所述漏极走线对称。
  17. 根据权利要求16所述的显示装置，其中，所述第二子源极走线与所述第一方向平行，且所述第二子源极走线与相邻两个所述透光区的分界线重合。
  18. 根据权利要求16所述的显示装置，其中，两条所述第一子源极走线的其中之一与相邻的所述数据信号线电连接。
  19. 根据权利要求18所述的显示装置，其中，所述第一子源极走线与相邻的所述数据信号线之间的间隔小于或等于1.5微米。
  20. 根据权利要求14所述的显示装置，其中，所述源极走线包括一条第一子源极走线和一条第二子源极走线，所述第一子源极走线设置于所述透光区的边界且平行于所述数据信号线的延伸方向，所述第二子源极走线的一端与所述第一子源极走线连接，所述第二子源极走线的另一端与远离所述第一子源极走线的所述数据信号线连接。
PCT/CN2021/095452 2021-04-29 2021-05-24 显示面板和显示装置 Ceased WO2022227150A1 (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US17/423,956 US12009369B2 (en) 2021-04-29 2021-05-24 Display panel and display device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202110473830.6A CN113193031B (zh) 2021-04-29 2021-04-29 显示面板和显示装置
CN202110473830.6 2021-04-29

Publications (1)

Publication Number Publication Date
WO2022227150A1 true WO2022227150A1 (zh) 2022-11-03

Family

ID=76980648

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/095452 Ceased WO2022227150A1 (zh) 2021-04-29 2021-05-24 显示面板和显示装置

Country Status (2)

Country Link
CN (1) CN113193031B (zh)
WO (1) WO2022227150A1 (zh)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870284A (zh) * 2005-05-03 2006-11-29 三星电子株式会社 有机薄膜晶体管阵列板及其制造方法
CN101424841A (zh) * 2007-11-02 2009-05-06 上海广电Nec液晶显示器有限公司 液晶显示装置及其制造方法
JP2010243939A (ja) * 2009-04-09 2010-10-28 Hitachi Displays Ltd 液晶表示装置およびその製造方法
CN103137616A (zh) * 2011-11-25 2013-06-05 上海天马微电子有限公司 Tft阵列基板及其形成方法、显示面板
CN103946741A (zh) * 2011-11-18 2014-07-23 夏普株式会社 有源矩阵基板、液晶显示装置以及有源矩阵基板的制造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005223254A (ja) * 2004-02-09 2005-08-18 Sharp Corp 薄膜トランジスタ
JP2006308862A (ja) * 2005-04-28 2006-11-09 Sanyo Electric Co Ltd エレクトロルミネッセンス表示装置
KR101281830B1 (ko) * 2006-09-26 2013-07-03 엘지디스플레이 주식회사 멀티 터치 감지기능을 갖는 액정표시장치와 그 구동방법
KR102327918B1 (ko) * 2015-01-02 2021-11-17 삼성디스플레이 주식회사 투명 디스플레이 장치와 그의 제조 방법
CN104656333A (zh) * 2015-03-18 2015-05-27 深圳市华星光电技术有限公司 Coa型液晶面板的制作方法及coa型液晶面板
KR102626961B1 (ko) * 2016-07-27 2024-01-17 엘지디스플레이 주식회사 하이브리드 타입의 박막 트랜지스터 및 이를 이용한 유기발광 표시장치
KR102654918B1 (ko) * 2018-10-08 2024-04-05 삼성디스플레이 주식회사 표시장치
CN109449182A (zh) * 2018-10-30 2019-03-08 京东方科技集团股份有限公司 显示基板及其制造方法、显示装置
CN111552132A (zh) * 2020-03-31 2020-08-18 浙江大学 一种应用在投影面板上的像素结构及投影面板

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1870284A (zh) * 2005-05-03 2006-11-29 三星电子株式会社 有机薄膜晶体管阵列板及其制造方法
CN101424841A (zh) * 2007-11-02 2009-05-06 上海广电Nec液晶显示器有限公司 液晶显示装置及其制造方法
JP2010243939A (ja) * 2009-04-09 2010-10-28 Hitachi Displays Ltd 液晶表示装置およびその製造方法
CN103946741A (zh) * 2011-11-18 2014-07-23 夏普株式会社 有源矩阵基板、液晶显示装置以及有源矩阵基板的制造方法
CN103137616A (zh) * 2011-11-25 2013-06-05 上海天马微电子有限公司 Tft阵列基板及其形成方法、显示面板

Also Published As

Publication number Publication date
CN113193031A (zh) 2021-07-30
CN113193031B (zh) 2022-10-04

Similar Documents

Publication Publication Date Title
US20240357894A1 (en) Display substrate and manufacturing method thereof
US11271062B2 (en) Double-sided display panel and preparation method thereof
CN113767475B (zh) 柔性显示面板、显示装置及制备方法
KR102313366B1 (ko) 플렉서블 디스플레이 장치와, 이의 제조 방법
WO2022052226A1 (zh) 一种显示面板及显示装置
KR102312557B1 (ko) 유기 발광 표시 장치
CN114039013B (zh) 显示面板及其制备方法、显示装置
WO2021078175A1 (zh) 显示基板及其制备方法、显示面板
CN110164879A (zh) 阵列基板、显示装置
WO2021226879A1 (zh) 显示基板及其制备方法、显示装置
WO2023087367A1 (zh) 显示面板和电子装置
WO2023197373A1 (zh) 显示面板及显示装置
WO2021097798A1 (zh) 显示基板及其制备方法、显示装置
WO2020233698A1 (zh) 显示基板和显示装置
WO2023159511A1 (zh) 显示基板及其制备方法、显示装置
CN114141853A (zh) 一种显示面板、制作方法以及显示装置
CN117460334A (zh) 阵列基板和显示面板
US20250275388A1 (en) Display substrate
CN113113452A (zh) 显示面板及其制备方法
US12009369B2 (en) Display panel and display device
CN115568252A (zh) 显示基板、显示面板和显示装置
WO2023184402A1 (zh) 显示基板及其制作方法、显示面板
WO2022252230A1 (zh) 显示基板和显示装置
CN119300665A (zh) 显示面板和显示装置
WO2022227150A1 (zh) 显示面板和显示装置

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21938621

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21938621

Country of ref document: EP

Kind code of ref document: A1