WO2022226981A1 - 一种可拉伸显示基板及其制备方法、显示装置 - Google Patents

一种可拉伸显示基板及其制备方法、显示装置 Download PDF

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Publication number
WO2022226981A1
WO2022226981A1 PCT/CN2021/091405 CN2021091405W WO2022226981A1 WO 2022226981 A1 WO2022226981 A1 WO 2022226981A1 CN 2021091405 W CN2021091405 W CN 2021091405W WO 2022226981 A1 WO2022226981 A1 WO 2022226981A1
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Prior art keywords
layer
sub
hole
hollow portion
display substrate
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PCT/CN2021/091405
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English (en)
French (fr)
Inventor
汪炳伟
赵佳
王晶
王品凡
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京东方科技集团股份有限公司
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Priority to EP21938455.9A priority Critical patent/EP4203052A4/en
Priority to US17/755,131 priority patent/US20240188351A1/en
Priority to JP2023521911A priority patent/JP2024517525A/ja
Priority to KR1020237012336A priority patent/KR20240004207A/ko
Priority to PCT/CN2021/091405 priority patent/WO2022226981A1/zh
Priority to CN202180001013.9A priority patent/CN115552620A/zh
Publication of WO2022226981A1 publication Critical patent/WO2022226981A1/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K77/00—Constructional details of devices covered by this subclass and not covered by groups H10K10/80, H10K30/80, H10K50/80 or H10K59/80
    • H10K77/10—Substrates, e.g. flexible substrates
    • H10K77/111—Flexible substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/122—Pixel-defining structures or layers, e.g. banks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/1201—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/124—Insulating layers formed between TFT elements and OLED elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10—OLED displays
    • H10K59/12—Active-matrix OLED [AMOLED] displays
    • H10K59/131—Interconnections, e.g. wiring lines or terminals
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K2102/00—Constructional details relating to the organic devices covered by this subclass
    • H10K2102/301—Details of OLEDs
    • H10K2102/311—Flexible OLED
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/80—Constructional details
    • H10K59/87—Passivation; Containers; Encapsulations
    • H10K59/873—Encapsulations
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/549—Organic PV cells

Definitions

  • OLEDs organic light-emitting diodes
  • display technology organic light-emitting diodes
  • OLED flexible display devices can satisfy the bending of two-dimensional surfaces, but are not suitable for the flexibility requirements of stretchable display substrates for display devices with more complex conditions (eg, wearable devices, etc.).
  • holes are formed on the substrate material of the OLED flexible display device to form islands for preparing pixel regions and bridges for wiring, and The deformation of the bridge achieves the stretching of the display device.
  • a pixel unit arranged on the substrate
  • a signal line disposed on the substrate, and electrically connected to the pixel unit
  • a plurality of inorganic insulating layers are stacked on the substrate, at least one layer of the plurality of inorganic insulating layers has a first hollow portion near the hole region, and the first hollow portion is on the positive side of the substrate.
  • the projections do not overlap the orthographic projections of the signal lines and the pixel units on the substrate.
  • connection bridge area includes at least one of the pixel units, the first hollow portion is located in the connection bridge area, and the first hollow portion is located between the pixel unit of the connection bridge area and the hole area.
  • connection bridge region includes a plurality of the pixel units, and the orthographic projection of the signal line on the substrate is at least located in the connection bridge The pixel units of the area and the area between the pixel units of the connecting bridge area are in the orthographic projection on the substrate.
  • the first hollow portion is not communicated with the hole area.
  • the first hollow portion and the hole area are communicated with each other.
  • an edge of the first hollow portion close to the hole area overlaps an edge of the hole area near the first hollow portion.
  • the pixel unit includes at least one sub-pixel, and the sub-pixel includes a pixel circuit and a light-emitting device, and the light-emitting device includes stacked anodes, an organic light-emitting layer and a cathode; a partition structure is provided in the connection bridge region near the pixel unit, the organic light-emitting layer is disconnected at the partition structure, and the cathode is disconnected at the partition structure;
  • the distance between the side wall of the first hollow portion close to the pixel unit and the partition structure is greater than or equal to 2um.
  • the first hollow portion is a closed structure provided around the hole area.
  • the partition structure is a closed structure provided around the first hollow portion.
  • a part of the hole regions include: a first sub-hole region and a second sub-hole region extending along the first direction and arranged along the second direction, and a third sub-hole area extending along the second direction; another part of the hole area includes: a fourth sub-hole area and a fifth sub-hole area extending along the second direction and arranged along the first direction, and The sixth sub-hole area extending in the first direction; the first direction and the second direction are substantially perpendicular, and the third sub-hole area is substantially connected to the first sub-hole area and the second sub-hole area , the sixth sub-hole area roughly connects the fourth sub-hole area and the center area of the fifth sub-hole area;
  • the first hollow portion is arranged at at least one of the following positions: one side of the connecting position of the first sub-hole region and the third sub-hole region, the second sub-hole region and the third sub-hole region one side of the area connection position, one side of the end of the first sub-hole area and one side of the end of the second sub-hole area, the connection position of the fourth sub-hole area and the sixth sub-hole area the side of the connection position of the fifth sub-hole area and the sixth sub-hole area, the end side of the fourth sub-hole area and the end side of the fifth sub-hole area .
  • one side of the connecting position of the first sub-hole area and the third sub-hole area, the second sub-hole area and the One side of the connection position of the third sub-hole area, one side of the end of the first sub-hole area, one side of the end of the second sub-hole area, the fourth sub-hole area and the sixth sub-hole area is provided with the first hollow portion.
  • the pixel island region includes at least one of the pixel units, and the pixel resolution of the pixel island region is different from that of the connection bridge region. rates are roughly the same.
  • the plurality of inorganic insulating layers include a first barrier layer, a buffer layer, a first gate insulating layer, a first barrier layer, a first gate insulating layer, a Two gate insulating layers, interlayer dielectric layers, first passivation layers, second passivation layers and inorganic encapsulation layers, the first barrier layer, the buffer layer, the first gate insulating layer, the second At least one of the gate insulating layer, the interlayer dielectric layer, the first passivation layer, the second passivation layer and the inorganic encapsulation layer is provided with the first hollow portion.
  • the interlayer dielectric layer, the first passivation layer, the second passivation layer and the inorganic encapsulation layer are all provided with all of them.
  • the first hollow parts are substantially overlapped.
  • the inorganic encapsulation layer includes a first inorganic layer and a second inorganic layer stacked on the second passivation layer;
  • the stretchable display substrate further includes: a first planarization layer and a second planarization layer located between the interlayer dielectric layer and the first passivation layer, located between the second passivation layer and the inorganic a pixel defining layer between the encapsulation layers, and an organic layer between the first inorganic layer and the second inorganic layer;
  • At least one of the first flat layer, the second flat layer, the pixel defining layer and the organic layer has a second hollow portion near the hole area, the first hollow portion and the The second hollow portions are substantially overlapped.
  • the base includes a flexible layer, or the base includes a layer disposed on the side of the first barrier layer away from the buffer layer.
  • the first flexible layer, the second barrier layer and the second flexible layer are optionally, in the above-mentioned stretchable display substrate provided by the embodiment of the present disclosure.
  • an embodiment of the present disclosure further provides a display device including the above-mentioned stretchable display substrate.
  • an embodiment of the present disclosure also provides a method for preparing the above stretchable display substrate, including:
  • a plurality of stacked inorganic insulating layers are formed on the substrate; wherein, at least one layer of the plurality of inorganic insulating layers has a first hollow portion near the hole region, and the first hollow portion is located on the substrate.
  • the orthographic projection on the substrate does not overlap with the orthographic projection of the signal line and the pixel unit on the substrate.
  • At least one layer of the plurality of inorganic insulating layers has a first hollow portion near the hole region, which specifically includes:
  • first barrier layer depositing a first barrier layer, a buffer layer, a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, a first passivation layer, a second passivation layer and an inorganic encapsulation layer on the substrate;
  • the first barrier layer, the buffer layer, the first gate insulating layer, the second gate insulating layer, the interlayer dielectric layer, the first passivation layer, the At least one of the second passivation layer and the inorganic encapsulation layer forms the first hollow portion.
  • FIG. 1 is a schematic top view of a stretchable display substrate according to an embodiment of the present disclosure
  • FIG. 2 is a schematic top view of yet another stretchable display substrate according to an embodiment of the present disclosure
  • Fig. 3 is the cross-sectional schematic diagram along AA' direction in Fig. 1;
  • Fig. 4 is a schematic cross-sectional view along the AA' direction in Fig. 2;
  • FIG. 5 is a flowchart of a method for fabricating a stretchable display substrate according to an embodiment of the present disclosure
  • FIG. 6 is a flowchart of another method for fabricating a stretchable display substrate according to an embodiment of the present disclosure
  • FIGS. 7A-7K are schematic structural diagrams of each step performed in the method for fabricating a stretchable display substrate according to an embodiment of the present disclosure.
  • An embodiment of the present disclosure provides a stretchable display substrate, as shown in FIG. 1 and FIG. 2 , which includes a plurality of hole regions Q2 ; specifically, the hole regions Q2 are used to provide deformation space for the display substrate during stretching.
  • FIG. 3 is a schematic cross-sectional view of the partial structure along the AA' direction in FIG. 1
  • FIG. 4 is a cross-sectional schematic view of the partial structure along the AA' direction in FIG. 2
  • the stretchable display substrate include:
  • Substrate 1 can be a flexible substrate, so that the stretchable area of the stretchable display substrate can be stretched;
  • the pixel unit 4 is arranged on the substrate 1;
  • the signal line 2 is disposed on the substrate 1 and is electrically connected to the pixel unit 4; specifically, the signal line 2 may include gate lines, data lines, etc.;
  • a plurality of inorganic insulating layers are stacked on the substrate 1, and at least one layer of the plurality of inorganic insulating layers has a first hollow portion 3 near the hole region Q2, and the orthographic projection of the first hollow portion 3 on the substrate 1 corresponds to the signal line 2 It does not overlap with the orthographic projection of the pixel unit 4 on the substrate 1 .
  • the position close to the hole region Q2 is subjected to tensile force and deformed.
  • the hole region Q2 has the first hollow portion 3, that is, by removing at least one layer of the plurality of inorganic insulating layers at the position close to the hole region Q2, the buckling deformation behavior of the position close to the hole region Q2 when being stretched can be improved, so that the The position close to the hole region Q2 is less likely to be broken and the pixel unit 4 is less likely to be damaged, thereby improving the stretching performance of the stretchable display substrate.
  • the hole area Q2 in the embodiment of the present disclosure may completely penetrate the stretchable display substrate.
  • the hole area Q2 may also penetrate through the base of the stretchable display substrate. of all film layers and part of the substrate.
  • the stretchable panel designed with the island bridge structure in the related art faces problems such as low display resolution (PPI) and uneven display.
  • the stretchable display substrate provided by the embodiment of the present disclosure, in order to improve the display
  • the problem of resolution and improving display unevenness also includes: a plurality of pixel island regions Q1 arranged at intervals between the hole regions Q2, and a plurality of pixel island regions Q1 located between the pixel island region Q1 and the hole region Q2
  • the connection bridge area Q3 Specifically, the pixel island area Q1 is used for displaying images, and the connection bridge area Q3 is used for routing (making the signal between the adjacent pixel island areas Q1 connected) and transmitting tension;
  • connection bridge area Q3 includes at least one pixel unit 4, the first hollow portion 3 is located in the connection bridge area Q3, and the first hollow portion 3 is located between the pixel unit 4 of the connection bridge area Q3 and the hole area Q2;
  • the pixel units are arranged in the pixel island area Q1, and the pixel units are also arranged in the connection bridge area Q3, so that the display resolution can be improved and the problem of uneven display can be improved.
  • connection bridge area Q3 may include a plurality of pixel units 4, and the orthographic projection of the signal line 2 on the substrate 1 is located at least at the pixel units 4 connected to the bridge area Q3 and the pixel units 4 connected to the bridge area Q3 The region in between is in the orthographic projection on substrate 1 . That is, the signal lines 2 are routed under the pixel units 4 in the connection bridge region Q3 and between the pixel units 4 to realize electrical connection between the pixel units 4 .
  • the extending direction of the first hollow portion 3 is substantially the same as the edge of the hole region Q2 .
  • the first hollow portion 3 surrounding the hole region Q2 is arranged around the hole region Q2, so as to further improve the stretching performance of the stretchable display substrate.
  • the first hollow portion 3 is not connected to the hole area Q2, because the first hollow portion 3 is formed on a plurality of inorganic insulating layers. It is formed in at least one of the layers, that is, a plurality of inorganic insulating layers are retained between the first hollow portion 3 and the hole region Q2, and at least one inorganic insulating layer is removed in the connection bridge region Q3 to form the first hollow portion 3, so as to improve the connection bridge region.
  • the buckling deformation behavior of Q3 when stretched makes the connection bridge region Q3 less prone to breakage and the pixel island region Q1 adjacent to the connection bridge region Q3 is not easily damaged, thereby improving the tensile properties of the stretchable display substrate.
  • the distance therebetween is greater than or equal to 2 ⁇ m.
  • the width is greater than or equal to 5um, so that the difficulty of the exposure, development and etching process can be reduced when each inorganic insulating layer is removed by the exposure, development and etching process.
  • the first hollow portion 3 and the hole region Q2 are connected to each other, that is, when the connection bridge region Q3 is etched to each inorganic insulating layer , directly etching the inorganic insulating layer connecting the bridge region Q3 to connect with the hole region Q2, further reducing the inorganic insulating layer connecting the bridge region Q3, thereby further improving the tensile properties of the connecting bridge region Q3.
  • the inorganic insulating layer is not retained between the first hollow portion 3 and the hole region Q2, that is, when each inorganic insulating layer is etched in the connecting bridge region Q3, the inorganic insulating layer in the corresponding region of the first hollow portion 3 is directly etched to the same level as the one.
  • the edge of the hole region Q2 further reduces the inorganic insulating layer connecting the bridge region Q3, thereby further improving the tensile properties of the bridge region Q3.
  • the pixel unit 4 includes at least one sub-pixel, and the sub-pixel includes a pixel circuit and a light-emitting device, and the pixel circuit is located in the light-emitting device.
  • the light-emitting device includes a stacked anode 6, an organic light-emitting layer 7 and a cathode 8; a partition structure 9 is provided in the connecting bridge region Q3 near the pixel unit 4, and the partition structure 9 is shown in FIG. 1 and FIG. 2 .
  • the middle is arranged around the first hollow part 3, that is, the partition structure 9 is located between the pixel unit 4 and the first hollow part 3, the organic light-emitting layer 7 is disconnected at the partition structure 9, and the cathode 8 is disconnected at the partition structure 9; Since the partition structure 9 is located in the connection bridge region Q3, and because the connection bridge region Q3 is located between the hole region Q2 and the pixel island region Q1, that is, the organic light-emitting layer 7 and the cathode 8 partitioned by the partition structure 9 are partially located in the pixel island region Q1, Part of the organic light-emitting layer 7 and the cathode 8 near the hole area Q2 are easily invaded by water and oxygen.
  • the water and oxygen in the organic light-emitting layer 7 and the cathode 8 of Q2 invade into the isolation path distance between the organic light-emitting layer 7 and the cathode 8 in the sub-pixel, that is to ensure that the water and oxygen cannot invade the organic light-emitting layer 7 and the cathode 8 in the sub-pixel, thereby ensuring Displays the normal display of the product.
  • the light emitting device may be a red (R) light emitting device emitting red light, a green (G) light emitting device emitting green light, and a blue (B) light emitting device emitting blue light.
  • the light-emitting device may be an inorganic light-emitting diode, an organic light-emitting diode (OLED) made of organic materials, or a micro light-emitting diode (Micro LED) or a mini light-emitting diode (mini LED).
  • OLED organic light-emitting diode
  • Micro light-emitting diodes refer to ultra-small inorganic light-emitting elements with a size of less than 100 microns that emit light without backlight and filters.
  • the pixel circuit can adopt various structures.
  • the pixel circuit can include a structure of 2 transistors and 1 capacitor (2T1C), or a structure of 7 transistors and 1 capacitor (7T1C), or a structure of 12 transistors and 1 capacitor (12T1C).
  • a pixel circuit generally includes a driving transistor and other switching transistors, as shown in FIG. 3 and FIG. 4 , which illustrate schematic diagrams of the driving transistor, the light-emitting device and the storage capacitor in the pixel circuit.
  • the driving transistor can be a top-gate type, and includes an active layer 21, a first gate insulating layer 22, a gate electrode 23, a second gate insulating layer 24, an interlayer dielectric layer 25, a source electrode 26, Drain 27.
  • the active layer 21 may be formed on the buffer layer 28, the buffer layer 28 is disposed on the first barrier layer 29, the first gate insulating layer 22 covers the buffer layer 28 and the active layer 21, and the gate 23 is formed on the first barrier layer 29.
  • the source electrode 26 and the drain electrode 27 can respectively contact the opposite sides of the active layer 21 through via holes. As shown in FIG. 3 and FIG.
  • the capacitor structure (for example, the storage capacitor Cst in the pixel circuit) may include a first electrode plate C1 and a second electrode plate C2, and the second electrode plate C2 and the gate electrode 23 are arranged in the same layer.
  • a pole plate C1 is located between the second gate insulating layer 24 and the interlayer dielectric layer 25 , and the first pole plate C1 is disposed opposite to the second pole plate C2 .
  • the signal line 2 located in the connection bridge region Q3 is provided in the film layer where the source electrode 26 and the drain electrode 27 are located.
  • the anode 6 and the drain 27 of the light-emitting device can be directly electrically connected (ie, a single-layer SD structure), or they can be electrically connected through an overlap electrode 30 located therebetween (ie, a double-layer SD structure).
  • a first flat layer 31 is arranged between the electrodes 27, a second flat layer 32, a first passivation layer 33 and a second passivation layer 34 are arranged between the overlap electrode 30 and the anode 6, which can stretch the surface of the display substrate.
  • Each light-emitting device is generally defined by a pixel-defining layer 35, and the pixel-defining layer 35 has an opening region that exposes the light-emitting device.
  • the substrate may include a flexible layer, or as shown in FIG. 3 and FIG. the first flexible layer 11 , the second barrier layer 12 and the second flexible layer 13 .
  • the material of the flexible layer may be polyimide (PI), polyester, polyamide, or the like.
  • the substrate 1 may be disposed on the glass substrate 10 to facilitate subsequent peeling.
  • the distance between the side wall of the first hollow part 3 and the partition structure 9 close to the first hollow part 3 can be greater than or equal to 2um
  • the organic light-emitting layer 7 is disconnected at the partition structure 9
  • the cathode 8 is disconnected at the partition structure 9.
  • the first hollow portion 3 is a closed structure arranged around the hole region Q2, so that the connection bridge region Q3 can be removed as much as possible.
  • the inorganic insulating layer maximizes the tensile properties of the connection bridge area.
  • the partition structure 9 is a closed structure arranged around the first hollow portion 3, that is, the orthographic projection pattern of the partition structure 9 on the substrate 1 is the same as the boundary pattern of the hole area Q2, that is, the partition structure 9 is arranged around the hole area Q2, so as to ensure the partition The structure 9 prevents water and oxygen from intruding into the pixel island region Q1 from the hole region Q2 at various positions.
  • a part of the hole area Q2 includes: a first sub-hole area extending along the first direction X and arranged along the second direction Y Q21 and the second sub-hole area Q22, and a third sub-hole area Q23 extending along the second direction Y; another part of the hole area Q2 includes: a fourth sub-hole area extending along the second direction Y and arranged along the first direction X Q24 and a fifth sub-hole region (not shown), and a sixth sub-hole region Q26 extending along the first direction X; the first direction X and the second direction Y are substantially perpendicular, and the sixth sub-hole region Q26 is substantially connected to the fourth the central area of the sub-hole area Q24 and the fifth sub-hole area;
  • the inorganic insulating layer at these positions breaks first.
  • the first hollow portion 3 is at least arranged at at least one of the following positions: the first sub-hole The side of the connection position between the region Q21 and the third sub-hole region Q23, the side of the connection position between the second sub-hole region Q22 and the third sub-hole region Q23, the end of the first sub-hole region Q21 and the second sub-hole One side of the end of the area Q22, one side of the connection position of the fourth sub-hole area Q24 and the sixth sub-hole area Q26, one side of the connection position of the fifth sub-hole area and the sixth sub-hole area Q26, and the fourth sub-hole area One side of the end of Q24 and one side of the end of the fifth sub-hole region.
  • the difficulty of manufacturing the large-area first hollow portion 3 can be reduced, and the problem of breaking the inorganic insulating layer at the position where the inorganic insulating layer is prone to breakage corresponding to the hole region Q2 can be avoided.
  • the shape of the hole area Q2 is approximately an “I” shape as an example for schematic illustration.
  • the shape of the hole area Q2 is not limited to this.
  • it can also be a "T" font, a "one” font, and so on.
  • one side of the connecting position of the first sub-hole region Q21 and the third sub-hole region Q23 , the second sub-hole region Q22 and the third sub-hole region Q23 One side of the connection position of the third sub-hole area Q23, the end side of the first sub-hole area Q21 and the end side of the second sub-hole area Q22, the connection position of the fourth sub-hole area Q24 and the sixth sub-hole area Q26
  • a first hollow is provided on one side, the side where the fifth sub-hole area is connected to the sixth sub-hole area Q26, the end of the fourth sub-hole area Q24 and the end side of the fifth sub-hole area.
  • the pixel island region Q1 includes at least one pixel unit 4 , and the pixel resolution of the pixel island region Q1 is the same as the pixel resolution of the connection bridge region Q3 rates are roughly the same. This can improve display resolution and improve display unevenness.
  • the plurality of inorganic insulating layers include a first barrier layer 29 , a buffer layer 28 , and a first gate insulating layer stacked on the substrate 1 .
  • At least one of the second gate insulating layer 24 , the interlayer dielectric layer 25 , the first passivation layer 33 , the second passivation layer 34 and the inorganic encapsulation layer 36 is provided with the first hollow portion 3 .
  • the interlayer dielectric layer 25 , the first passivation layer 33 , the second passivation layer 34 and the inorganic packaging Each of the layers 36 is provided with first hollow portions 3 , and the first hollow portions 3 are substantially overlapped.
  • the first hollow portion 3 may also be provided on the first barrier layer 29 , the buffer layer 28 , the first gate insulating layer 22 , and the second gate insulating layer 24 .
  • the first passivation layer 33 , the second passivation layer 34 and the inorganic encapsulation layer 36 are all provided with the first hollow portion 3 as schematically illustrated.
  • the plurality of inorganic insulating layers are provided with the first hollow portion 3 (that is, each inorganic insulating layer is etched to hollow out the corresponding area of the inorganic insulating layer).
  • the layer 36 is hollowed out to any inorganic insulating layer above the second flexible layer 13 , for example, directly hollowed out above the second flexible layer 13 , or directly hollowed out to the first barrier layer 29 , the buffer layer 28 , and the first gate insulating layer 22 , any one of the second gate insulating layer 24 , the interlayer dielectric layer 25 , the first passivation layer 33 , the second passivation layer 34 and the inorganic encapsulation layer 36 .
  • the first barrier layer 29, the buffer layer 28, the first gate insulating layer 22, the second gate insulating layer 24, and the interlayer dielectric layer 25 can be hollowed out once or twice in the manufacturing process of the stretchable display substrate
  • the etching process is realized, and the hollowing out of the inorganic encapsulation layer 36 is achieved by etching thinning through a single exposure and etching process after the inorganic encapsulation layer 36 is fabricated.
  • the hollowing out of all the inorganic insulating layers can also be realized by a single exposure and deep hole etching process after all the inorganic insulating layers are finished; the specific etching process can be selected according to actual needs.
  • the inorganic encapsulation layer 36 includes a first inorganic layer and a first inorganic layer and a second passivation layer that are stacked on the second passivation layer 34 .
  • the stretchable display substrate further includes: a first planarization layer 31 and a second planarization layer 32 between the interlayer dielectric layer 25 and the first passivation layer 33 , and between the second passivation layer 34 and the inorganic encapsulation layer 36
  • At least one of the first flat layer 31 , the second flat layer 32 , the pixel defining layer 35 and the organic layer has a second hollow portion near the hole region Q2 , and the first hollow portion 3 and the second hollow portion substantially overlap.
  • the second passivation layer 34 and the inorganic encapsulation layer 36 can be made of inorganic insulating materials such as silicon oxide and silicon nitride.
  • the first flat layer 31 , the second flat layer 32 , the pixel defining layer 35 and the organic layer can be organic film layers, that is, they can be made of organic insulating materials such as photoresist and PI.
  • the inventors of the present case have tested the tensile properties of the stretchable display substrate shown in FIG. 3 provided by the embodiment of the present disclosure and the stretchable display substrate in the related art without the first hollow portion in the connecting bridge region.
  • the test found that The stretching amount of the present disclosure is approximately 2%, and the stretching amount in the related art is less than 1%. Therefore, the stretchable display substrate provided by the embodiments of the present disclosure significantly improves the stretching performance.
  • an embodiment of the present disclosure also provides a method for preparing the above stretchable display substrate, as shown in FIG. 5 , including:
  • At least one layer of the plurality of inorganic insulating layers has a first hollow portion near the hole region, as shown in FIG. 6 , which specifically includes:
  • S601 depositing a first barrier layer, a buffer layer, a first gate insulating layer, a second gate insulating layer, an interlayer dielectric layer, a first passivation layer, a second passivation layer, and an inorganic encapsulation layer on the substrate;
  • each layer structure in the embodiment of the present disclosure may include a patterning process, a photolithography process, etc.
  • the patterning process may include depositing a film layer, coating a photoresist, mask exposure, developing, etching, and stripping the photoresist
  • the photolithography process may include coating film layer, mask exposure, development and other processes, and the adopted evaporation, deposition, coating, coating, etc. are all mature preparation processes in related technologies.
  • the preparation process of the stretchable display substrate shown in FIG. 3 will be described in detail below, which may include the following steps:
  • the substrate 1 including a two-layer flexible layer structure as an example, the substrate 1 is divided into a pixel island area Q1, a hole area Q2 and a connection bridge area Q3, and the first flexible layer 11, The second barrier layer 12 and the second flexible layer 13 ; when the second barrier layer 12 is formed, the second barrier layer 12 corresponding to the hole area Q2 is etched away; then, the first barrier layer 29 is formed on the second flexible layer 13 ; As shown in Figure 7A.
  • the material of the flexible layer may be polyimide (PI), polyester, polyamide, or the like.
  • the material of the barrier layer can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate.
  • a buffer layer 28 is formed on the first barrier layer 29, an active layer film is deposited on the buffer layer 28, the active layer film is patterned by a patterning process, an active layer 21 is formed on the buffer layer 28, and an active layer is formed on the buffer layer 28.
  • a first gate insulating layer 22 is formed on the source layer 21, as shown in FIG. 7B.
  • a layer of metal film (SD1 layer) on the interlayer dielectric layer 25, pattern the metal film through a patterning process, and form a source electrode 26, a drain electrode 27 and a signal line 2 (data line 2) on the interlayer dielectric layer 25. line), the source electrode 26 and the drain electrode 27 are respectively connected to the active layer 21 through vias penetrating the first gate insulating layer 22, the second gate insulating layer 24 and the interlayer dielectric layer 25; 2.
  • the substrate 1 of the drain electrode 27 is coated with a flat thin film of organic material, and a first flat layer 31 is formed by masking, exposing and developing processes.
  • the first flat layer 31 corresponds to the position of the source electrode 26, the position of the hole region Q2, and the corresponding connection.
  • the positions of the first hollow portion 3 of the bridge region Q3 are all developed, as shown in FIG. 7E .
  • (6) deposit a layer of metal thin film (SD2 layer, or without SD2 layer) on the first flat layer 31, pattern the metal thin film through a patterning process, and form a lap electrode 30 on the first flat layer 31;
  • a flat film coated with organic material is formed on the film layer where the connecting electrode 30 is located, and a second flat layer 32 is formed by masking, exposing and developing processes. The positions of the first hollow portion 3 are all developed; then, an inorganic insulating material is deposited on the second flat layer 32, and then, the buffer layer 28 and the first barrier layer 29 in the hole region Q2 are first etched away, and the hole region is etched away.
  • the first flexible layer 11 and the second flexible layer 13 of Q2; the inorganic insulating material, the buffer layer 28 and the first barrier layer 29 at the corresponding positions of the first hollow portion 3 are etched away, and the connection bridge region Q3 is etched away to form a corresponding isolation structure
  • the inorganic insulating material at position 9, the second planarization layer 32 and part of the first planarization layer 31, and the etched inorganic insulating material forms a first passivation layer 33, as shown in FIG. 7F .
  • An inorganic insulating material is deposited on the first passivation layer 33 , and the inorganic insulating material corresponding to the position of the hole region Q2 and the position of the first hollow portion 3 is etched away, and the inorganic insulating material corresponding to the position of the overlap electrode 30 is etched away and the first passivation layer 33 to form a second passivation layer 34, as shown in FIG. 7G.
  • the conductive film is deposited on the second passivation layer 34, and the conductive film is patterned by a patterning process to form an anode 6, and the anode 6 passes through the first passivation layer 33 and the second passivation layer.
  • the contact electrodes 30 are electrically connected, as shown in FIG. 7H.
  • the conductive film may be a three-layer stack structure of transparent conductive film/metal film/transparent conductive film, wherein the material of the transparent conductive film may be indium tin oxide ITO or indium zinc oxide IZO, and the metal film may be Al, Metal thin films such as Ag and Cu.
  • a pixel defining film is coated on the anode 6, and a pixel defining layer 35 is formed by masking, exposing and developing processes.
  • a pixel opening is provided on the pixel defining layer 35 of the pixel island region Q1, and the pixel defining layer 35 in the pixel opening is developed to expose the surface of the anode 6; and the pixel defining layer 35 corresponds to the position of the hole region Q2 and the connection bridge region Q3
  • the locations are all developed as shown in Figure 7I.
  • the organic light-emitting layer 7 and the cathode 8 are sequentially formed on the pixel defining layer 35, the organic light-emitting layer 7 is formed in the pixel opening of the pixel defining layer 35 and is connected to the anode 6, and the organic light-emitting layer 7 and the cathode 8 are respectively in the partition structure 9. disconnected at the location, as shown in Figure 7J.
  • the organic light-emitting layer 6 and the cathode 7 can both be prepared and formed by an evaporation process.
  • the material of the cathode 8 can be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu) and lithium (Li), or any one or more of the above metals. made of alloys.
  • An inorganic encapsulation layer 36 is formed on the cathode 8.
  • the inorganic encapsulation layer 36 may include a first inorganic layer, an organic layer and a second inorganic layer that are stacked and arranged, corresponding to the position of the hole area Q2 and to the position of the first hollow part 3
  • the inorganic encapsulation layer 36 , the cathode 8 , and the organic light-emitting layer 6 are etched away, as shown in FIG. 7K , that is, the stretchable display substrate shown in FIG. 3 provided by the embodiment of the present disclosure is formed.
  • the embodiment of the present disclosure is described by taking the preparation method of the stretchable display substrate shown in FIG. 3 as an example, and the preparation method of the stretchable display substrate shown in FIG. 4 is the same as the preparation method shown in FIG. 3 .
  • the method is similar, the difference is that all the inorganic insulating layers and organic insulating layers between the first hollow part 3 and the hole area Q2 in FIG. 3 are etched away to form a structure in which the first hollow part 3 and the hole area Q2 are connected.
  • the shown preparation method will not be described in detail.
  • the inorganic insulating layer and the organic insulating layer between the first hollow portion 3 and the hole region Q2 can be etched together with the same film layers in other regions during etching.
  • the stretchable display substrate can be obtained by peeling off the glass substrate 10 under the stretchable display substrate shown in FIGS. 3 and 4 from the stretchable display substrate.
  • an embodiment of the present disclosure further provides a display device, including any of the above-mentioned stretchable display substrates provided by the embodiment of the present disclosure.
  • the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • a display function such as a mobile phone, a tablet computer, a TV, a monitor, a notebook computer, a digital photo frame, a navigator, and the like.
  • the above-mentioned display device can be any product or component with a display function, such as an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a display module, a curved screen mobile phone, and a smart watch.
  • a display function such as an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a display module, a curved screen mobile phone, and a smart watch.
  • Embodiments of the present disclosure provide a stretchable display substrate, a preparation method thereof, and a display device.
  • the connecting bridge region adjacent to the hole region is subjected to tensile force and deformed.
  • At least one layer of the plurality of inorganic insulating layers has a first hollow portion in the connection bridge region near the hole region, that is, by removing at least one layer of the plurality of inorganic insulating layers in the connection bridge region near the hole region, it can improve the The buckling deformation behavior of the connecting bridge region when stretched makes the connecting bridge region less prone to breakage and the pixel island region adjacent to the connecting bridge region is not easily damaged, thereby improving the tensile performance of the stretchable display substrate.

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Abstract

本公开实施例公开了一种可拉伸显示基板及其制备方法、显示装置，包括多个孔区; 可拉伸显示基板包括: 基底; 像素单元，设置在基底上; 信号线，设置在基底上，且与像素单元电连接; 多个无机绝缘层，层叠设置在基底上，多个无机绝缘层中至少一层在靠近孔区具有第一镂空部，第一镂空部在基底上的正投影与信号线和像素单元在基底上的正投影不交叠。

Description

一种可拉伸显示基板及其制备方法、显示装置 技术领域
本公开涉及显示技术领域，特别涉及一种可拉伸显示基板及其制备方法、显示装置。
背景技术
随着显示技术的发展，能够进行柔性显示的有机发光二极管(organic light-emitting diode，简称OLED)促进了显示的多样化，逐渐成为显示技术的主流。在一些相关技术中，OLED柔性显示装置能够满足二维面的弯折，但不适用于情况更复杂的显示装置(例如：可穿戴设备等)对于可拉伸显示基板的柔性需求。
为了发展可拉伸(Stretchable)的OLED显示功能，一些相关技术中，通过在OLED柔性显示装置的衬底材料上开孔，形成用于制备像素区的岛和用于走线的桥，并通过桥的变形来实现显示装置的拉伸。
发明内容
本公开实施例提供了一种可拉伸显示基板，包括多个孔区；所述可拉伸显示基板包括：
基底；
像素单元，设置在所述基底上；
信号线，设置在所述基底上，且与所述像素单元电连接；
多个无机绝缘层，层叠设置在所述基底上，所述多个无机绝缘层中至少一层在靠近所述孔区具有第一镂空部，所述第一镂空部在所述基底上的正投影与所述信号线和所述像素单元在所述基底上的正投影不交叠。
可选地，在本公开实施例提供的上述可拉伸显示基板中，还包括：位于 所述孔区之间间隔设置的多个像素岛区，以及位于所述像素岛区和所述孔区之间的连接桥区；
所述连接桥区包括至少一个所述像素单元，所述第一镂空部位于所述连接桥区，且所述第一镂空部位于所述连接桥区的像素单元和所述孔区之间。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述连接桥区包括多个所述像素单元，所述信号线在所述基底上的正投影至少位于所述连接桥区的像素单元以及所述连接桥区的像素单元之间区域在所述基底上的正投影内。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述第一镂空部的延伸方向与所述孔区的边缘大致相同。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述第一镂空部与所述孔区不连通。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述第一镂空部靠近所述孔区的侧壁与所述孔区靠近所述第一镂空部的侧壁之间的距离大于或等于2μm。
可选地，在本公开实施例提供的上述可拉伸显示基板中，沿所述像素岛区指向所述孔区的方向上，所述第一镂空部的宽度大于或等于5um。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述第一镂空部与所述孔区相互连通。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述第一镂空部中靠近所述孔区的边缘与所述孔区中靠近所述第一镂空部的边缘重叠。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述像素单元包括至少一个子像素，所述子像素包括像素电路和发光器件，所述发光器件包括层叠设置的阳极、有机发光层和阴极；所述连接桥区中靠近所述像素单元位置处设置有隔断结构，所述有机发光层在所述隔断结构处断开，所述阴极在所述隔断结构处断开；
所述第一镂空部靠近所述像素单元的侧壁与所述隔断结构之间的距离大 于或等于2um。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述第一镂空部为环绕所述孔区设置的封闭结构。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述隔断结构为环绕所述第一镂空部设置的封闭结构。
可选地，在本公开实施例提供的上述可拉伸显示基板中，一部分所述孔区包括：沿第一方向延伸且沿第二方向排列的第一子孔区和第二子孔区，以及沿所述第二方向延伸的第三子孔区；另一部分所述孔区包括：沿第二方向延伸且沿第一方向排列的第四子孔区和第五子孔区，以及沿所述第一方向延伸的第六子孔区；所述第一方向和所述第二方向大致垂直，所述第三子孔区大致连接所述第一子孔区和所述第二子孔区的中心区域，所述第六子孔区大致连接所述第四子孔区和所述第五子孔区的中心区域；
所述第一镂空部至少设置在以下至少之一位置：所述第一子孔区与所述第三子孔区连接位置的一侧、所述第二子孔区与所述第三子孔区连接位置的一侧、所述第一子孔区的端部一侧和所述第二子孔区的端部一侧、所述第四子孔区与所述第六子孔区连接位置的一侧、所述第五子孔区与所述第六子孔区连接位置的一侧、所述第四子孔区的端部一侧和所述第五子孔区的端部一侧。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述第一子孔区与所述第三子孔区连接位置的一侧、所述第二子孔区与所述第三子孔区连接位置的一侧、所述第一子孔区的端部一侧和所述第二子孔区的端部一侧、所述第四子孔区与所述第六子孔区连接位置的一侧、所述第五子孔区与所述第六子孔区连接位置的一侧、所述第四子孔区的端部一侧和所述第五子孔区的端部一侧均设置有所述第一镂空部。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述像素岛区包括至少一个所述像素单元，所述像素岛区的像素分辨率与所述连接桥区的像素分辨率大致相同。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述多个无机绝缘层包括层叠设置在所述基底上的第一阻挡层、缓冲层、第一栅绝缘层、第二栅绝缘层、层间介质层、第一钝化层、第二钝化层和无机封装层，所述第一阻挡层、所述缓冲层、所述第一栅绝缘层、所述第二栅绝缘层、所述层间介质层、所述第一钝化层、所述第二钝化层和所述无机封装层中的至少一层设置所述第一镂空部。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述层间介质层、所述第一钝化层、所述第二钝化层和所述无机封装层均设置所述第一镂空部，各所述第一镂空部大致重叠。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述无机封装层包括层叠设置在所述第二钝化层上的第一无机层和第二无机层；
所述可拉伸显示基板还包括：位于所述层间介质层和所述第一钝化层之间的第一平坦层和第二平坦层，位于所述第二钝化层和所述无机封装层之间的像素界定层，以及位于所述第一无机层和所述第二无机层之间的有机层；
所述第一平坦层、所述第二平坦层、所述像素界定层和所述有机层中的至少一层在靠近所述孔区具有第二镂空部，所述第一镂空部和所述第二镂空部大致重叠。
可选地，在本公开实施例提供的上述可拉伸显示基板中，所述基底包括一层柔性层，或所述基底包括设置在所述第一阻挡层背离所述缓冲层一侧层叠设置的第一柔性层、第二阻挡层和第二柔性层。
相应地，本公开实施例还提供了一种显示装置，包括上述可拉伸显示基板。
相应地，本公开实施例还提供了一种上述可拉伸显示基板的制备方法，包括：
提供基底；
在所述基底上形成像素单元以及与所述像素单元电连接的信号线；
在所述基底上形成层叠设置的多个无机绝缘层；其中，所述多个无机绝 缘层中至少一层在靠近所述孔区具有第一镂空部，所述第一镂空部在所述基底上的正投影与所述信号线和所述像素单元在所述基底上的正投影不交叠。
可选地，在本公开实施例提供的上述制备方法中，所述多个无机绝缘层中至少一层在靠近所述孔区具有第一镂空部，具体包括：
在所述基底之上沉积第一阻挡层、缓冲层、第一栅绝缘层、第二栅绝缘层、层间介质层、第一钝化层、第二钝化层和无机封装层；
采用构图工艺，在所述第一阻挡层、所述缓冲层、所述第一栅绝缘层、所述第二栅绝缘层、所述层间介质层、所述第一钝化层、所述第二钝化层和所述无机封装层中至少一层形成所述第一镂空部。
附图说明
图1为本公开实施例提供的一种可拉伸显示基板的俯视示意图；
图2为本公开实施例提供的又一种可拉伸显示基板的俯视示意图；
图3为图1中沿AA’方向的截面示意图；
图4为图2中沿AA’方向的截面示意图；
图5为本公开实施例提供的一种可拉伸显示基板的制作方法流程图；
图6为本公开实施例提供的又一种可拉伸显示基板的制作方法流程图；
图7A-图7K为本公开实施例提供的可拉伸显示基板的制作方法执行各步骤的结构示意图。
具体实施方式
为了使本公开的目的，技术方案和优点更加清楚，下面结合附图，对本公开实施例提供的可拉伸显示基板的制作方法的具体实施方式进行详细地说明。应当理解，下面所描述的优选实施例仅用于说明和解释本公开，并不用于限定本公开。并且在不冲突的情况下，本申请中的实施例及实施例中的特征可以相互组合。
附图中各层薄膜厚度、大小和形状不反映可拉伸显示基板的真实比例， 目的只是示意说明本公开内容。
本公开实施例提供了一种可拉伸显示基板，如图1和图2所示，包括多个孔区Q2；具体地，孔区Q2用于为显示基板在拉伸时提供变形空间。
具体地，如图3和图4所示，图3为图1中沿AA’方向部分结构的截面示意图，图4为图2中沿AA’方向部分结构的截面示意图，该可拉伸显示基板包括：
基底1；基底1可以为柔性基底，使可拉伸显示基板的可拉伸区域能够拉伸；
像素单元4，设置在基底1上；
信号线2，设置在基底1上，且与像素单元4电连接；具体地，信号线2可以包括栅线、数据线等；
多个无机绝缘层，层叠设置在基底1上，多个无机绝缘层中至少一层在靠近孔区Q2具有第一镂空部3，第一镂空部3在基底1上的正投影与信号线2和像素单元4在基底1上的正投影不交叠。
本公开实施例提供的上述可拉伸显示基板，可拉伸显示基板在被拉伸时，靠近孔区Q2的位置承受拉力并变形，本公开通过设置多个无机绝缘层中至少一层在靠近孔区Q2具有第一镂空部3，即通过在靠近孔区Q2的位置去除多个无机绝缘层中的至少一层，这样可以提升靠近孔区Q2的位置受拉伸时的屈曲变形行为，使得靠近孔区Q2的位置不容易发生断裂以及像素单元4不易损坏，从而提升可拉伸显示基板的拉伸性能。
需要说明的是，如图1和图2所示，本公开实施例中的孔区Q2可以是完全贯穿可拉伸显示基板，当然，孔区Q2也可以是贯穿可拉伸显示基板的基底上的所有膜层以及部分所述基底。
需要说明的是，如图3和图4所示，本公开实施例是以位于基底1上的所有无机绝缘层均去除形成第一镂空部3为例进行示意说明的，当然，也可以仅其中任意一层无机绝缘层或多层无机绝缘层被去除形成第一镂空部3。
在具体实施时，相关技术中岛桥结构设计的可拉伸面板面临着显示分辨 率(PPI)低、显示不均匀等问题，在本公开实施例提供的可拉伸显示基板中，为了提升显示分辨率及改善显示不均匀的问题，如图1-图4所示，还包括：位于孔区Q2之间间隔设置的多个像素岛区Q1，以及位于像素岛区Q1和孔区Q2之间的连接桥区Q3；具体地，像素岛区Q1用于显示图像，连接桥区Q3用于走线(使相邻像素岛区Q1之间信号连通)和传递拉力；
连接桥区Q3包括至少一个像素单元4，第一镂空部3位于连接桥区Q3，且第一镂空部3位于连接桥区Q3的像素单元4和孔区Q2之间；即本公开将原先只在像素岛区Q1设置像素单元，扩展到在连接桥区Q3也设置像素单元，从而可以提升显示分辨率及改善显示不均匀的问题。
如图1-图4所示，连接桥区Q3可以包括多个像素单元4，信号线2在基底1上的正投影至少位于连接桥区Q3的像素单元4以及连接桥区Q3的像素单元4之间区域在基底1上的正投影内。即信号线2在连接桥区Q3的像素单元4下方以及像素单元4之间区域走线，实现各个像素单元4之间电连接。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图1所示，第一镂空部3的延伸方向与孔区Q2的边缘大致相同。这样在孔区Q2周边设置围绕孔区Q2的第一镂空部3，进一步提升可拉伸显示基板的拉伸性能。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图3所示，第一镂空部3与孔区Q2不连通，由于第一镂空部3是在多个无机绝缘层中的至少一层中形成，即第一镂空部3与孔区Q2之间保留多个无机绝缘层，在连接桥区Q3去除至少一层无机绝缘层形成第一镂空部3，提高连接桥区Q3受拉伸时的屈曲变形行为，使得连接桥区Q3不容易发生断裂以及邻近连接桥区Q3的像素岛区Q1不易损坏，从而提升可拉伸显示基板的拉伸性能。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图3所示，第一镂空部3靠近孔区Q2的侧壁与孔区Q2靠近第一镂空部3的侧壁之间的距离(该距离为孔区Q2与第一镂空部3之间的无机绝缘层的宽度)大于或等于2μm。
在具体实施时，为了降低制作工艺难度，在本公开实施例提供的可拉伸 显示基板中，如图3所示，沿像素岛区Q1指向孔区Q2的方向上，第一镂空部3的宽度大于或等于5um，这样在采用曝光显影刻蚀工艺去除各无机绝缘层时，可以降低曝光显影刻蚀工艺的难度。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图4所示，第一镂空部3与孔区Q2相互连通，即在连接桥区Q3刻蚀各无机绝缘层时，直接将连接桥区Q3的无机绝缘层刻蚀至与孔区Q2连通，进一步减少连接桥区Q3的无机绝缘层，从而进一步提高连接桥区Q3的拉伸性能。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图4所示，第一镂空部3中靠近孔区Q2的边缘与孔区Q2中靠近第一镂空部3的边缘重叠。即在第一镂空部3和孔区Q2之间不保留无机绝缘层，即在连接桥区Q3刻蚀各无机绝缘层时，直接将第一镂空部3对应区域的无机绝缘层刻蚀至与孔区Q2边缘，进一步减少连接桥区Q3的无机绝缘层，从而进一步提高连接桥区Q3的拉伸性能。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图3和图4所示，像素单元4包括至少一个子像素，子像素包括像素电路和发光器件，像素电路位于发光器件和基底1之间，发光器件包括层叠设置的阳极6、有机发光层7和阴极8；连接桥区Q3中靠近像素单元4位置处设置有隔断结构9，隔断结构9在图1和图2中是围绕第一镂空部3设置的，即隔断结构9位于像素单元4和第一镂空部3之间，有机发光层7在隔断结构9处断开，阴极8在隔断结构9处断开；由于隔断结构9位于连接桥区Q3内，又由于连接桥区Q3位于孔区Q2与像素岛区Q1之间，即隔断结构9隔断的有机发光层7和阴极8部分位于像素岛区Q1内，部分靠近孔区Q2，靠近孔区Q2的有机发光层7和阴极8容易遭到水氧侵入，通过将有机发光层7和阴极8分为相互隔断的两个部分，有效延长了通过靠近孔区Q2的有机发光层7和阴极8内的水氧入侵到子像素中有机发光层7和阴极8的隔离路径距离，即确保水氧无法侵入子像素中的有机发光层7与阴极8，从而确保显示产品的正常显示。
发光器件可以有发出红色光的红色(R)发光器件、发绿色光的绿色(G)发光 器件以及发蓝色光的蓝色(B)发光器件。发光器件可以是无机发光二极管，也可以是利用有机材料制造的有机发光二极管(OLED)，还可以是微型发光二极管(Micro LED)或迷你发光二极管(mini LED)。微型发光二极管是指没有背光和滤光片而自发光的100微米以下大小的超小型无机发光元件。
像素电路可以采用多种结构，例如像素电路可以包括2个晶体管1个电容(2T1C)的结构，或7个晶体管1个电容(7T1C)的结构，或12个晶体管1个电容(12T1C)的结构等。像素电路中一般包括一个驱动晶体管和其余的开关晶体管，如图3和图4所示，示意出了像素电路中的驱动晶体管、发光器件和存储电容的示意图。该驱动晶体管可为顶栅型，包括位于基底1上层叠设置的有源层21、第一栅绝缘层22、栅极23、第二栅绝缘层24、层间介质层25、源极26、漏极27。具体地，有源层21可形成在缓冲层28上，缓冲层28设置在第一阻挡层29上，第一栅绝缘层22覆盖缓冲层28及有源层21，栅极23形成在第一栅绝缘层22背离有源层21的一侧，第二栅绝缘层24覆盖栅极23和第一栅绝缘层22，层间介质层25覆盖第二栅绝缘层24，源极26和漏极27形成在层间介质层25背离基底1的一侧并分别位于栅极23的相对两侧，该源极26和漏极27可分别通过过孔与有源层21的相对两侧接触。如图3和图4所示，电容结构(例如像素电路中的存储电容Cst)可包括第一极板C1和第二极板C2，此第二极板C2与栅极23同层设置，第一极板C1位于第二栅绝缘层24与层间介质层25之间，且第一极板C1并与第二极板C2相对设置。
具体地，如图3和图4所示，位于连接桥区Q3的信号线2设置在源极26和漏极27所在膜层。发光器件的阳极6和漏极27可以直接电连接(即单层SD结构)，也可以通过位于二者之间的搭接电极30电连接(即双层SD结构)，搭接电极30和漏极27之间设置有第一平坦层31，搭接电极30和阳极6之间设置有第二平坦层32、第一钝化层33和第二钝化层34，可拉伸显示基板中的各发光器件一般通过像素界定层35界定出来，像素界定层35具有裸露发光器件的开口区。
在本公开实施例提供的可拉伸显示基板中，基底可以包括一层柔性层， 或如图3和图4所示，基底1包括设置在第一阻挡层29背离缓冲层28一侧层叠设置的第一柔性层11、第二阻挡层12和第二柔性层13。
具体地，柔性层的材料可以是聚酰亚胺(PI)、聚酯、聚酰胺等。
具体地，如图3和图4所示，基底1可以设置在玻璃衬底10上，方便后续剥离。
具体地，如图3和图4所示，第一镂空部3靠近第像素单元4的侧壁与隔断结构9之间的距离(即第一镂空部3与隔断结构9之间的无机绝缘层的宽度)可以大于或等于2um，有机发光层7在隔断结构9处断开，以及使阴极8在隔断结构9处断开。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图1所示，第一镂空部3为环绕孔区Q2设置的封闭结构，这样可以尽可能的去除连接桥区Q3的无机绝缘层，最大限度的提升连接桥区的拉伸性能。
在具体实施时，由于水氧容易从孔区侵入像素单元中，为了阻断孔区各个位置的水氧侵入路径，在本公开实施例提供的可拉伸显示基板中，如图3所示，隔断结构9为环绕第一镂空部3设置的封闭结构，即隔断结构9在基底1上的正投影图形与孔区Q2的边界图形相同，即隔断结构9环绕孔区Q2设置，从而能够确保隔断结构9在各个位置防止水氧从孔区Q2侵入像素岛区Q1。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图2所示，一部分孔区Q2包括：沿第一方向X延伸且沿第二方向Y排列的第一子孔区Q21和第二子孔区Q22，以及沿第二方向Y延伸的第三子孔区Q23；另一部分孔区Q2包括：沿第二方向Y延伸且沿第一方向X排列的第四子孔区Q24和第五子孔区(未示出)，以及沿第一方向X延伸的第六子孔区Q26；第一方向X和第二方向Y大致垂直，第六子孔区Q26大致连接第四子孔区Q24和第五子孔区的中心区域；
在可拉伸显示基板进行拉伸时，如图2所示，第一子孔区Q21与第三子孔区Q23连接位置的一侧(拐角)、第二子孔区Q22与第三子孔区Q23连接 位置的一侧(拐角)、第一子孔区Q21的端部一侧和第二子孔区Q22的端部一侧、第四子孔区Q24与第六子孔区Q26连接位置的一侧(拐角)、第五子孔区与第六子孔区Q26连接位置的一侧、第四子孔区Q24的端部一侧和第五子孔区的端部一侧均为拉伸时产生的应力集中处，这些位置的无机绝缘层最先发生断裂，本公开为了避免这些位置的无机绝缘层发生断裂，第一镂空部3至少设置在以下至少之一位置：第一子孔区Q21与第三子孔区Q23连接位置的一侧、第二子孔区Q22与第三子孔区Q23连接位置的一侧、第一子孔区Q21的端部一侧和第二子孔区Q22的端部一侧、第四子孔区Q24与第六子孔区Q26连接位置的一侧、第五子孔区与第六子孔区Q26连接位置的一侧、第四子孔区Q24的端部一侧和第五子孔区的端部一侧。这样一方面可以降低制作大面积第一镂空部3的制作难度，并且可以避免孔区Q2对应的无机绝缘层易断裂位置的无机绝缘层断裂的问题。
需要说明的是，如图1和图2所示，本公开实施例是以孔区Q2的形状近似为“工”字型为例进行示意说明的，当然，孔区Q2的形状不限于此，例如还可以为“T”字型、“一”字型等等。
优选地，在本公开实施例提供的可拉伸显示基板中，如图2所示，第一子孔区Q21与第三子孔区Q23连接位置的一侧、第二子孔区Q22与第三子孔区Q23连接位置的一侧、第一子孔区Q21的端部一侧和第二子孔区Q22的端部一侧、第四子孔区Q24与第六子孔区Q26连接位置的一侧、第五子孔区与第六子孔区Q26连接位置的一侧、第四子孔区Q24的端部一侧和第五子孔区的端部一侧均设置有第一镂空部3。
在本公开实施例提供的可拉伸显示基板中，如图1和图2所示，像素岛区Q1包括至少一个像素单元4，像素岛区Q1的像素分辨率与连接桥区Q3的像素分辨率大致相同。这样可以提升显示分辨率及改善显示不均匀的问题。
在本公开实施例提供的可拉伸显示基板中，如图3和图4所示，多个无机绝缘层包括层叠设置在基底1上的第一阻挡层29、缓冲层28、第一栅绝缘层22、第二栅绝缘层24、层间介质层25、第一钝化层33、第二钝化层34和 无机封装层36，第一阻挡层29、缓冲层28、第一栅绝缘层22、第二栅绝缘层24、层间介质层25、第一钝化层33、第二钝化层34和无机封装层36中的至少一层设置第一镂空部3。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图3和图4所示，层间介质层25、第一钝化层33、第二钝化层34和无机封装层36均设置第一镂空部3，各第一镂空部3大致重叠。当然，在具体实施时，也可以在第一阻挡层29、缓冲层28、第一栅绝缘层22、第二栅绝缘层24均设置第一镂空部3。
需要说明的是，如图3和图4所示，本公开实施例是以第一阻挡层29、缓冲层28、第一栅绝缘层22、第二栅绝缘层24、层间介质层25、第一钝化层33、第二钝化层34和无机封装层36均设置第一镂空部3示意性说明的。当然，多个无机绝缘层设置第一镂空部3(即对各个无机绝缘层进行刻蚀以挖空对应区域的无机绝缘层)，多个无机绝缘层挖空处理可以是从最上侧的无机封装层36挖空至第二柔性层13上方任一无机绝缘层，例如直接挖空到第二柔性层13上方，或直接挖空至第一阻挡层29、缓冲层28、第一栅绝缘层22、第二栅绝缘层24、层间介质层25、第一钝化层33、第二钝化层34和无机封装层36膜层中的任意一层。其中第一阻挡层29、缓冲层28、第一栅绝缘层22、第二栅绝缘层24、层间介质层25膜层挖空可在可拉伸显示基板制备工艺中通过1次或2次刻蚀工艺实现，无机封装层36挖空是在无机封装层36制作完后，通过一次曝光、刻蚀工艺实现刻蚀减薄。当然，所有无机绝缘层挖空也可以在所有无机绝缘层做完后，通过一次曝光、深孔刻蚀工艺实现；具体的刻蚀工艺可以根据实际需要进行选择。
在具体实施时，在本公开实施例提供的可拉伸显示基板中，如图3和图4所示，无机封装层36包括层叠设置在第二钝化层34上的第一无机层和第二无机层；
可拉伸显示基板还包括：位于层间介质层25和第一钝化层33之间的第一平坦层31和第二平坦层32，位于第二钝化层34和无机封装层36之间的像 素界定层35，以及位于第一无机层和第二无机层之间的有机层；
第一平坦层31、第二平坦层32、像素界定层35和有机层中的至少一层在靠近孔区Q2具有第二镂空部，第一镂空部3和第二镂空部大致重叠。
应当理解的是，本公开实施例中提到的第一阻挡层29、缓冲层28、第一栅绝缘层22、第二栅绝缘层24、层间介质层25、第一钝化层33、第二钝化层34和无机封装层36可采用氧化硅、氮化硅等无机绝缘材料制作而成。第一平坦层31、第二平坦层32、像素界定层35和有机层可为有机膜层，即：可采用光刻胶、PI等有机绝缘材料制作而成。
需要说明的是，当在连接桥区Q3刻蚀掉基底1上的所有无机绝缘层时，会将第一平坦层31、第二平坦层32、像素界定层35和有机层也刻蚀掉，即在连接桥区Q3中形成贯穿所有无机绝缘层和有机绝缘层的过孔，即采用第一镂空部3表示即可。
本案的发明人对本公开实施例提供的图3所示的可拉伸显示基板与相关技术中没有在连接桥区设置第一镂空部的可拉伸显示基板的拉伸性能进行了测试，测试发现本公开的拉伸量近似为2％，相关技术中的拉伸量小于1％，因此本公开实施例提供的可拉伸显示基板明显提升了拉伸性能。
基于同一发明构思，本公开实施例还提供了一种上述可拉伸显示基板的制备方法，如图5所示，包括：
S501、提供基底；
S502、在基底上形成像素单元以及与像素单元电连接的信号线；
S503、在基底上形成层叠设置的多个无机绝缘层；其中，多个无机绝缘层中至少一层在靠近孔区具有第一镂空部，第一镂空部在基底上的正投影与信号线和像素单元在基底上的正投影不交叠。
在具体实施时，在本公开实施例提供的上述制备方法中，多个无机绝缘层中至少一层在靠近孔区具有第一镂空部，如图6所示，具体包括：
S601、在基底之上沉积第一阻挡层、缓冲层、第一栅绝缘层、第二栅绝缘层、层间介质层、第一钝化层、第二钝化层和无机封装层；
S602、采用构图工艺，在第一阻挡层、缓冲层、第一栅绝缘层、第二栅绝缘层、层间介质层、第一钝化层、第二钝化层和无机封装层中至少一层形成第一镂空部。
本公开实施例中形成各层结构的工艺可以包括构图工艺和光刻工艺等，其中，构图工艺可以包括沉积膜层、涂覆光刻胶、掩模曝光、显影、刻蚀、剥离光刻胶等处理，而光刻工艺可以包括涂覆膜层、掩模曝光、显影等处理，采用的蒸镀、沉积、涂覆、涂布等均是相关技术中成熟的制备工艺。
下面详细说明图3所示的可拉伸显示基板的制备过程，可以包括如下步骤：
(1)以基底1包括两层柔性层结构为例，基底1划分出像素岛区Q1、孔区Q2和连接桥区Q3，在玻璃衬底10上形成依次层叠设置的第一柔性层11、第二阻挡层12和第二柔性层13；在形成第二阻挡层12时，刻蚀掉孔区Q2对应的第二阻挡层12；接着，在第二柔性层13上形成第一阻挡层29；如图7A所示。柔性层的材料可以是聚酰亚胺(PI)、聚酯、聚酰胺等。阻挡层的材料可以采用氮化硅(SiNx)或氧化硅(SiOx)等，用于提高基底的抗水氧能力。
(2)在第一阻挡层29上形成缓冲层28，在缓冲层28上沉积有源层薄膜，通过构图工艺对有源层薄膜进行构图，在缓冲层28上形成有源层21，在有源层21上形成第一栅绝缘层22，如图7B所示。
(3)在第一栅绝缘层22上沉积一层金属薄膜，通过构图工艺对金属薄膜进行构图，在第一绝缘层22上形成栅极23、第二极板C2和栅线(图未示)以及形成在连接桥区Q3的栅连接线(图未示)，随后，在栅极23上形成第二栅绝缘层24，如图7C所示。
(4)在第二栅绝缘层24上沉积一层金属薄膜，通过构图工艺对金属薄膜进行构图，在第二绝缘层24上形成第一极板C1，第一极板C1的位置与第二极板C2的位置相对应；接着，在第一极板C1所在膜层上形成层间介质层25，对第一栅绝缘层22、第二栅绝缘层24和层间介质层25进行构图，形成位于有源层21两端上方的过孔、对应孔区Q2的过孔以及位于连接桥区Q3对应 的第一镂空部3，如图7D所示。
(5)在层间介质层25上沉积一层金属薄膜(SD1层)，通过构图工艺对金属薄膜进行构图，在层间介质层25上形成源极26、漏极27和信号线2(数据线)，源极26、漏极27分别通过贯穿第一栅绝缘层22、第二栅绝缘层24和层间介质层25的过孔与有源层21连接；接着，在形成有源极26、漏极27的基底1上涂覆有机材料的平坦薄膜，通过掩膜、曝光、显影工艺形成第一平坦层31，第一平坦层31对应源极26位置、对应孔区Q2位置、对应连接桥区Q3第一镂空部3位置均被显影掉，如图7E所示。
(6)在第一平坦层31上沉积一层金属薄膜(SD2层，也可以没有SD2层)，通过构图工艺对金属薄膜进行构图，在第一平坦层31上形成搭接电极30；在搭接电极30所在膜层上形成涂覆有机材料的平坦薄膜，通过掩膜、曝光、显影工艺形成第二平坦层32，第二平坦层32对应搭接电极30位置、对应孔区Q2位置、对应第一镂空部3位置均被显影掉；接着，在第二平坦层32上沉积无机绝缘材料，接着，首先刻蚀掉孔区Q2的缓冲层28和第一阻挡层29以及刻蚀掉孔区Q2的第一柔性层11和第二柔性层13；刻蚀掉第一镂空部3对应位置的无机绝缘材料、缓冲层28和第一阻挡层29，刻蚀掉连接桥区Q3对应形成隔断结构9位置的无机绝缘材料、第二平坦层32和部分第一平坦层31，刻蚀后的无机绝缘材料形成第一钝化层33，如图7F所示。
(7)在第一钝化层33上沉积无机绝缘材料，刻蚀掉孔区Q2位置、第一镂空部3位置对应的无机绝缘材料，以及刻蚀掉搭接电极30对应位置的无机绝缘材料和第一钝化层33，形成第二钝化层34，如图7G所示。
(8)在第二钝化层34上沉积导电薄膜，通过构图工艺对导电薄膜进行构图，形成阳极6，阳极6通过贯穿第一钝化层33和第二钝化层34的过孔与搭接电极30电连接，如图7H所示。在示例性实施方式中，导电薄膜可以为透明导电薄膜/金属薄膜/透明导电薄膜三层堆叠结构，其中透明导电薄膜的材料可以采用氧化铟锡ITO或氧化铟锌IZO，金属薄膜可为Al、Ag、Cu等金属薄膜。
(9)在阳极6上涂覆像素界定薄膜，通过掩膜、曝光、显影工艺，形成像 素界定层35。像素岛区Q1的像素界定层35上设有像素开口，像素开口内的像素界定层35被显影掉，暴露出阳极6的表面；并且像素界定层35对应于孔区Q2位置、连接桥区Q3位置均被显影掉，如图7I所示。
(10)在像素界定层35依次形成有机发光层7和阴极8，有机发光层7形成在像素界定层35的像素开口内并与阳极6连接，有机发光层7和阴极8分别在隔断结构9位置处断开，如图7J所示。具体地，有机发光层6和阴极7可均采用蒸镀工艺制备形成。阴极8的材料可以采用镁(Mg)、银(Ag)、铝(Al)、铜(Cu)和锂(Li)中的任意一种或更多种，或采用上述金属中任意一种或多种制成的合金。
(11)在阴极8上形成无机封装层36，无机封装层36可以包括层叠设置的第一无机层、有机层和第二无机层，对应于孔区Q2位置和对应于第一镂空部3位置的无机封装层36和阴极8、有机发光层6被刻蚀掉，如图7K所示，也即形成了本公开实施例提供的图3所示的可拉伸显示基板。
需要说明的是，本公开实施例是以图3所示的可拉伸显示基板的制备方法为例进行说明的，图4所示的可拉伸显示基板的制备方法与图3所示的制备方法类似，区别在于将图3中第一镂空部3和孔区Q2之间的所有无机绝缘层和有机绝缘层刻蚀掉，形成第一镂空部3和孔区Q2连通的结构，对图4所示的制备方法不再详述，第一镂空部3和孔区Q2之间的无机绝缘层和有机绝缘层的刻蚀与其它区域相同膜层在刻蚀时一起刻蚀即可。
最后，将图3和图4所示的可拉伸显示基板下方的玻璃衬底10与可拉伸显示基板剥离即可制得可拉伸显示基板。
基于同一发明构思，本公开实施例还提供了一种显示装置，包括本公开实施例提供的上述任一种可拉伸显示基板。该显示装置可以为：手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。该显示装置的实施可以参见上述可拉伸显示基板的实施例，重复之处不再赘述。
上述显示装置可以是有机发光二极管显示面板、量子点发光二极管显示 面板、显示模组、曲面屏手机、智能手表等任意具有显示功能的产品或部件。
本公开实施例提供的一种可拉伸显示基板及其制备方法、显示装置，可拉伸显示基板在被拉伸时，靠近孔区相邻的连接桥区承受拉力并变形，本公开通过设置多个无机绝缘层中至少一层在连接桥区中靠近孔区具有第一镂空部，即通过在连接桥区中靠近孔区的位置去除多个无机绝缘层中的至少一层，这样可以提升连接桥区受拉伸时的屈曲变形行为，使得连接桥区不容易发生断裂以及邻近连接桥区的像素岛区不易损坏，从而提升可拉伸显示基板的拉伸性能。
显然，本领域的技术人员可以对本公开进行各种改动和变型而不脱离本公开的精神和范围。这样，倘若本公开的这些修改和变型属于本公开权利要求及其等同技术的范围之内，则本公开也意图包含这些改动和变型在内。

Claims (22)

  1. 一种可拉伸显示基板，其中，包括多个孔区；所述可拉伸显示基板包括：
    基底；
    像素单元，设置在所述基底上；
    信号线，设置在所述基底上，且与所述像素单元电连接；
    多个无机绝缘层，层叠设置在所述基底上，所述多个无机绝缘层中至少一层在靠近所述孔区具有第一镂空部，所述第一镂空部在所述基底上的正投影与所述信号线和所述像素单元在所述基底上的正投影不交叠。
  2. 根据权利要求1所述的可拉伸显示基板，其中，还包括：位于所述孔区之间间隔设置的多个像素岛区，以及位于所述像素岛区和所述孔区之间的连接桥区；
    所述连接桥区包括至少一个所述像素单元，所述第一镂空部位于所述连接桥区，且所述第一镂空部位于所述连接桥区的像素单元和所述孔区之间。
  3. 根据权利要求2所述的可拉伸显示基板，其中，所述连接桥区包括多个所述像素单元，所述信号线在所述基底上的正投影至少位于所述连接桥区的像素单元以及所述连接桥区的像素单元之间区域在所述基底上的正投影内。
  4. 根据权利要求1所述的可拉伸显示基板，其中，所述第一镂空部的延伸方向与所述孔区的边缘大致相同。
  5. 根据权利要求1所述的可拉伸显示基板，其中，所述第一镂空部与所述孔区不连通。
  6. 根据权利要求5所述的可拉伸显示基板，其中，所述第一镂空部靠近所述孔区的侧壁与所述孔区靠近所述第一镂空部的侧壁之间的距离大于或等于2μm。
  7. 根据权利要求5所述的可拉伸显示基板，其中，沿所述像素岛区指向所述孔区的方向上，所述第一镂空部的宽度大于或等于5um。
  8. 根据权利要求1所述的可拉伸显示基板，其中，所述第一镂空部与所述孔区相互连通。
  9. 根据权利要求8所述的可拉伸显示基板，其中，所述第一镂空部中靠近所述孔区的边缘与所述孔区中靠近所述第一镂空部的边缘重叠。
  10. 根据权利要求5、8和9任一项所述的可拉伸显示基板，其中，所述像素单元包括至少一个子像素，所述子像素包括像素电路和发光器件，所述发光器件包括层叠设置的阳极、有机发光层和阴极；所述连接桥区中靠近所述像素单元位置处设置有隔断结构，所述有机发光层在所述隔断结构处断开，所述阴极在所述隔断结构处断开；
    所述第一镂空部靠近所述像素单元的侧壁与所述隔断结构之间的距离大于或等于2um。
  11. 根据权利要求5、6和7任一项所述的可拉伸显示基板，其中，所述第一镂空部为环绕所述孔区设置的封闭结构。
  12. 根据权利要求11所述的可拉伸显示基板，其中，所述隔断结构为环绕所述第一镂空部设置的封闭结构。
  13. 根据权利要求1所述的可拉伸显示基板，其中，一部分所述孔区包括：沿第一方向延伸且沿第二方向排列的第一子孔区和第二子孔区，以及沿所述第二方向延伸的第三子孔区；另一部分所述孔区包括：沿第二方向延伸且沿第一方向排列的第四子孔区和第五子孔区，以及沿所述第一方向延伸的第六子孔区；所述第一方向和所述第二方向大致垂直，所述第三子孔区大致连接所述第一子孔区和所述第二子孔区的中心区域，所述第六子孔区大致连接所述第四子孔区和所述第五子孔区的中心区域；
    所述第一镂空部至少设置在以下至少之一位置：所述第一子孔区与所述第三子孔区连接位置的一侧、所述第二子孔区与所述第三子孔区连接位置的一侧、所述第一子孔区的端部一侧和所述第二子孔区的端部一侧、所述第四子孔区与所述第六子孔区连接位置的一侧、所述第五子孔区与所述第六子孔区连接位置的一侧、所述第四子孔区的端部一侧和所述第五子孔区的端部一 侧。
  14. 根据权利要求13所述的可拉伸显示基板，其中，所述第一子孔区与所述第三子孔区连接位置的一侧、所述第二子孔区与所述第三子孔区连接位置的一侧、所述第一子孔区的端部一侧和所述第二子孔区的端部一侧、所述第四子孔区与所述第六子孔区连接位置的一侧、所述第五子孔区与所述第六子孔区连接位置的一侧、所述第四子孔区的端部一侧和所述第五子孔区的端部一侧均设置有所述第一镂空部。
  15. 根据权利要求1所述的可拉伸显示基板，其中，所述像素岛区包括至少一个所述像素单元，所述像素岛区的像素分辨率与所述连接桥区的像素分辨率大致相同。
  16. 根据权利要求1所述的可拉伸显示基板，其中，所述多个无机绝缘层包括层叠设置在所述基底上的第一阻挡层、缓冲层、第一栅绝缘层、第二栅绝缘层、层间介质层、第一钝化层、第二钝化层和无机封装层，所述第一阻挡层、所述缓冲层、所述第一栅绝缘层、所述第二栅绝缘层、所述层间介质层、所述第一钝化层、所述第二钝化层和所述无机封装层中的至少一层设置所述第一镂空部。
  17. 根据权利要求16所述的可拉伸显示基板，其中，所述层间介质层、所述第一钝化层、所述第二钝化层和所述无机封装层均设置所述第一镂空部，各所述第一镂空部大致重叠。
  18. 根据权利要求16所述的可拉伸显示基板，其中，所述无机封装层包括层叠设置在所述第二钝化层上的第一无机层和第二无机层；
    所述可拉伸显示基板还包括：位于所述层间介质层和所述第一钝化层之间的第一平坦层和第二平坦层，位于所述第二钝化层和所述无机封装层之间的像素界定层，以及位于所述第一无机层和所述第二无机层之间的有机层；
    所述第一平坦层、所述第二平坦层、所述像素界定层和所述有机层中的至少一层在靠近所述孔区具有第二镂空部，所述第一镂空部和所述第二镂空部大致重叠。
  19. 根据权利要求16所述的可拉伸显示基板，其中，所述基底包括一层柔性层，或所述基底包括设置在所述第一阻挡层背离所述缓冲层一侧层叠设置的第一柔性层、第二阻挡层和第二柔性层。
  20. 一种显示装置，其中，包括根据权利要求1-19任一项所述的可拉伸显示基板。
  21. 一种根据权利要求1-19任一项所述的可拉伸显示基板的制备方法，其中，包括：
    提供基底；
    在所述基底上形成像素单元以及与所述像素单元电连接的信号线；
    在所述基底上形成层叠设置的多个无机绝缘层；其中，所述多个无机绝缘层中至少一层在靠近所述孔区具有第一镂空部，所述第一镂空部在所述基底上的正投影与所述信号线和所述像素单元在所述基底上的正投影不交叠。
  22. 根据权利要求21所述的制备方法，其中，所述多个无机绝缘层中至少一层在靠近所述孔区具有第一镂空部，具体包括：
    在所述基底之上沉积第一阻挡层、缓冲层、第一栅绝缘层、第二栅绝缘层、层间介质层、第一钝化层、第二钝化层和无机封装层；
    采用构图工艺，在所述第一阻挡层、所述缓冲层、所述第一栅绝缘层、所述第二栅绝缘层、所述层间介质层、所述第一钝化层、所述第二钝化层和所述无机封装层中至少一层形成所述第一镂空部。
PCT/CN2021/091405 2021-04-30 2021-04-30 一种可拉伸显示基板及其制备方法、显示装置 WO2022226981A1 (zh)

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PCT/CN2021/091405 WO2022226981A1 (zh) 2021-04-30 2021-04-30 一种可拉伸显示基板及其制备方法、显示装置
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