WO2022226931A1 - 用于电子器件的层叠结构及其制造方法 - Google Patents

用于电子器件的层叠结构及其制造方法 Download PDF

Info

Publication number
WO2022226931A1
WO2022226931A1 PCT/CN2021/091157 CN2021091157W WO2022226931A1 WO 2022226931 A1 WO2022226931 A1 WO 2022226931A1 CN 2021091157 W CN2021091157 W CN 2021091157W WO 2022226931 A1 WO2022226931 A1 WO 2022226931A1
Authority
WO
WIPO (PCT)
Prior art keywords
substrate
layer
bonding layer
thermal resistance
debye temperature
Prior art date
Application number
PCT/CN2021/091157
Other languages
English (en)
French (fr)
Inventor
赫然
周宇杰
焦慧芳
Original Assignee
华为技术有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to CN202180093531.8A priority Critical patent/CN116868349A/zh
Priority to PCT/CN2021/091157 priority patent/WO2022226931A1/zh
Publication of WO2022226931A1 publication Critical patent/WO2022226931A1/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface

Definitions

  • Embodiments of the present disclosure generally relate to the field of electronic devices, and more particularly, to a stacked structure for electronic devices and a method of fabricating the same.
  • thermal conductivity materials to dissipate heat from electronic devices is one of the main ways to solve the problem of limited power density.
  • synthetic diamond films can be prepared on electronic devices by chemical vapor deposition.
  • the thermal conductivity of diamond films can be as high as 1000-2200 W/mK, which has broad application prospects in the field of thermal management of high-power integrated circuits and semiconductor devices.
  • FIG. 1 shows a conventional scheme for dissipating heat from electronic devices using high thermal conductivity materials.
  • silicon nitride (SiN) dielectric layers are first fabricated on the surface of the silicon or gallium nitride substrate and on the surface of the diamond substrate, respectively, and then as shown in the right half of Figure 1, The surfaces of the two SiN dielectric layers are bonded to form a stacked structure.
  • the surface of the silicon or gallium nitride substrate can be used to fabricate semiconductor devices, while the diamond substrate is used to dissipate the heat generated by the semiconductor device during operation.
  • the Debye temperatures of silicon, gallium nitride, silicon nitride and diamond are 625K, 600K, 763K, and 1860K, respectively.
  • FIG. 2 shows another conventional solution for dissipating heat from electronic devices using high thermal conductivity materials.
  • CVD chemical vapor deposition
  • diamond can be deposited on the surface of silicon nitride along the rutile growth direction to form a stacked structure.
  • the surface of the gallium nitride substrate can be used to fabricate semiconductor devices, while the diamond substrate is used to dissipate the heat generated by the semiconductor device during operation. Due to the large Debye temperature mismatch between diamond and silicon nitride, the laminated structure shown in FIG. 2 also has the problem of large interfacial thermal resistance caused by the large Debye temperature mismatch.
  • Embodiments of the present disclosure provide a stacked structure for an electronic device and a method for manufacturing the same, aiming to solve the above-mentioned problems and other potential problems of conventional heat dissipation solutions for electronic devices.
  • a stacked structure for an electronic device includes: a first substrate; at least one adjustment layer stacked on the first substrate, the Debye temperature of the at least one adjustment layer is lower than the Debye temperature of the first substrate; at least one a bonding layer stacked on the at least one conditioning layer, the at least one bonding layer having a Debye temperature less than the Debye temperature of the at least one conditioning layer; and a second substrate stacked on the at least one bonding layer layer, the Debye temperature of the second substrate is less than the Debye temperature of the first substrate, and the Debye temperature mismatch between the second substrate and the at least one bonding layer is less than the Debye temperature of the first substrate Debye temperature mismatch between the second substrate and the first substrate.
  • At least one conditioning layer is disposed between the at least one bonding layer and the first substrate.
  • the at least one bonding layer is primarily used to achieve bonding between the first substrate and the second substrate.
  • the at least one adjustment layer is mainly used to adjust the interface thermal resistance between the at least one bonding layer and the first substrate, and at the same time, the at least one adjustment layer can also play a role in realizing the adhesion between the first substrate and the second substrate. effect.
  • the Debye temperature of the at least one conditioning layer is less than the Debye temperature of the first substrate and greater than the Debye temperature of the at least one bonding layer.
  • the Debye temperature mismatch between the at least one conditioning layer and the first substrate can be made smaller than the Debye temperature mismatch between the at least one bonding layer and the first substrate, and the at least one bonding layer is associated with the at least one bonding layer.
  • the Debye temperature mismatch between the one tuning layer is less than the Debye temperature mismatch between the at least one bonding layer and the first substrate. Since the Debye temperature mismatch between the at least one adjustment layer and the first substrate is small, the interfacial thermal resistance between the two is small, so that there is a high heat transfer efficiency between the two.
  • the Debye temperature mismatch between the at least one bonding layer and the at least one adjustment layer is small, the interfacial thermal resistance between the two is also small, resulting in a high heat transfer efficiency between the two.
  • the heat transfer efficiency between the at least one bonding layer and the first substrate can be significantly improved compared to the arrangement in which the bonding layer is used to directly connect the first substrate and the second substrate, thereby improving the heat dissipation performance of the electronic device .
  • the material of the first substrate includes at least one of: diamond, graphene, graphite, and silicon carbide (SiC).
  • the material of the second substrate includes at least one of the following: silicon (Si), gallium nitride (GaN), gallium oxide (Ga2O3), silicon carbide (SiC), silicon-based heteroepitaxial liner substrate, and a silicon carbide-based heteroepitaxial substrate.
  • the at least one adjustment layer includes a first interfacial thermal resistance adjustment layer
  • the at least one bonding layer includes a first bonding layer
  • the material of the first interface thermal resistance adjustment layer includes at least one of the following: titanium nitride (TiN), magnesium oxide (MgO), aluminum oxide (Al2O3), aluminum nitride (AlN), carbide Silicon (SiC), Titanium (Ti), and Chromium (Cr).
  • the material of the first bonding layer includes at least one of the following: silicon (Si), silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), aluminum nitride (AlN) , silicon carbide (SiC), gold (Au), and copper (Cu).
  • the at least one adjustment layer further comprises: a second interface thermal resistance adjustment layer disposed between the first interface thermal resistance adjustment layer and the first bonding layer, the second interface thermal resistance The Debye temperature of the resistance adjustment layer is lower than the Debye temperature of the first interface thermal resistance adjustment layer.
  • the material of the second interface thermal resistance adjustment layer includes at least one of the following: titanium nitride (TiN), magnesium oxide (MgO), and copper (Cu).
  • the at least one adjustment layer further includes: a third interface thermal resistance adjustment layer disposed between the second interface thermal resistance adjustment layer and the first bonding layer, the third interface thermal resistance adjustment layer The Debye temperature of the resistance adjustment layer is lower than the Debye temperature of the second interface thermal resistance adjustment layer.
  • the material of the third interface thermal resistance adjustment layer includes at least one of the following: titanium (Ti) and tantalum (Ta).
  • the at least one bonding layer further includes a second bonding layer disposed between the second substrate and the first bonding layer.
  • the material of the second bonding layer is the same or different from the material of the first bonding layer.
  • the material of the second bonding layer includes at least one of the following: silicon (Si), silicon oxide (SiO2), silicon nitride (SiN), aluminum oxide (Al2O3), aluminum nitride (AlN) , silicon carbide (SiC), gold (Au), and copper (Cu).
  • the stacked structure further includes: at least one additional interface thermal resistance adjustment layer disposed between the second substrate and the at least one bonding layer, the at least one additional interface thermal resistance adjustment layer
  • the Debye temperature is between the Debye temperature of the second substrate and the Debye temperature of the at least one bonding layer.
  • the material of the at least one additional interfacial thermal resistance adjustment layer includes at least one of the following: tantalum (Ta), titanium (Ti), chromium (Cr), and titanium nitride (TiN).
  • the stacked structure further includes: a semiconductor device layer disposed on a surface of the second substrate opposite the at least one bonding layer; and a metal interconnect layer disposed on the semiconductor on the surface of the device layer opposite the second substrate.
  • the first substrate, the at least one conditioning layer, the at least one bonding layer, and the second substrate are aligned in a lateral direction.
  • the first substrate, the at least one conditioning layer, and the at least one bonding layer are aligned in a lateral direction
  • the second substrate has a dimension in the lateral direction larger than the first substrate A substrate
  • the stacked structure further includes an insulating layer surrounding the first substrate, the at least one conditioning layer, and the at least one bonding layer in a lateral direction.
  • the first substrate, the at least one conditioning layer, and the at least one bonding layer are aligned in a lateral direction
  • the second substrate has a dimension in the lateral direction smaller than the first substrate A substrate
  • the stacked structure further includes an insulating layer surrounding the second substrate in a lateral direction.
  • the at least one conditioning layer and the at least one bonding layer are formed on the first substrate by a deposition process, and the at least one bonding layer is connected to the second substrate by a bonding process end.
  • the at least one bonding layer and the at least one conditioning layer are formed on the second substrate by a deposition process, and the first substrate is formed on the at least one conditioning layer by a deposition process superior.
  • a method of fabricating a stacked structure for an electronic device includes: providing a first substrate; providing at least one conditioning layer, the at least one conditioning layer stacked on the first substrate, the at least one conditioning layer having a Debye temperature lower than the first substrate the Debye temperature; providing at least one bonding layer stacked on the at least one conditioning layer, the Debye temperature of the at least one bonding layer being less than the Debye temperature of the at least one conditioning layer; and providing a second substrate stacked on the at least one bonding layer, the second substrate having a Debye temperature less than the Debye temperature of the first substrate, and the first substrate
  • the Debye temperature mismatch between the second substrate and the at least one bonding layer is smaller than the Debye temperature mismatch between the second substrate and the first substrate.
  • the at least one conditioning layer and the at least one bonding layer are formed on the first substrate by a deposition process, and the at least one bonding layer is connected to the second substrate by a bonding process end.
  • the at least one bonding layer and the at least one adjustment layer are formed on the second substrate by a deposition process, and the first substrate is formed on the at least one substrate by a deposition process on a conditioning layer.
  • FIG. 1 shows a schematic diagram of a conventional stack structure for electronic devices.
  • FIG. 2 shows a schematic diagram of another conventional stack structure for electronic devices.
  • FIG. 3 shows a schematic diagram of a stacked structure for an electronic device according to the first embodiment of the present disclosure.
  • FIG. 4 shows a manufacturing process of the laminated structure shown in FIG. 3 .
  • FIG. 5 shows another manufacturing process of the laminated structure shown in FIG. 3 .
  • FIG. 6 shows a schematic diagram of a stacked structure for an electronic device according to a second embodiment of the present disclosure.
  • FIG. 7 shows a schematic diagram of a stacked structure for an electronic device according to a third embodiment of the present disclosure.
  • FIG. 8 shows a schematic diagram of a stacked structure for an electronic device according to a fourth embodiment of the present disclosure.
  • FIG 9 shows a schematic diagram of a stacked structure for an electronic device according to a fifth embodiment of the present disclosure.
  • FIG. 10 shows a schematic diagram of a stacked structure for an electronic device according to a sixth embodiment of the present disclosure.
  • FIG. 11 shows a schematic diagram of a stacked structure for an electronic device according to a seventh embodiment of the present disclosure.
  • FIG. 12 shows a schematic diagram of a stacked structure for an electronic device according to an eighth embodiment of the present disclosure.
  • the term “including” and variations thereof mean open-ended inclusion, ie, "including but not limited to”.
  • the term “or” means “and/or” unless specifically stated otherwise.
  • the term “based on” means “based at least in part on”.
  • the terms “one example embodiment” and “one embodiment” mean “at least one example embodiment.”
  • the term “another embodiment” means “at least one additional embodiment.”
  • the terms “upper”, “lower”, “front”, “rear” and other words indicating placement or positional relationship are all based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the principles of the present disclosure, rather than indicating or implying The elements referred to must have, be constructed, or operate in a particular orientation and are therefore not to be construed as limitations of the present disclosure.
  • Embodiments of the present disclosure provide a stacked structure for an electronic device and a method for fabricating the same, so as to solve the above-mentioned problems and other potential problems of conventional solutions for dissipating heat from electronic devices using high thermal conductivity materials.
  • a "Debye temperature mismatch" is employed to describe the difference between the Debye temperatures of two materials.
  • the Debye temperatures of the two materials are assumed to be ⁇ D1 and ⁇ D2 , respectively, where ⁇ D1 is the Debye temperature of the material with the larger Debye temperature of the two materials, and ⁇ D2 is the The Debye temperature of a material with a smaller Debye temperature, ie ⁇ D1 > ⁇ D2 .
  • R ⁇ 2 the Debye temperature mismatch between the two materials is small.
  • R>2 the Debye temperature mismatch between the two materials is larger.
  • Table 1 shows the Debye temperatures for some materials that can be used in embodiments of the present disclosure. It should be understood that the listed materials are merely examples of materials that may be applied to embodiments of the present disclosure, and are not intended to be exhaustive of materials that may be used in embodiments of the present disclosure. Other materials having different Debye temperatures can be readily envisioned by those skilled in the art in light of the teachings of the present disclosure.
  • Table 2 shows the Debye temperature mismatch between various materials, where each term is the Debye temperature of the material with the larger Debye temperature and the material with the smaller Debye temperature of the corresponding two materials The ratio between the Debye temperatures.
  • FIG. 3 shows a schematic diagram of a stacked structure for an electronic device according to the first embodiment of the present disclosure.
  • the stacked structure 100 generally includes a first substrate 21 , a first interface thermal resistance adjustment layer 31 , a first bonding layer 41 and a second substrate 22 .
  • the first interface thermal resistance adjustment layer 31 is stacked on the first substrate 21 .
  • the first bonding layer 41 is stacked on the first interface thermal resistance adjustment layer 31 .
  • the second substrate 22 is stacked on the first bonding layer 41 .
  • the surface of the second substrate 22 opposite to the first bonding layer 41 is used to fabricate the semiconductor device, and the first substrate 21 is used to dissipate the heat generated by the semiconductor device during operation.
  • the first substrate 21 is made of a material with higher thermal conductivity, so that the Debye temperature of the second substrate 22 is lower than that of the first substrate 21 .
  • the first bonding layer 41 is used to realize the connection between the first substrate 21 and the second substrate 22 .
  • the Debye temperature of the first bonding layer 41 is smaller than the Debye temperature of the first substrate 21 , and the Debye temperature mismatch between the second substrate 22 and the first bonding layer 41 is smaller than that of the second substrate 22 and the first substrate Debye temperature mismatch between base 21.
  • There is a large Debye temperature mismatch between the first bonding layer 41 and the first substrate 21 that is, the ratio between the Debye temperature of the first substrate 21 and the Debye temperature of the first bonding layer 41 is large .
  • the interfacial thermal resistance between two solid materials is affected by the degree of Debye temperature mismatch between the materials.
  • the Debye temperature mismatch between the two solid materials is large, the phonon scattering is severe, resulting in a large interfacial thermal resistance between the two materials, so the heat transfer efficiency between the materials will decrease.
  • the first interface thermal resistance adjustment layer 31 is provided between the first bonding layer 41 and the first substrate 21 .
  • the Debye temperature of the first interfacial thermal resistance adjustment layer 31 is lower than the Debye temperature of the first substrate 21 and greater than the Debye temperature of the first bonding layer 41 .
  • the Debye temperature mismatch between the first interface thermal resistance adjustment layer 31 and the first substrate 21 can be made smaller than the Debye temperature mismatch between the first bonding layer 41 and the first substrate 21 , And the Debye temperature mismatch between the first bonding layer 41 and the first interface thermal resistance adjustment layer 31 is smaller than the Debye temperature mismatch between the first bonding layer 41 and the first substrate 21 . Since the Debye temperature mismatch between the first interfacial thermal resistance adjusting layer 31 and the first substrate 21 is small, the interfacial thermal resistance between the two is small, resulting in higher heat transfer between the two. efficiency.
  • the interfacial thermal resistance between the two is also small, resulting in a higher interfacial thermal resistance between the two. heat transfer efficiency.
  • the heat transfer efficiency between the first bonding layer 41 and the first substrate 21 can be significantly improved.
  • Table 3 shows some examples of materials that can be applied to the laminated structure 100 of the first embodiment. It should be understood that the listed materials are only some exemplary materials that may be applied to the first embodiment and are not intended to be exhaustive of the materials available in the first embodiment. Those skilled in the art will readily appreciate the use of other materials in light of the teachings of this disclosure.
  • the material of the first substrate 21 is diamond
  • the material of the second substrate 22 is gallium nitride
  • the material of the first bonding layer 41 is silicon nitride
  • the material of the first interface thermal resistance adjustment layer 31 is nitride
  • the Debye temperature mismatch between the first interface thermal resistance adjustment layer 31 and the first substrate 21 is less than 2, so the interface thermal resistance between the two is relatively small, so that there is a higher thermal conductivity between the two. Thermal efficiency.
  • the Debye temperature mismatch between the first bonding layer 41 and the first interfacial thermal resistance adjusting layer 31 is also less than 2, so the interfacial thermal resistance between the two is small, so that there is a higher heat transfer efficiency. In this way, compared to the arrangement in which the first substrate 21 and the second substrate 22 are directly connected using the first bonding layer 41, the heat transfer efficiency between the first bonding layer 41 and the first substrate 21 can be significantly improved.
  • the first interface thermal resistance adjustment layer 31 and the first interface thermal resistance adjustment layer 31 can also be Smaller interface thermal resistance is achieved between the first substrates 21 and between the first bonding layer 41 and the first interface thermal resistance adjusting layer 31 , thereby improving the heat transfer efficiency of the stacked structure 100 .
  • the first substrate 21, the second substrate 22, the first bonding layer 41 and the first interface thermal resistance adjusting layer 31 are materials having the Debye temperature relationship as described above, it is also possible to heat the first interface Smaller interface thermal resistance is achieved between the resistance adjustment layer 31 and the first substrate 21 and between the first bonding layer 41 and the first interface thermal resistance adjustment layer 31 , thereby improving the heat transfer efficiency of the stacked structure 100 .
  • the Debye temperature of the second substrate 22 is lower than the Debye temperature of the first substrate 21
  • the Debye temperature of the first bonding layer 41 is lower than the Debye temperature of the first substrate 21
  • the second substrate 22 is the same as the Debye temperature of the first substrate 21 .
  • the Debye temperature mismatch between the first bonding layers 41 is smaller than the Debye temperature mismatch between the second substrate 22 and the first substrate 21 , and the Debye temperature of the first interfacial thermal resistance adjustment layer 31 is smaller than the first The Debye temperature of the substrate 21 is greater than the Debye temperature of the first bonding layer 41 .
  • the first substrate 21 , the first interface thermal resistance adjustment layer 31 , the first bonding layer 41 , and the second substrate 22 are substantially in the lateral direction X Align.
  • the first substrate 21 , the first interfacial thermal resistance adjustment layer 31 , the first bonding layer 41 , and the second substrate 22 may be misaligned in the lateral direction X, which will be described below in conjunction with FIGS. 7 and 22 .
  • Fig. 8 is explained.
  • the laminated structure 100 of the first embodiment can be manufactured using various processes. 4 and 5 illustrate an exemplary manufacturing process of the stacked structure 100 of the first embodiment.
  • the first substrate 21 is provided first.
  • the first interfacial thermal resistance adjustment layer 31 and the first bonding layer 41 are sequentially formed on the first substrate 21 through a deposition process.
  • the second substrate 22 is connected to the first bonding layer 41 through a bonding process, thereby obtaining the laminated structure 100 of the first embodiment.
  • the second substrate 22 is first provided.
  • the first bonding layer 41 and the first interface thermal resistance adjusting layer 31 are sequentially formed on the second substrate 22 through a deposition process.
  • the first substrate 21 is formed on the first interface thermal resistance adjustment layer 31 through a deposition process, thereby obtaining the stacked structure 100 of the first embodiment.
  • FIGS. 4 and 5 merely illustrate an exemplary fabrication process of the stacked structure 100 of the first embodiment, and are not intended to limit the scope of the present disclosure. Based on the teachings of the present disclosure, those skilled in the art can easily conceive of using other processes to manufacture the stacked structure 100 of the first embodiment.
  • FIG. 6 shows a schematic diagram of a stacked structure for an electronic device according to a second embodiment of the present disclosure.
  • the stacked structure 100 of the second embodiment includes a first substrate 21 , a first interface thermal resistance adjustment layer 31 , a first bonding layer 41 , a second substrate 22 , and a semiconductor device layer 6 arranged in order. and metal interconnect layer 7.
  • the first substrate 21 , the first interface thermal resistance adjusting layer 31 , the first bonding layer 41 and the second substrate 22 in the laminated structure 100 of the second embodiment are the same as the first substrate in the laminated structure 100 of the first embodiment
  • the bottom 21 , the first interface thermal resistance adjustment layer 31 , the first bonding layer 41 and the second substrate 22 have the same arrangement.
  • the semiconductor device layer 6 is provided on the surface of the second substrate 22 opposite to the first bonding layer 41 .
  • the metal interconnection layer 7 is provided on the surface of the semiconductor device layer 6 opposite to the second substrate 22 .
  • the heat generated by the semiconductor device layer 6 during operation can be transferred to the first substrate 21 via the second substrate 22 , the first bonding layer 41 and the first interfacial thermal resistance adjusting layer 31 , and then via the first substrate 21 .
  • the substrate 21 is dissipated. Since the first interface thermal resistance adjustment layer 31 is provided between the first bonding layer 41 and the first substrate 21 , heat is generated between the first bonding layer 41 and the first interface thermal resistance adjustment layer 31 and at the first interface. Smaller interface thermal resistances are respectively achieved between the resistance adjustment layer 31 and the first substrate 21 , thereby improving the heat transfer efficiency of the stacked structure 100 .
  • the first substrate 21 , the first interface thermal resistance adjustment layer 31 , the first bonding layer 41 , the second substrate 22 , the semiconductor device layer 6 , and The metal interconnect layers 7 are substantially aligned in the lateral direction X.
  • the first substrate 21 , the first interfacial thermal resistance adjustment layer 31 , the first bonding layer 41 , the second substrate 22 , the semiconductor device layer 6 , and the metal interconnection layer 7 in the lateral direction X may be Misalignment, which will be explained below in conjunction with FIGS. 7 and 8 .
  • FIG. 7 shows a schematic diagram of a stacked structure for an electronic device according to a third embodiment of the present disclosure.
  • the stacked structure 100 of the third embodiment includes a first substrate 21 , a first interface thermal resistance adjustment layer 31 , a first bonding layer 41 , a second substrate 22 , and a semiconductor device layer 6 arranged in order. , a metal interconnect layer 7 , and a micro-bump 9 .
  • the stacked structure 100 of the third embodiment has a similar arrangement to the stacked structure 100 of the second embodiment, the main difference being that the first substrate 21 , the first interface thermal resistance adjustment layer 31 , and the first bonding layer 41 are arranged in the lateral direction X are not aligned with the second substrate 22 .
  • micro-bumps 9 are provided on the metal interconnection layer 7 for realizing electrical connection between the stacked structure 100 and external circuits.
  • the first substrate 21 , the first interface thermal resistance adjustment layer 31 , and the first bonding layer 41 are substantially aligned in the lateral direction X, and the second substrate
  • the size of the bottom 22 in the lateral direction X is larger than that of the first substrate 21 .
  • the stacked structure 100 further includes an insulating layer 8 surrounding the first substrate 21 , the first interface thermal resistance adjusting layer 31 , and the first bonding layer 41 in the lateral direction X.
  • the second substrate 22 , the semiconductor device layer 6 , and the metal interconnect layer 7 are substantially aligned in the lateral direction X.
  • the outer edges of insulating layer 8 are substantially aligned with second substrate 22 , semiconductor device layer 6 , and metal interconnect layer 7 .
  • the heat generated by the semiconductor device layer 6 during operation can be transferred to the first substrate 21 via the second substrate 22 , the first bonding layer 41 and the first interfacial thermal resistance adjusting layer 31 , and then via the first substrate 21 .
  • the substrate 21 is dissipated. Since the first interface thermal resistance adjustment layer 31 is provided between the first bonding layer 41 and the first substrate 21 , heat is generated between the first bonding layer 41 and the first interface thermal resistance adjustment layer 31 and at the first interface. Smaller interface thermal resistances are respectively achieved between the resistance adjustment layer 31 and the first substrate 21 , thereby improving the heat transfer efficiency of the stacked structure 100 .
  • FIG. 8 shows a schematic diagram of a stacked structure for an electronic device according to a fourth embodiment of the present disclosure.
  • the stacked structure 100 of the fourth embodiment includes a first substrate 21 , a first interface thermal resistance adjustment layer 31 , a first bonding layer 41 , a second substrate 22 , and a semiconductor device layer 6 arranged in order , a metal interconnect layer 7 , and a micro-bump 9 .
  • the stacked structure 100 of the fourth embodiment has a similar arrangement to the stacked structure 100 of the second embodiment, the main difference being that the first substrate 21 , the first interface thermal resistance adjustment layer 31 , and the first bonding layer 41 are arranged in the lateral direction X are not aligned with the second substrate 22 .
  • micro-bumps 9 are provided on the metal interconnection layer 7 for realizing electrical connection between the stacked structure 100 and external circuits.
  • the first substrate 21 , the first interface thermal resistance adjustment layer 31 , and the first bonding layer 41 are substantially aligned in the lateral direction X, and the second substrate
  • the size of the bottom 22 in the lateral direction X is smaller than that of the first substrate 21 .
  • the second substrate 22 , the semiconductor device layer 6 , and the metal interconnect layer 7 are substantially aligned in the lateral direction X.
  • the stacked structure 100 also includes an insulating layer 8 surrounding the second substrate 22 , the semiconductor device layer 6 , and the metal interconnect layer 7 in the lateral direction X.
  • the outer edge of the insulating layer 8 is substantially aligned with the first substrate 21 , the first interfacial thermal resistance adjustment layer 31 , and the first bonding layer 41 .
  • the heat generated by the semiconductor device layer 6 during operation can be transferred to the first substrate 21 via the second substrate 22 , the first bonding layer 41 and the first interfacial thermal resistance adjusting layer 31 , and then via the first substrate 21 .
  • the substrate 21 is dissipated. Since the first interface thermal resistance adjustment layer 31 is provided between the first bonding layer 41 and the first substrate 21 , heat is generated between the first bonding layer 41 and the first interface thermal resistance adjustment layer 31 and at the first interface. Smaller interface thermal resistances are respectively achieved between the resistance adjustment layer 31 and the first substrate 21 , thereby improving the heat transfer efficiency of the stacked structure 100 .
  • FIG. 9 shows a schematic diagram of a stacked structure for an electronic device according to a fifth embodiment of the present disclosure.
  • the stacked structure 100 of the fifth embodiment has a similar arrangement to the stacked structure 100 of the first embodiment shown in FIG. 3 , the main difference is that the stacked structure 100 further includes a second interface thermal resistance adjustment layer 32 .
  • the second interface thermal resistance adjustment layer 32 is disposed between the first interface thermal resistance adjustment layer 31 and the first bonding layer 41 .
  • the Debye temperature of the second interface thermal resistance adjustment layer 32 is lower than the Debye temperature of the first interface thermal resistance adjustment layer 31 and greater than the Debye temperature of the first bonding layer 41 .
  • Table 4 shows some examples of materials that can be applied to the laminated structure 100 of the fifth embodiment. It should be understood that the listed materials are only some exemplary materials that may be applied to the fifth embodiment and are not intended to be exhaustive of the materials that may be used in the fifth embodiment. Those skilled in the art will readily appreciate the use of other materials in light of the teachings of this disclosure.
  • the stacked structure 100 of the fifth embodiment can be manufactured using various processes.
  • the first interfacial thermal resistance adjusting layer 31 , the second interfacial thermal resistance adjusting layer 32 , and the first bonding layer 41 may be sequentially formed on the first substrate 21 through a deposition process. Subsequently, the second substrate 22 may be connected to the first bonding layer 41 through a bonding process, thereby obtaining the stacked structure 100 of the fifth embodiment.
  • the first bonding layer 41 , the second interface thermal resistance adjustment layer 32 , and the first interface thermal resistance adjustment layer 31 may be sequentially formed on the second substrate 22 through a deposition process. Subsequently, the first substrate 21 may be formed on the first interface thermal resistance adjustment layer 31 through a deposition process, thereby obtaining the stacked structure 100 of the first embodiment.
  • interface thermal resistance adjustment layers may be disposed between the first bonding layer 41 and the first substrate 21 to further reduce the interface thermal resistance between adjacent layers.
  • the bonding performance between the second substrate 22 and the first bonding layer 41 may not be strong enough.
  • more bonding layers may be provided between the first bonding layer 41 and the second substrate 22 , one such structure is shown in FIG. 10 .
  • FIG. 10 shows a schematic diagram of a stacked structure for an electronic device according to a sixth embodiment of the present disclosure.
  • the laminated structure 100 of the sixth embodiment has a similar arrangement to the laminated structure 100 of the first embodiment as shown in FIG. 3 , and the main difference is that the laminated structure 100 further includes the second bonding layer 42 .
  • the second bonding layer 42 is provided between the second substrate 22 and the first bonding layer 41 .
  • the material of the second bonding layer 42 and the material of the first bonding layer 41 may be the same or different. As shown in the left half of FIG.
  • the first interfacial thermal resistance adjustment layer 31 and the first bonding layer 41 may be sequentially formed on the first substrate 21 by a deposition process, and the second bonding layer 42 may be formed by a deposition process formed on the second substrate 22 . Subsequently, as shown in the right half of FIG. 10 , the first bonding layer 41 and the second bonding layer 42 may be connected together through a bonding process, thereby forming the stacked structure 100 .
  • utilizing the second bonding layer 42 in the arrangement of the sixth embodiment can enhance the bonding strength between the second substrate 22 and other layers, thereby making the laminated structure 100 is more stable and reliable and has higher heat transfer efficiency.
  • bonding layers may be disposed between the first interface thermal resistance adjustment layer 31 and the second substrate 22 to further enhance the bonding strength between the second substrate 22 and other layers.
  • Table 5 shows some examples of materials that can be applied to the laminated structure 100 of the sixth embodiment. It should be understood that the listed materials are only some exemplary materials that may be applied to the sixth embodiment, and are not intended to be exhaustive of the materials available in the sixth embodiment. Those skilled in the art will readily appreciate the use of other materials in light of the teachings of this disclosure.
  • FIG. 11 shows a schematic diagram of a stacked structure for an electronic device according to a seventh embodiment of the present disclosure.
  • the stacked structure 100 of the seventh embodiment has a similar arrangement to the stacked structure 100 of the sixth embodiment as shown in FIG. 10 , and the main difference is that the stacked structure 100 further includes the second interface thermal resistance adjustment layer 32 .
  • the second interface thermal resistance adjustment layer 32 is disposed between the first interface thermal resistance adjustment layer 31 and the first bonding layer 41 .
  • the Debye temperature of the second interface thermal resistance adjustment layer 32 is lower than the Debye temperature of the first interface thermal resistance adjustment layer 31 and greater than the Debye temperature of the first bonding layer 41.
  • Table 6 shows some examples of materials that can be applied to the laminated structure 100 of the seventh embodiment. It should be understood that the listed materials are only some exemplary materials that may be applied to the seventh embodiment and are not intended to be exhaustive of the materials that may be used in the seventh embodiment. Those skilled in the art will readily appreciate the use of other materials in light of the teachings of this disclosure.
  • FIG. 12 shows a schematic diagram of a stacked structure for an electronic device according to an eighth embodiment of the present disclosure.
  • the stacked structure 100 of the eighth embodiment has a similar arrangement to the stacked structure 100 of the seventh embodiment shown in FIG. 11 , the main difference is that the stacked structure 100 further includes a third interface thermal resistance adjustment layer 33 and an additional interface thermal resistance adjustment Layer 5.
  • the third interface thermal resistance adjustment layer 33 is disposed between the second interface thermal resistance adjustment layer 32 and the first bonding layer 41 .
  • the Debye temperature of the third interface thermal resistance adjustment layer 33 is lower than the Debye temperature of the second interface thermal resistance adjustment layer 32 and greater than the Debye temperature of the first bonding layer 41 .
  • the additional interface thermal resistance adjustment layer 5 is provided between the second substrate 22 and the second bonding layer 42 .
  • the Debye temperature of the additional interface thermal resistance adjustment layer 5 is between the Debye temperature of the second substrate 22 and the Debye temperature of the second bonding layer 42 .
  • the additional interface thermal resistance adjustment layer 5 between the second substrate 22 and the second bonding layer 42 , it is possible to adjust the interface thermal resistance between the second substrate 22 and the additional interface thermal resistance adjustment layer 5 and at the additional interface thermal resistance A smaller interfacial thermal resistance is achieved between the layer 5 and the second bonding layer 42 , thereby further improving the heat transfer efficiency of the stacked structure 100 .
  • more additional interface thermal resistance adjustment layers 5 may be provided between the second substrate 22 and the second bonding layer 42 to further reduce the interface thermal resistance between adjacent layers and improve heat transfer efficiency.
  • the additional interfacial thermal resistance adjusting layer 5 may be directly disposed between the second substrate 22 and the first bonding layer 41 .
  • Table 7 shows some examples of materials that can be applied to the laminated structure 100 of the eighth embodiment. It should be understood that the listed materials are only some exemplary materials that may be applied to the eighth embodiment and are not intended to be exhaustive of the materials available in the eighth embodiment. Those skilled in the art will readily appreciate the use of other materials in light of the teachings of this disclosure.
  • the at least one adjustment layer disposed between the at least one bonding layer and the first substrate may include more or fewer interfacial thermal resistance adjustment layers.
  • the stacked structure 100 may be applied to various electronic devices, including but not limited to high-power chips, system-on-chip (SoC), high electron mobility transistor (HEMT), monolithic microwave integrated circuit (MMIC), Lasers etc.
  • SoC system-on-chip
  • HEMT high electron mobility transistor
  • MMIC monolithic microwave integrated circuit
  • Lasers etc.
  • Embodiments according to the present disclosure also provide a method for manufacturing the above-mentioned laminated structure 100 , including: providing a first substrate 21 ; providing at least one adjustment layer, and the at least one adjustment layer is stacked and disposed on the first substrate 21 , the Debye temperature of at least one adjustment layer is lower than the Debye temperature of the first substrate 21; at least one bonding layer is provided, at least one bonding layer is stacked on the at least one adjustment layer, and the Debye temperature of at least one bonding layer is lower than at least one bonding layer adjusting the Debye temperature of the layer; and providing a second substrate 22, the second substrate 22 being stacked on the at least one bonding layer, the Debye temperature of the second substrate 22 being less than the Debye temperature of the first substrate 21, and The Debye temperature mismatch between the second substrate 22 and the at least one bonding layer is smaller than the Debye temperature mismatch between the second substrate 22 and the first substrate 21 .
  • the at least one conditioning layer and the at least one bonding layer are formed on the first substrate 21 by a deposition process, and the at least one bonding layer is connected to the second substrate 22 by a bonding process.
  • At least one bonding layer and at least one conditioning layer are formed on the second substrate 22 by a deposition process, and the first substrate 21 is formed on the at least one conditioning layer by a deposition process.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

本公开的实施例涉及用于电子器件的层叠结构及其制造方法。该层叠结构包括：第一衬底；至少一个调节层，堆叠设置在第一衬底上，至少一个调节层的德拜温度小于第一衬底的德拜温度；至少一个接合层，堆叠设置在至少一个调节层上，至少一个接合层的德拜温度小于至少一个调节层的德拜温度；以及第二衬底，堆叠设置在至少一个接合层上，第二衬底的德拜温度小于第一衬底的德拜温度，并且第二衬底与至少一个接合层之间的德拜温度失配小于第二衬底与第一衬底之间的德拜温度失配。利用上述层叠结构，可以显著提升电子器件的散热性能。

Description

用于电子器件的层叠结构及其制造方法 技术领域
本公开的实施例总体上涉及电子器件领域，并且更具体地，涉及一种用于电子器件的层叠结构及其制造方法。
背景技术
随着智能时代对计算机算力日益增长的需求以及集成电路技术的飞速发展，集成电路的功率密度不断提高。然而，当前的电子系统的散热能力限制了功率密度的进一步提升。随着电子器件的功率密度的增大，电子器件的结温显著上升，从而导致器件性能下降以及可靠性降低等风险。
利用高热导率材料对电子器件进行散热是解决功率密度受限这一问题的主要途径之一。例如，可以采用化学气相沉积方法在电子器件上制备人造金刚石薄膜，金刚石薄膜的热导率可高达1000-2200W/mK，这在大功率集成电路和半导体器件的热管理领域具有广阔的应用前景。然而，集成电路或半导体器件与由高热导率材料制成的衬底之间存在较大的界面热阻，较大的界面热阻会降低系统的散热能力。
图1示出了一种常规的利用高热导率材料对电子器件进行散热的方案。如图1的左半部分所示，首先在硅或氮化镓衬底的表面和金刚石衬底的表面上分别制作氮化硅(SiN)介质层，然后如图1的右半部分所示，将两个SiN介质层的表面进行键合，以形成层叠结构。硅或氮化镓衬底的表面可以用于制作半导体器件，而金刚石衬底用于对半导体器件在工作时产生的热量进行消散。硅、氮化镓、氮化硅和金刚石的德拜温度分别为625K、600K、763K、1860K。氮化硅与硅之间的德拜温度失配为763K/625K＝1.22，氮化硅与氮化镓之间的德拜温度失配为763K/600K＝1.27，金刚石与氮化硅之间的德拜温度失配为1860K/763K＝2.44。可见，氮化硅与硅或氮化镓之间的德拜温度失配较小，而金刚石与氮化硅之间的德拜温度失配很大，这将会导致在氮化硅与金刚石之间存在较大的界面热阻。由于较大的界面热阻会降低系统的散热能力，因此如图1所示的层叠结构的散热性能较差。
图2示出了另一种常规的利用高热导率材料对电子器件进行散热的方案。如图2所示，可以首先采用化学气相沉积(CVD)在氮化镓的表面上沉积氮化硅，随后可以沿着金光石生长方向在氮化硅表面上沉积金刚石，从而形成层叠结构。类似地，氮化镓衬底的表面可以用于制作半导体器件，而金刚石衬底用于对半导体器件在工作时产生的热量进行消散。由于金刚石与氮化硅之间的德拜温度失配很大，因此图2所示的层叠结构同样存在由德拜温度失配较大带来的界面热阻较大的问题。
因此，为了充分发挥诸如金刚石之类的高热导率材料的散热能力，需要进一步降低用于制作集成电路或半导体器件的衬底与高热导率材料衬底之间的界面热阻。
发明内容
本公开的实施例提供了一种用于电子器件的层叠结构及其制造方法，旨在解决常规的电子器件散热方案存在的上述问题以及其他潜在的问题。
根据本公开的一个方面，提供了一种用于电子器件的层叠结构。该层叠结构包括： 第一衬底；至少一个调节层，堆叠设置在所述第一衬底上，所述至少一个调节层的德拜温度小于所述第一衬底的德拜温度；至少一个接合层，堆叠设置在所述至少一个调节层上，所述至少一个接合层的德拜温度小于所述至少一个调节层的德拜温度；以及第二衬底，堆叠设置在所述至少一个接合层上，所述第二衬底的德拜温度小于所述第一衬底的德拜温度，并且所述第二衬底与所述至少一个接合层之间的德拜温度失配小于所述第二衬底与所述第一衬底之间的德拜温度失配。
在根据本公开的实施例中，在至少一个接合层与第一衬底之间设置了至少一个调节层。至少一个接合层主要用于实现第一衬底与第二衬底之间的粘接。至少一个调节层主要用于调节至少一个接合层与第一衬底之间的界面热阻，同时该至少一个调节层也能起到实现第一衬底与第二衬底之间的粘接的作用。至少一个调节层的德拜温度小于第一衬底的德拜温度并且大于至少一个接合层的德拜温度。利用这样的布置，可以使得至少一个调节层与第一衬底之间的德拜温度失配小于至少一个接合层与第一衬底之间的德拜温度失配，并且至少一个接合层与至少一个调节层之间的德拜温度失配小于至少一个接合层与第一衬底之间的德拜温度失配。由于至少一个调节层与第一衬底之间的德拜温度失配较小，因此二者之间的界面热阻较小，从而使得二者之间具有较高的传热效率。此外，由于至少一个接合层与至少一个调节层之间的德拜温度失配较小，因此二者之间的界面热阻也较小，从而使得二者之间具有较高的传热效率。以此方式，与利用接合层直接连接第一衬底和第二衬底的布置相比，可以显著提升至少一个接合层与第一衬底之间的传热效率，从而提升电子器件的散热性能。
在一些实施例中，所述第一衬底的材料包括以下至少一项：金刚石、石墨烯、石墨、以及碳化硅(SiC)。
在一些实施例中，所述第二衬底的材料包括以下至少一项：硅(Si)、氮化镓(GaN)、氧化镓(Ga2O3)、碳化硅(SiC)、硅基异质外延衬底、以及碳化硅基异质外延衬底。
在一些实施例中，所述至少一个调节层包括第一界面热阻调节层，并且所述至少一个接合层包括第一接合层。
在一些实施例中，所述第一界面热阻调节层的材料包括以下至少一项：氮化钛(TiN)、氧化镁(MgO)、氧化铝(Al2O3)、氮化铝(AlN)、碳化硅(SiC)、钛(Ti)、以及铬(Cr)。
在一些实施例中，所述第一接合层的材料包括以下至少一项：硅(Si)、氧化硅(SiO2)、氮化硅(SiN)、氧化铝(Al2O3)、氮化铝(AlN)、碳化硅(SiC)、金(Au)、以及铜(Cu)。
在一些实施例中，所述至少一个调节层还包括：第二界面热阻调节层，设置在所述第一界面热阻调节层与所述第一接合层之间，所述第二界面热阻调节层的德拜温度小于所述第一界面热阻调节层的德拜温度。
在一些实施例中，所述第二界面热阻调节层的材料包括以下至少一项：氮化钛(TiN)、氧化镁(MgO)、以及铜(Cu)。
在一些实施例中，所述至少一个调节层还包括：第三界面热阻调节层，设置在所述第二界面热阻调节层与所述第一接合层之间，所述第三界面热阻调节层的德拜温度小于所述第二界面热阻调节层的德拜温度。
在一些实施例中，所述第三界面热阻调节层的材料包括以下至少一项：钛(Ti)和 钽(Ta)。
在一些实施例中，所述至少一个接合层还包括：第二接合层，设置在所述第二衬底与所述第一接合层之间。
在一些实施例中，所述第二接合层的材料与所述第一接合层的材料相同或不同。
在一些实施例中，所述第二接合层的材料包括以下至少一项：硅(Si)、氧化硅(SiO2)、氮化硅(SiN)、氧化铝(Al2O3)、氮化铝(AlN)、碳化硅(SiC)、金(Au)、以及铜(Cu)。
在一些实施例中，所述层叠结构还包括：至少一个附加界面热阻调节层，设置在所述第二衬底与所述至少一个接合层之间，所述至少一个附加界面热阻调节层的德拜温度介于所述第二衬底的德拜温度与所述至少一个接合层的德拜温度之间。
在一些实施例中，所述至少一个附加界面热阻调节层的材料包括以下至少一项：钽(Ta)、钛(Ti)、铬(Cr)、以及氮化钛(TiN)。
在一些实施例中，所述层叠结构还包括：半导体器件层，设置在所述第二衬底的与所述至少一个接合层相背的表面上；以及金属互连层，设置在所述半导体器件层的与所述第二衬底相背的表面上。
在一些实施例中，所述第一衬底、所述至少一个调节层、所述至少一个接合层、以及所述第二衬底在横向方向上对齐。
在一些实施例中，所述第一衬底、所述至少一个调节层、以及所述至少一个接合层在横向方向上对齐，并且所述第二衬底在横向方向上的尺寸大于所述第一衬底，以及所述层叠结构还包括绝缘层，所述绝缘层在横向方向上包围所述第一衬底、所述至少一个调节层、以及所述至少一个接合层。
在一些实施例中，所述第一衬底、所述至少一个调节层、以及所述至少一个接合层在横向方向上对齐，并且所述第二衬底在横向方向上的尺寸小于所述第一衬底，以及所述层叠结构还包括绝缘层，所述绝缘层在横向方向上包围所述第二衬底。
在一些实施例中，所述至少一个调节层和所述至少一个接合层通过沉积工艺形成于所述第一衬底上，并且所述至少一个接合层通过键合工艺连接至所述第二衬底。
在一些实施例中，所述至少一个接合层和所述至少一个调节层通过沉积工艺形成于所述第二衬底上，并且所述第一衬底通过沉积工艺形成于所述至少一个调节层上。
根据本公开的另一方面，提供了一种制造用于电子器件的层叠结构的方法。该方法包括：提供第一衬底；提供至少一个调节层，所述至少一个调节层堆叠设置在所述第一衬底上，所述至少一个调节层的德拜温度小于所述第一衬底的德拜温度；提供至少一个接合层，所述至少一个接合层堆叠设置在所述至少一个调节层上，所述至少一个接合层的德拜温度小于所述至少一个调节层的德拜温度；以及提供第二衬底，所述第二衬底堆叠设置在所述至少一个接合层上，所述第二衬底的德拜温度小于所述第一衬底的德拜温度，并且所述第二衬底与所述至少一个接合层之间的德拜温度失配小于所述第二衬底与所述第一衬底之间的德拜温度失配。
在一些实施例中，所述至少一个调节层和所述至少一个接合层通过沉积工艺形成于所述第一衬底上，并且所述至少一个接合层通过键合工艺连接至所述第二衬底。
根据本公开的一个方面，提供了所述至少一个接合层和所述至少一个调节层通过沉积工艺形成于所述第二衬底上，并且所述第一衬底通过沉积工艺形成于所述至少一个调 节层上。
提供发明内容部分是为了简化的形式来介绍对概念的选择，它们在下文的具体实施方式中将被进一步描述。发明内容部分无意标识本公开内容的关键特征或主要特征，也无意限制本公开内容的范围。
附图说明
通过参考附图阅读下文的详细描述，本公开的实施例的上述以及其他目的、特征和优点将变得易于理解。在附图中，以示例而非限制性的方式示出了本公开的若干实施例。
图1示出了一种常规的用于电子器件的层叠结构的示意图。
图2示出了另一种常规的用于电子器件的层叠结构的示意图。
图3示出了根据本公开的第一实施例的用于电子器件的层叠结构的示意图。
图4示出了如图3所示的层叠结构的一种制造工艺。
图5示出了如图3所示的层叠结构的另一种制造工艺。
图6示出了根据本公开的第二实施例的用于电子器件的层叠结构的示意图。
图7示出了根据本公开的第三实施例的用于电子器件的层叠结构的示意图。
图8示出了根据本公开的第四实施例的用于电子器件的层叠结构的示意图。
图9示出了根据本公开的第五实施例的用于电子器件的层叠结构的示意图。
图10示出了根据本公开的第六实施例的用于电子器件的层叠结构的示意图。
图11示出了根据本公开的第七实施例的用于电子器件的层叠结构的示意图。
图12示出了根据本公开的第八实施例的用于电子器件的层叠结构的示意图。
在各个附图中，相同或对应的标号表示相同或对应的部分。
具体实施方式
下面将参照附图更详细地描述本公开的优选实施例。虽然附图中显示了本公开的优选实施例，然而应该理解，可以以各种形式实现本公开而不应被这里阐述的实施例所限制。相反，提供这些实施例是为了使本公开更加透彻和完整，并且能够将本公开的范围完整地传达给本领域的技术人员。
在本文中使用的术语“包括”及其变形表示开放性包括，即“包括但不限于”。除非特别申明，术语“或”表示“和/或”。术语“基于”表示“至少部分地基于”。术语“一个示例实施例”和“一个实施例”表示“至少一个示例实施例”。术语“另一实施例”表示“至少一个另外的实施例”。术语“上”、“下”、“前”、“后”等指示放置或者位置关系的词汇均基于附图所示的方位或者位置关系，仅为了便于描述本公开的原理，而不是指示或者暗示所指的元件必须具有特定的方位、以特定的方位构造或操作，因此不能理解为对本公开的限制。
如在上文中所描述的，集成电路或半导体器件与由高热导率材料制成的衬底之间存在较大的界面热阻，较大的界面热阻会降低系统的散热能力。本公开的实施例提供了一种用于电子器件的层叠结构及其制造方法，以解决常规的利用高热导率材料对电子器件进行散热的方案存在的上述问题以及其他潜在的问题。在下文中将参考附图结合示例性实施例来详细描述本公开的原理。
在根据本公开的实施例中，采用“德拜温度失配”来描述两种材料的德拜温度之间 的差异。具体而言，假定两种材料的德拜温度分别为Θ D1和Θ D2，其中Θ D1为两种材料中具有较大德拜温度的材料的德拜温度，而Θ D2为两种材料中具有较小德拜温度的材料的德拜温度，即Θ D1>Θ D2。两种材料之间的德拜温度失配R被描述为R＝Θ D1/Θ D2，即具有较大德拜温度的材料的德拜温度与具有较小德拜温度的材料的德拜温度之间的比值。当R≤2时，两种材料之间的德拜温度失配较小。当R>2时，两种材料之间的德拜温度失配较大。
表1示出了可以在本公开的实施例中使用的一些材料的德拜温度。应当理解，所列出的材料仅为可以应用于本公开的实施例的材料的示例，而非意在穷举在本公开的实施例中可用的材料。本领域技术人员根据本公开的教导容易想到可以使用具有不同德拜温度的其他材料。
表1
材料 德拜温度(K)
金Au 170
钽Ta 240
铜Cu 315
钛Ti 420
铬Cr 460
二氧化硅SiO2 470
氮化钽TaN 527
氮化镓GaN 600
硅Si 625
氮化硅Si3N4 763
氮化钛TiN 865
氧化镁MgO 941
氧化铝Al2O3 980
氮化铝AlN 1150
碳化硅SiC 1195
金刚石 1860
石墨烯(面外) 1287
表2示出了各种材料之间的德拜温度失配，其中每一项为所对应的两种材料中具有较大德拜温度的材料的德拜温度与具有较小德拜温度的材料的德拜温度之间的比值。
表2
Figure PCTCN2021091157-appb-000001
第一实施例
图3示出了根据本公开的第一实施例的用于电子器件的层叠结构的示意图。如图3所示，层叠结构100总体上包括第一衬底21、第一界面热阻调节层31、第一接合层41和第二衬底22。第一界面热阻调节层31堆叠设置在第一衬底21上。第一接合层41堆叠设置在第一界面热阻调节层31上。第二衬底22堆叠设置在第一接合层41。
第二衬底22的与第一接合层41相背的表面用于制作半导体器件，而第一衬底21用于对半导体器件在工作时产生的热量进行消散。为了对半导体器件在工作时产生的热量进行消散，第一衬底21由具有较高热导率的材料制成，使得第二衬底22的德拜温度小于第一衬底21的德拜温度。第一接合层41用于实现第一衬底21与第二衬底22之间的连接。第一接合层41的德拜温度小于第一衬底21的德拜温度，且第二衬底22与第一接合层41之间的德拜温度失配小于第二衬底22与第一衬底21之间的德拜温度失配。第一接合层41与第一衬底21之间具有较大的德拜温度失配，也即第一衬底21的德拜温度与第一接合层41的德拜温度之间的比值较大。
根据声子扩散失配模型(phonon diffuse mismatch model)，两种固体材料之间的界面热阻受材料之间的德拜温度失配程度的影响。当两种固体材料之间的德拜温度失配很大时，声子散射严重，导致两种材料之间的界面热阻很大，因此材料之间的传热效率会降低。
如果利用第一接合层41直接连接第一衬底21和第二衬底22，则第一接合层41与第一衬底21之间的传热效率将会较低，这是因为第一接合层41与第一衬底21之间具有较大的德拜温度失配，并且因此具有较大的界面热阻。在第一实施例中，为了解决这一问题，在第一接合层41与第一衬底21之间设置了第一界面热阻调节层31。第一界面热阻调节层31的德拜温度小于第一衬底21的德拜温度并且大于第一接合层41的德拜温度。利用这样的布置，可以使得第一界面热阻调节层31与第一衬底21之间的德拜温度失配小于第一接合层41与第一衬底21之间的德拜温度失配，并且第一接合层41与第一界面热阻调节层31之间的德拜温度失配小于第一接合层41与第一衬底21之间的德拜温度失配。由于第一界面热阻调节层31与第一衬底21之间的德拜温度失配较小，因此二者之间的界面热阻较小，从而使得二者之间具有较高的传热效率。此外，由于第一接合层41与第一界面热阻调节层31之间的德拜温度失配较小，因此二者之间的界面热阻也较小，从而使得二者之间具有较高的传热效率。以此方式，与利用第一接合层41直接连接第一衬底21和第二衬底22的布置相比，可以显著提升第一接合层41与第一衬底21之间的传热效率。
表3示出了可以应用于第一实施例的层叠结构100中的材料的一些示例。应当理解，所列出的材料仅为可以应用于第一实施例的一些示例性材料，而非意在穷举在第一实施例中可用的材料。本领域技术人员根据本公开的教导容易想到可以使用其他材料。
表3
Figure PCTCN2021091157-appb-000002
例如，当第一衬底21的材料为金刚石、第二衬底22的材料为氮化镓、第一接合层41的材料为氮化硅并且第一界面热阻调节层31的材料为氮化铝时，第一衬底21与第一界面热阻调节层31之间的德拜温度失配R＝1860/1150＝1.62，而第一界面热阻调节层31与第一接合层41之间的德拜温度失配RR＝1150/763＝1.51。可见，第一界面热阻调节层31与第一衬底21之间的德拜温度失配小于2，因此二者之间的界面热阻较小，从而使得二者之间具有较高的传热效率。此外，第一接合层41与第一界面热阻调节层31之间的德拜温度失配也小于2，因此二者之间的界面热阻较小，从而使得二者之间具有较高的传热效率。以此方式，与利用第一接合层41直接连接第一衬底21和第二衬底22的布置 相比，可以显著提升第一接合层41与第一衬底21之间的传热效率。
当第一衬底21、第二衬底22、第一接合层41和第一界面热阻调节层31为表3中所列的其他材料时，也可以在第一界面热阻调节层31与第一衬底21之间以及在第一接合层41与第一界面热阻调节层31之间实现较小的界面热阻，从而提高层叠结构100的传热效率。
此外，当第一衬底21、第二衬底22、第一接合层41和第一界面热阻调节层31为具有如上所述的德拜温度关系的材料时，也可以在第一界面热阻调节层31与第一衬底21之间以及在第一接合层41与第一界面热阻调节层31之间实现较小的界面热阻，从而提高层叠结构100的传热效率。具体而言，第二衬底22的德拜温度小于第一衬底21的德拜温度，第一接合层41的德拜温度小于第一衬底21的德拜温度，第二衬底22与第一接合层41之间的德拜温度失配小于第二衬底22与第一衬底21之间的德拜温度失配，以及第一界面热阻调节层31的德拜温度小于第一衬底21的德拜温度并且大于第一接合层41的德拜温度。
如图3所示，在第一实施例的层叠结构100中，第一衬底21、第一界面热阻调节层31、第一接合层41、以及第二衬底22在横向方向X上基本对齐。在其他实施例中，第一衬底21、第一界面热阻调节层31、第一接合层41、以及第二衬底22在横向方向X上可以不对齐，这将在下文中结合图7和图8进行说明。
第一实施例的层叠结构100可以采用多种工艺进行制造。图4和图5示出了第一实施例的层叠结构100的示例性制造工艺。
如图4的左半部分所示，首先提供第一衬底21。如图4的中间部分所示，通过沉积工艺将第一界面热阻调节层31和第一接合层41按顺序形成在第一衬底21上。如图4的右半部分所示，通过键合工艺将第二衬底22连接至第一接合层41，从而得到第一实施例的层叠结构100。
如图5的左半部分所示，首先提供第二衬底22。如图5的中间部分所示，通过沉积工艺将第一接合层41和第一界面热阻调节层31按顺序形成在第二衬底22上。如图5的右半部分所示，通过沉积工艺将第一衬底21形成在第一界面热阻调节层31上，从而得到第一实施例的层叠结构100。
应当理解，图4和图5仅仅示出了第一实施例的层叠结构100的示例性制造工艺，而非意在限制本公开的范围。本领域技术人员根据本公开的教导，容易想到利用其他工艺来制造第一实施例的层叠结构100。
第二实施例
图6示出了根据本公开的第二实施例的用于电子器件的层叠结构的示意图。如图6所示，第二实施例的层叠结构100包括按顺序布置的第一衬底21、第一界面热阻调节层31、第一接合层41、第二衬底22、半导体器件层6和金属互连层7。第二实施例的层叠结构100中的第一衬底21、第一界面热阻调节层31、第一接合层41和第二衬底22与第一实施例的层叠结构100中的第一衬底21、第一界面热阻调节层31、第一接合层41和第二衬底22具有相同的布置，具体细节可以参见第一实施例中的描述，在此将不再赘述。半导体器件层6设置在第二衬底22的与第一接合层41相背的表面上。金属互连层7设置在半导体器件层6的与第二衬底22相背的表面上。
利用上述布置，半导体器件层6在工作时产生的热量可以经由第二衬底22、第一接合层41和第一界面热阻调节层31被传递到第一衬底21，并且继而经由第一衬底21进行消散。由于在第一接合层41与第一衬底21之间提供了第一界面热阻调节层31，因此在第一接合层41与第一界面热阻调节层31之间以及在第一界面热阻调节层31与第一衬底21之间分别实现了较小的界面热阻，从而提高了层叠结构100的传热效率。
如图6所示，在第二实施例的层叠结构100中，第一衬底21、第一界面热阻调节层31、第一接合层41、第二衬底22、半导体器件层6、以及金属互连层7在横向方向X上基本对齐。在其他实施例中，第一衬底21、第一界面热阻调节层31、第一接合层41、第二衬底22、半导体器件层6、以及金属互连层7在横向方向X上可以不对齐，这将在下文中结合图7和图8进行说明。
第三实施例
图7示出了根据本公开的第三实施例的用于电子器件的层叠结构的示意图。如图7所示，第三实施例的层叠结构100包括按顺序布置的第一衬底21、第一界面热阻调节层31、第一接合层41、第二衬底22、半导体器件层6、金属互连层7、以及微凸块9。第三实施例的层叠结构100与第二实施例的层叠结构100具有类似的布置，主要区别在于第一衬底21、第一界面热阻调节层31、以及第一接合层41在横向方向X上与第二衬底22不对齐。另外，在金属互连层7上设置了微凸块9，以用于实现层叠结构100与外部电路之间的电连接。
如图7所示，在第三实施例的层叠结构100中，第一衬底21、第一界面热阻调节层31、以及第一接合层41在横向方向X上基本对齐，并且第二衬底22在横向方向X上的尺寸大于第一衬底21。层叠结构100还包括绝缘层8，绝缘层8在横向方向X上包围第一衬底21、第一界面热阻调节层31、以及第一接合层41。第二衬底22、半导体器件层6、以及金属互连层7在横向方向X上基本对齐。绝缘层8的外边缘与第二衬底22、半导体器件层6、以及金属互连层7基本对齐。
利用上述布置，半导体器件层6在工作时产生的热量可以经由第二衬底22、第一接合层41和第一界面热阻调节层31被传递到第一衬底21，并且继而经由第一衬底21进行消散。由于在第一接合层41与第一衬底21之间提供了第一界面热阻调节层31，因此在第一接合层41与第一界面热阻调节层31之间以及在第一界面热阻调节层31与第一衬底21之间分别实现了较小的界面热阻，从而提高了层叠结构100的传热效率。
第四实施例
图8示出了根据本公开的第四实施例的用于电子器件的层叠结构的示意图。如图8所示，第四实施例的层叠结构100包括按顺序布置的第一衬底21、第一界面热阻调节层31、第一接合层41、第二衬底22、半导体器件层6、金属互连层7、以及微凸块9。第四实施例的层叠结构100与第二实施例的层叠结构100具有类似的布置，主要区别在于第一衬底21、第一界面热阻调节层31、以及第一接合层41在横向方向X上与第二衬底22不对齐。另外，在金属互连层7上设置了微凸块9，以用于实现层叠结构100与外部电路之间的电连接。
如图8所示，在第四实施例的层叠结构100中，第一衬底21、第一界面热阻调节层 31、以及第一接合层41在横向方向X上基本对齐，并且第二衬底22在横向方向X上的尺寸小于第一衬底21。第二衬底22、半导体器件层6、以及金属互连层7在横向方向X上基本对齐。层叠结构100还包括绝缘层8，绝缘层8在横向方向X上包围第二衬底22、半导体器件层6、以及金属互连层7。绝缘层8的外边缘与第一衬底21、第一界面热阻调节层31、以及第一接合层41基本对齐。
利用上述布置，半导体器件层6在工作时产生的热量可以经由第二衬底22、第一接合层41和第一界面热阻调节层31被传递到第一衬底21，并且继而经由第一衬底21进行消散。由于在第一接合层41与第一衬底21之间提供了第一界面热阻调节层31，因此在第一接合层41与第一界面热阻调节层31之间以及在第一界面热阻调节层31与第一衬底21之间分别实现了较小的界面热阻，从而提高了层叠结构100的传热效率。
第五实施例
图9示出了根据本公开的第五实施例的用于电子器件的层叠结构的示意图。第五实施例的层叠结构100与如图3所示的第一实施例的层叠结构100具有类似的布置，主要区别在于层叠结构100还包括第二界面热阻调节层32。第二界面热阻调节层32设置在第一界面热阻调节层31与第一接合层41之间。第二界面热阻调节层32的德拜温度小于第一界面热阻调节层31的德拜温度并且大于第一接合层41的德拜温度。
与如图3所示的第一实施例的布置相比，利用如图9所示的第五实施例的布置可以在第一结合层41与第二界面热阻调节层32之间以及在第二界面热阻调节层32与第一界面热阻调节层31之间实现更小的界面热阻，从而进一步提升层叠结构100的传热效率。
表4示出了可以应用于第五实施例的层叠结构100中的材料的一些示例。应当理解，所列出的材料仅为可以应用于第五实施例的一些示例性材料，而非意在穷举在第五实施例中可用的材料。本领域技术人员根据本公开的教导容易想到可以使用其他材料。
表4
Figure PCTCN2021091157-appb-000003
第五实施例的层叠结构100可以采用多种工艺进行制造。
例如，在一种制造工艺中，可以首先通过沉积工艺将第一界面热阻调节层31、第二界面热阻调节层32、以及第一接合层41按顺序形成在第一衬底21上。随后，可以通过键合工艺将第二衬底22连接至第一接合层41，从而得到第五实施例的层叠结构100。
在另一种制造工艺中，可以首先通过沉积工艺将第一接合层41、第二界面热阻调节层32、以及第一界面热阻调节层31按顺序形成在第二衬底22上。随后，可以通过沉积工艺将第一衬底21形成在第一界面热阻调节层31上，从而得到第一实施例的层叠结构 100。
应当理解，可以在第一接合层41与第一衬底21之间设置更多个界面热阻调节层，以进一步减小相邻层之间的界面热阻。
第六实施例
在一些情况下，由于材料的原因，第二衬底22与第一接合层41之间的接合性能可能不够稳固。为此，可以在第一接合层41与第二衬底22之间提供更多个接合层，图10中示出了一种这样的结构。
图10示出了根据本公开的第六实施例的用于电子器件的层叠结构的示意图。第六实施例的层叠结构100与如图3所示的第一实施例的层叠结构100具有类似的布置，主要区别在于层叠结构100还包括第二接合层42。第二接合层42设置在第二衬底22与第一接合层41之间。第二接合层42的材料与第一接合层41的材料可以相同或不同。如图10的左半部分所示，可以通过沉积工艺将第一界面热阻调节层31和第一接合层41按顺序形成在第一衬底21上，并且通过沉积工艺将第二接合层42形成在第二衬底22上。随后，如图10的右半部分所示，可以通过键合工艺将第一接合层41与第二接合层42连接在一起，从而形成层叠结构100。
与如图3所示的第一实施例的布置相比，利用第六实施例的布置中的第二接合层42可以增强第二衬底22与其他层之间的接合强度，从而使得层叠结构100更加稳定可靠并且传热效率更高。
应当理解，可以在第一界面热阻调节层31与第二衬底22之间设置更多个接合层，以进一步增强第二衬底22与其他层之间的接合强度。
表5示出了可以应用于第六实施例的层叠结构100中的材料的一些示例。应当理解，所列出的材料仅为可以应用于第六实施例的一些示例性材料，而非意在穷举在第六实施例中可用的材料。本领域技术人员根据本公开的教导容易想到可以使用其他材料。
表5
Figure PCTCN2021091157-appb-000004
第七实施例
图11示出了根据本公开的第七实施例的用于电子器件的层叠结构的示意图。第七实施例的层叠结构100与如图10所示的第六实施例的层叠结构100具有类似的布置，主要区别在于层叠结构100还包括第二界面热阻调节层32。第二界面热阻调节层32设置在第一界面热阻调节层31与第一接合层41之间。第二界面热阻调节层32的德拜温度小 于第一界面热阻调节层31的德拜温度并且大于第一接合层41的德拜温度。
与如图10所示的第六实施例的布置相比，利用如图11所示的第七实施例的布置可以在第一结合层41与第二界面热阻调节层32之间以及在第二界面热阻调节层32与第一界面热阻调节层31之间实现更小的界面热阻，从而进一步提升层叠结构100的传热效率。
表6示出了可以应用于第七实施例的层叠结构100中的材料的一些示例。应当理解，所列出的材料仅为可以应用于第七实施例的一些示例性材料，而非意在穷举在第七实施例中可用的材料。本领域技术人员根据本公开的教导容易想到可以使用其他材料。
表6
Figure PCTCN2021091157-appb-000005
第八实施例
图12示出了根据本公开的第八实施例的用于电子器件的层叠结构的示意图。第八实施例的层叠结构100与如图11所示的第七实施例的层叠结构100具有类似的布置，主要区别在于层叠结构100还包括第三界面热阻调节层33以及附加界面热阻调节层5。第三界面热阻调节层33设置在第二界面热阻调节层32与第一接合层41之间。第三界面热阻调节层33的德拜温度小于第二界面热阻调节层32的德拜温度并且大于第一接合层41的德拜温度。附加界面热阻调节层5设置在第二衬底22与第二接合层42之间。附加界面热阻调节层5的德拜温度介于第二衬底22的德拜温度与第二接合层42的德拜温度之间。
与如图11所示的第七实施例的布置相比，利用如图12所示的第八实施例的布置可以在第一结合层41与第三界面热阻调节层33之间、在第三界面热阻调节层33与第二界面热阻调节层32之间、以及在第二界面热阻调节层32与第一界面热阻调节层31之间实现更小的界面热阻，从而进一步提升层叠结构100的传热效率。此外，通过在第二衬底22与第二接合层42之间设置附加界面热阻调节层5，可以在第二衬底22与附加界面热阻调节层5之间以及在附加界面热阻调节层5与第二接合层42之间实现较小的界面热阻，从而进一步提升层叠结构100的传热效率。
在其他实施例中，可以在第二衬底22与第二接合层42之间提供更多个附加界面热阻调节层5，以进一步减小相邻层之间的界面热阻，提高传热效率。在层叠结构100不包括第二接合层42的实施例中，附加界面热阻调节层5可以直接设置在第二衬底22与第一接合层41之间。
表7示出了可以应用于第八实施例的层叠结构100中的材料的一些示例。应当理解，所列出的材料仅为可以应用于第八实施例的一些示例性材料，而非意在穷举在第八实施 例中可用的材料。本领域技术人员根据本公开的教导容易想到可以使用其他材料。
表7
Figure PCTCN2021091157-appb-000006
虽然在上文中结合附图描述了层叠结构100的一些实施例，但是这些实施例仅仅是示例性的，本领域技术人员根据本公开的教导容易想到其他修改或变形。例如，根据本公开的教导，本领域技术人员容易想到设置在至少一个接合层与第一衬底之间的至少一个调节层可以包括更多或更少的界面热阻调节层。
根据本公开的实施例的层叠结构100可以应用于各种电子器件，包括但不限于大功率芯片、片上系统(SoC)、高电子迁移率晶体管(HEMT)、单片微波集成电路(MMIC)、激光器等。
根据本公开的实施例还提供了一种制造如上所述的层叠结构100的方法，包括：提供第一衬底21；提供至少一个调节层，至少一个调节层堆叠设置在第一衬底21上，至少一个调节层的德拜温度小于第一衬底21的德拜温度；提供至少一个接合层，至少一个接合层堆叠设置在至少一个调节层上，至少一个接合层的德拜温度小于至少一个调节层的德拜温度；以及提供第二衬底22，第二衬底22堆叠设置在至少一个接合层上，第二衬底22的德拜温度小于第一衬底21的德拜温度，并且第二衬底22与至少一个接合层之间的德拜温度失配小于第二衬底22与第一衬底21之间的德拜温度失配。
在一些实施例中，至少一个调节层和至少一个接合层通过沉积工艺形成于第一衬底21上，并且至少一个接合层通过键合工艺连接至第二衬底22。
在一些实施例中，至少一个接合层和至少一个调节层通过沉积工艺形成于第二衬底22上，并且第一衬底21通过沉积工艺形成于至少一个调节层上。
以上已经描述了本公开的各实施例，上述说明是示例性的，并非穷尽性的，并且也不限于所披露的各实施例。在不偏离所说明的各实施例的范围和精神的情况下，对于本技术领域的普通技术人员来说许多修改和变更都是显而易见的。本文中所用术语的选择，旨在最好地解释各实施例的原理、实际应用或对市场中的技术改进，或者使本技术领域的其它普通技术人员能理解本文披露的各实施例。

Claims (24)

  1. 一种用于电子器件的层叠结构(100)，包括：
    第一衬底(21)；
    至少一个调节层，堆叠设置在所述第一衬底(21)上，所述至少一个调节层的德拜温度小于所述第一衬底(21)的德拜温度；
    至少一个接合层，堆叠设置在所述至少一个调节层上，所述至少一个接合层的德拜温度小于所述至少一个调节层的德拜温度；以及
    第二衬底(22)，堆叠设置在所述至少一个接合层上，所述第二衬底(22)的德拜温度小于所述第一衬底(21)的德拜温度，并且所述第二衬底(22)与所述至少一个接合层之间的德拜温度失配小于所述第二衬底(22)与所述第一衬底(21)之间的德拜温度失配。
  2. 根据权利要求1所述的层叠结构(100)，其中所述第一衬底(21)的材料包括以下至少一项：金刚石、石墨烯、石墨、以及碳化硅(SiC)。
  3. 根据权利要求1所述的层叠结构(100)，其中所述第二衬底(22)的材料包括以下至少一项：硅(Si)、氮化镓(GaN)、氧化镓(Ga2O3)、碳化硅(SiC)、硅基异质外延衬底、以及碳化硅基异质外延衬底。
  4. 根据权利要求1所述的层叠结构(100)，其中所述至少一个调节层包括第一界面热阻调节层(31)，并且所述至少一个接合层包括第一接合层(41)。
  5. 根据权利要求4所述的层叠结构(100)，其中所述第一界面热阻调节层(31)的材料包括以下至少一项：氮化钛(TiN)、氧化镁(MgO)、氧化铝(Al2O3)、氮化铝(AlN)、碳化硅(SiC)、钛(Ti)、以及铬(Cr)。
  6. 根据权利要求4所述的层叠结构(100)，其中所述第一接合层(41)的材料包括以下至少一项：硅(Si)、氧化硅(SiO2)、氮化硅(SiN)、氧化铝(Al2O3)、氮化铝(AlN)、碳化硅(SiC)、金(Au)、以及铜(Cu)。
  7. 根据权利要求4所述的层叠结构(100)，其中所述至少一个调节层还包括：
    第二界面热阻调节层(32)，设置在所述第一界面热阻调节层(31)与所述第一接合层(41)之间，所述第二界面热阻调节层(32)的德拜温度小于所述第一界面热阻调节层(31)的德拜温度。
  8. 根据权利要求7所述的层叠结构(100)，其中所述第二界面热阻调节层(32)的材料包括以下至少一项：氮化钛(TiN)、氧化镁(MgO)、以及铜(Cu)。
  9. 根据权利要求7所述的层叠结构(100)，其中所述至少一个调节层还包括：
    第三界面热阻调节层(33)，设置在所述第二界面热阻调节层(32)与所述第一接合层(41) 之间，所述第三界面热阻调节层(33)的德拜温度小于所述第二界面热阻调节层(32)的德拜温度。
  10. 根据权利要求9所述的层叠结构(100)，其中所述第三界面热阻调节层(33)的材料包括以下至少一项：钛(Ti)和钽(Ta)。
  11. 根据权利要求4所述的层叠结构(100)，其中所述至少一个接合层还包括：
    第二接合层(42)，设置在所述第二衬底(22)与所述第一接合层(41)之间。
  12. 根据权利要求11所述的层叠结构(100)，其中所述第二接合层(42)的材料与所述第一接合层(41)的材料相同或不同。
  13. 根据权利要求11所述的层叠结构(100)，其中所述第二接合层(42)的材料包括以下至少一项：硅(Si)、氧化硅(SiO2)、氮化硅(SiN)、氧化铝(Al2O3)、氮化铝(AlN)、碳化硅(SiC)、金(Au)、以及铜(Cu)。
  14. 根据权利要求4所述的层叠结构(100)，其中所述层叠结构(100)还包括：
    至少一个附加界面热阻调节层(5)，设置在所述第二衬底(22)与所述至少一个接合层之间，所述至少一个附加界面热阻调节层(5)的德拜温度介于所述第二衬底(22)的德拜温度与所述至少一个接合层的德拜温度之间。
  15. 根据权利要求14所述的层叠结构(100)，其中所述至少一个附加界面热阻调节层(5)的材料包括以下至少一项：钽(Ta)、钛(Ti)、铬(Cr)、以及氮化钛(TiN)。
  16. 根据权利要求1所述的层叠结构(100)，还包括：
    半导体器件层(6)，设置在所述第二衬底(22)的与所述至少一个接合层相背的表面上；以及
    金属互连层(7)，设置在所述半导体器件层(6)的与所述第二衬底(22)相背的表面上。
  17. 根据权利要求1所述的层叠结构(100)，其中所述第一衬底(21)、所述至少一个调节层、所述至少一个接合层、以及所述第二衬底(22)在横向方向(X)上对齐。
  18. 根据权利要求1所述的层叠结构(100)，其中所述第一衬底(21)、所述至少一个调节层、以及所述至少一个接合层在横向方向(X)上对齐，并且所述第二衬底(22)在横向方向(X)上的尺寸大于所述第一衬底(21)，以及
    其中所述层叠结构(100)还包括绝缘层(8)，所述绝缘层(8)在横向方向(X)上包围所述第一衬底(21)、所述至少一个调节层、以及所述至少一个接合层。
  19. 根据权利要求1所述的层叠结构(100)，其中所述第一衬底(21)、所述至少一个调节层、以及所述至少一个接合层在横向方向(X)上对齐，并且所述第二衬底(22)在横向 方向(X)上的尺寸小于所述第一衬底(21)，以及
    其中所述层叠结构(100)还包括绝缘层(8)，所述绝缘层(8)在横向方向(X)上包围所述第二衬底(22)。
  20. 根据权利要求1所述的层叠结构(100)，其中所述至少一个调节层和所述至少一个接合层通过沉积工艺形成于所述第一衬底(21)上，并且所述至少一个接合层通过键合工艺连接至所述第二衬底(22)。
  21. 根据权利要求1所述的层叠结构(100)，其中所述至少一个接合层和所述至少一个调节层通过沉积工艺形成于所述第二衬底(22)上，并且所述第一衬底(21)通过沉积工艺形成于所述至少一个调节层上。
  22. 一种制造用于电子器件的层叠结构(100)的方法，包括：
    提供第一衬底(21)；
    提供至少一个调节层，所述至少一个调节层堆叠设置在所述第一衬底(21)上，所述至少一个调节层的德拜温度小于所述第一衬底(21)的德拜温度；
    提供至少一个接合层，所述至少一个接合层堆叠设置在所述至少一个调节层上，所述至少一个接合层的德拜温度小于所述至少一个调节层的德拜温度；以及
    提供第二衬底(22)，所述第二衬底(22)堆叠设置在所述至少一个接合层上，所述第二衬底(22)的德拜温度小于所述第一衬底(21)的德拜温度，并且所述第二衬底(22)与所述至少一个接合层之间的德拜温度失配小于所述第二衬底(22)与所述第一衬底(21)之间的德拜温度失配。
  23. 根据权利要求22所述的方法，其中所述至少一个调节层和所述至少一个接合层通过沉积工艺形成于所述第一衬底(21)上，并且所述至少一个接合层通过键合工艺连接至所述第二衬底(22)。
  24. 根据权利要求22所述的方法，其中所述至少一个接合层和所述至少一个调节层通过沉积工艺形成于所述第二衬底(22)上，并且所述第一衬底(21)通过沉积工艺形成于所述至少一个调节层上。
PCT/CN2021/091157 2021-04-29 2021-04-29 用于电子器件的层叠结构及其制造方法 WO2022226931A1 (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202180093531.8A CN116868349A (zh) 2021-04-29 2021-04-29 用于电子器件的层叠结构及其制造方法
PCT/CN2021/091157 WO2022226931A1 (zh) 2021-04-29 2021-04-29 用于电子器件的层叠结构及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/091157 WO2022226931A1 (zh) 2021-04-29 2021-04-29 用于电子器件的层叠结构及其制造方法

Publications (1)

Publication Number Publication Date
WO2022226931A1 true WO2022226931A1 (zh) 2022-11-03

Family

ID=83846614

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2021/091157 WO2022226931A1 (zh) 2021-04-29 2021-04-29 用于电子器件的层叠结构及其制造方法

Country Status (2)

Country Link
CN (1) CN116868349A (zh)
WO (1) WO2022226931A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105322007A (zh) * 2015-07-20 2016-02-10 苏州能讯高能半导体有限公司 基于金刚石衬底的氮化物结构、制备方法及半导体器件
CN107204282A (zh) * 2017-06-26 2017-09-26 北京科技大学 一种基于非自支撑GaN对粘制备金刚石基GaN的方法
CN208297403U (zh) * 2018-05-29 2018-12-28 哈尔滨工业大学深圳研究生院 一种GaN外延晶片界面热阻的测量装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105322007A (zh) * 2015-07-20 2016-02-10 苏州能讯高能半导体有限公司 基于金刚石衬底的氮化物结构、制备方法及半导体器件
CN107204282A (zh) * 2017-06-26 2017-09-26 北京科技大学 一种基于非自支撑GaN对粘制备金刚石基GaN的方法
CN208297403U (zh) * 2018-05-29 2018-12-28 哈尔滨工业大学深圳研究生院 一种GaN外延晶片界面热阻的测量装置

Also Published As

Publication number Publication date
CN116868349A (zh) 2023-10-10

Similar Documents

Publication Publication Date Title
US6337513B1 (en) Chip packaging system and method using deposited diamond film
US7997087B2 (en) Thin film thermoelectric devices for hot-spot thermal management in microprocessors and other electronics
US20100085713A1 (en) Lateral graphene heat spreaders for electronic and optoelectronic devices and circuits
US8853007B2 (en) In-plane silicon heat spreader and method therefor
US7586191B2 (en) Integrated circuit apparatus with heat spreader
US9496197B1 (en) Near junction cooling for GaN devices
CN106910725B (zh) 一种半导体芯片的封装结构
TW415053B (en) Semiconductor device and method for manufacturing same
JP2013243362A (ja) 段階的熱膨張パラメータを有する熱分散部
US6292367B1 (en) Thermally efficient semiconductor chip
US20190043709A1 (en) Method for gallium nitride on diamond semiconductor wafer production
CN104733399A (zh) 一种层状高导热绝缘基板及其制备方法
WO2022226931A1 (zh) 用于电子器件的层叠结构及其制造方法
Gu et al. Interface engineering enabling next generation GaN-on-diamond power devices
CN109560457A (zh) 一种面射型激光器芯片的散热结构及其制作方法
TWM595383U (zh) 散熱型電子裝置
KR20090087106A (ko) 전자 컴포넌트 모듈 및 상기 전자 컴포넌트 모듈 형성 방법
US11862529B2 (en) Chip and manufacturing method thereof, and electronic device
CN111682002A (zh) 散热板
KR20020084897A (ko) 플라스틱 주조 패키지 및 직접 결합 기판을 갖는 전력 장치
TW202247401A (zh) 在積體電路封裝體中之有機基體上之無機重分佈層
JP2018142569A (ja) 放熱基板
JP3419642B2 (ja) パワーモジュール
US10060036B2 (en) Plated-layer structure for improving interface stress between aluminium nitride substrate and copper-plated layer
KR20150086014A (ko) 개선된 본딩 패드 구조를 갖는 GaN 트랜지스터 및 그의 제조방법

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 21938410

Country of ref document: EP

Kind code of ref document: A1

WWE Wipo information: entry into national phase

Ref document number: 202180093531.8

Country of ref document: CN

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 21938410

Country of ref document: EP

Kind code of ref document: A1