WO2022222944A1 - 量子计算平台适配方法、装置及量子计算机操作系统 - Google Patents

量子计算平台适配方法、装置及量子计算机操作系统 Download PDF

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WO2022222944A1
WO2022222944A1 PCT/CN2022/087842 CN2022087842W WO2022222944A1 WO 2022222944 A1 WO2022222944 A1 WO 2022222944A1 CN 2022087842 W CN2022087842 W CN 2022087842W WO 2022222944 A1 WO2022222944 A1 WO 2022222944A1
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subgraph
isomorphic
cost
subgraphs
quantum
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PCT/CN2022/087842
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English (en)
French (fr)
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窦猛汉
方圆
王晶
赵东一
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合肥本源量子计算科技有限责任公司
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Priority claimed from CN202110430149.3A external-priority patent/CN115310612A/zh
Priority claimed from CN202110431607.5A external-priority patent/CN115310614B/zh
Priority claimed from CN202110430151.0A external-priority patent/CN115310613A/zh
Application filed by 合肥本源量子计算科技有限责任公司 filed Critical 合肥本源量子计算科技有限责任公司
Priority to EP22791051.0A priority Critical patent/EP4328807A1/en
Publication of WO2022222944A1 publication Critical patent/WO2022222944A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/40—Physical realisations or architectures of quantum processors or components for manipulating qubits, e.g. qubit coupling or qubit control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N10/00—Quantum computing, i.e. information processing based on quantum-mechanical phenomena
    • G06N10/20—Models of quantum computing, e.g. quantum circuits or universal quantum computers

Definitions

  • the present application relates to the technical field of quantum computing, and in particular, to a quantum computing platform adaptation method, device and quantum computer operating system.
  • Different quantum computing platforms include different quantum chips, and different quantum computing chips support different sets of quantum logic gates.
  • quantum software developers implement quantum algorithms, the quantum programs they develop often only run on specific quantum chips. Therefore, how to improve the scalability of quantum programs so that they can be adapted to different quantum computing platforms and run on different quantum chips is a problem that needs to be solved.
  • Embodiments of the present application provide a quantum computing platform adaptation method, device, and quantum computer operating system, which are used to improve the scalability of quantum programs so that they can be adapted to different quantum computing platforms and run on different quantum chips.
  • an embodiment of the present application provides a method for adapting a quantum computing platform, and the method includes:
  • the quantum program is adapted to the quantum computing platform based on the topology.
  • a quantum circuit is constructed based on the set of N isomorphic subgraphs, the quantum circuit allowing operation on the quantum computing platform.
  • the aspect of constructing the first directed acyclic graph of the quantum program including:
  • a first directed acyclic graph is constructed based on the quantum logic gate, and the first directed acyclic graph includes a node and a directed edge; the node includes two points and an edge, and the two points are used to represent The two logic qubits corresponding to the quantum logic gate, the one edge is used to represent the quantum logic gate acting on the two logic qubits; the directed edge is used to represent that the quantum logic gate is a logic qubit The dependence of the quantum state evolution timing.
  • the quantum logic gate includes multiple quantum logic gates; the construction of the first directed acyclic graph based on the quantum logic gate includes:
  • the single quantum logic gate is deleted, and a first directed acyclic graph is constructed based on the two quantum logic gates.
  • the aspect of constructing the first directed acyclic graph based on the quantum logic gate including:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on the same two logic qubits, then based on the number of consecutive two-quantum logic gates in the Either one constructs the first directed acyclic graph.
  • the method further includes:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on two different logic qubits, then based on the plurality of consecutive two-quantum logic gates, the Construct the first directed acyclic graph.
  • the aspect of obtaining the maximum subgraph sequence by traversing the first directed acyclic graph it includes:
  • the method further includes:
  • the second node exists in the second directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent Two logical qubits in a quantum program, the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the The first subgraph is determined;
  • a maximum subgraph is generated.
  • the method includes:
  • the priority of the second node is the first priority
  • the first subgraph is expanded into a second subgraph, and the second subgraph is used as a new first subgraph subgraph
  • the method further includes:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • Priority aspects of nodes including:
  • the priority of the second node is determined as the first sub-priority; the priorities in descending order are: the first sub-priority A sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraph sets are all
  • the N largest subgraphs are based on the bit relationship graph on the quantum chip obtained by mapping the topological structure of the quantum chip in the electronic device, and the N is an integer greater than or equal to 1;
  • the exchange cost constructs a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for conversion between the quantum logic gates corresponding to the isomorphic subgraph .
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the largest subgraph set includes k i isomorphic subgraphs.
  • the numbering of the subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange costs between the two graphs, and the construction of quantum circuits based on the fixed costs and the exchange costs include:
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the largest subgraph set includes k i isomorphic subgraphs.
  • the numbering of the subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange costs between the two graphs, and the construction of quantum circuits based on the fixed costs and the exchange costs include:
  • Each exchange cost set includes k 0 exchange costs
  • each consumption cost set includes k 0 consumption costs
  • Each second isomorphic subgraph and its corresponding first isomorphic subgraph in the k i second isomorphic subgraphs are formed into a new first isomorphic subgraph, and k i new first isomorphic subgraphs are obtained. isomorphism subgraph;
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the largest subgraph set includes k i isomorphic subgraphs.
  • the numbering of the subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange costs between the two graphs, and the construction of quantum circuits based on the fixed costs and the exchange costs include:
  • Each exchange cost set includes k i exchange costs
  • each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph to obtain k 0 new first isomorphic subgraphs isomorphism subgraph;
  • the fixed cost and the exchange cost are determined based on fidelity.
  • the fixed cost and the exchange cost are determined based on the number of CZ gates.
  • an embodiment of the present application provides a method for constructing a quantum circuit, the method comprising:
  • a quantum circuit is constructed according to the N largest subgraphs and the topology, and the topology is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits.
  • a quantum circuit is constructed based on the set of N isomorphic subgraphs.
  • the method includes:
  • the method further includes:
  • the second node exists in the second directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent Two logical qubits in a quantum program, the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the The first subgraph is determined;
  • a maximum subgraph is generated.
  • the method includes:
  • the priority of the second node is the first priority
  • the first subgraph is expanded into a second subgraph, and the second subgraph is used as a new first subgraph subgraph
  • the method further includes:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • the determining the second node priority including:
  • the priority of the second node is determined as the first sub-priority; the priorities in descending order are: the first sub-priority A sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • an embodiment of the present application provides a method for constructing a quantum circuit, including:
  • N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraph sets are all
  • the N largest subgraphs are based on the bit relationship graph on the quantum chip obtained by mapping the topological structure of the quantum chip in the electronic device, and the N is an integer greater than or equal to 1;
  • the exchange cost constructs a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for conversion between the quantum logic gates corresponding to the isomorphic subgraph .
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the largest subgraph set includes k i isomorphic subgraphs.
  • the numbering of the subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange costs between the two graphs, and the construction of quantum circuits based on the fixed costs and the exchange costs include:
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the largest subgraph set includes k i isomorphic subgraphs.
  • the numbering of the subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange costs between the two graphs, and the construction of quantum circuits based on the fixed costs and the exchange costs include:
  • Each exchange cost set includes k 0 exchange costs
  • each consumption cost set includes k 0 consumption costs
  • Each second isomorphic subgraph and its corresponding first isomorphic subgraph in the k i second isomorphic subgraphs are formed into a new first isomorphic subgraph, and k i new first isomorphic subgraphs are obtained. isomorphism subgraph;
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the largest subgraph set includes k i isomorphic subgraphs.
  • the numbering of the subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange costs between the two graphs, and the construction of quantum circuits based on the fixed costs and the exchange costs include:
  • Each exchange cost set includes k i exchange costs
  • each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph to obtain k 0 new first isomorphic subgraphs isomorphism subgraph;
  • the fixed cost and the exchange cost are determined based on fidelity.
  • the fixed cost and the exchange cost are determined based on the number of CZ gates.
  • an embodiment of the present application provides a quantum computing platform adaptation device, the device comprising:
  • an acquisition unit configured to acquire the quantum program to be run and the topological structure of the quantum chip corresponding to the quantum computing platform, where the topological structure is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits;
  • An adaptation unit configured to adapt the quantum program to the quantum computing platform based on the topology.
  • an embodiment of the present application provides an apparatus for constructing a quantum circuit, the apparatus comprising:
  • a traversal unit for traversing the first directed acyclic graph of the quantum program to obtain a maximum subgraph sequence, where the maximum subgraph sequence includes N maximum subgraphs, and N is an integer greater than or equal to 1;
  • the construction unit is configured to construct a quantum circuit according to the N largest subgraphs and a topology structure, where the topology structure is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits.
  • an embodiment of the present application provides an apparatus for constructing a quantum circuit, the apparatus comprising:
  • a determination unit configured to determine the set of N isomorphic subgraphs corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N is greater than or an integer equal to 1;
  • the building unit is used to determine the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and the exchange cost between the isomorphic subgraphs in any adjacent isomorphic subgraph sets, and based on the The fixed cost and the exchange cost construct a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is based on the transformation between the quantum logic gates corresponding to the isomorphic subgraph.
  • the required SWAP gate is determined.
  • an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory, and are configured to be processed by the above-mentioned
  • the above program includes instructions for executing the steps in the method described in the first aspect or the second aspect or the third aspect of the embodiments of the present application.
  • an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute the computer program as described in the first embodiment of the present application.
  • an embodiment of the present application provides a computer program product, wherein the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute the program as implemented in the present application.
  • the computer program product may be a software installation package.
  • an embodiment of the present application provides a quantum computer operating system, wherein the quantum computer operating system is based on a part or part of the method described in the first aspect or the second aspect or the third aspect of the embodiment of the present application. All steps realize the adaptation of the quantum computing platform.
  • the topology structure of the quantum chip corresponding to the quantum program to be run and the quantum computing platform is obtained first, and the topology structure is used to represent the physical qubits in the electronic device and the relationship between the physical qubits. connection relationship; then adapt the quantum program to the quantum computing platform based on the topology; whether the quantum program can run on the quantum chip mainly depends on the topology of the chip, so to adapt the quantum program based on the topology, you can Quantum programs are adapted to different quantum computing platforms and run the same quantum program on different quantum chips, thereby improving the scalability of quantum programs. In addition, the workload of quantum software developers is also reduced, and there is no need to develop quantum software with the same function for different quantum chips.
  • FIG. 1 is a hardware structural block diagram of a computer terminal of a quantum computing platform adaptation method provided by an embodiment of the present application
  • 2A is a schematic flowchart of a method for adapting a quantum computing platform according to an embodiment of the present application
  • 2B is a schematic structural diagram of a quantum circuit provided by an embodiment of the present application.
  • FIG. 2C is a schematic diagram of a first directed acyclic graph corresponding to the quantum circuit shown in FIG. 2B;
  • 2D is a schematic diagram of a first subgraph determined based on a first node in the first directed acyclic graph shown in FIG. 2C;
  • FIG. 2E is a schematic diagram of a second directed acyclic graph obtained after deleting the first node in FIG. 2C;
  • FIG. 2F is a schematic diagram of a second subgraph obtained by expanding on FIG. 2D based on a second node;
  • 2G is a schematic diagram of a third directed acyclic graph obtained after deleting the second node in FIG. 2E;
  • 2H is a schematic diagram of a second subgraph obtained by extending on FIG. 2F based on a new second node
  • Fig. 2I is the schematic diagram of the new first directed acyclic graph obtained after Fig. 2G deletes the new second node;
  • 2J is a schematic diagram of a first subgraph determined based on a first node in the first directed acyclic graph shown in FIG. 2I;
  • 2K is a schematic diagram of the second directed acyclic graph obtained after deleting the first node in FIG. 2J;
  • 2L is a schematic diagram of a second subgraph obtained by expanding on FIG. 2J based on a second node
  • 2M is a schematic diagram of a third directed acyclic graph obtained after the second node is deleted in FIG. 2K;
  • 2N is a schematic diagram of a first subgraph determined based on a first node in the third directed acyclic graph shown in FIG. 2M;
  • 20 is a schematic diagram of a first directed acyclic graph including a single quantum logic gate according to an embodiment of the present application
  • 2P is a schematic diagram of a new first directed acyclic graph obtained based on FIG. 20;
  • 2Q is a topological structure diagram of a physical qubit in an electronic device provided by an embodiment of the application.
  • 2R is a schematic diagram of an isomorphic subgraph provided by an embodiment of the present application.
  • 2S is a schematic diagram of mutual matching between isomorphic subgraphs provided by an embodiment of the present application.
  • 2T is a schematic diagram of mutual matching between isomorphic subgraphs provided by an embodiment of the present application.
  • 2U is a schematic diagram of mutual matching between isomorphic subgraphs according to an embodiment of the present application.
  • FIG. 3 is a schematic flowchart of another quantum computing platform adaptation method provided by an embodiment of the present application.
  • FIG. 4 is a schematic flowchart of a method for constructing a quantum circuit according to an embodiment of the present application
  • FIG. 5 is a schematic flowchart of another quantum circuit construction method provided by an embodiment of the present application.
  • FIG. 6 is a schematic flowchart of a third method for constructing a quantum circuit according to an embodiment of the present application.
  • FIG. 7 is a schematic flowchart of a fourth quantum circuit construction method provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 9 is a schematic structural diagram of a quantum computing platform adaptation device provided by an embodiment of the present application.
  • FIG. 10 is a schematic structural diagram of a quantum circuit construction device provided by an embodiment of the present application.
  • FIG. 11 is a schematic structural diagram of another quantum circuit construction apparatus provided by an embodiment of the present application.
  • the embodiments of the present application first provide a method for adapting a quantum computing platform, and the method can be applied to electronic devices, such as computer terminals, specifically, ordinary computers, quantum computers, and the like.
  • Fig. 1 is a hardware structural block diagram of a computer terminal of a quantum computing platform adaptation method provided by an embodiment of the present application.
  • the computer terminal may include one or more (only one is shown in FIG. 1 ) processor 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA, etc.) and the memory 104 for storing the quantum computing platform-based adaptation method, optionally, the above-mentioned computer terminal may further include a transmission device 106 and an input/output device 108 for a communication function.
  • the structure shown in FIG. 1 is only a schematic diagram, which does not limit the structure of the above-mentioned computer terminal.
  • the computer terminal may also include more or fewer components than shown in FIG. 1 , or have a different configuration than that shown in FIG. 1 .
  • the memory 104 may be used to store software programs and modules of application software, such as program instructions/modules corresponding to the quantum computing platform adaptation method in the embodiments of the present application.
  • the processor 102 runs the software programs and modules stored in the memory 104, thereby Executing various functional applications and data processing implements the above-mentioned methods.
  • Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory.
  • memory 104 may further include memory located remotely from processor 102, which may be connected to a computer terminal through a network. Examples of such networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
  • Transmission means 106 are used to receive or transmit data via a network.
  • the specific example of the above-mentioned network may include a wireless network provided by the communication provider of the computer terminal.
  • the transmission device 106 includes a network adapter (Network Interface Controller, NIC), which can be connected to other network devices through a base station so as to communicate with the Internet.
  • the transmission device 106 may be a radio frequency (Radio Frequency, RF) module, which is used for wirelessly communicating with the Internet.
  • RF Radio Frequency
  • a real quantum computer is a hybrid structure, which consists of two parts: one part is a classical computer, which is responsible for performing classical calculations and control; the other part is a quantum device, which is responsible for running quantum programs to realize quantum computing.
  • a quantum program is a sequence of instructions written in a quantum language such as QRunes that can run on a quantum computer, which supports the operation of quantum logic gates, and finally realizes quantum computing.
  • a quantum program is a series of instruction sequences that operate quantum logic gates in a certain sequence.
  • Quantum computing simulation is a process in which a virtual architecture (ie, a quantum virtual machine) built with the resources of an ordinary computer realizes the simulation operation of a quantum program corresponding to a specific problem. Often, it is necessary to construct a quantum program corresponding to a particular problem.
  • the quantum program referred to in the embodiments of the present application refers to a program written in a classical language to characterize qubits and their evolution, wherein qubits, quantum logic gates, etc. related to quantum computing are represented by corresponding classical codes.
  • quantum circuits also known as quantum logic circuits
  • quantum logic circuits are the most commonly used general-purpose quantum computing models, representing circuits that operate on qubits under abstract concepts, including qubits, circuits (timelines) , and various quantum logic gates, and finally the results are often read out through quantum measurement operations.
  • the wires can be regarded as connected by time, that is, the state of qubits evolves naturally with time.
  • the instruction of the Hamiltonian operator which is operated until it encounters a logic gate.
  • a quantum program as a whole corresponds to a total quantum circuit
  • the quantum program in the present invention refers to the total quantum circuit, wherein the total number of qubits in the total quantum circuit is the same as the total number of qubits in the quantum program.
  • a quantum program can be composed of quantum circuits, measurement operations for qubits in the quantum circuits, registers to save the measurement results, and control flow nodes (jump instructions).
  • a quantum circuit can contain dozens, hundreds or even thousands of them. Tens of thousands of quantum logic gate operations.
  • the execution process of a quantum program is the process of executing all quantum logic gates in a certain sequence. It should be noted that timing is the time sequence in which a single quantum logic gate is executed.
  • Quantum logic gates are the basis of quantum circuits. Quantum logic gates include single-bit quantum logic gates, such as Hadamard gates (H gates, Hadamard gates), Pauli-X gates ( X gate), Pauli-Y gate (Y gate), Pauli-Z gate (Z gate), RX gate, RY gate, RZ gate, etc.; multi-bit quantum logic gates, such as CNOT gate, CR gate, iSWAP gate , Toffoli doors and more.
  • Quantum logic gates are generally represented by a unitary matrix, and a unitary matrix is not only a matrix form, but also an operation and transformation.
  • the function of the general quantum logic gate in the quantum state is to calculate by multiplying the unitary matrix left by the matrix corresponding to the right vector of the quantum state.
  • FIG. 2A is a schematic flowchart of a method for adapting a quantum computing platform provided by an embodiment of the present application. The method includes:
  • Step 201 Obtain the quantum program to be run and the topological structure of the quantum chip corresponding to the quantum computing platform, where the topological structure is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits.
  • the quantum computing platform may include quantum computing platforms of different systems, such as one of quantum computers, quantum virtual machines, and classical computers, or a quantum computing platform composed of a combination of several systems.
  • the quantum computing platform in the embodiments of the present application is any one of the above quantum computing platforms.
  • connection relationship indicates that two quantum logic gates can act on two physical qubits.
  • Step 202 Adapt the quantum program to the quantum computing platform based on the topology.
  • the topology structure of the quantum chip corresponding to the quantum program to be run and the quantum computing platform is obtained first, and the topology structure is used to represent the physical qubits in the electronic device and the relationship between the physical qubits. connection relationship; then adapt the quantum program to the quantum computing platform based on the topology; whether the quantum program can run on the quantum chip mainly depends on the topology of the chip, so to adapt the quantum program based on the topology, you can Quantum programs are adapted to different quantum computing platforms and run the same quantum program on different quantum chips, thereby improving the scalability of quantum programs. In addition, the workload of quantum software developers is also reduced, and there is no need to develop quantum software with the same function for different quantum chips.
  • N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraph sets are all
  • the N largest subgraphs are based on the bit relationship graph on the quantum chip obtained by mapping the topological structure of the quantum chip in the electronic device, and the N is an integer greater than or equal to 1;
  • the exchange cost constructs a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for conversion between the quantum logic gates corresponding to the isomorphic subgraph .
  • the isomorphic subgraphs of the N largest subgraphs in the topology structure are determined, and N isomorphic subgraph sets are obtained, and the N isomorphic subgraph sets are in one-to-one correspondence with the N largest subgraphs.
  • the method in the aspect of adapting the quantum program to the quantum computing platform based on the topology structure, includes:
  • a quantum circuit is constructed based on the set of N isomorphic subgraphs, the quantum circuit allowing operation on the quantum computing platform.
  • the N largest subgraphs are arranged in sequence according to the obtained order, and the largest subgraph sequence is obtained.
  • the isomorphic subgraph is a bit relation graph on the quantum chip obtained by mapping the largest subgraph based on the topological structure of the quantum chip in the electronic device. For example, assuming that the largest subgraph is "q[0]-q[1]", the topology of quantum chips in electronic devices is linear "Q[0]-Q[1]-Q[2]-Q[3 ]", you can map "q[0]-q[1]” to "Q[0]-Q[1]", or map to "Q[1]-Q[2]", or map To "Q[2]-Q[3]", then the isomorphic subgraph of the largest subgraph "q[0]-q[1]” is: "Q[0]-Q[1]", "Q[ 1]—Q[2]”, “Q[2]—Q[3]”.
  • constructing a quantum circuit based on the N isomorphic subgraph sets may include selecting one isomorphic subgraph from each isomorphic subgraph set, and constructing a quantum circuit based on the obtained N isomorphic subgraphs.
  • the first directed acyclic graph of the quantum program is first constructed, and then the first directed acyclic graph is traversed to obtain a maximum subgraph sequence including N maximum subgraphs, and then N maximum subgraphs are determined.
  • the largest subgraph is the isomorphic subgraph in the topology structure, and finally a quantum circuit is constructed based on the obtained set of N largest subgraphs, so as to convert the quantum program into a quantum circuit supported by the current quantum computing platform, and realize the construction of a quantum circuit.
  • the construction of the first directed acyclic graph of the quantum program includes:
  • a first directed acyclic graph is constructed based on the quantum logic gate, and the first directed acyclic graph includes a node and a directed edge; the node includes two points and an edge, and the two points are used to represent The two logic qubits corresponding to the quantum logic gate, the one edge is used to represent the quantum logic gate acting on the two logic qubits; the directed edge is used to represent that the quantum logic gate is a logic qubit The dependence of the quantum state evolution timing.
  • the quantum logic gate includes multiple quantum logic gates; and the construction of the first directed acyclic graph based on the quantum logic gate includes:
  • the single quantum logic gate is deleted, and a first directed acyclic graph is constructed based on the two quantum logic gates.
  • the quantum program includes a single quantum logic gate, two quantum logic gates, and multiple quantum logic gates
  • the multiple quantum logic gates are first converted into single quantum logic gates and two quantum logic gates, and then the single quantum logic gates obtained after conversion are converted into single quantum logic gates and two quantum logic gates.
  • the quantum logic gate and the single quantum logic gate existing in the quantum program before the transformation are deleted, and then the first directed acyclic graph is constructed based on the two quantum logic gates obtained after the transformation and the two quantum logic gates existing in the quantum program before the transformation.
  • the existence of the single quantum logic gate in the first directed acyclic graph does not affect the construction of the maximum subgraph.
  • the largest subgraph obtained by the first directed acyclic graph is the same. Therefore, the single quantum logic gate is removed here for simplicity.
  • the construction of the first directed acyclic graph based on the quantum logic gate includes:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on the same two logic qubits, then based on the number of consecutive two-quantum logic gates in the Either one constructs the first directed acyclic graph.
  • a quantum program includes two CZs (q[0], q[1]) and two CZs (q[0], q[1]) are adjacent in time sequence, then the two CZs (q [0], q[1]) are two quantum logic gates that are continuous and act on the same two logic qubits. There are other two quantum logic gates between the two CZs (q[0], q[1]), so the two are not two consecutive quantum logic gates that act on the same two logic qubits.
  • first directed acyclic graph For multiple consecutive two-quantum logic gates acting on the same two logic qubits, construct the first directed acyclic graph based on any one of them, or construct the first directed acyclic graph based on multiple of them, through The largest subgraph generated by the first directed acyclic graph constructed by the two is the same. Also, for simplicity, the first directed acyclic graph is constructed based on only one of them.
  • the method further includes:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on two different logic qubits, then based on the plurality of consecutive two-quantum logic gates, the Construct the first directed acyclic graph.
  • a quantum program includes two consecutive CZs. As long as one of the qubits acting on the two CZs is different, then the two are two consecutive logical qubits with different functions of the two quantum logic gates. When building to an acyclic graph, you need to build based on both.
  • the transposed conjugated quantum circuit needs to be transformed, and then the first directed acyclic graph is constructed based on the transformed quantum circuit; If there is a measurement operation in the quantum program, the processing method for the measurement operation is the same as that of the single quantum logic gate, delete the measurement operation or single quantum logic gate, record the measurement operation or single quantum logic gate information, and then base on the two quantum logic The gate constructs the first directed acyclic graph.
  • the specific implementation method of constructing the first directed acyclic graph based on two quantum logic gates is:
  • the node Constructing a node corresponding to the two quantum logic gates, the node includes two points and an edge, the two points are used to represent the two logic qubits corresponding to the two quantum logic gates, and the one edge is used for represents a quantum logic gate acting on two logic qubits;
  • a first directed acyclic graph is obtained based on the nodes and the directed edges.
  • FIG. 2B is a schematic structural diagram of a quantum circuit provided by an embodiment of the present application.
  • a first directed acyclic graph of the quantum circuit can be constructed, as shown in FIG. 2C , which is a schematic diagram of the first directed acyclic graph corresponding to the quantum circuit shown in FIG. 2B .
  • the first directed acyclic graph includes 6 nodes and 8 directed edges.
  • in-degree is one of the important concepts in graph theory algorithms, which usually refers to the sum of the times that a certain point in a directed graph is used as the end point of an edge in the graph.
  • the first node with an in-degree of 0 in the first directed acyclic graph is first determined, and the first subgraph is generated based on the first node; then the first node is deleted to obtain the second In the directed acyclic graph, determine whether there is a second node with an in-degree of 0 in the second directed acyclic graph; if there is no second node in the second directed acyclic graph, the first subgraph is determined as the largest subgraph graph, and arrange the largest subgraphs in the order of generation to obtain the largest subgraph sequence.
  • the embodiment of the present application provides a method for determining the maximum subgraph sequence, which determines the maximum subgraph sequence from the perspective of graph theory, and realizes the maximum subgraph sequence when the second node does not exist in the second directed acyclic graph. ok.
  • the method further includes:
  • the second node exists in the second directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent Two logical qubits in a quantum program, the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the The first subgraph is determined;
  • a maximum subgraph is generated.
  • the node corresponding to CZ(q[0], q[1] it includes two points and one edge: the point corresponding to q[0] and the point corresponding to q[1], The edge between the point corresponding to q[0] and the point corresponding to q[1].
  • the point corresponding to q[0] represents the logical qubit q[0]
  • the point corresponding to q[1] represents the logical qubit q[1]
  • the edges represent CZ gates acting on logical qubits q[0] and logical qubits q[1].
  • the priority of the second node is determined, and the maximum subgraph is generated based on the priority of the second node and the second node .
  • the embodiment of the present application provides a method for determining the maximum subgraph sequence. From the perspective of graph theory, the maximum subgraph sequence is determined. When there is a second node in the second directed acyclic graph, the priority of the second node is based on the second node. and the second node to generate the largest subgraph, thereby realizing the determination of the largest subgraph sequence.
  • the priority of the second node is the first priority
  • the first subgraph is expanded into a second subgraph, and the second subgraph is used as a new first subgraph subgraph
  • the specific implementation manner of extending the first subgraph to the second subgraph is: if there is one of the two points in the first subgraph and the one edge does not exist , then take one of the existing two points as the vertex as the edge, get the other point in the two points, take the connection between the two points as the one edge, set the The expanded first subgraph is used as the second subgraph.
  • the first subgraph is expanded into the second subgraph based on the second node, and the second subgraph is used as a new The first subgraph; then delete the second node to obtain a third directed acyclic graph; take the third directed acyclic graph as a new second directed acyclic graph, and then perform the steps described in determining the second directed acyclic graph Whether there is a second node in the acyclic graph.
  • An embodiment of the present application provides a method for determining the largest subgraph. When the priority of the second node is the first priority, the first subgraph is expanded until the first subgraph cannot be expanded, and the obtained result is The largest subgraph, thus realizing the determination of the largest subgraph.
  • the method further includes:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the method further includes:
  • the second node whose priority is the first priority is deleted, and the new first subgraph is determined as the largest subgraph.
  • the second node there are two situations: one is that the subgraph can be continued to expand based on the second node, so as to obtain a larger subgraph than the previous one; the other is that it cannot be based on the second node.
  • the two nodes continue to expand the subgraph, then the current subgraph is the largest subgraph.
  • the priority of the first case must be greater than the priority of the second case, otherwise, the obtained subgraph is not the largest subgraph.
  • the priority of the second node is the second priority
  • the second node is used as the new first node, and then the steps described in the steps to generate the first node based on the first node are performed.
  • subgraph The embodiment of the present application provides a method for determining the largest subgraph.
  • the priority of the second node is the second priority, that is, the first subgraph cannot be expanded, it is the largest subgraph, so the obtained first subgraph
  • the graph is determined as the largest subgraph, and then the second node is used as the new first node to start searching for other largest subgraphs, thereby realizing the determination of the largest subgraph.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • the priorities in descending order are: the first sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • the above embodiments have described the basis for determining the first priority (ie, the first sub-priority and the second sub-priority) and the second priority (ie, the third sub-priority and the fourth sub-priority), that is, it can be obtained.
  • the third sub-priority is smaller than the second sub-priority, which is not described here. Therefore, it can be determined that the priorities in descending order are: the first sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • the priority of the second node is determined as the fourth subpriority; points and there is no edge, then the priority of the second node is determined as the third sub-priority; if there is one of the two points in the first subgraph and there is no edge, then the second node is The priority of the node is determined as the second sub-priority; if there are two points and one edge in the first sub-graph, the priority of the second node is determined as the first sub-priority; the priorities from large to small are: First sub-priority, second sub-priority, third sub-priority, fourth sub-priority.
  • An embodiment of the present application provides a method for determining the priority of a second node. Two points and an edge included in the second node are used as feature points, and the size of the priority is determined according to the number of the feature points. Priority determination.
  • the first directed acyclic graph corresponding to the quantum program is shown in Fig. 2C.
  • the first node in the directed acyclic graph is the node corresponding to CZ(q[0], q[1]). Take the two points included in the first node (the point corresponding to q[0] and the point corresponding to q[1]) as the two endpoints in the first subgraph, and the edge included in the first node as the first subgraph The edge of , obtains the first subgraph, as shown in FIG. 2D , which is a schematic diagram of the first subgraph determined based on the first node in the first directed acyclic graph shown in FIG. 2C .
  • the second directed acyclic graph is obtained by deleting the first node, as shown in FIG. 2E , which is a schematic diagram of the second directed acyclic graph obtained after deleting the first node in FIG. 2C . Then determine whether there is a second node in the second directed acyclic graph.
  • the in-degree of the node corresponding to CZ(q[0], q[2]) in the second directed acyclic graph is 0, so CZ(q[0 ], the node corresponding to q[2]) is the second node.
  • the second node includes two points: a point corresponding to q[0] and a point corresponding to q[2], and an edge therebetween.
  • FIG. 2F is a schematic diagram of a second subgraph obtained by extending the second node on FIG. 2D based on the second node. Then, the above-mentioned second subgraph is taken as the new first subgraph, the second node is deleted, and the third directed acyclic graph is obtained, as shown in Fig. 2G, which is the third directed acyclic graph obtained after deleting the second node in Fig. 2E.
  • the third directed acyclic graph is regarded as a new second directed acyclic graph, and then it is determined whether there is a second node in the new second directed acyclic graph. Since the in-degree of the node corresponding to CZ(q[0], q[3]) and the in-degree of the node corresponding to CZ(q[1], q[2]) are both 0, there are two second nodes here . Determine the priority of the node corresponding to CZ(q[0], q[3]) and the priority of the node corresponding to CZ(q[1], q[2]).
  • a point in the node corresponding to CZ(q[0], q[3]) is in the new first subgraph, and its priority is the second subpriority; CZ(q[1], q[2])
  • the two points in the corresponding node are in the new first subgraph, but the edge between the two points is not in the new first subgraph, so its priority is the fourth subpriority.
  • the second sub-priority is greater than the fourth sub-priority, and the node corresponding to the second sub-priority is executed first.
  • the new first subgraph is expanded into a second subgraph, as shown in Figure 2H, which is the second subgraph obtained by expanding on Figure 2F based on the new second node.
  • Figure 2H Schematic diagram of the subgraph. Then execute the node corresponding to CZ(q[1], q[2]), since the priority corresponding to the node is the fourth sub-priority, the new first sub-graph obtained above is determined as the largest sub-graph.
  • FIG. 2J which is a schematic diagram of the first subgraph determined based on the first node in the first directed acyclic graph shown in FIG. 2I .
  • Figure 2K is the second directed acyclic graph obtained after deleting the first node in Figure 2J Schematic diagram of an acyclic graph. Then it is determined whether there is a second node in the second directed acyclic graph.
  • the in-degree of the node corresponding to CZ(q[1], q[3]) in the second directed acyclic graph is 0, so CZ(q[1] ], the node corresponding to q[3]) is the second node.
  • the second node includes two points: a point corresponding to q[1] and a point corresponding to q[3], and an edge therebetween.
  • 2L is a schematic diagram of a second subgraph obtained by extending on FIG. 2J based on the second node. Then, the above-mentioned second subgraph is taken as the new first subgraph, and the node corresponding to the second node CZ(q[1], q[3]) is deleted to obtain a third directed acyclic graph, as shown in Figure 2M 2M is a schematic diagram of the third directed acyclic graph obtained after deleting the second node in FIG. 2K .
  • the third directed acyclic graph is regarded as a new second directed acyclic graph, and then it is determined whether there is a second node in the new second directed acyclic graph.
  • the node corresponding to CZ(q[2], q[3]) is the second node. Both points in the node corresponding to CZ(q[2], q[3]) are in the new first subgraph, but the edge between the two points is not in the new first subgraph, so its priority is the fourth sub-priority.
  • the new first subgraph obtained above is determined as the largest subgraph.
  • the first node includes two points (the point corresponding to q[2] and the point corresponding to q[3]) as the two endpoints in the first subgraph, and the edge included in the first node is used as the edge of the first subgraph
  • the first subgraph is obtained, as shown in FIG. 2N , which is a schematic diagram of the first subgraph determined based on the first node in the third directed acyclic graph shown in FIG. 2M .
  • the obtained second DAG is empty, there is no second node in the second DAG, and the first subgraph is determined as Maximum subgraph.
  • three maximum subgraphs can be obtained: CZ(q[0], q[1]) ⁇ CZ(q[0], q[2]) ⁇ CZ(q[0], q[3] ) (as shown in Figure 2H); CZ(q[1], q[2]) ⁇ CZ(q[1], q[3])
  • the largest subgraph (as shown in Figure 2L) shown); the largest subgraph formed by CZ(q[2], q[3]) (as shown in Figure 2N). Arrange the three subgraphs in the order in which they are obtained to obtain the largest subgraph sequence.
  • FIG. 20 is a schematic diagram of a first directed acyclic graph including a single quantum logic gate according to an embodiment of the present application.
  • the node corresponding to H[0] only includes one point (the point corresponding to q[0]), so the obtained first subgraph is a point. Expand at this point and execute the node corresponding to CZ(q[0], q[1]), the first subgraph above can be expanded to Figure 2D, the subsequent steps are the same, and the 0th largest subgraph (Figure 2D) can be obtained. 2H). Delete the node corresponding to CZ(q[0], q[3]) to obtain a new first directed acyclic graph, as shown in Fig. 2P, Fig. 2P is a new first directed acyclic graph obtained based on Fig. 2O Schematic diagram of the figure.
  • the in-degree of the node corresponding to CZ(q[1], q[2]) and the node corresponding to H(q[3]) are both 0, and the two nodes are the new first
  • the first subgraph does not include the points or edges that both include, so both have the same priority.
  • Either build the first subgraph based on the nodes corresponding to CZ(q[1], q[2]) or build the first subgraph based on the nodes corresponding to H(q[3]), H(q[3] ) corresponding nodes include points that can be incorporated into the first largest subgraph (Fig. 2L).
  • the subsequent steps are the same to obtain the second largest subgraph (Fig. 2N).
  • the exchange cost constructs a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for conversion between the quantum logic gates corresponding to the isomorphic subgraph .
  • FIG. 2Q is a topological structure diagram of a physical qubit in an electronic device provided by an embodiment of the present application.
  • the electronic device includes 8 physical qubits, Q[0], Q[1], Q[2], Q[3], Q[4], Q[5], Q[6], Q[7 ].
  • Q[0] is connected to Q[1] and Q[4]
  • Q[5] is connected to Q[1]
  • Q[2] is connected to Q[1]
  • Q [6] and Q[3] are connected
  • Q[7] is connected to Q[3] and Q[6].
  • FIG. 2R is a schematic diagram of an isomorphic subgraph provided by an embodiment of the present application. The specific forms of each first isomorphic subgraph, each second isomorphic subgraph, and each third isomorphic subgraph will not be listed in detail here.
  • the first fixed cost set includes 24 first fixed cost sets.
  • Fixed cost, the second fixed cost set includes 32 second fixed costs, and the third fixed cost set includes 20 third fixed costs; determine the isomorphism in any adjacent isomorphic subgraph sets in the above three isomorphic subgraph sets
  • the exchange cost between pairs of subgraphs can be obtained by obtaining the first exchange cost between the 24 ⁇ 32 0th isomorphic subgraph set and the isomorphic subgraphs in the first isomorphic subgraph set, and can Obtain the second exchange cost between the isomorphic subgraphs in the 32 ⁇ 20 first isomorphic subgraph set and the second isomorphic subgraph set.
  • a quantum circuit is constructed based on 24 first fixed costs, 32 second fixed costs, 20 third fixed costs, 24 ⁇ 32 first exchange costs, and 32 ⁇ 20 second exchange costs.
  • the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and the exchange between the isomorphic subgraphs in any adjacent isomorphic subgraph sets are determined first. cost, and constructing a quantum circuit based on fixed cost and exchange cost; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for the transformation between the quantum logic gates corresponding to the isomorphic subgraph.
  • the embodiment of the present application provides a method for constructing a quantum circuit, which constructs a quantum circuit through the fixed cost of the isomorphic subgraph and the exchange cost between the isomorphic subgraphs, thereby realizing the construction of the quantum circuit.
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs, and the largest subgraph
  • the numbering of the graph sequence starts from 0 and goes up to N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and the isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange cost between the two, and the construction of a quantum circuit based on the fixed cost and the exchange cost including:
  • the 0th isomorphic subgraph set includes 24 first isomorphic subgraphs, each first isomorphic subgraph corresponds to a fixed cost, and the first fixed cost set includes 24 first isomorphic subgraphs Fixed cost;
  • the first isomorphic subgraph set includes 32 second isomorphic subgraphs, each second isomorphic subgraph corresponds to a fixed cost, and the second fixed cost set includes 32 second fixed costs;
  • the second The isomorphic subgraph set includes 20 third isomorphic subgraphs, each third isomorphic subgraph corresponds to a fixed cost, and the third fixed cost set includes 20 third fixed costs;
  • the 0th isomorphic subgraph set is the same as the There are 24 ⁇ 32 first exchange costs between the first isomorphic subgraph, and 32 ⁇ 20 second exchange costs between the first isomorphic subgraph set and the second isomorphic subgraph.
  • 24 ⁇ 32 ⁇ 20 can be constructed based on the 0th isomorphic subgraph set, the first isomorphic subgraph set and the second isomorphic subgraph set
  • each quantum circuit corresponds to a consumption cost
  • each consumption cost is determined based on a first fixed cost, a second fixed cost, a third fixed cost, a first exchange cost and a second exchange cost.
  • the quantum circuit with the least consumption cost can be selected.
  • the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets is determined, and N fixed cost sets are obtained, N fixed cost sets and N isomorphic subgraph sets One-to-one correspondence; determine the exchange cost between any adjacent isomorphic subgraph sets in the N isomorphic subgraph sets, and obtain N-1 exchange cost sets, each exchange cost set includes k i ⁇ k i+1 exchange costs; determined based on N fixed cost sets and N-1 exchange cost sets consumption cost; based on A consumption cost to build a quantum circuit.
  • the embodiment of the present application provides a method for constructing a quantum circuit.
  • the quantum circuit constructed in the embodiment of the present application has the lowest consumption cost and is more accurate. The highest degree is obtained, and the quality of the resulting quantum circuit is also the highest.
  • the quantum circuit construction method provided by the above application embodiment can find the quantum circuit with the lowest consumption cost. However, the amount of calculation and storage is very huge. Therefore, this application provides another method for constructing a quantum circuit. Please refer to the specific method. See the examples below.
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs, and the largest subgraph
  • the numbering of the graph sequence starts from 0 and goes up to N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and the isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange cost between the two, and the construction of a quantum circuit based on the fixed cost and the exchange cost including:
  • Each exchange cost set includes k i exchange costs
  • each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph to obtain k 0 new first isomorphic subgraphs isomorphism subgraph;
  • the first fixed cost of the new first isomorphic subgraph is based on its corresponding first fixed cost of the previous first isomorphic subgraph, the second fixed cost of the previous second isomorphic subgraph, and the above
  • the exchange cost of a first isomorphic subgraph with the previous second isomorphic subgraph is determined.
  • FIG. 2S is a schematic diagram of mutual matching between isomorphic subgraphs provided by an embodiment of the present application.
  • the first fixed cost set includes 24 first fixed costs, which are respectively the first fixed cost 0.
  • It includes 32 second fixed costs, which are respectively second fixed cost 0, second fixed cost 1...second fixed cost 31.
  • the exchange cost set 0 can be obtained, and the exchange cost set 0 includes the exchange cost 00.
  • Exchange cost 10 exchange cost 20...exchange cost 310; determine the exchange cost of the second isomorphic subgraph 0, the second isomorphic subgraph 1...the second isomorphic subgraph 31 and the first isomorphic subgraph 1,
  • Exchange cost set 1 can be obtained.
  • Exchange cost set 1 includes exchange cost 01, exchange cost 11, exchange cost 21...exchange cost 311...until the second isomorphic subgraph 0, the second isomorphic subgraph 1...the second isomorphic subgraph is determined.
  • the exchange cost of the sub-graph 31 and the first isomorphic sub-graph 23 can be obtained to obtain the exchange cost set 23.
  • the exchange cost set 23 includes exchange cost 023, exchange cost 123, exchange cost 223...exchange cost 3123.
  • the consumption cost 00 of the first isomorphic subgraph 0 and the second isomorphic subgraph 0 is determined based on the exchange cost 00, the first fixed cost 0, and the second fixed cost 0; the first isomorphic subgraph 0 and the second isomorphic subgraph 0
  • the consumption cost 10 of FIG. 1 is determined based on the exchange cost 10, the first fixed cost 0, the second fixed cost 1...
  • the consumption cost 310 of the first isomorphic subgraph 0 and the second isomorphic subgraph 31 is based on the exchange cost 310, the first The fixed cost 0 and the second fixed cost 31 are determined; the consumption cost 00, the consumption cost 10...the consumption cost 310 constitute the consumption cost set 0;
  • the consumption cost 01 of the first isomorphic subgraph 1 and the second isomorphic subgraph 0 is determined based on the exchange cost 01, the first fixed cost 1, and the second fixed cost 0; the first isomorphic subgraph 1 and the second isomorphic subgraph
  • the consumption cost 11 of Fig. 1 is determined based on the exchange cost 11, the first fixed cost 1, the second fixed cost 1...
  • the consumption cost 311 of the first isomorphic subgraph 1 and the second isomorphic subgraph 31 is based on the exchange cost 311, the first The fixed cost 1 and the second fixed cost 31 are determined; the consumption cost 01, the consumption cost 11...the consumption cost 311 constitute the consumption cost set 1;
  • the consumption cost 023 of the first isomorphic subgraph 23 and the second isomorphic subgraph 0 is determined based on the exchange cost 023, the first fixed cost 23, and the second fixed cost 0; the first isomorphic subgraph 23 and the second isomorphic subgraph 0
  • the consumption cost 123 of Fig. 1 is determined based on the exchange cost 123, the first fixed cost 23, the second fixed cost 1...
  • the consumption cost 3123 of the first isomorphic subgraph 23 and the second isomorphic subgraph 31 is based on the exchange cost 3123, the first isomorphic subgraph 31
  • the fixed cost 23 and the second fixed cost 31 are determined; the consumption cost 023 , the consumption cost 123 , and the consumption cost 3123 constitute the consumption cost set 23 .
  • Determine the minimum consumption cost in the consumption cost set 0 determine the minimum consumption cost in the consumption cost set 1... Determine the minimum consumption cost in the consumption cost set 23, and obtain 24 minimum consumption costs.
  • the first isomorphic subgraph 0 and its corresponding second isomorphic subgraph form a new first isomorphic subgraph 0, and the first isomorphic subgraph 1 and its corresponding second isomorphic subgraph are formed
  • the first isomorphic subgraph 23 and its corresponding second isomorphic subgraph form a new first isomorphic subgraph 23; the new first isomorphic subgraph 0,
  • the new first isomorphic subgraph 1 . . . the new first isomorphic subgraph 23 constitutes a new first isomorphic subgraph set.
  • the first fixed cost set includes 24 first fixed costs, which are respectively the first fixed cost 0 ', the first fixed cost 1'...the first fixed cost 23'; determine each second isomorphic subgraph in the second isomorphic subgraph set (here the third isomorphic subgraph is a new second isomorphic subgraph The second fixed cost of Fig. ) is obtained, and the second fixed cost set is obtained.
  • the second fixed cost set includes 32 second fixed costs, which are respectively the second fixed cost 0', the second fixed cost 1'...the second fixed cost 31' .
  • the exchange cost set 0' can be obtained, the exchange cost Set 0' includes exchange cost 00', exchange cost 10', exchange cost 20'...exchange cost 310'; determine second isomorphic subgraph 0', second isomorphic subgraph 1'...second isomorphic subgraph 31
  • the exchange cost of 'with the first isomorphic subgraph 1', the exchange cost set 1' can be obtained, and the exchange cost set 1' includes exchange cost 01', exchange cost 11', exchange cost 21'...exchange cost 311'...
  • the exchange cost set 23' includes exchange cost 023', exchange cost 123', exchange cost 223'...exchange cost 3123'.
  • the consumption cost 00' of the first isomorphic subgraph 0' and the second isomorphic subgraph 0' is determined based on the exchange cost 00', the first fixed cost 0', and the second fixed cost 0'; the first isomorphic subgraph 0 'Consumption cost 10' with second isomorphic subgraph 1' is determined based on exchange cost 10', first fixed cost 0', second fixed cost 1'... First isomorphic subgraph 0' and second isomorphic subgraph
  • the consumption cost 310' of FIG. 31' is determined based on the exchange cost 310', the first fixed cost 0', the second fixed cost 31'; the consumption cost 00', the consumption cost 10'...the consumption cost 310' constitute the consumption cost set 0';
  • the consumption cost 01' of the first isomorphic subgraph 1' and the second isomorphic subgraph 0' is determined based on the exchange cost 01', the first fixed cost 1', and the second fixed cost 0'; the first isomorphic subgraph 1 'Consumption cost 11' with second isomorphic subgraph 1' is determined based on exchange cost 11', first fixed cost 1', second fixed cost 1'... First isomorphic subgraph 1' and second isomorphic subgraph 1'
  • the consumption cost 311' in Fig. 31' is determined based on the exchange cost 311', the first fixed cost 1', the second fixed cost 31'; the consumption cost 01', the consumption cost 11'...the consumption cost 311' constitute the consumption cost set 1';
  • the consumption cost 023' of the first isomorphic subgraph 23' and the second isomorphic subgraph 0' is determined based on the exchange cost 023', the first fixed cost 23', and the second fixed cost 0';
  • the first isomorphic subgraph 23 'Consumption cost 123' with second isomorphic subgraph 1' is determined based on exchange cost 123', first fixed cost 23', second fixed cost 1'...
  • first isomorphic subgraph 23' and second isomorphic subgraph Consumption cost 3123' in Fig. 31' is determined based on exchange cost 3123', first fixed cost 23', second fixed cost 31';
  • Quantum circuit 0 is composed of a first isomorphic subgraph 0, its corresponding second isomorphic subgraph, and its corresponding third isomorphic subgraph;
  • quantum circuit 1 is composed of a first isomorphic subgraph 1, its corresponding second isomorphic subgraph The isomorphic subgraph and its corresponding third isomorphic subgraph constitute...
  • the quantum circuit 23 is composed of the first isomorphic subgraph 23 , its corresponding second isomorphic subgraph, and its corresponding third isomorphic subgraph. Choose the quantum circuit with the least consumption cost.
  • the first fixed cost of each first isomorphic subgraph in the first isomorphic subgraph set is determined, and the first fixed cost set is obtained, and the first isomorphic subgraph set is the first isomorphic subgraph set.
  • the first isomorphic subgraphs are in one-to-one correspondence; each first
  • the embodiment of the present application provides another method for constructing a quantum circuit.
  • the largest subgraph sequence is matched from front to back, and k 0 consumption costs are found, and the number of consumption costs corresponds to the 0th largest subgraph The number of isomorphic subgraphs is equal.
  • an isomorphic subgraph corresponding to each largest subgraph is determined, and then a isomorphic subgraph corresponding to each largest subgraph is used to construct a quantum circuit.
  • every two adjacent isomorphic subgraph sets are screened once, and only the optimal isomorphic subgraphs with the same number of isomorphic subgraphs corresponding to the 0th largest subgraph are obtained each time. While reducing the amount of computation and storage, quantum circuits can be constructed.
  • the quantum circuit construction method provided by the above-mentioned one embodiment of the application can find the quantum circuit with the least consumption, however, the amount of calculation and storage thereof is very huge; although the construction method of the quantum circuit provided by the above-mentioned another application embodiment reduces the amount of calculation and storage, but may ignore the optimal quantum circuit. Therefore, the present application provides another method for constructing a quantum circuit. For the specific method, please refer to the following embodiments.
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs, and the largest subgraph
  • the numbering of the graph sequence starts from 0 and goes up to N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and the isomorphic subgraphs in any adjacent isomorphic subgraph sets
  • the exchange cost between the two, and the construction of a quantum circuit based on the fixed cost and the exchange cost including:
  • Each exchange cost set includes k 0 exchange costs
  • each consumption cost set includes k 0 consumption costs
  • Each second isomorphic subgraph and its corresponding first isomorphic subgraph in the k i second isomorphic subgraphs are formed into a new first isomorphic subgraph, and k i new first isomorphic subgraphs are obtained. isomorphism subgraph;
  • FIG. 2T is a schematic diagram of mutual matching between isomorphic subgraphs provided by an embodiment of the present application.
  • the first fixed cost set includes 24 first fixed costs, which are respectively the first fixed cost 0.
  • the exchange cost set 0 can be obtained, and the exchange cost set 0 includes the exchange cost 00, exchange cost 01, exchange cost 01...exchange cost 023; determine the exchange cost of the first isomorphic subgraph 0, the first isomorphic subgraph 1...the first isomorphic subgraph 23 and the second isomorphic subgraph 1, Exchange cost set 1 can be obtained, and exchange cost set 1 includes exchange cost 10, exchange cost 11, exchange cost 12...exchange cost 123; ...
  • the exchange cost of the isomorphic subgraph 23 and the second isomorphic subgraph 31 can be obtained as an exchange cost set 31, and the exchange cost set 31 includes an exchange cost 310, an exchange cost 311, an exchange cost 312... an exchange cost 3123.
  • the consumption cost 00 of the first isomorphic subgraph 0 and the second isomorphic subgraph 0 is determined based on the exchange cost 00, the first fixed cost 0, and the second fixed cost 0; the first isomorphic subgraph 1 and the second isomorphic subgraph 0
  • the consumption cost 01 of the graph 0 is determined based on the exchange cost 01, the first fixed cost 1, the second fixed cost 0..
  • the consumption cost 023 of the first isomorphic subgraph 23 and the second isomorphic subgraph 0 is based on the exchange cost 023, the first The fixed cost 23 and the second fixed cost 0 are determined; the consumption cost 00, the consumption cost 01...the consumption cost 023 constitute the consumption cost set 0;
  • the consumption cost 10 of the first isomorphic subgraph 0 and the second isomorphic subgraph 1 is determined based on the exchange cost 10, the first fixed cost 0, and the second fixed cost 1; the first isomorphic subgraph 1 and the second isomorphic subgraph 1
  • the consumption cost 11 of Fig. 1 is determined based on the exchange cost 11, the first fixed cost 1, the second fixed cost 1...
  • the consumption cost 123 of the first isomorphic subgraph 23 and the second isomorphic subgraph 1 is based on the exchange cost 123, the first The fixed cost 23 and the second fixed cost 1 are determined; the consumption cost 10, the consumption cost 11...the consumption cost 123 constitute the consumption cost set 1;
  • the consumption cost 310 of the first isomorphic subgraph 0 and the second isomorphic subgraph 31 is determined based on the exchange cost 310, the first fixed cost 0, and the second fixed cost 31; the first isomorphic subgraph 1 and the second isomorphic subgraph 31
  • the consumption cost 311 of Fig. 31 is determined based on the exchange cost 311, the first fixed cost 1, the second fixed cost 31...
  • the consumption cost 3123 of the first isomorphic subgraph 23 and the second isomorphic subgraph 31 is based on the exchange cost 3123, the first isomorphic subgraph 31
  • the fixed cost 23 and the second fixed cost 31 are determined; the consumption cost 310 , the consumption cost 311 , and the consumption cost 3123 constitute the consumption cost set 31 .
  • Determine the minimum consumption cost in the consumption cost set 0 determine the minimum consumption cost in the consumption cost set 1... Determine the minimum consumption cost in the consumption cost set 31, and obtain 32 minimum consumption costs.
  • the second isomorphic subgraph 0 and its corresponding first isomorphic subgraph form a new first isomorphic subgraph 0, and the second isomorphic subgraph 1 and its corresponding first isomorphic subgraph form a new first isomorphic subgraph
  • the second isomorphic subgraph 31 and its corresponding first isomorphic subgraph form a new first isomorphic subgraph 31; the new first isomorphic subgraph 0,
  • the new first isomorphic subgraph 1 . . . the new first isomorphic subgraph 31 constitutes a new set of first isomorphic subgraphs.
  • the first fixed cost set includes 32 first fixed costs, which are respectively the first fixed cost 0 ', the first fixed cost 1'...the first fixed cost 31'; determine each second isomorphic subgraph in the second isomorphic subgraph set (here the third isomorphic subgraph is a new second isomorphic subgraph The second fixed cost of Fig. ) is obtained, and the second fixed cost set is obtained.
  • the second fixed cost set includes 20 second fixed costs, which are respectively the second fixed cost 0', the second fixed cost 1'...the second fixed cost 19' .
  • the exchange cost set 0' includes exchange cost 00', exchange cost 10', exchange cost 20'...exchange cost 310'; determine the first isomorphic subgraph 0', the first isomorphic subgraph 1'...the first isomorphic subgraph 31
  • the exchange cost of 'with the second isomorphic subgraph 1', the exchange cost set 1' can be obtained.
  • the exchange cost set 1' includes exchange cost 01', exchange cost 11', exchange cost 21'...exchange cost 311'...
  • the exchange cost set 19' includes exchange cost 019', exchange cost 119', exchange cost 219'...exchange cost 3119'.
  • the consumption cost 00' of the first isomorphic subgraph 0' and the second isomorphic subgraph 0' is determined based on the exchange cost 00', the first fixed cost 0', and the second fixed cost 0';
  • the first isomorphic subgraph 1 'Consumption cost 01' with the second isomorphic subgraph 0' is determined based on the exchange cost 01', the first fixed cost 1', the second fixed cost 0'...
  • the first isomorphic subgraph 31' and the second isomorphic subgraph Consumption cost 031' in Fig. 0' is determined based on exchange cost 031', first fixed cost 31', second fixed cost 0'; consumption cost 00', consumption cost 01'...consumption cost 031' constitutes consumption cost set 0';
  • the consumption cost 10' of the first isomorphic subgraph 0' and the second isomorphic subgraph 1' is determined based on the exchange cost 10', the first fixed cost 0', and the second fixed cost 1'; the first isomorphic subgraph 1 'Consumption cost 11' with second isomorphic subgraph 1' is determined based on exchange cost 11', first fixed cost 1', second fixed cost 1'... First isomorphic subgraph 31' and second isomorphic subgraph 31'
  • the consumption cost 131' of FIG. 1' is determined based on the exchange cost 131', the first fixed cost 31', and the second fixed cost 1'; the consumption cost 10', the consumption cost 11'...the consumption cost 131' constitutes the consumption cost set 1';
  • the consumption cost 310' of the first isomorphic subgraph 0' and the second isomorphic subgraph 31' is determined based on the exchange cost 310', the first fixed cost 0', and the second fixed cost 31'; the first isomorphic subgraph 1 'Consumption cost 311' with second isomorphic subgraph 31' is determined based on exchange cost 311', first fixed cost 1', second fixed cost 31'...
  • Consumption cost 1931' of FIG. 19' is determined based on exchange cost 1931', first fixed cost 31', second fixed cost 19'; consumption cost 310', consumption cost 311'... consumption cost 3119' constitutes consumption cost set 19'.
  • the quantum circuit 19 is composed of the third isomorphic subgraph 19 , its corresponding second isomorphic subgraph, and its corresponding first isomorphic subgraph. Choose the quantum circuit with the least consumption cost.
  • the first fixed cost of each first isomorphic subgraph in the first isomorphic subgraph set is determined, and the first fixed cost set is obtained, and the first isomorphic subgraph set is the first isomorphic subgraph set.
  • the k i second isomorphic subgraphs are in one-to-one correspondence; each second iso
  • the embodiment of the present application provides another method for constructing a quantum circuit.
  • the largest subgraph sequence is matched from the back to the front, and k N-1 consumption costs are found, and the number of consumption costs is the same as the N-1th consumption cost.
  • the number of isomorphic subgraphs corresponding to the largest subgraphs is equal.
  • an isomorphic subgraph corresponding to each largest subgraph is determined, and then an isomorphic subgraph corresponding to each largest subgraph is used.
  • screening is performed once every two adjacent isomorphic subgraph sets, and each time only the optimal isomorphic subgraphs with the same number of isomorphic subgraphs corresponding to the next largest subgraph are obtained, which greatly reduces the number of isomorphic subgraphs. While not only the amount of calculation and storage, but also the optimal quantum circuit can be constructed.
  • FIG. 2U is a schematic diagram of mutual matching between isomorphic subgraphs according to an embodiment of the present application.
  • the 0th isomorphic subgraph set includes the first isomorphic subgraph 0 and the first isomorphic subgraph 1, the first isomorphic subgraph set includes the second isomorphic subgraph 0 and the second isomorphic subgraph 1,
  • the second isomorphic subgraph set includes the third isomorphic subgraph 0 and the third isomorphic subgraph 1; the first isomorphic subgraph 0, the first isomorphic subgraph 1, the second isomorphic subgraph 0, the The fidelity of the two isomorphic subgraph 1, the third isomorphic subgraph 0 and the third isomorphic subgraph 1 itself is 1, and the fidelity between the first isomorphic subgraph 0 and the second isomorphic subgraph 0 degree is 0.9, the fidelity between the first isomorphic subgraph 0 and the second isomorphic subgraph 1 is 0.85, and
  • the quantum circuit is constructed by traversing from front to back: the consumption cost of the first isomorphic subgraph 0 and the second isomorphic subgraph 0 is 0.1 (1-1 ⁇ 0.9 ⁇ 1), and the first isomorphic subgraph 0 and the second isomorphism
  • the consumption cost of subgraph 1 is 0.15 (1-1 ⁇ 0.85 ⁇ 1), and the lowest consumption cost is selected to obtain a new first isomorphic subgraph 0.
  • the new first isomorphic subgraph 0 consists of the first isomorphic subgraph Figure 0 is composed of the second isomorphic subgraph 0; the consumption cost of the first isomorphic subgraph 1 and the second isomorphic subgraph 0 is 0.1 (1-1 ⁇ 0.9 ⁇ 1), and the first isomorphic subgraph 1 and The consumption cost of the second isomorphic subgraph 1 is 0.15 (1-1 ⁇ 0.85 ⁇ 1). Select the one with the lowest consumption cost to obtain a new first isomorphic subgraph 1.
  • the new first isomorphic subgraph 1 consists of the first
  • the isomorphic subgraph 1 is composed of the second isomorphic subgraph 0; the consumption cost of the new first isomorphic subgraph 0 and the third isomorphic subgraph 0 is 0.19 (1-1 ⁇ 0.9 ⁇ 1 ⁇ 0.9 ⁇ 1 ), the consumption cost of the new first isomorphic subgraph 0 and the third isomorphic subgraph 1 is 0.28 (1-1 ⁇ 0.9 ⁇ 1 ⁇ 0.8 ⁇ 1), select the one with the lowest consumption cost to get the new first isomorphic subgraph 1
  • Construct subgraph 0 the new first isomorphic subgraph 0 is composed of the first isomorphic subgraph 0, the second isomorphic subgraph 0, and the third isomorphic subgraph 0; the new first isomorphic subgraph 1 and The consumption cost of the third isomorphic subgraph 0 is 0.19(1-1 ⁇ 0.9 ⁇ 1 ⁇ 0.9 ⁇ 1), and the consumption cost of the new first isomorphic subgraph 1 and the third isomorphic sub
  • the quantum circuit can be constructed based on the first isomorphic subgraph 0, the second isomorphic subgraph 0, and the third isomorphic subgraph 0, or can be based on the first isomorphic subgraph 1, the third isomorphic subgraph
  • the second isomorphic subgraph 0 and the third isomorphic subgraph 0 construct quantum circuits.
  • the consumption cost of the second isomorphic subgraph 0 and the first isomorphic subgraph 0 is 0.1 (1-1 ⁇ 0.9 ⁇ 1)
  • the second isomorphic subgraph 0 is the same as the first isomorphic subgraph 0.
  • the consumption cost of subgraph 1 is 0.1 (1-1 ⁇ 0.9 ⁇ 1), and the one with the lowest consumption cost is selected to obtain a new first isomorphic subgraph 0.
  • the consumption cost of the two is the same, so the new first isomorphic Figure 0 can be composed of the first isomorphic subgraph 0 and the second isomorphic subgraph 0, or can be composed of the first isomorphic subgraph 1 and the second isomorphic subgraph 0; the second isomorphic subgraph 1 and the second isomorphic subgraph 0
  • the consumption cost of isomorphic subgraph 0 is 0.15 (1-1 ⁇ 0.85 ⁇ 1)
  • the consumption cost of second isomorphic subgraph 1 and second isomorphic subgraph 1 is 0.15 (1-1 ⁇ 0.85 ⁇ 1) , select the lowest consumption cost to obtain a new first isomorphic subgraph 1, both of which have the same consumption cost, so the new first isomorphic subgraph 1 can be composed of the first isomorphic subgraph 1 and the second isomorphic subgraph 0, it can also be composed of the first isomorphic subgraph 1 and the second isomorphic subgraph 1; the consumption cost of the new first isomorphic subgraph 0 and the
  • the new first isomorphic subgraph 1 can be composed of the first isomorphic subgraph 0, the second isomorphic subgraph 1,
  • the third isomorphic subgraph 0 can also be composed of the first isomorphic subgraph 1, the second isomorphic subgraph 1, and the third isomorphic subgraph 0; finally, from the new first isomorphic subgraph 0 and the new isomorphic subgraph 0
  • the isomorphic subgraph with the lowest consumption cost is selected to construct a quantum circuit.
  • the consumption cost of the new first isomorphic subgraph 1 is at least 0.85, so it can be based on the first isomorphic subgraph 0 and the second isomorphic subgraph 1.
  • the isomorphic subgraph 1 and the third isomorphic subgraph 0 construct a quantum circuit, or a quantum circuit can be constructed based on the first isomorphic subgraph 1, the second isomorphic subgraph 1, and the third isomorphic subgraph 0.
  • the result obtained is to construct a quantum circuit based on the first isomorphic subgraph 0, the second isomorphic subgraph 0, and the third isomorphic subgraph 0, or build a quantum circuit based on the first isomorphism Subgraph 1, the second isomorphic subgraph 0, and the third isomorphic subgraph 0 construct a quantum circuit; traverse the quantum circuit from front to back, and the result is based on the first isomorphic subgraph 0 and the second isomorphic subgraph 1.
  • the third isomorphic subgraph 0 constructs a quantum circuit, or constructs a quantum circuit based on the first isomorphic subgraph 1, the second isomorphic subgraph 1, and the third isomorphic subgraph 0.
  • the results obtained by the two are different.
  • the overall consumption cost of the former is 0.19, and the overall consumption cost of the latter is 0.15. Obviously, because of the former, the former is not the optimal way to construct quantum circuits.
  • the largest subgraph the largest subgraph sequence, the isomorphic subgraph, the isomorphic subgraph set, the first fixed cost set, the second fixed cost set, and the consumption cost set
  • the numbering starts from 0, and it can also be numbered from 1 or any other number or letter, which will not be illustrated here.
  • the fixed cost and the exchange cost are determined based on fidelity.
  • the fixed cost and the exchange cost are determined based on the number of CZ gates.
  • the fidelity corresponding to any double quantum logic gate can be equivalent to the fidelity corresponding to at least one CZ gate.
  • each isomorphic subgraph corresponds to a maximal subgraph
  • each maximal subgraph is determined based on at least one two-quantum logic gate
  • the fixed cost of each isomorphic subgraph is based on the fidelity corresponding to at least one two-quantum logic gate The product is determined.
  • the quantum logic gates corresponding to the largest subgraph 2H are CZ(q[0], q[1]), CZ(q[0], q[2]), CZ(q[0], q[3] );
  • the quantum logic gates corresponding to the largest subgraph 2L are CZ(q[1], q[2]), CZ(q[1], q[3]). Map the largest subgraph 2H and the largest subgraph 2L to Figure 2Q.
  • mapping relationship of the largest subgraph 2H is as follows: q[1]—>Q[0], q[0]—>Q[1], q[3 ]—>Q[2], q[2]—>Q[5], the mapping relationship of the largest subgraph 2L is as follows: q[3]—>Q[2], q[1]—>Q[1], q[2]—>Q[5].
  • the fidelity of the analog signal corresponding to the CZ gate acting on Q[0] and Q[1] is F01
  • the fidelity of the analog signal corresponding to the CZ gate acting on Q[1] and Q[2] is F12
  • the fidelity of the analog signal corresponding to the CZ gate acting on Q[1] and Q[5] is F15.
  • the fixed cost of the largest subgraph 2H is 1-F01 ⁇ F12 ⁇ F15; when executing CZ(q[1], q[2]), CZ(q[1], q[3]), you need to convert q[1]
  • the mapping relationship of q[0] is transformed from Q[0] to Q[1]
  • the fixed cost of the largest subgraph 2L is 1-F12 ⁇ F15;
  • the total consumption cost is 1-F01 ⁇ F12 ⁇ F15 ⁇ F12 ⁇ F15 ⁇ F013.
  • the fixed cost of the largest subgraph 2H is 3 CZ gates
  • the fixed cost of the largest subgraph 2L is 2 CZ gates
  • the exchange of the largest subgraph 2H and the largest subgraph 2L The cost is 3 CZ gates
  • the total consumption cost is 8 CZ gates.
  • FIG. 3 is a schematic flowchart of another quantum computing platform adaptation method provided by an embodiment of the present application. The method includes:
  • Step 301 Obtain the quantum program to be run and the topological structure of the quantum chip corresponding to the quantum computing platform, where the topological structure is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits.
  • Step 302 Obtain quantum logic gates in the quantum program.
  • Step 303 If the quantum logic gate includes multiple quantum logic gates, convert the multiple quantum logic gates into single quantum logic gates and two quantum logic gates.
  • Step 304 Delete the single quantum logic gate, and construct a first directed acyclic graph based on the two quantum logic gates.
  • Step 305 If the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on the same two logic qubits, then based on the plurality of consecutive two-quantum logic gates Any of the logic gates constructs a first directed acyclic graph.
  • Step 306 If the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on two different logic qubits, then based on the plurality of consecutive two-quantum logic gates
  • the logic gates construct a first directed acyclic graph in sequence, and the first directed acyclic graph includes a node and a directed edge; the node includes two points and an edge, and the two points are used to represent the quantum Two logic qubits corresponding to the logic gate, the one edge is used to represent the quantum logic gate acting on the two logic qubits; the directed edge is used to represent the quantum state of the quantum logic gate according to the logic qubit Evolutionary timing dependencies.
  • Step 307 Traverse the first directed acyclic graph to obtain a maximum subgraph sequence, where the maximum subgraph sequence includes N maximum subgraphs, where N is an integer greater than or equal to 1;
  • Step 308 Determine the isomorphic subgraphs of the N largest subgraphs in the topology structure, and obtain N isomorphic subgraph sets, the N isomorphic subgraph sets and the N largest subgraphs are one one correspondence;
  • Step 309 Construct a quantum circuit based on the set of N isomorphic subgraphs, the quantum circuit is allowed to run on the quantum computing platform.
  • the embodiments of the present application further provide the quantum circuit construction method shown in FIG. 4 to FIG. 7 , and the above quantum circuit construction method can be used to realize the above step of adapting the quantum program to the quantum computing platform based on the topology structure.
  • FIG. 4 is a schematic flowchart of another method for constructing a quantum circuit according to an embodiment of the present application.
  • the method includes:
  • Step 401 Construct a first directed acyclic graph of the quantum program.
  • Step 402 Determine a first node in the first directed acyclic graph, where the in-degree of the first node is 0.
  • Step 403 Generate a first subgraph based on the first node.
  • Step 404 Delete the first node to obtain a second directed acyclic graph.
  • Step 405 Determine whether there is a second node in the second directed acyclic graph, and the in-degree of the second node is 0; the second node includes two points and an edge, and the two points are is used to represent two logical qubits in a quantum program, and the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the first subgraph is determined;
  • step 415 is executed.
  • Step 406 Determine whether the two points and the one edge exist in the first subgraph.
  • Step 407 If one of the two points exists in the first subgraph and the one edge does not exist, determine the priority of the second node as the second subpriority.
  • Step 408 If the two points and the one edge exist in the first subgraph, determine the priority of the second node as the first subpriority.
  • Step 409 If the two points and the one edge do not exist in the first sub-graph, determine the priority of the second node as the fourth sub-priority.
  • Step 410 If the two points exist in the first subgraph and the one edge does not exist, determine the priority of the second node as a third subpriority.
  • the priorities in descending order are: the first sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • Step 411 If the priority of the second node is the second priority, the second node is used as the new first node, and then step 403 is performed, where the second priority includes the third sub-priority, Fourth child priority.
  • Step 412 If the priority of the second node is the first priority, then based on the second node, expand the first subgraph into a second subgraph, and use the second subgraph as a new subgraph.
  • the first sub-picture of , the first priority includes a first sub-priority and a second sub-priority.
  • Step 413 Delete the second node to obtain a third directed acyclic graph.
  • Step 414 Use the third DAG as a new second DAG, and then perform step 405 .
  • Step 415 Determine the first subgraph as the largest subgraph.
  • Step 416 Arrange the largest subgraphs in the order of generation to obtain a largest subgraph sequence, where the largest subgraph sequence includes N largest subgraphs, where N is an integer greater than or equal to 1.
  • Step 417 Determine the isomorphic subgraphs of the N largest subgraphs in the topology structure, and obtain a set of N isomorphic subgraphs, and the topology structure is used to represent the physical qubits in the electronic device and between the physical qubits.
  • the connection relationship of the N isomorphic subgraph sets is in one-to-one correspondence with the N largest subgraphs.
  • Step 418 Construct a quantum circuit based on the N isomorphic subgraph sets.
  • FIG. 5 is a schematic flowchart of another quantum circuit construction method provided by an embodiment of the present application. The method includes:
  • Step 501 Determine N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraphs are determined based on the directed acyclic graph of the quantum program.
  • the set is a bit relationship graph on the quantum chip obtained by the N largest subgraphs based on the topological structure of the quantum chip in the electronic device, where N is an integer greater than or equal to 1; the N largest subgraphs A maximum subgraph sequence is formed, the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs, and the number of the largest subgraph sequence starts from 0 and reaches N -1.
  • Step 502 Determine the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets, and obtain N fixed cost sets, the N fixed cost sets and the N isomorphic subgraph sets one by one correspond.
  • Step 503 Determine the exchange cost between two isomorphic subgraphs in any adjacent isomorphic subgraph sets in the N isomorphic subgraph sets, and obtain N-1 exchange cost sets, each of the exchange cost The set includes k i ⁇ k i+1 exchange costs.
  • Step 504 Determine based on the N fixed cost sets and the N-1 exchange cost sets consumption cost.
  • Step 505 Based on the A consumption cost to build a quantum circuit.
  • FIG. 6 is a schematic flowchart of still another quantum circuit construction method provided by an embodiment of the present application. The method includes:
  • Step 601 Determine N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraphs are determined based on the directed acyclic graph of the quantum program.
  • the set is a bit relationship graph on the quantum chip obtained by the N largest subgraphs based on the topological structure of the quantum chip in the electronic device, where N is an integer greater than or equal to 1; the N largest subgraphs A maximum subgraph sequence is formed, the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs, and the number of the largest subgraph sequence starts from 0 and reaches N -1.
  • Step 602 Determine the first fixed cost of each first isomorphic subgraph in the first isomorphic subgraph set, and obtain a first fixed cost set, where the first isomorphic subgraph set is the 0th largest subgraph The set of isomorphic subgraphs corresponding to the graph.
  • Step 603 Determine the second fixed cost of each second isomorphic subgraph in the second isomorphic subgraph set, and obtain a second fixed cost set, where the second isomorphic subgraph set is the i-th largest subgraph The set of isomorphic subgraphs corresponding to the graph.
  • Step 604 Determine the exchange cost of all the first isomorphic subgraphs in the first isomorphic subgraph set and each second isomorphic subgraph in the second isomorphic subgraph set, and obtain k i exchanges Cost sets, each exchange cost set includes k 0 exchange costs.
  • Step 605 Determine ki consumption cost sets based on the first fixed cost set, the second fixed cost set and the ki exchange cost sets, each consumption cost set includes k 0 consumption costs.
  • Step 606 Determine the minimum consumption cost in each of the consumption cost sets, and obtain ki minimum consumption costs, the ki minimum consumption costs are the same as the ki minimum consumption costs in the second isomorphic subgraph set.
  • the second isomorphic subgraphs are in one-to-one correspondence.
  • Step 607 compose each second isomorphic subgraph in the k i second isomorphic subgraphs and its corresponding first isomorphic subgraph into a new first isomorphic subgraph, and obtain k i isomorphic subgraphs The new first isomorphic subgraph.
  • Step 608 Determine the set formed by the k i new first isomorphic subgraphs as a new first isomorphic subgraph set.
  • Step 609 Determine whether i is equal to N-1;
  • step 610 If not, go to step 610;
  • Step 611 Construct quantum circuits based on the obtained k N-1 minimum consumption costs.
  • the quantum circuit construction method provided by the above-mentioned embodiment of the application can find the quantum circuit with the least consumption of the quantum program, however, the amount of calculation and storage is very huge; although the construction method of the quantum circuit provided by the above-mentioned other application embodiment reduces the The amount of computation and storage is reduced, but the optimal quantum circuit may be ignored. Therefore, the present application provides another method for constructing a quantum circuit. For the specific method, please refer to the following embodiments.
  • FIG. 7 is a schematic flowchart of still another quantum circuit construction method provided by an embodiment of the present application. The method includes:
  • Step 701 Determine N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraphs are determined based on the directed acyclic graph of the quantum program.
  • the set is a bit relationship graph on the quantum chip obtained by the N largest subgraphs based on the topological structure of the quantum chip in the electronic device, where N is an integer greater than or equal to 1; the N largest subgraphs A maximum subgraph sequence is formed, the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs, and the number of the largest subgraph sequence starts from 0 and reaches N -1.
  • Step 702 Determine the first fixed cost of each first isomorphic subgraph in the first isomorphic subgraph set, and obtain a first fixed cost set, where the first isomorphic subgraph set is the 0th largest subgraph The set of isomorphic subgraphs corresponding to the graph.
  • Step 703 Determine the second fixed cost of each second isomorphic subgraph in the second isomorphic subgraph set, and obtain a second fixed cost set, where the second isomorphic subgraph set is the i-th largest subgraph The set of isomorphic subgraphs corresponding to the graph.
  • Step 704 Determine the exchange cost of all second isomorphic subgraphs in the second isomorphic subgraph set and each first isomorphic subgraph in the first isomorphic subgraph set, and obtain k 0 exchanges Cost sets, each exchange cost set includes k i exchange costs.
  • Step 705 Determine k 0 consumption cost sets based on the first fixed cost set, the second fixed cost set and the k 0 exchange cost sets, each consumption cost set including k i consumption costs.
  • Step 706 Determine the minimum consumption cost in each of the consumption cost sets, and obtain k 0 minimum consumption costs, and the k 0 minimum consumption costs are the same as the k 0 minimum consumption costs in the first isomorphic subgraph set
  • the first isomorphic subgraphs are in one-to-one correspondence.
  • Step 707 Combine each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph, and obtain k 0 isomorphic subgraphs The new first isomorphic subgraph.
  • Step 708 Determine the set formed by the k 0 new first isomorphic subgraphs as a new first isomorphic subgraph set.
  • Step 709 Determine whether i is equal to N-1, the initial value of i is 1;
  • step 711 is executed.
  • Step 711 Construct quantum circuits based on the obtained k 0 minimum consumption costs.
  • FIG. 8 is a schematic structural diagram of an electronic device provided by an embodiment of the present application.
  • the electronic device includes a processor, a A memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, the program comprising instructions for performing the following steps:
  • the quantum program is adapted to the quantum computing platform based on the topology.
  • the program in terms of adapting the quantum program to the quantum computing platform based on the topology, includes instructions specifically for executing the following steps:
  • a quantum circuit is constructed based on the set of N isomorphic subgraphs, the quantum circuit allowing operation on the quantum computing platform.
  • the above-mentioned program includes instructions specifically for executing the following steps:
  • a first directed acyclic graph is constructed based on the quantum logic gate, and the first directed acyclic graph includes a node and a directed edge; the node includes two points and an edge, and the two points are used to represent The two logic qubits corresponding to the quantum logic gate, the one edge is used to represent the quantum logic gate acting on the two logic qubits; the directed edge is used to represent that the quantum logic gate is a logical quantum gate The dependence of the quantum state evolution timing of bits.
  • the quantum logic gate includes multiple quantum logic gates; in the aspect of constructing the first directed acyclic graph based on the quantum logic gate, the above program includes instructions specifically for executing the following steps :
  • the single quantum logic gate is deleted, and a first directed acyclic graph is constructed based on the two quantum logic gates.
  • the above program includes instructions specifically for executing the following steps:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on the same two logic qubits, then based on the number of consecutive two-quantum logic gates in the Either one constructs the first directed acyclic graph.
  • the above-mentioned program includes instructions further used to perform the following steps:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on two different logic qubits, then based on the plurality of consecutive two-quantum logic gates, the Construct the first directed acyclic graph.
  • the above program includes instructions specifically for executing the following steps:
  • the above program further includes instructions for executing the following steps:
  • the second node exists in the second directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent Two logical qubits in a quantum program, the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the The first subgraph is determined;
  • a maximum subgraph is generated.
  • the above program includes instructions specifically for executing the following steps:
  • the priority of the second node is the first priority
  • the first subgraph is expanded into a second subgraph, and the second subgraph is used as a new first subgraph subgraph
  • the above-mentioned program further includes instructions for executing the following steps:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • the above program includes instructions specifically for executing the following steps:
  • the priority of the second node is determined as the first sub-priority; the priorities in descending order are: the first sub-priority A sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • the program in terms of adapting the quantum program to the quantum computing platform based on the topology, includes instructions specifically for executing the following steps:
  • N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraph sets are all
  • the N largest subgraphs are based on the bit relationship graph on the quantum chip obtained by mapping the topological structure of the quantum chip in the electronic device, and the N is an integer greater than or equal to 1;
  • the exchange cost constructs a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for conversion between the quantum logic gates corresponding to the isomorphic subgraph .
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs , the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and any adjacent isomorphic subgraph set
  • the adaptation unit 902 is specifically used for:
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs , the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and any adjacent isomorphic subgraph set
  • the above program includes instructions specifically for performing the following steps:
  • Each exchange cost set includes k 0 exchange costs
  • each consumption cost set includes k 0 consumption costs
  • Each second isomorphic subgraph and its corresponding first isomorphic subgraph in the k i second isomorphic subgraphs are formed into a new first isomorphic subgraph, and k i new first isomorphic subgraphs are obtained. isomorphism subgraph;
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs , the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and any adjacent isomorphic subgraph set
  • the above program includes instructions specifically for performing the following steps:
  • Each exchange cost set includes k i exchange costs
  • each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph to obtain k 0 new first isomorphic subgraphs isomorphism subgraph;
  • the fixed cost and the exchange cost are determined based on fidelity.
  • the fixed cost and the exchange cost are determined based on the number of CZ gates.
  • the structure of the electronic device is shown in FIG. 4 , the electronic device includes a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs above Stored in the above-mentioned memory and configured to be executed by the above-mentioned processor, the above-mentioned program includes instructions for performing the following steps:
  • a quantum circuit is constructed according to the N largest subgraphs and the topology, and the topology is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits.
  • the above program includes instructions specifically for executing the following steps:
  • a quantum circuit is constructed based on the set of N isomorphic subgraphs.
  • the above-mentioned program includes instructions specifically for executing the following steps:
  • the above program in terms of traversing the first directed acyclic graph of the quantum program to obtain the maximum subgraph sequence, the above program further includes instructions for executing the following steps:
  • the second node exists in the second directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent Two logical qubits in a quantum program, the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the The first subgraph is determined;
  • a maximum subgraph is generated.
  • the above program includes instructions specifically for executing the following steps:
  • the priority of the second node is the first priority
  • the first subgraph is expanded into a second subgraph, and the second subgraph is used as a new first subgraph subgraph
  • the above program further includes instructions for executing the following steps:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • the priority of the second node is determined as the first sub-priority; the priorities in descending order are: the first sub-priority A sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • the structure of the electronic device is shown in FIG. 4 , the electronic device includes a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs above Stored in the above-mentioned memory and configured to be executed by the above-mentioned processor, the above-mentioned program includes instructions for performing the following steps:
  • N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraph sets are all
  • the N largest subgraphs are based on the bit relationship graph on the quantum chip obtained by mapping the topological structure of the quantum chip in the electronic device, and the N is an integer greater than or equal to 1;
  • the exchange cost constructs a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for conversion between the quantum logic gates corresponding to the isomorphic subgraph .
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the ith largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs The number of the largest subgraph sequence starts from 0 and reaches N-1; in the determining the fixed cost of each isomorphic subgraph in the set of N isomorphic subgraphs and any adjacent isomorphic subgraph
  • the above program includes instructions specifically for performing the following steps:
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the ith largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs The number of the largest subgraph sequence starts from 0 and reaches N-1; in the determining the fixed cost of each isomorphic subgraph in the set of N isomorphic subgraphs and any adjacent isomorphic subgraph
  • the above program includes instructions specifically for performing the following steps:
  • Each exchange cost set includes k 0 exchange costs
  • each consumption cost set includes k 0 consumption costs
  • Each second isomorphic subgraph and its corresponding first isomorphic subgraph in the k i second isomorphic subgraphs are formed into a new first isomorphic subgraph, and k i new first isomorphic subgraphs are obtained. isomorphism subgraph;
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the ith largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs The number of the largest subgraph sequence starts from 0 and reaches N-1; in the determining the fixed cost of each isomorphic subgraph in the set of N isomorphic subgraphs and any adjacent isomorphic subgraph
  • the above program includes instructions specifically for performing the following steps:
  • Each exchange cost set includes k i exchange costs
  • each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph to obtain k 0 new first isomorphic subgraphs isomorphism subgraph;
  • the fixed cost and the exchange cost are determined based on fidelity.
  • the fixed cost and the exchange cost are determined based on the number of CZ gates.
  • the electronic device may be divided into functional units according to the method examples.
  • each functional unit may be divided corresponding to each function, or two or more functions may be integrated into one processing unit.
  • the integrated unit may be implemented in the form of hardware, or may be implemented in the form of software functional units. It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical function division, and other division methods may be used in actual implementation.
  • FIG. 9 is a schematic structural diagram of a quantum computing platform adaptation device provided by an embodiment of the present application.
  • the device includes:
  • an acquisition unit 901 configured to acquire the quantum program to be run and the topology of the quantum chip corresponding to the quantum computing platform, where the topology is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits;
  • An adaptation unit 902 configured to adapt the quantum program to the quantum computing platform based on the topology.
  • the adaptation unit 902 in terms of adapting the quantum program to the quantum computing platform based on the topology, is specifically configured to:
  • a quantum circuit is constructed based on the set of N isomorphic subgraphs, the quantum circuit allowing operation on the quantum computing platform.
  • the adaptation unit 902 is specifically configured to:
  • a first directed acyclic graph is constructed based on the quantum logic gate, and the first directed acyclic graph includes a node and a directed edge; the node includes two points and an edge, and the two points are used to represent The two logic qubits corresponding to the quantum logic gate, the one edge is used to represent the quantum logic gate acting on the two logic qubits; the directed edge is used to represent that the quantum logic gate is a logic qubit The dependence of the quantum state evolution timing.
  • the quantum logic gate includes multiple quantum logic gates; in the aspect of constructing the first directed acyclic graph based on the quantum logic gate, the adaptation unit 902 is specifically configured to:
  • the single quantum logic gate is deleted, and a first directed acyclic graph is constructed based on the two quantum logic gates.
  • the adaptation unit 902 is specifically configured to:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on the same two logic qubits, then based on the number of consecutive two-quantum logic gates in the Either one constructs the first directed acyclic graph.
  • the adaptation unit 902 is further configured to:
  • the quantum logic gate includes a plurality of consecutive two-quantum logic gates, and the plurality of consecutive two-quantum logic gates act on two different logic qubits, then based on the plurality of consecutive two-quantum logic gates, the Construct the first directed acyclic graph.
  • the adaptation unit 902 in terms of traversing the first directed acyclic graph to obtain a maximum subgraph sequence, is specifically configured to:
  • the adaptation unit 902 in terms of traversing the first directed acyclic graph to obtain a maximum subgraph sequence, is further configured to:
  • the second node exists in the second directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent Two logical qubits in a quantum program, the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the The first subgraph is determined;
  • a maximum subgraph is generated.
  • the adaptation unit 902 is specifically configured to:
  • the priority of the second node is the first priority
  • the first subgraph is expanded into a second subgraph, and the second subgraph is used as a new first subgraph subgraph
  • the adaptation unit 902 is further configured to:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • the adaptation unit 902 is specifically configured to:
  • the priority of the second node is determined as the first sub-priority; the priorities in descending order are: the first sub-priority A sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • the adaptation unit 902 in terms of adapting the quantum program to the quantum computing platform based on the topology, is specifically configured to:
  • N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N isomorphic subgraph sets are all
  • the N largest subgraphs are based on the bit relationship graph on the quantum chip obtained by mapping the topological structure of the quantum chip in the electronic device, and the N is an integer greater than or equal to 1;
  • the exchange cost constructs a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is determined based on the SWAP gate required for conversion between the quantum logic gates corresponding to the isomorphic subgraph .
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs , the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and any adjacent isomorphic subgraph set
  • the adaptation unit 902 is specifically used for:
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs , the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and any adjacent isomorphic subgraph set
  • the adaptation unit 902 is specifically used for:
  • Each exchange cost set includes k 0 exchange costs
  • each consumption cost set includes k 0 consumption costs
  • Each second isomorphic subgraph and its corresponding first isomorphic subgraph in the k i second isomorphic subgraphs are formed into a new first isomorphic subgraph, and k i new first isomorphic subgraphs are obtained. isomorphism subgraph;
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the i-th largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs , the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determination of the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and any adjacent isomorphic subgraph set
  • the adaptation unit 902 is specifically used for:
  • Each exchange cost set includes k i exchange costs
  • each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph to obtain k 0 new first isomorphic subgraphs isomorphism subgraph;
  • the fixed cost and the exchange cost are determined based on fidelity.
  • the fixed cost and the exchange cost are determined based on the number of CZ gates.
  • the acquiring unit 901 and the adapting unit 902 may be implemented by a processor.
  • FIG. 10 is a schematic structural diagram of a device for constructing a quantum circuit provided by an embodiment of the present application.
  • the device includes:
  • Traversing unit 1001 configured to traverse the first directed acyclic graph of the quantum program to obtain a maximum subgraph sequence, where the maximum subgraph sequence includes N maximum subgraphs, and N is an integer greater than or equal to 1;
  • a construction unit 1002 is configured to construct a quantum circuit according to the N largest subgraphs and a topological structure, where the topological structure is used to represent the physical qubits in the electronic device and the connection relationship between the physical qubits.
  • the construction unit 1002 may be specifically configured to: determine the sameness of the N largest subgraphs in the topology structure. Constructing a subgraph to obtain N isomorphic subgraph sets, where the N isomorphic subgraph sets are in one-to-one correspondence with the N largest subgraphs; a quantum circuit is constructed based on the N isomorphic subgraph sets.
  • the traversing unit 1001 in terms of obtaining the maximum subgraph sequence by traversing the first directed acyclic graph of the quantum program, can be specifically used for:
  • the traversing unit 1001 in terms of traversing the first directed acyclic graph of the quantum program to obtain the maximum subgraph sequence, can also be used to:
  • the second node exists in the second directed acyclic graph, determine the priority of the second node, the second node includes two points and an edge, and the two points are used to represent Two logical qubits in a quantum program, the one edge is used to represent the quantum logic gate acting on the two logical qubits; the priority of the second node is based on the two points and one edge, the The first subgraph is determined;
  • a maximum subgraph is generated.
  • the traversing unit 1001 may be specifically used for:
  • the priority of the second node is the first priority
  • the first subgraph is expanded into a second subgraph, and the second subgraph is used as a new first subgraph subgraph
  • the traversing unit 1001 may also be used to:
  • the priority of the second node is the second priority
  • the second node is used as a new first node, and then the step of generating a first subgraph based on the first node is performed, and the first subgraph is generated based on the first node.
  • the priority is greater than the second priority.
  • the first priority includes a first sub-priority and a second sub-priority
  • the second priority includes a third sub-priority and a fourth sub-priority
  • the priority of the second node is determined as the first sub-priority; the priorities in descending order are: the first sub-priority A sub-priority, the second sub-priority, the third sub-priority, and the fourth sub-priority.
  • traversing unit 1001 and the constructing unit 1002 may be implemented by a processor.
  • FIG. 11 is a schematic structural diagram of a quantum circuit construction device provided by an embodiment of the present application, and the device includes:
  • Determining unit 1101 configured to determine N isomorphic subgraph sets corresponding to the N largest subgraphs of the quantum program, the N largest subgraphs are determined based on the directed acyclic graph of the quantum program, and the N is greater than or an integer equal to 1;
  • the construction unit 1102 is configured to determine the fixed cost of each isomorphic subgraph in the N isomorphic subgraph sets and the exchange cost between two isomorphic subgraphs in any adjacent isomorphic subgraph set, and based on the The fixed cost and the exchange cost construct a quantum circuit; the fixed cost is determined based on the quantum logic gate corresponding to the isomorphic subgraph, and the exchange cost is based on the conversion between the quantum logic gates corresponding to the isomorphic subgraph The required SWAP gates are identified.
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the ith largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determining the fixed cost of each isomorphic subgraph in the set of N isomorphic subgraphs and any adjacent isomorphic subgraph
  • the exchange cost between the isomorphic subgraphs in the set, and the construction of quantum circuits based on the fixed cost and the exchange cost, the construction unit 1102 is specifically used for:
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the ith largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determining the fixed cost of each isomorphic subgraph in the set of N isomorphic subgraphs and any adjacent isomorphic subgraph
  • the exchange cost between the isomorphic subgraphs in the set, and the construction of quantum circuits based on the fixed cost and the exchange cost, the construction unit 1102 is specifically used for:
  • Each exchange cost set includes k 0 exchange costs
  • each consumption cost set includes k 0 consumption costs
  • Each second isomorphic subgraph and its corresponding first isomorphic subgraph in the k i second isomorphic subgraphs are formed into a new first isomorphic subgraph, and k i new first isomorphic subgraphs are obtained. isomorphism subgraph;
  • the N largest subgraphs constitute a largest subgraph sequence
  • the isomorphic subgraph set corresponding to the ith largest subgraph in the largest subgraph sequence includes k i isomorphic subgraphs
  • the number of the largest subgraph sequence starts from 0 and reaches N-1; in the determining the fixed cost of each isomorphic subgraph in the set of N isomorphic subgraphs and any adjacent isomorphic subgraph
  • the exchange cost between the isomorphic subgraphs in the set, and the construction of quantum circuits based on the fixed cost and the exchange cost, the construction unit 1102 is specifically used for:
  • Each exchange cost set includes k i exchange costs
  • each first isomorphic subgraph and its corresponding second isomorphic subgraph in the k 0 first isomorphic subgraphs into a new first isomorphic subgraph to obtain k 0 new first isomorphic subgraphs isomorphism subgraph;
  • the fixed cost and the exchange cost are determined based on fidelity.
  • the fixed cost and the exchange cost are determined based on the number of CZ gates.
  • determining unit 1101 and the constructing unit 1102 may be implemented by a processor.
  • Embodiments of the present application further provide a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, and the computer program enables a computer to execute any method described in the foregoing method embodiments. Part or all of the steps, the above computer includes electronic equipment.
  • Embodiments of the present application further provide a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute any one of the method embodiments described above. some or all of the steps of the method.
  • the computer program product may be a software installation package, and the computer includes an electronic device.
  • Embodiments of the present application further provide a quantum computer operating system, which implements adaptation of the quantum computing platform according to some or all of the steps of any of the methods described in the above method embodiments.
  • the disclosed apparatus may be implemented in other manners.
  • the device embodiments described above are only illustrative.
  • the division of the above-mentioned units is only a logical function division.
  • multiple units or components may be combined or integrated. to another system, or some features can be ignored, or not implemented.
  • the shown or discussed mutual coupling or direct coupling or communication connection may be through some interfaces, indirect coupling or communication connection of devices or units, and may be in electrical or other forms.
  • the units described above as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution in this embodiment.
  • each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the above-mentioned integrated units if implemented in the form of software functional units and sold or used as independent products, may be stored in a computer-readable memory.
  • the technical solution of the present application can be embodied in the form of a software product in essence, or the part that contributes to the prior art, or all or part of the technical solution, and the computer software product is stored in a memory.
  • a computer device which may be a personal computer, a server, or a network device, etc.
  • the aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, magnetic disk or optical disk and other media that can store program codes.

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Abstract

一种量子计算平台适配方法、装置及量子计算机操作系统，该方法包括：获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；基于所述拓扑结构将所述量子程序适配至所述量子计算平台。采用本申请实施例可提升量子程序的可拓展性，使其能够适配不同的量子计算平台，在不同的量子芯片上运行。

Description

量子计算平台适配方法、装置及量子计算机操作系统
本申请要求于2021年04月21日提交中国专利局、申请号为202110431607.5、发明名称为“量子线路构建方法、装置及量子计算机操作系统”的中国专利申请的优先权，并且，要求于2021年04月21日提交中国专利局、申请号为202110430149.3、发明名称为“量子线路构建方法、装置及量子计算机操作系统”的中国专利申请的优先权，并且，要求于2021年04月21日提交中国专利局、申请号为202110430151.0、发明名称为“量子计算平台适配方法、装置及量子计算机操作系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及量子计算技术领域，尤其涉及一种量子计算平台适配方法、装置及量子计算机操作系统。
背景技术
不同的量子计算平台包括不同的量子芯片，不同的量子计算芯片支持不同的量子逻辑门集合。量子软件开发者在进行量子算法实现时，开发的量子程序往往只能在特定的量子芯片上运行。因此，如何提升量子程序的可扩展性，使其能够适配不同的量子计算平台，在不同的量子芯片上运行，是一个需要解决的问题。
发明内容
本申请实施例提供一种量子计算平台适配方法、装置及量子计算机操作系统，用于提升量子程序的可拓展性，使其能够适配不同的量子计算平台，在不同的量子芯片上运行。
第一方面，本申请实施例提供一种量子计算平台适配方法，所述方法包括：
获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；
基于所述拓扑结构将所述量子程序适配至所述量子计算平台。
可选地，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，包括：
构建所述量子程序的第一有向无环图；
遍历所述第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
确定所述N个最大子图在所述拓扑结构中的同构子图，得到N个同构子图集合， 所述N个同构子图集合与所述N个最大子图一一对应；
基于所述N个同构子图集合构建量子线路，所述量子线路允许在所述量子计算平台上运行。
可选地，在所述构建所述量子程序的第一有向无环图方面，包括：
获取所述量子程序中的量子逻辑门；
基于所述量子逻辑门构建第一有向无环图，所述第一有向无环图包括节点和有向边；所述节点包括两个点和一条边，所述两个点用于表示所述量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述有向边用于表示所述量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系。
可选地，在所述量子逻辑门包括多量子逻辑门；所述基于所述量子逻辑门构建第一有向无环图方面，包括：
将所述多量子逻辑门转化为单量子逻辑门与两量子逻辑门；
删除所述单量子逻辑门，以及基于所述两量子逻辑门构建第一有向无环图。
可选地，在所述基于所述量子逻辑门构建第一有向无环图方面，包括：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用相同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门中的任一个构建第一有向无环图。
可选地，所述方法还包括：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用不同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门依次构建第一有向无环图。
可选地，在所述遍历所述第一有向无环图得到最大子图序列方面，包括：
确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
基于所述第一节点生成第一子图；
删除所述第一节点得到第二有向无环图；
确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
将所述最大子图按照生成顺序排列，得到最大子图序列。
可选地，在所述遍历所述第一有向无环图得到最大子图序列方面，还包括：
若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
基于所述第二节点的优先级和所述第二节点，生成最大子图。
可选地，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，包括：
若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子 图拓展为第二子图，以及将所述第二子图作为新的第一子图；
删除所述第二节点，得到第三有向无环图；
将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
可选地，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，还包括：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
可选地，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；在所述确定所述第二节点的优先级方面，包括：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
可选地，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，包括：
确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；
确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
可选地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交 换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000001
个消耗成本；
基于所述
Figure PCTCN2022087842-appb-000002
个消耗成本构建量子线路。
可选地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
可选地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
可选地，所述固定成本和所述交换成本基于保真度确定。
可选地，所述固定成本和所述交换成本基于CZ门的个数确定。
第二方面，本申请实施例提供一种量子线路构建方法，所述方法包括：
遍历量子程序的第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
根据所述N个最大子图以及拓扑结构构建量子线路，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系。
可选地，在所述根据所述N个最大子图以及拓扑结构构建量子线路方面，包括：
确定所述N个最大子图在拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
基于所述N个同构子图集合构建量子线路。
可选地，在所述遍历量子程序的第一有向无环图得到最大子图序列方面，包括：
确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
基于所述第一节点生成第一子图；
删除所述第一节点得到第二有向无环图；
确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
将所述最大子图按照生成顺序排列，得到最大子图序列。
可选地，在所述遍历量子程序的第一有向无环图得到最大子图序列方面，还包括：
若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
基于所述第二节点的优先级和所述第二节点，生成最大子图。
可选地，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，包括：
若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
删除所述第二节点，得到第三有向无环图；
将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
可选地，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，还包括：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
可选地，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；所述确定所述第二节点的优先级，包括：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
第三方面，本申请实施例提供一种量子线路构建方法，包括：
确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；
确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
可选地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交 换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000003
个消耗成本；
基于所述
Figure PCTCN2022087842-appb-000004
个消耗成本构建量子线路。
可选地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
可选地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
可选地，所述固定成本和所述交换成本基于保真度确定。
可选地，所述固定成本和所述交换成本基于CZ门的个数确定。
第四方面，本申请实施例提供一种量子计算平台适配装置，所述装置包括：
获取单元，用于获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；
适配单元，用于基于所述拓扑结构将所述量子程序适配至所述量子计算平台。
第五方面，本申请实施例提供一种量子线路构建装置，所述装置包括：
遍历单元，用于遍历量子程序的第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
构建单元，用于根据所述N个最大子图以及拓扑结构构建量子线路，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系。
第六方面，本申请实施例提供一种量子线路构建装置，所述装置包括：
确定单元，用于确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N为大于或等于1的整数；
构建单元，用于确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
第七方面，本申请实施例提供一种电子设备，包括处理器、存储器、通信接口以及一个或多个程序，其中，上述一个或多个程序被存储在上述存储器中，并且被配置由上述处理器执行，上述程序包括用于执行本申请实施例第一方面或者第二方面或者第三方面所述的方法中的步骤的指令。
第八方面，本申请实施例提供了一种计算机可读存储介质，其中，上述计算机可读存储介质存储用于电子数据交换的计算机程序，其中，上述计算机程序使得计算机执行如本申请实施例第一方面或者第二方面或者第三方面所述的方法中所描述的部分或全部步骤。
第九方面，本申请实施例提供了一种计算机程序产品，其中，上述计算机程序产 品包括存储了计算机程序的非瞬时性计算机可读存储介质，上述计算机程序可操作来使计算机执行如本申请实施例第一方面或者第二方面或者第三方面所述的方法中所描述的部分或全部步骤。该计算机程序产品可以为一个软件安装包。
第十方面，本申请实施例提供了一种量子计算机操作系统，其中，上述量子计算机操作系统根据本申请实施例第一方面或者第二方面或者第三方面所述的方法中所描述的部分或全部步骤实现所述量子计算平台的适配。
可以看出，在本申请实施例中，首先获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，该拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；然后基于该拓扑结构将量子程序适配至该量子计算平台；量子程序能否在量子芯片上运行主要取决于由芯片的拓扑结构，因此基于拓扑结构对量子程序进行适配，可以将量子程序适配至不同的量子计算平台，在不同的量子芯片上运行同一量子程序，从而提升了量子程序的可拓展性。除此之外，也减少了量子软件开发者的工作量，不用针对不同的量子芯片开发相同功能的量子软件。
本申请的这些方面或其他方面在以下实施例的描述中会更加简明易懂。
附图说明
为了更清楚地说明本申请实施例或现有技术中的技术方案，下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请实施例提供的一种量子计算平台适配方法的计算机终端的硬件结构框图；
图2A为本申请实施例提供的一种量子计算平台适配方法的流程示意图；
图2B为本申请实施例提供的一种量子线路的结构示意图；
图2C为图2B所示的量子线路对应的第一有向无环图的示意图；
图2D为基于图2C所示的第一有向无环图中的第一节点确定的第一子图的示意图；
图2E为图2C删除第一节点后得到的第二有向无环图的示意图；
图2F为基于第二节点在图2D上进行拓展得到的第二子图的示意图；
图2G为图2E删除第二节点后得到的第三有向无环图的示意图；
图2H为基于新的第二节点在图2F上进行拓展得到的第二子图的示意图；
图2I为图2G删除新的第二节点后得到的新的第一有向无环图的示意图；
图2J为基于图2I所示的第一有向无环图中的第一节点确定的第一子图的示意图；
图2K为图2J删除第一节点后得到的第二有向无环图的示意图；
图2L为基于第二节点在图2J上进行拓展得到的第二子图的示意图；
图2M为图2K删除第二节点后得到的第三有向无环图的示意图；
图2N为基于图2M所示的第三有向无环图中的第一节点确定的第一子图的示意图；
图2O为本申请实施例提供的一种包括单量子逻辑门的第一有向无环图的示意图；
图2P为基于图2O得到的新的第一有向无环图的示意图；
图2Q为本申请实施例提供的一种电子设备中的物理量子比特的拓扑结构图；
图2R为本申请实施例提供的一种同构子图的示意图；
图2S为本申请实施例提供的一种同构子图之间相互匹配的示意图；
图2T为本申请实施例提供的一种同构子图之间相互匹配的示意图；
图2U为本申请实施例提供的一种同构子图之间相互匹配的示意图；
图3为本申请实施例提供的另一种量子计算平台适配方法的流程示意图；
图4为本申请实施例提供的一种量子线路构建方法的流程示意图；
图5为本申请实施例提供的另一种量子线路构建方法的流程示意图；
图6为本申请实施例提供的第三种量子线路构建方法的流程示意图；
图7为本申请实施例提供的第四种量子线路构建方法的流程示意图；
图8为本申请实施例提供的一种电子设备的结构示意图；
图9是本申请实施例提供的一种量子计算平台适配装置的结构示意图；
图10为本申请实施例提供的一种量子线路构建装置的结构示意图；
图11为本申请实施例提供的另一种量子线路构建装置的结构示意图。
具体实施方式
为了使本技术领域的人员更好地理解本申请方案，下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分的实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例，都应当属于本申请保护的范围。
以下分别进行详细说明。
本申请的说明书和权利要求书及所述附图中的术语“第一”、“第二”、“第三”和“第四”等是用于区别不同对象，而不是用于描述特定顺序。此外，术语“包括”和“具有”以及它们任何变形，意图在于覆盖不排他的包含。例如包含了一系列步骤或单元的过程、方法、系统、产品或设备没有限定于已列出的步骤或单元，而是可选地还包括没有列出的步骤或单元，或可选地还包括对于这些过程、方法、产品或设备固有的其它步骤或单元。
在本文中提及“实施例”意味着，结合实施例描述的特定特征、结构或特性可以包含在本申请的至少一个实施例中。在说明书中的各个位置出现该短语并不一定均是指相同的实施例，也不是与其它实施例互斥的独立的或备选的实施例。本领域技术人员显式地和隐式地理解的是，本文所描述的实施例可以与其它实施例相结合。
本申请实施例首先提供了一种量子计算平台适配方法，该方法可以应用于电子设备，如计算机终端，具体如普通电脑、量子计算机等。
下面以运行在计算机终端上为例对其进行详细说明。图1为本申请实施例提供的 一种量子计算平台适配方法的计算机终端的硬件结构框图。如图1所示，计算机终端可以包括一个或多个(图1中仅示出一个)处理器102(处理器102可以包括但不限于微处理器MCU或可编程逻辑器件FPGA等的处理装置)和用于存储基于量子计算平台适配方法的存储器104，可选地，上述计算机终端还可以包括用于通信功能的传输装置106以及输入输出设备108。本领域普通技术人员可以理解，图1所示的结构仅为示意，其并不对上述计算机终端的结构造成限定。例如，计算机终端还可包括比图1中所示更多或者更少的组件，或者具有与图1所示不同的配置。
存储器104可用于存储应用软件的软件程序以及模块，如本申请实施例中的量子计算平台适配方法对应的程序指令/模块，处理器102通过运行存储在存储器104内的软件程序以及模块，从而执行各种功能应用以及数据处理，即实现上述的方法。存储器104可包括高速随机存储器，还可包括非易失性存储器，如一个或者多个磁性存储装置、闪存、或者其他非易失性固态存储器。在一些实例中，存储器104可进一步包括相对于处理器102远程设置的存储器，这些远程存储器可以通过网络连接至计算机终端。上述网络的实例包括但不限于互联网、企业内部网、局域网、移动通信网及其组合。
传输装置106用于经由一个网络接收或者发送数据。上述的网络具体实例可包括计算机终端的通信供应商提供的无线网络。在一个实例中，传输装置106包括一个网络适配器(Network Interface Controller，NIC)，其可通过基站与其他网络设备相连从而可与互联网进行通讯。在一个实例中，传输装置106可以为射频(Radio Frequency，RF)模块，其用于通过无线方式与互联网进行通讯。
需要说明的是，真正的量子计算机是混合结构的，它包含两大部分：一部分是经典计算机，负责执行经典计算与控制；另一部分是量子设备，负责运行量子程序进而实现量子计算。而量子程序是由量子语言如QRunes语言编写的一串能够在量子计算机上运行的指令序列，实现了对量子逻辑门操作的支持，并最终实现量子计算。具体的说，量子程序就是一系列按照一定时序操作量子逻辑门的指令序列。
在实际应用中，因受限于量子设备硬件的发展，通常需要进行量子计算模拟以验证量子算法、量子应用等等。量子计算模拟即借助普通计算机的资源搭建的虚拟架构(即量子虚拟机)实现特定问题对应的量子程序的模拟运行的过程。通常，需要构建特定问题对应的量子程序。本申请实施例所指量子程序，即是经典语言编写的表征量子比特及其演化的程序，其中与量子计算相关的量子比特、量子逻辑门等等均有相应的经典代码表示。
量子线路作为量子程序的一种体现方式，也称量子逻辑电路，是最常用的通用量子计算模型，表示在抽象概念下对于量子比特进行操作的线路，其组成包括量子比特、线路(时间线)、以及各种量子逻辑门，最后常需要通过量子测量操作将结果读取出来。
不同于传统电路是用金属线所连接以传递电压信号或电流信号，在量子线路中，线路可看成是由时间所连接，亦即量子比特的状态随着时间自然演化，在这过程中按照哈密顿运算符的指示，一直到遇上逻辑门而被操作。
一个量子程序整体上对应有一条总的量子线路，本发明所述量子程序即指该条总的量子线路，其中，该总的量子线路中的量子比特总数与量子程序的量子比特总数相同。可以理解为：一个量子程序可以由量子线路、针对量子线路中量子比特的测量操作、保存测量结果的寄存器及控制流节点(跳转指令)组成，一条量子线路可以包含几十上百个甚至千上万个量子逻辑门操作。量子程序的执行过程，就是对所有的量子逻辑门按照一定时序执行的过程。需要说明的是，时序即单个量子逻辑门被执行的时间顺序。
需要说明的是，经典计算中，最基本的单元是比特，而最基本的控制模式是逻辑门，可以通过逻辑门的组合来达到控制电路的目的。类似地，处理量子比特的方式就是量子逻辑门。使用量子逻辑门，能够使量子态发生演化，量子逻辑门是构成量子线路的基础，量子逻辑门包括单比特量子逻辑门，如Hadamard门(H门，阿达马门)、泡利-X门(X门)、泡利-Y门(Y门)、泡利-Z门(Z门)、RX门、RY门、RZ门等等；多比特量子逻辑门，如CNOT门、CR门、iSWAP门、Toffoli门等等。量子逻辑门一般使用酉矩阵表示，而酉矩阵不仅是矩阵形式，也是一种操作和变换。一般量子逻辑门在量子态上的作用是通过酉矩阵左乘以量子态右矢对应的矩阵进行计算。
参见图2A，图2A为本申请实施例提供的一种量子计算平台适配方法的流程示意图。该方法包括：
步骤201：获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系。
其中，量子计算平台可以包括不同体系的量子计算平台，如量子计算机、量子虚拟机、经典计算机中的一种或是几种体系组合构成的量子计算平台。本申请实施例中的量子计算平台为上述量子计算平台中的任意一个。
其中，所述连接关系表示两量子逻辑门可以作用在两个物理量子比特上。
步骤202：基于所述拓扑结构将所述量子程序适配至所述量子计算平台。
可以看出，在本申请实施例中，首先获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，该拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；然后基于该拓扑结构将量子程序适配至该量子计算平台；量子程序能否在量子芯片上运行主要取决于由芯片的拓扑结构，因此基于拓扑结构对量子程序进行适配，可以将量子程序适配至不同的量子计算平台，在不同的量子芯片上运行同一量子程序，从而提升了量子程序的可拓展性。除此之外，也减少了量子软件开发者的工作量，不用针对不同的量子芯片开发相同功能的量子软件。
在本申请的一实施例中，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，包括：
确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所 述N为大于或等于1的整数；
确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
在本申请的一实施例中，在所述确定量子程序的N个最大子图对应的N个同构子图集合方面，包括：
构建所述量子程序的第一有向无环图；
遍历所述第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
确定所述N个最大子图在所述拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应。
在本申请的另一实施例中，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，包括：
构建所述量子程序的第一有向无环图；
遍历所述第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
确定所述N个最大子图在所述拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
基于所述N个同构子图集合构建量子线路，所述量子线路允许在所述量子计算平台上运行。
其中，N个最大子图按照各自得到的顺序依次排列，得到最大子图序列。
其中，同构子图是最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图。举例说明，假定最大子图为“q[0]—q[1]”，电子设备中量子芯片的拓扑结构为线性的“Q[0]—Q[1]—Q[2]—Q[3]”，则可以将“q[0]—q[1]”映射到“Q[0]—Q[1]”，也可以映射到“Q[1]—Q[2]”，还可以映射到“Q[2]—Q[3]”，那么最大子图“q[0]—q[1]”的同构子图为：“Q[0]—Q[1]”、“Q[1]—Q[2]”、“Q[2]—Q[3]”。
其中，基于所述N个同构子图集合构建量子线路可以是从每个同构子图集合中任选一个同构子图，基于得到的N个同构子图构建量子线路。
可以看出，在本申请实施例中，首先构建量子程序的第一有向无环图，然后遍历第一有向无环图得到包括N个最大子图的最大子图序列，接着确定N个最大子图在拓扑结构中的同构子图，最后基于得到的N个最大子图集合构建量子线路，从而将量子程序转化成当前量子计算平台支持的量子线路，实现了量子线路的构建。
在本申请的一实施例中，在所述构建所述量子程序的第一有向无环图方面，包括：
获取所述量子程序中的量子逻辑门；
基于所述量子逻辑门构建第一有向无环图，所述第一有向无环图包括节点和有向边；所述节点包括两个点和一条边，所述两个点用于表示所述量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述 有向边用于表示所述量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系。
在本申请的一实施例中，所述量子逻辑门包括多量子逻辑门；在所述基于所述量子逻辑门构建第一有向无环图方面，包括：
将所述多量子逻辑门转化为单量子逻辑门与两量子逻辑门；
删除所述单量子逻辑门，以及基于所述两量子逻辑门构建第一有向无环图。
需要说明的是，若量子程序包括单量子逻辑门、两量子逻辑门、多量子逻辑门，则首先将多量子逻辑门转化成单量子逻辑门和两量子逻辑门，然后将转化后得到的单量子逻辑门和转化前量子程序中本身存在的单量子逻辑门删除，再基于转化后得到的两量子逻辑门和转化前量子程序中本身存在的两量子逻辑门构建第一有向无环图。
第一有向无环图中单量子逻辑门的存在并不影响最大子图的构建，通过有单量子逻辑门的第一有向无环图得到的最大子图与通过无单量子逻辑门的第一有向无环图得到的最大子图相同。因此，在这里为了简便，删除了单量子逻辑门。
在后续最大子图序列的构建过程中，会通过图形举例说明两者得到的最大子图序列相同，在这不再详细阐述。
在本申请的一实施例中，在所述基于所述量子逻辑门构建第一有向无环图方面，包括：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用相同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门中的任一个构建第一有向无环图。
其中，这里的多个指的是两个或两个以上。
举例说明，量子程序包括两个CZ(q[0]，q[1])且两个CZ(q[0]，q[1])在时序上是相邻的，那么这两个CZ(q[0]，q[1])就是多个连续且作用在相同的两个逻辑量子比特上的两量子逻辑门。两个CZ(q[0]，q[1])中间还存在其他的两量子逻辑门，那么这两者就不是多个连续且作用在相同的两个逻辑量子比特上的两量子逻辑门。对于多个连续且作用在相同的两个逻辑量子比特上的两量子逻辑门，基于其中任一个构建第一有向无环图，或是基于其中多个构建第一有向无环图，通过这两者构建的第一有向无环图去生成的最大子图是相同的。同样，在这里为了简便，只基于其中一个去构建第一有向无环图。
在本申请的一实施例中，在所述基于所述量子逻辑门构建第一有向无环图方面，所述方法还包括：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用不同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门依次构建第一有向无环图。
举例说明，量子程序包括两个连续的CZ，只要两个CZ作用的量子比特有一个不同，那么两者就是多个连续的两量子逻辑门作用不同的两个逻辑量子比特上，在第一有向无环图构建时，就需要基于两者去构建。
还需要说明的是，若量子程序中包括共轭转置的量子线路，则需要将该转置共轭的量子线路进行转化，然后再基于转化后的量子线路构建第一有向无环图；若量子程 序中存在测量操作，对于测量操作的处理方式与单量子逻辑门的处理方式相同，删除该测量操作或单量子逻辑门，记录该测量操作或单量子逻辑门信息后再基于两量子逻辑门构建第一有向无环图。
进一步地，基于两量子逻辑门构建第一有向无环图的具体实现方式为：
获取两量子逻辑门作用的逻辑量子比特信息；
基于所述逻辑量子比特信息依次执行所述两量子逻辑门，确定当前执行的所述两量子逻辑门与下一待执行的所述两量子逻辑门的相邻关系；
构建所述两量子逻辑门对应的节点，所述节点包括两个点和一条边，所述两个点用于表示所述两量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；
基于所述相邻关系构建所述节点之间的有向边，所述有向边用于表示所述两量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系；
基于所述节点和所述有向边得到第一有向无环图。
举例说明，假定量子程序为CZ(q[0]，q[1])<<CZ(q[0]，q[2])<<CZ(q[0]，q[3])<<CZ(q[1]，q[2])<<CZ(q[1]，q[3])<<CZ(q[2]，q[3])。该量子程序对应的量子线路如图2B所示，图2B为本申请实施例提供的一种量子线路的结构示意图。根据上述实施例，可以构建出该量子线路的第一有向无环图，如图2C所示，图2C为图2B所示的量子线路对应的第一有向无环图的示意图。第一有向无环图包括6个节点和8条有向边。
进一步地，在所述遍历所述第一有向无环图得到最大子图序列方面，包括：
确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
基于所述第一节点生成第一子图；
删除所述第一节点得到第二有向无环图；
确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
将所述最大子图按照生成顺序排列，得到最大子图序列。
其中，入度是图论算法中重要的概念之一，它通常指有向图中某点作为图中边的终点的次数之和。
可以看出，在本申请实施例中，首先确定第一有向无环图中的入度为0的第一节点，基于第一节点生成第一子图；然后删除第一节点得到第二有向无环图，确定第二有向无环图中是否存在入度为0的第二节点；若第二有向无环图中不存在第二节点，则将第一子图确定为最大子图，以及将最大子图按照生成顺序排列，得到最大子图序列。本申请实施例提供了一种最大子图序列确定的方法，从图论的角度去确定最大子图序列，在第二有向无环图中不存在第二节点时，实现了最大子图序列的确定。
进一步地，在所述遍历所述第一有向无环图得到最大子图序列方面，所述方法还包括：
若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所 述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
基于所述第二节点的优先级和所述第二节点，生成最大子图。
举例说明，如图2C所示，对于CZ(q[0]，q[1])对应的节点，包括两个点和一条边：q[0]对应的点和q[1]对应的点，q[0]对应的点和q[1]对应的点之间的边。q[0]对应的点表示逻辑量子比特q[0]，q[1]对应的点表示逻辑量子比特q[1]，q[0]对应的点和q[1]对应的点之间的边表示作用在逻辑量子比特q[0]和逻辑量子比特q[1]上的CZ门。
可以看出，在本申请实施例中，若第二有向无环图中存在第二节点，则确定第二节点的优先级，基于第二节点的优先级和第二节点，生成最大子图。本申请实施例提供了一种最大子图序列确定的方法，从图论的角度去确定最大子图序列，在第二有向无环图中存在第二节点时，基于第二节点的优先级和第二节点生成最大子图，进而实现了最大子图序列的确定。
进一步地，在基于所述第二节点的优先级和所述第二节点，生成最大子图方面，包括：
若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
删除所述第二节点，得到第三有向无环图；
将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
进一步地，所述将所述第一子图拓展为第二子图的具体实现方式为：若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则以存在的所述两个点中的其中之一为顶点作边，得到所述两个点中的另外一个点，将所述两个点之间的连线作为所述一条边，将拓展后的所述第一子图作为第二子图。
可以看出，在本申请实施例中，若第二节点的优先级为第一优先级，则基于第二节点将第一子图拓展为第二子图，以及将第二子图作为新的第一子图；然后删除第二节点，得到第三有向无环图；将第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。本申请实施例提供了一种最大子图的确定方法，在第二节点的优先级为第一优先级时，对第一子图进行拓展，直到第一子图无法拓展时，得到的即为最大子图，从而实现了最大子图的确定。
进一步地，在基于所述第二节点的优先级和所述第二节点，生成最大子图方面，所述方法还包括：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
进一步地，在将所述第二节点作为新的第一节点之前，所述方法还包括：
删除优先级为第一优先级的第二节点，将所述新的第一子图确定为最大子图。
需要说明的是，若包括第二节点，则存在两种情况：一种是可以基于第二节点继续拓展子图，从而得到相较于先前更大的子图；另一种是不可以基于第二节点继续拓展子图，那么当前的子图即为最大子图。对于第一种情况的优先级必定大于第二种情况的优先级，否则，得到的子图不是最大子图。
可以看出，在本申请实施例中，若第二节点的优先级为第二优先级，则将第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图。本申请实施例提供了一种最大子图的确定方法，在第二节点的优先级为第二优先级时，即第一子图已经无法拓展，就是最大子图，故将得到的第一子图确定为最大子图，然后将第二节点作为新的第一节点，重新开始寻找其他的最大子图，从而实现了最大子图的确定。
进一步地，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；在所述确定所述第二节点的优先级方面，包括：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；
优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
需要说明的是，对于不能拓展最大子图的情况包括两种子情况：一是第一子图中不存在两个点和一条边，二是第一子图中存在两个点且不存在一条边。若将两个点和一条边作为特征点，则前一种子情况包括的特征点数量为0，后一种子情况包括的特征点数量为2。若根据特征点的数量多少去确定优先级，则前一种子情况的优先级小于后一种子情况的优先级，即第四子优先级小于第三子优先级。
同理，对于能拓展最大子图的情况包括两种子情况：一是第一子图中存在两个点中的其中之一且不存在一条边，二是第一子图中存在两个点和一条边。若将两个点和一条边作为特征点，则前一种子情况包括的特征点数量为1，后一种子情况包括的特征点数量为3。若根据特征点的数量多少去确定优先级，则前一种子情况的优先级小于后一种子情况的优先级，即第二子优先级小于第一子优先级。
上述实施例已经说明了第一优先级(即第一子优先级和第二子优先级)和第二优先级(即第三子优先级和第四子优先级)的确定依据，即可以得到第三子优先级小于第二子优先级，在这不在阐述。因此，可以确定优先级从大到小依次为：第一子优先级、第二子优先级、第三子优先级、第四子优先级。
可以看出，在本申请实施例中，若第一子图中不存在两个点和一条边，则将第二节点的优先级确定为第四子优先级；若第一子图中存在两个点且不存在一条边，则将 第二节点的优先级确定为第三子优先级；若第一子图中存在两个点中的其中之一且不存在一条边，则将第二节点的优先级确定为第二子优先级；若第一子图中存在两个点和一条边，则将第二节点的优先级确定为第一子优先级；优先级从大到小依次为：第一子优先级、第二子优先级、第三子优先级、第四子优先级。本申请实施例提供一种第二节点的优先级确定方法，将第二节点包括的两个点和一条边作为特征点，根据该特征点的数量多少去确定优先级的大小，实现了第二优先级的确定。
下面为本申请实施例提供的最大子图序列确定方法的一具体应用场景。
举例说明，假定量子程序为CZ(q[0]，q[1])<<CZ(q[0]，q[2])<<CZ(q[0]，q[3])<<CZ(q[1]，q[2])<<CZ(q[1]，q[3])<<CZ(q[2]，q[3])。量子程序对应的第一有向无环图为图2C所示。根据图2C所示的第一有向无环图确定最大子图序列的步骤如下：由于CZ(q[0]，q[1])对应的节点的入度为0，首先可以确定第一有向无环图中的第一节点为CZ(q[0]，q[1])对应的节点。将第一节点包括的两个点(q[0]对应的点和q[1]对应的点)作为第一子图中的两个端点，将第一节点包括的边作为第一子图中的边得到第一子图，如图2D所示，图2D为基于图2C所示的第一有向无环图中的第一节点确定的第一子图的示意图。删除第一节点，得到第二有向无环图，如图2E所示，图2E为图2C删除第一节点后得到的第二有向无环图的示意图。然后确定第二有向无环图中是否存在第二节点，第二有向无环图中CZ(q[0]，q[2])对应的节点入度为0，因此CZ(q[0]，q[2])对应的节点为第二节点。该第二节点包括两个点：q[0]对应的点和q[2]对应的点，以及两者间的一条边。第一子图中存在q[0]对应的点，将该第二节点的优先级确定为第二子优先级；以q[0]对应的点作边，将第一子图拓展为第二子图，如图2F所示，图2F为基于第二节点在图2D上进行拓展得到的第二子图的示意图。然后将上述的第二子图作为新的第一子图，删除第二节点，得到第三有向无环图，如图2G所示，图2G为图2E删除第二节点后得到的第三有向无环图的示意图。将第三有向无环图作为新的第二有向无环图，然后确定该新的第二有向无环图中是否存在第二节点。由于CZ(q[0]，q[3])对应的节点的入度、CZ(q[1]，q[2])对应的节点的入度均为0，因此这里存在2个第二节点。确定CZ(q[0]，q[3])对应的节点的优先级和CZ(q[1]，q[2])对应的节点优先级。CZ(q[0]，q[3])对应的节点中的一个点在新的第一子图中，其优先级为第二子优先级；CZ(q[1]，q[2])对应的节点中的两个点均在新的第一子图中但两个点间的边却不在新的第一子图中，因此其优先级为第四子优先级。第二子优先级大于第四子优先级，先执行第二子优先级对应的节点。以q[0]对应的点作边，将新的第一子图拓展为第二子图，如图2H所示，图2H为基于新的第二节点在图2F上进行拓展得到的第二子图的示意图。再执行CZ(q[1]，q[2])对应的节点，由于该节点对应的优先级为第四子优先级，则将上述得到的新的第一子图确定为最大子图。
删除CZ(q[0]，q[3])对应的节点，得到新的第一有向无环图，如图2I所示，图2I为图2G删除新的第二节点后得到的新的第一有向无环图的示意图。将CZ(q[1]，q[2])对应的节点作为新的第一节点。将第一节点包括的两个点(q[1]对应的点和q[2]对应的点)作为第一子图中的两个端点，将第一节点包括的边作为第一子图的边得到 第一子图，如图2J所示，图2J为基于图2I所示的第一有向无环图中的第一节点确定的第一子图的示意图。删除第一节点CZ(q[1]，q[2])对应的节点，得到第二有向无环图，如图2K所示，图2K为图2J删除第一节点后得到的第二有向无环图的示意图。然后确定第二有向无环图中是否存在第二节点，第二有向无环图中CZ(q[1]，q[3])对应的节点入度为0，因此CZ(q[1]，q[3])对应的节点为第二节点。该第二节点包括2个点：q[1]对应的点和q[3]对应的点，以及两者间的一条边。第一子图中存在q[1]对应的点，将该第二节点的优先级确定为第二子优先级；以q[1]对应的点作边，将第一子图拓展为第二子图，如图2L所示，图2L为基于第二节点在图2J上进行拓展得到的第二子图的示意图。然后将上述的第二子图作为新的第一子图，删除第二节点CZ(q[1]，q[3])对应的节点，得到第三有向无环图，如图2M所示，图2M为图2K删除第二节点后得到的第三有向无环图的示意图。将第三有向无环图作为新的第二有向无环图，然后确定该新的第二有向无环图中是否存在第二节点。由于CZ(q[2]，q[3])对应的节点的入度为0，因此CZ(q[2]，q[3])对应的节点为第二节点。CZ(q[2]，q[3])对应的节点中的两个点均在新的第一子图中但两个点间的边却不在新的第一子图中，因此其优先级为第四子优先级。将上述得到的新的第一子图确定为最大子图。
将CZ(q[2]，q[3])对应的节点作为新的第一节点。将第一节点包括两个点(q[2]对应的点和q[3]对应的点)作为第一子图中的两个端点，将第一节点包括的边作为第一子图的边得到第一子图，如图2N所示，图2N为基于图2M所示的第三有向无环图中的第一节点确定的第一子图的示意图。删除CZ(q[2]，q[3])对应的节点，得到的第二有向无环图为空，第二有向无环图中不存在第二节点，将第一子图确定为最大子图。
综上，可以得到三个最大子图：CZ(q[0]，q[1])<<CZ(q[0]，q[2])<<CZ(q[0]，q[3])构成的最大子图(如图2H所示)；CZ(q[1]，q[2])<<CZ(q[1]，q[3])构成的最大子图(如图2L所示)；CZ(q[2]，q[3])构成的最大子图(如图2N所示)。将三个子图按照得到的顺序依次排列即可得到最大子图序列。
需要说明的是，若量子程序中存在单量子逻辑门，其最大子图序列与上述实施例中得到的最大子图序列相同。假定量子程序为H(q[0])<<CZ(q[0]，q[1])<<CZ(q[0]，q[2])<<H(q[3])<<CZ(q[0]，q[3])<<CZ(q[1]，q[2])<<CZ(q[1]，q[3])<<CZ(q[2]，q[3])。如图2O所示，图2O为本申请实施例提供的一种包括单量子逻辑门的第一有向无环图的示意图。对于H[0]对应的节点只包括一个点(q[0]对应的点)，因此得到的第一子图为一个点。在该点上进行拓展，执行CZ(q[0]，q[1])对应的节点，可以将上述第一子图拓展为图2D，后续步骤相同，可以得到第0个最大子图(图2H)。删除CZ(q[0]，q[3])对应的节点，得到新的第一有向无环图，如图2P所示，图2P为基于图2O得到的新的第一有向无环图的示意图。第一有向无环图中，CZ(q[1]，q[2])对应的节点和H(q[3])对应的节点入度均为0，且两个节点是新的第一子图构建的开始，第一子图中不包括两者包括的点或边，因此两者的优先级相同。先基于CZ(q[1]，q[2])对应的节点构建第一子图或是先基于H(q[3])对应的节点构建第一子图均可，H(q[3])对应的节点包括的点都可以并入第1个最大子图(图2L)。 后续步骤相同，可得到第2个最大子图(图2N)。
具体地，在所述基于所述N个同构子图集合构建量子线路方面，包括：
确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
举例说明，假定量子程序为CZ(q[0]，q[1])<<CZ(q[0]，q[2])<<CZ(q[0]，q[3])<<CZ(q[1]，q[2])<<CZ(q[1]，q[3])<<CZ(q[2]，q[3])。可以得到三个最大子图：CZ(q[0]，q[1])<<CZ(q[0]，q[2])<<CZ(q[0]，q[3])构成的最大子图(如图2H所示)；CZ(q[1]，q[2])<<CZ(q[1]，q[3])构成的最大子图(如图2L所示)；CZ(q[2]，q[3])构成的最大子图(如图2N所示)。
如图2Q所示，图2Q为本申请实施例提供的一种电子设备中的物理量子比特的拓扑结构图。该电子设备包括8个物理量子比特，分别为Q[0]、Q[1]、Q[2]、Q[3]、Q[4]、Q[5]、Q[6]、Q[7]。其中，Q[0]与Q[1]及Q[4]连接，Q[5]与Q[1]、Q[4]及Q[6]连接，Q[2]与Q[1]、Q[6]及Q[3]连接，Q[7]与Q[3]及Q[6]连接。
将第0个最大子图(图2H)在图2Q中进行映射，可以得到24个第一同构子图，该24个第一同构子图构成第0个同构子图集合；将第1个最大子图(图2L)在图2Q中进行映射，可以得到32个第二同构子图，该32个第二同构子图构成第1个同构子图集合；将第2个最大子图(图2L)在图2Q中进行映射，可以得到20个第三同构子图，该20个第三同构子图构成第2个同构子图集合，如图2R所示，图2R为本申请实施例提供的一种同构子图的示意图。每个第一同构子图、每个第二同构子图、每个第三同构子图的具体形式，在此就不一一详细列举。
确定上述3个同构子图集合中每个同构子图的固定成本，可以得到第一固定成本集合、第二固定成本集合、第三固定成本集合，第一固定成本集合包括24个第一固定成本，第二固定成本集合包括32个第二固定成本，第三固定成本集合包括20个第三固定成本；确定上述3个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，可以得到24×32个第0个同构子图集合与第1个同构子图集合中同构子图两两之间的第一交换成本，以及可以得到32×20个第1个同构子图集合与第2个同构子图集合中同构子图两两之间的第二交换成本。基于24个第一固定成本、32个第二固定成本、20个第三固定成本、24×32个第一交换成本和32×20个第二交换成本构建量子线路。
可以看出，在本申请实施例中，先确定N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于固定成本和交换成本构建量子线路；固定成本基于同构子图对应的量子逻辑门确定，交换成本基于同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。本申请实施例提供了一种量子线路构建的方法，通过同构子图的固定成本和同构子图间的交换成本构建量子线路，实现了量子线路的构建。
进一步地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个 最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000005
个消耗成本；
基于所述
Figure PCTCN2022087842-appb-000006
个消耗成本构建量子线路。
举例说明，如图2Q所示，第0个同构子图集合包括24个第一同构子图，每个第一同构子图对应一个固定成本，第一固定成本集合包括24个第一固定成本；第1个同构子图集合包括32个第二同构子图，每个第二同构子图对应一个固定成本，第二固定成本集合包括32个第二固定成本；第2个同构子图集合包括20个第三同构子图，每个第三同构子图对应一个固定成本，第三固定成本集合包括20个第三固定成本；第0个同构子图集合与第1个同构子图间存在24×32个第一交换成本，第1个同构子图集合与第2个同构子图间存在32×20个第二交换成本。
如图2Q所示，可以基于第0个同构子图集合、第1个同构子图集合和第2个同构子图集合构建出24×32×20
Figure PCTCN2022087842-appb-000007
条量子线路，每条量子线路对应一个消耗成本，每个消耗成本基于一个第一固定成本、一个第二固定成本、一个第三固定成本、一个第一交换成本和一个第二交换成本确定。可以选取消耗成本最小的构建量子线路。
可以看出，在本申请实施例中，确定N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，N个固定成本集合与N个同构子图集合一一对应；确定N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个交换成本集合包括k i·k i+1个交换成本；基于N个固定成本集合与N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000008
个消耗成本；基于
Figure PCTCN2022087842-appb-000009
个消耗成本构建量子线路。本申请实施例提供了一种量子线路的构建方法，通过计算出所有量子线路的消耗成本，然后选取消耗成本最小的量子线路进行构建，本申请实施例构建的量子线路的消耗成本最少，保真度最高，从而得到的量子线路的品质也是最高的。
上述申请实施例提供的量子线路构建方法可以找到消耗成本最小的量子线路，然而，其计算量和存储量是非常巨大的，因此，本申请提供了另外一种量子线路构建的方法，具体方式请参见下述实施例。
进一步地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
进一步地，新的第一同构子图的第一固定成本基于其对应的上一个第一同构子图的第一固定成本，上一个第二同构子图的第二固定成本，以及上一个第一同构子图与上一个第二同构子图的交换成本确定。
举例说明，如图2S所示，图2S为本申请实施例提供的一种同构子图之间相互匹配的示意图。确定第0个同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，第一固定成本集合包括24个第一固定成本，分别为第一固定成本0、第一固定成本1…第一固定成本23；确定第1个同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，第二固定成本集合包括32个第二固定成本，分别为第二固定成本0、第二固定成本1…第二固定成本31。
确定第二同构子图0、第二同构子图1…第二同构子图31与第一同构子图0的交换成本，可以得到交换成本集合0，交换成本集合0包括交换成本00、交换成本10、交换成本20…交换成本310；确定第二同构子图0、第二同构子图1…第二同构子图31与第一同构子图1的交换成本，可以得到交换成本集合1，交换成本集合1包括交换成本01、交换成本11、交换成本21…交换成本311…一直到确定第二同构子图0、第二同构子图1…第二同构子图31与第一同构子图23的交换成本，可以得到交换成本集合23，交换成本集合23包括交换成本023、交换成本123、交换成本223…交换成本3123。
第一同构子图0与第二同构子图0的消耗成本00基于交换成本00、第一固定成本0、第二固定成本0确定；第一同构子图0与第二同构子图1的消耗成本10基于交换成本10、第一固定成本0、第二固定成本1确定…第一同构子图0与第二同构子图31的消耗成本310基于交换成本310、第一固定成本0、第二固定成本31确定；消耗 成本00、消耗成本10…消耗成本310构成消耗成本集合0；
第一同构子图1与第二同构子图0的消耗成本01基于交换成本01、第一固定成本1、第二固定成本0确定；第一同构子图1与第二同构子图1的消耗成本11基于交换成本11、第一固定成本1、第二固定成本1确定…第一同构子图1与第二同构子图31的消耗成本311基于交换成本311、第一固定成本1、第二固定成本31确定；消耗成本01、消耗成本11…消耗成本311构成消耗成本集合1；
…
第一同构子图23与第二同构子图0的消耗成本023基于交换成本023、第一固定成本23、第二固定成本0确定；第一同构子图23与第二同构子图1的消耗成本123基于交换成本123、第一固定成本23、第二固定成本1确定…第一同构子图23与第二同构子图31的消耗成本3123基于交换成本3123、第一固定成本23、第二固定成本31确定；消耗成本023、消耗成本123…消耗成本3123构成消耗成本集合23。
确定消耗成本集合0中最小的消耗成本，确定消耗成本集合1中最小的消耗成本…确定消耗成本集合23中最小的消耗成本，得到24个最小的消耗成本。
将第一同构子图0与及其对应的第二同构子图组成新的第一同构子图0，将第一同构子图1与及其对应的第二同构子图组成新的第一同构子图1…将第一同构子图23与及其对应的第二同构子图组成新的第一同构子图23；新的第一同构子图0、新的第一同构子图1…新的第一同构子图23构成新的第一同构子图集合。
确定新的同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，第一固定成本集合包括24个第一固定成本，分别为第一固定成本0’、第一固定成本1’…第一固定成本23’；确定第2个同构子图集合中每个第二同构子图(这里第三同构子图为新的第二同构子图)的第二固定成本，得到第二固定成本集合，第二固定成本集合包括32个第二固定成本，分别为第二固定成本0’、第二固定成本1’…第二固定成本31’。
确定第二同构子图0’、第二同构子图1’…第二同构子图31’与第一同构子图0’的交换成本，可以得到交换成本集合0’，交换成本集合0’包括交换成本00’、交换成本10’、交换成本20’…交换成本310’；确定第二同构子图0’、第二同构子图1’…第二同构子图31’与第一同构子图1’的交换成本，可以得到交换成本集合1’，交换成本集合1’包括交换成本01’、交换成本11’、交换成本21’…交换成本311’…一直到确定第二同构子图0’、第二同构子图1’…第二同构子图31’与第一同构子图23’的交换成本，可以得到交换成本集合23’，交换成本集合23’包括交换成本023’、交换成本123’、交换成本223’…交换成本3123’。
第一同构子图0’与第二同构子图0’的消耗成本00’基于交换成本00’、第一固定成本0’、第二固定成本0’确定；第一同构子图0’与第二同构子图1’的消耗成本10’基于交换成本10’、第一固定成本0’、第二固定成本1’确定…第一同构子图0’与第二同构子图31’的消耗成本310’基于交换成本310’、第一固定成本0’、第二固定成本31’确定；消耗成本00’、消耗成本10’…消耗成本310’构成消耗成本集合0’；
第一同构子图1’与第二同构子图0’的消耗成本01’基于交换成本01’、第一固定 成本1’、第二固定成本0’确定；第一同构子图1’与第二同构子图1’的消耗成本11’基于交换成本11’、第一固定成本1’、第二固定成本1’确定…第一同构子图1’与第二同构子图31’的消耗成本311’基于交换成本311’、第一固定成本1’、第二固定成本31’确定；消耗成本01’、消耗成本11’…消耗成本311’构成消耗成本集合1’；
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第一同构子图23’与第二同构子图0’的消耗成本023’基于交换成本023’、第一固定成本23’、第二固定成本0’确定；第一同构子图23’与第二同构子图1’的消耗成本123’基于交换成本123’、第一固定成本23’、第二固定成本1’确定…第一同构子图23’与第二同构子图31’的消耗成本3123’基于交换成本3123’、第一固定成本23’、第二固定成本31’确定；消耗成本023’、消耗成本123’…消耗成本3123’构成消耗成本集合23’。
确定消耗成本集合0’中最小的消耗成本，确定消耗成本集合1’中最小的消耗成本…确定消耗成本集合23’中最小的消耗成本，得到24个最小的消耗成本。确定24个最小的消耗成本对应的24个量子线路。量子线路0由第一同构子图0、其对应的第二同构子图、其对应的第三同构子图构成；量子线路1由第一同构子图1、其对应的第二同构子图、其对应的第三同构子图构成…量子线路23由第一同构子图23、其对应的第二同构子图、其对应的第三同构子图构成。选择其中消耗成本最小的量子线路。
可以看出，在本申请实施例中，确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，第一同构子图集合为第0个最大子图对应的同构子图集合；确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，第二同构子图集合为第i个最大子图对应的同构子图集合；确定第二同构子图集合中所有的第二同构子图与第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；基于第一固定成本集合、第二固定成本集合和k 0个交换成本集合确定k 0个消耗成本集合，消耗成本集合包括k i个消耗成本；确定每个消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，k 0个最小的消耗成本与第一同构子图集合中的k 0个第一同构子图一一对应；将k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；将k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；令i＝i+1，以及执行步骤确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，i的初始值为1；在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
本申请实施例提供了另外一种量子线路的构建方法，通过遍历的方式，对最大子图序列从前往后进行匹配，找到k 0个消耗成本，消耗成本的数量与第0个最大子图对应的同构子图数量相等，基于这k 0个消耗成本确定每一个最大子图对应的一个同构子图，然后用这每一个最大子图对应的一个同构子图构建量子线路。本申请实施例每两个相邻的同构子图集合就进行一次筛选，每次都只得到与第0个最大子图对应的同构子图数量相等的最优同构子图，在大大降低了计算量与存储量的同时，能够构建出量子线路。
上述一申请实施例提供的量子线路构建方法可以找到消耗最小的量子线路，然而，其计算量和存储量是非常巨大的；上述另一申请实施例提供的量子线路的构建方法虽然降低了计算量和存储量，但是可能忽略掉最优的量子线路。因此，本申请又提供了另外一种量子线路构建的方法，具体方式请参见下述实施例。
进一步地，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，包括：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
举例说明，如图2T所示，图2T为本申请实施例提供的一种同构子图之间相互匹配的示意图。确定第0个同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，第一固定成本集合包括24个第一固定成本，分别为第一固定成本0、第一固定成本1…第一固定成本23；确定第1个同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，第二固定成本集合包括32个第二固定成本，分别为第二固定成本0、第二固定成本1…第二固定成本31。
确定第一同构子图0、第一同构子图1…第一同构子图23与第二同构子图0的交换成本，可以得到交换成本集合0，交换成本集合0包括交换成本00、交换成本01、交换成本01…交换成本023；确定第一同构子图0、第一同构子图1…第一同构子图23与第二同构子图1的交换成本，可以得到交换成本集合1，交换成本集合1包括交换成本10、交换成本11、交换成本12…交换成本123；…一直到确定第一同构子图0、第一同构子图1…第一同构子图23与第二同构子图31的交换成本，可以得到交 换成本集合31，交换成本集合31包括交换成本310、交换成本311、交换成本312…交换成本3123。
第一同构子图0与第二同构子图0的消耗成本00基于交换成本00、第一固定成本0、第二固定成本0确定；第一同构子图1与第二同构子图0的消耗成本01基于交换成本01、第一固定成本1、第二固定成本0确定…第一同构子图23与第二同构子图0的消耗成本023基于交换成本023、第一固定成本23、第二固定成本0确定；消耗成本00、消耗成本01…消耗成本023构成消耗成本集合0；
第一同构子图0与第二同构子图1的消耗成本10基于交换成本10、第一固定成本0、第二固定成本1确定；第一同构子图1与第二同构子图1的消耗成本11基于交换成本11、第一固定成本1、第二固定成本1确定…第一同构子图23与第二同构子图1的消耗成本123基于交换成本123、第一固定成本23、第二固定成本1确定；消耗成本10、消耗成本11…消耗成本123构成消耗成本集合1；
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第一同构子图0与第二同构子图31的消耗成本310基于交换成本310、第一固定成本0、第二固定成本31确定；第一同构子图1与第二同构子图31的消耗成本311基于交换成本311、第一固定成本1、第二固定成本31确定…第一同构子图23与第二同构子图31的消耗成本3123基于交换成本3123、第一固定成本23、第二固定成本31确定；消耗成本310、消耗成本311…消耗成本3123构成消耗成本集合31。
确定消耗成本集合0中最小的消耗成本，确定消耗成本集合1中最小的消耗成本…确定消耗成本集合31中最小的消耗成本，得到32个最小的消耗成本。
将第二同构子图0与及其对应的第一同构子图组成新的第一同构子图0，将第二同构子图1与及其对应的第一同构子图组成新的第一同构子图1…将第二同构子图31与及其对应的第一同构子图组成新的第一同构子图31；新的第一同构子图0、新的第一同构子图1…新的第一同构子图31构成新的第一同构子图集合。
确定新的同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，第一固定成本集合包括32个第一固定成本，分别为第一固定成本0’、第一固定成本1’…第一固定成本31’；确定第2个同构子图集合中每个第二同构子图(这里第三同构子图为新的第二同构子图)的第二固定成本，得到第二固定成本集合，第二固定成本集合包括20个第二固定成本，分别为第二固定成本0’、第二固定成本1’…第二固定成本19’。
确定第一同构子图0’、第一同构子图1’…第一同构子图31’与第二同构子图0’的交换成本，可以得到交换成本集合0’，交换成本集合0’包括交换成本00’、交换成本10’、交换成本20’…交换成本310’；确定第一同构子图0’、第一同构子图1’…第一同构子图31’与第二同构子图1’的交换成本，可以得到交换成本集合1’，交换成本集合1’包括交换成本01’、交换成本11’、交换成本21’…交换成本311’…一直到确定第一同构子图0’、第一同构子图1’…第一同构子图31’与第二同构子图19’的交换成本，可以得到交换成本集合19’，交换成本集合19’包括交换成本019’、交换成本119’、交换成本219’…交换成本3119’。
第一同构子图0’与第二同构子图0’的消耗成本00’基于交换成本00’、第一固定成本0’、第二固定成本0’确定；第一同构子图1’与第二同构子图0’的消耗成本01’基于交换成本01’、第一固定成本1’、第二固定成本0’确定…第一同构子图31’与第二同构子图0’的消耗成本031’基于交换成本031’、第一固定成本31’、第二固定成本0’确定；消耗成本00’、消耗成本01’…消耗成本031’构成消耗成本集合0’；
第一同构子图0’与第二同构子图1’的消耗成本10’基于交换成本10’、第一固定成本0’、第二固定成本1’确定；第一同构子图1’与第二同构子图1’的消耗成本11’基于交换成本11’、第一固定成本1’、第二固定成本1’确定…第一同构子图31’与第二同构子图1’的消耗成本131’基于交换成本131’、第一固定成本31’、第二固定成本1’确定；消耗成本10’、消耗成本11’…消耗成本131’构成消耗成本集合1’；
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第一同构子图0’与第二同构子图31’的消耗成本310’基于交换成本310’、第一固定成本0’、第二固定成本31’确定；第一同构子图1’与第二同构子图31’的消耗成本311’基于交换成本311’、第一固定成本1’、第二固定成本31’确定…第一同构子图31’与第二同构子图19’的消耗成本1931’基于交换成本1931’、第一固定成本31’、第二固定成本19’确定；消耗成本310’、消耗成本311’…消耗成本3119’构成消耗成本集合19’。
确定消耗成本集合0’中最小的消耗成本，确定消耗成本集合1’中最小的消耗成本…确定消耗成本集合19’中最小的消耗成本，得到20个最小的消耗成本。确定20个最小的消耗成本对应的20个量子线路。量子线路0由第三同构子图0、其对应的第二同构子图、其对应的第一同构子图构成；量子线路1由第三同构子图1、其对应的第二同构子图、其对应的第一同构子图构成…量子线路19由第三同构子图19、其对应的第二同构子图、其对应的第一同构子图构成。选择其中消耗成本最小的量子线路。
可以看出，在本申请实施例中，确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，第一同构子图集合为第0个最大子图对应的同构子图集合；确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，第二同构子图集合为第i个最大子图对应的同构子图集合；确定第一同构子图集合中所有的第一同构子图与第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；基于第一固定成本集合、第二固定成本集合和k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，k i个最小的消耗成本与第二同构子图集合中的k i个第二同构子图一一对应；将k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；将k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；令i＝i+1，以及执行步骤确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，i的初始值为1；在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
本申请实施例提供了另外一种量子线路的构建方法，通过遍历的方式，对最大子 图序列从后往前进行匹配，找到k N-1个消耗成本，消耗成本的数量与第N-1个最大子图对应的同构子图数量相等，基于这k N-1个消耗成本确定每一个最大子图对应的一个同构子图，然后用这每一个最大子图对应的一个同构子图构建量子线路。本申请实施例每两个相邻的同构子图集合就进行一次筛选，每次都只得到与后一个最大子图对应的同构子图数量相等的最优同构子图，在大大降低了计算量与存储量的同时，也能够构建出最优的量子线路。
在下面的实施例中，再举一个具体的例子说明从前往后遍历构建量子线路和从后往前遍历构建量子线路两种方式的区别。
如图2U所示，图2U为本申请实施例提供的一种同构子图之间相互匹配的示意图。第0个同构子图集合包括第一同构子图0和第一同构子图1，第1个同构子图集合包括第二同构子图0和第二同构子图1，第2个同构子图集合包括第三同构子图0和第三同构子图1；第一同构子图0、第一同构子图1、第二同构子图0、第二同构子图1、第三同构子图0和第三同构子图1本身的保真度为1，第一同构子图0与第二同构子图0之间的保真度为0.9，第一同构子图0与第二同构子图1之间的保真度为0.85，第一同构子图1与第二同构子图0之间的保真度为0.9，第一同构子图1与第二同构子图1之间的保真度为0.85，第二同构子图0与第三同构子图0之间的保真度为0.9，第二同构子图0与第三同构子图1之间的保真度为0.8，第二同构子图1与第三同构子图0之间的保真度为1，第二同构子图1与第二同构子图1之间的保真度为0.7。
从前往后遍历构建量子线路：第一同构子图0与第二同构子图0的消耗成本为0.1(1-1×0.9×1)，第一同构子图0与第二同构子图1的消耗成本为0.15(1-1×0.85×1)，选取消耗成本最低的，得到新的第一同构子图0，新的第一同构子图0由第一同构子图0与第二同构子图0构成；第一同构子图1与第二同构子图0的消耗成本为0.1(1-1×0.9×1)，第一同构子图1与第二同构子图1的消耗成本为0.15(1-1×0.85×1)，选取消耗成本最低的，得到新的第一同构子图1，新的第一同构子图1由第一同构子图1与第二同构子图0构成；新的第一同构子图0与第三同构子图0的消耗成本为0.19(1-1×0.9×1×0.9×1)，新的第一同构子图0与第三同构子图1的消耗成本为0.28(1-1×0.9×1×0.8×1)，选取消耗成本最低的，得到新的第一同构子图0，新的第一同构子图0由第一同构子图0、第二同构子图0、第三同构子图0构成；新的第一同构子图1与第三同构子图0的消耗成本为0.19(1-1×0.9×1×0.9×1)，新的第一同构子图1与第三同构子图1的消耗成本为0.28(1-1×0.9×1×0.8×1)，选取消耗成本最低的，得到新的第一同构子图1，新的第一同构子图1由第一同构子图1、第二同构子图0、第三同构子图0构成；最后从新的第一同构子图0和新的第一同构子图1中选择消耗成本最低的同构子图构建量子线路，由于两者的消耗成本均为0.19，故可以基于第一同构子图0、第二同构子图0、第三同构子图0构建量子线路，或者可以基于第一同构子图1、第二同构子图0、第三同构子图0构建量子线路。
从后往前遍历构建量子线路：第二同构子图0与第一同构子图0的消耗成本为0.1(1-1×0.9×1)，第二同构子图0与第一同构子图1的消耗成本为0.1(1-1×0.9×1)， 选取消耗成本最低的，得到新的第一同构子图0，两者消耗成本相同，故新的第一同构子图0可以由第一同构子图0与第二同构子图0构成，也可以由第一同构子图1与第二同构子图0构成；第二同构子图1与第一同构子图0的消耗成本为0.15(1-1×0.85×1)，第二同构子图1与第二同构子图1的消耗成本为0.15(1-1×0.85×1)，选取消耗成本最低的，得到新的第一同构子图1，两者消耗成本相同，故新的第一同构子图1可以由第一同构子图1与第二同构子图0构成，也可以由第一同构子图1与第二同构子图1构成；新的第一同构子图0与第三同构子图0的消耗成本为0.19(1-1×0.9×1×0.9×1)，新的第一同构子图0与第三同构子图1的消耗成本为0.28(1-1×0.9×1×0.8×1)，选取消耗成本最低的，得到新的第一同构子图0，新的第一同构子图0由第一同构子图0、第二同构子图0、第三同构子图0构成，或者，新的第一同构子图0由第一同构子图1、第二同构子图0、第三同构子图0构成；新的第一同构子图1与第三同构子图0的消耗成本为0.15(1-1×0.85×1×1×1)，新的第一同构子图1与第三同构子图1的消耗成本为0.405(1-1×0.85×1×0.7×1)，选取消耗成本最低的，得到新的第一同构子图1，新的第一同构子图1可以由第一同构子图0、第二同构子图1、第三同构子图0构成，也可以由第一同构子图1、第二同构子图1、第三同构子图0构成；最后从新的第一同构子图0和新的第一同构子图1中选择消耗成本最低的同构子图构建量子线路，新的第一同构子图1的消耗成本最低为0.85，故可以基于第一同构子图0、第二同构子图1、第三同构子图0构建量子线路，或者可以基于第一同构子图1、第二同构子图1、第三同构子图0构建量子线路。
可以看出，从前往后遍历构建量子线路，得到的结果是基于第一同构子图0、第二同构子图0、第三同构子图0构建量子线路，或者基于第一同构子图1、第二同构子图0、第三同构子图0构建量子线路；从前往后遍历构建量子线路，得到的结果是基于第一同构子图0、第二同构子图1、第三同构子图0构建量子线路，或者基于第一同构子图1、第二同构子图1、第三同构子图0构建量子线路。两者得到的结果不同，前者的总体消耗成本为0.19，后者的总体消耗成本为0.15，明显后者由于前者，前者找到的不是最优的构建量子线路的方法。
需要说明的是，上述三个构建量子线路的实施例中最大子图、最大子图序列、同构子图、同构子图集合、第一固定成本集合、第二固定成本集合、消耗成本集合等都是从0开始编号，其也可以是从1开始编号或是从其他任意数字或字母进行编号，在这里就不进行一一举例说明。
进一步地，所述固定成本和所述交换成本基于保真度确定。
进一步地，所述固定成本和所述交换成本基于CZ门的个数确定。
需要说明的是，任何一个双量子逻辑门对应的保真度都可以等价为至少一个CZ门对应的保真度。
其中，每个同构子图对应一个最大子图，每个最大子图基于至少一个两量子逻辑门确定，每个同构子图的固定成本则基于至少一个两量子逻辑门对应的保真度之积确定。
举例说明，最大子图2H对应的量子逻辑门为CZ(q[0]，q[1])、CZ(q[0]，q[2])、 CZ(q[0]，q[3])；最大子图2L对应的量子逻辑门为CZ(q[1]，q[2])、CZ(q[1]，q[3])。将最大子图2H和最大子图2L映射到图2Q中，最大子图2H的映射关系如下：q[1]—>Q[0]，q[0]—>Q[1]，q[3]—>Q[2]，q[2]—>Q[5]，最大子图2L的映射关系如下：q[3]—>Q[2]，q[1]—>Q[1]，q[2]—>Q[5]。
基于保真度确定固定成本和交换成本：
在CZ门对应的模拟信号作用在Q[0]和Q[1]上的保真度为F01，CZ门对应的模拟信号作用在Q[1]和Q[2]上的保真度为F12，CZ门对应的模拟信号作用在Q[1]和Q[5]上的保真度为F15。最大子图2H的固定成本为1-F01·F12·F15；执行CZ(q[1]，q[2])，CZ(q[1]，q[3])时，需要将q[1]的映射关系从Q[0]变换到Q[1]上，最大子图2L的固定成本为1-F12·F15；将q[1]的映射关系从Q[0]变换到Q[1]上，需要引入量子逻辑门SWAP(q[0]，q[1])，SWAP(q[0]，q[1])＝CZ(q[0]，q[1])CZ(q[0]，q[1])CZ(q[0]，q[1])，因此，最大子图2H与最大子图2L的交换成本为1-F013。总的消耗成本为1-F01·F12·F15·F12·F15·F013。
基于CZ门的个数确定固定成本和交换成本：最大子图2H的固定成本为3个CZ门，最大子图2L的固定成本为2个CZ门，最大子图2H与最大子图2L的交换成本为3个CZ门，总的消耗成本为8个CZ门。
参见图3，图3为本申请实施例提供的另一种量子计算平台适配方法的流程示意图。该方法包括：
步骤301：获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系。
步骤302：获取所述量子程序中的量子逻辑门。
步骤303：若所述量子逻辑门包括多量子逻辑门，则将所述多量子逻辑门转化为单量子逻辑门与两量子逻辑门。
步骤304：删除所述单量子逻辑门，以及基于所述两量子逻辑门构建第一有向无环图。
步骤305：若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用相同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门中的任一个构建第一有向无环图。
步骤306：若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用不同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门依次构建第一有向无环图，所述第一有向无环图包括节点和有向边；所述节点包括两个点和一条边，所述两个点用于表示所述量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述有向边用于表示所述量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系。
步骤307：遍历所述第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
步骤308：确定所述N个最大子图在所述拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
步骤309：基于所述N个同构子图集合构建量子线路，所述量子线路允许在所述量子计算平台上运行。
需要说明的是，本实施例的具体实现过程可参见上述方法实施例所述的具体实现过程，在此不再叙述。
本申请实施例还提供图4～图7所示的量子线路构建方法，上述量子线路构建方法可以用于实现上述基于所述拓扑结构将所述量子程序适配至所述量子计算平台的步骤。
参见图4，图4为本申请实施例提供的另一种量子线路构建方法的流程示意图。该方法包括：
步骤401：构建量子程序的第一有向无环图。
步骤402：确定所述第一有向无环图中的第一节点，所述第一节点的入度为0。
步骤403：基于所述第一节点生成第一子图。
步骤404：删除所述第一节点得到第二有向无环图。
步骤405：确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
若是，则执行步骤406；
若否，则执行步骤415。
步骤406：确定所述第一子图中是否存在所述两个点和所述一条边。
步骤407：若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级。
步骤408：若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级。
步骤409：若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级。
步骤410：若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级。优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
步骤411：若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤403，所述第二优先级包括第三子优先级、第四子优先级。
步骤412：若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图，所述第一优先级包括第一子优先级、第二子优先级。
步骤413：删除所述第二节点，得到第三有向无环图。
步骤414：将所述第三有向无环图作为新的第二有向无环图，然后执行步骤405。
步骤415：将所述第一子图确定为最大子图。
步骤416：将所述最大子图按照生成顺序排列，得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数。
步骤417：确定所述N个最大子图在拓扑结构中的同构子图，得到N个同构子图集合，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系，所述N个同构子图集合与所述N个最大子图一一对应。
步骤418：基于所述N个同构子图集合构建量子线路。
需要说明的是，本实施例的具体实现过程可参见上述方法实施例所述的具体实现过程，在此不再叙述。
参见图5，图5为本申请实施例提供的另一种量子线路构建方法的流程示意图。该方法包括：
步骤501：确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1。
步骤502：确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应。
步骤503：确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本。
步骤504：基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000010
个消耗成本。
步骤505：基于所述
Figure PCTCN2022087842-appb-000011
个消耗成本构建量子线路。
上述申请实施例提供的量子线路构建方法可以找到消耗成本最小的量子线路，然而，其计算量和存储量是非常巨大的，因此，本申请提供了另外一种量子线路构建的方法，具体方式请参见下述实施例。参见图6，图6为本申请实施例提供的又一种量子线路构建方法的流程示意图。该方法包括：
步骤601：确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1。
步骤602：确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合。
步骤603：确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合。
步骤604：确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本。
步骤605：基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本。
步骤606：确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应。
步骤607：将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图。
步骤608：将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合。
步骤609：确定i是否等于N-1；
若否，则执行步骤610；
若是，则执行步骤611.
步骤610：令i＝i+1，以及执行步骤602，所述i的初始值为1。
步骤611：基于得到的k N-1个最小的消耗成本构建量子线路。
上述一申请实施例提供的量子线路构建方法可以找到量子程序的消耗最小的量子线路，然而，其计算量和存储量是非常巨大的；上述另一申请实施例提供的量子线路的构建方法虽然降低了计算量和存储量，但是可能忽略掉最优的量子线路。因此，本申请又提供了另外一种量子线路构建的方法，具体方式请参见下述实施例。
参见图7，图7为本申请实施例提供的又一种量子线路构建方法的流程示意图。该方法包括：
步骤701：确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1。
步骤702：确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合。
步骤703：确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合。
步骤704：确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本。
步骤705：基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本。
步骤706：确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应。
步骤707：将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图。
步骤708：将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合。
步骤709：确定i是否等于N-1，所述i的初始值为1；
若否，则执行步骤710；
若是，则执行步骤711。
步骤710：令i＝i+1，以及执行步骤702。
步骤711：基于得到的k 0个最小的消耗成本构建量子线路。
与上述图1～图7所示的实施例一致的，请参阅图8，图8为本申请实施例提供的一种电子设备的结构示意图，如图8所示，该电子设备包括处理器、存储器、通信接口以及一个或多个程序，其中，上述一个或多个程序被存储在上述存储器中，并且被配置由上述处理器执行，上述程序包括用于执行以下步骤的指令：
获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；
基于所述拓扑结构将所述量子程序适配至所述量子计算平台。
在本申请的一实施例中，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，上述程序包括具体用于执行以下步骤的指令：
构建所述量子程序的第一有向无环图；
遍历所述第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
确定所述N个最大子图在所述拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
基于所述N个同构子图集合构建量子线路，所述量子线路允许在所述量子计算平台上运行。
在本申请的一实施例中，在所述构建所述量子程序的第一有向无环图方面，上述程序包括具体用于执行以下步骤的指令：
获取所述量子程序中的量子逻辑门；
基于所述量子逻辑门构建第一有向无环图，所述第一有向无环图包括节点和有向 边；所述节点包括两个点和一条边，所述两个点用于表示所述量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特之上的量子逻辑门；所述有向边用于表示所述量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系。
在本申请的一实施例中，所述量子逻辑门包括多量子逻辑门；在所述基于所述量子逻辑门构建第一有向无环图方面，上述程序包括具体用于执行以下步骤的指令：
将所述多量子逻辑门转化为单量子逻辑门与两量子逻辑门；
删除所述单量子逻辑门，以及基于所述两量子逻辑门构建第一有向无环图。
在本申请的一实施例中，在所述基于所述量子逻辑门构建第一有向无环图方面，上述程序包括具体用于执行以下步骤的指令：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用相同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门中的任一个构建第一有向无环图。
在本申请的一实施例中，上述程序包括还用于执行以下步骤的指令：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用不同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门依次构建第一有向无环图。
在本申请的一实施例中，在所述遍历所述第一有向无环图得到最大子图序列方面，上述程序包括具体用于执行以下步骤的指令：
确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
基于所述第一节点生成第一子图；
删除所述第一节点得到第二有向无环图；
确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
将所述最大子图按照生成顺序排列，得到最大子图序列。
在本申请的一实施例中，在所述遍历所述第一有向无环图得到最大子图序列方面，上述程序还包括具体用于执行以下步骤的指令：
若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
基于所述第二节点的优先级和所述第二节点，生成最大子图。
在本申请一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，上述程序包括具体用于执行以下步骤的指令：
若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
删除所述第二节点，得到第三有向无环图；
将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述 第二有向无环图中是否存在第二节点。
在本申请一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，上述程序还包括具体用于执行以下步骤的指令：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
在本申请一实施例中，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；在所述确定所述第二节点的优先级方面，上述程序包括具体用于执行以下步骤的指令：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
在本申请一实施例中，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，上述程序包括具体用于执行以下步骤的指令：
确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；
确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
在本申请一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，所述适配单元902，具体用于：
确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000012
个消耗成 本；
基于所述
Figure PCTCN2022087842-appb-000013
个消耗成本构建量子线路。
在本申请一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，上述程序包括具体用于执行以下步骤的指令：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
在本申请一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，上述程序包括具体用于执行以下步骤的指令：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
在本申请一实施例中，所述固定成本和所述交换成本基于保真度确定。
在本申请一实施例中，所述固定成本和所述交换成本基于CZ门的个数确定。
需要说明的是，本实施例的具体实现过程可参见上述方法实施例所述的具体实现过程，在此不再叙述。
在本申请提供的另一个实施例的电子设备中，电子设备的结构如图4所示，该电子设备包括处理器、存储器、通信接口以及一个或多个程序，其中，上述一个或多个程序被存储在上述存储器中，并且被配置由上述处理器执行，上述程序包括用于执行以下步骤的指令：
遍历量子程序的第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
根据所述N个最大子图以及拓扑结构构建量子线路，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系。
在本申请的一实施例中，在所述根据所述N个最大子图以及拓扑结构构建量子线路方法，上述程序包括具体用于执行以下步骤的指令：
确定所述N个最大子图在拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
基于所述N个同构子图集合构建量子线路。
在本申请的一实施例中，在遍历量子程序的第一有向无环图得到最大子图序列方面，上述程序包括具体用于执行以下步骤的指令：
确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
基于所述第一节点生成第一子图；
删除所述第一节点得到第二有向无环图；
确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
将所述最大子图按照生成顺序排列，得到最大子图序列。
在本申请的一实施例中，在遍历量子程序的第一有向无环图得到最大子图序列方面，上述程序还包括用于执行以下步骤的指令：
若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
基于所述第二节点的优先级和所述第二节点，生成最大子图。
在本申请的一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，上述程序包括具体用于执行以下步骤的指令：
若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
删除所述第二节点，得到第三有向无环图；
将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
在本申请的一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，上述程序还包括用于执行以下步骤的指令：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
在本申请的一实施例中，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；在所述确定所述第二节点的优先级方面，上述程序包括具体用于执行以下步骤的指令：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
需要说明的是，本实施例的具体实现过程可参见上述方法实施例所述的具体实现过程，在此不再叙述。
在本申请提供的又一个实施例的电子设备中，电子设备的结构如图4所示，该电子设备包括处理器、存储器、通信接口以及一个或多个程序，其中，上述一个或多个程序被存储在上述存储器中，并且被配置由上述处理器执行，上述程序包括用于执行以下步骤的指令：
确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述 N为大于或等于1的整数；
确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
在本申请的一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，上述程序包括具体用于执行以下步骤的指令：
确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000014
个消耗成本；
基于所述
Figure PCTCN2022087842-appb-000015
个消耗成本构建量子线路。
在本申请的一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，上述程序包括具体用于执行以下步骤的指令：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
在本申请的一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，上述程序包括具体用于执行以下步骤的指令：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
在本申请的一实施例中，所述固定成本和所述交换成本基于保真度确定。
在本申请的一实施例中，所述固定成本和所述交换成本基于CZ门的个数确定。
需要说明的是，本实施例的具体实现过程可参见上述方法实施例所述的具体实现过程，在此不再叙述。
本申请实施例可以根据所述方法示例对电子设备进行功能单元的划分，例如，可以对应各个功能划分各个功能单元，也可以将两个或两个以上的功能集成在一个处理单元中。所述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。需要说明的是，本申请实施例中对单元的划分是示意性的，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式。
下面为本申请装置实施例，本申请装置实施例用于执行本申请方法实施例所实现的方法。请参阅图9，图9是本申请实施例提供的一种量子计算平台适配装置的结构示意图，所述装置包括：
获取单元901，用于获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；
适配单元902，用于基于所述拓扑结构将所述量子程序适配至所述量子计算平台。
在本申请的一实施例中，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，所述适配单元902，具体用于：
构建所述量子程序的第一有向无环图；
遍历所述第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
确定所述N个最大子图在所述拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
基于所述N个同构子图集合构建量子线路，所述量子线路允许在所述量子计算平台上运行。
在本申请的一实施例中，在所述构建所述量子程序的第一有向无环图方面，所述适配单元902，具体用于：
获取所述量子程序中的量子逻辑门；
基于所述量子逻辑门构建第一有向无环图，所述第一有向无环图包括节点和有向边；所述节点包括两个点和一条边，所述两个点用于表示所述量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述有向边用于表示所述量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系。
在本申请的一实施例中，所述量子逻辑门包括多量子逻辑门；在所述基于所述量子逻辑门构建第一有向无环图方面，所述适配单元902，具体用于：
将所述多量子逻辑门转化为单量子逻辑门与两量子逻辑门；
删除所述单量子逻辑门，以及基于所述两量子逻辑门构建第一有向无环图。
在本申请的一实施例中，在所述基于所述量子逻辑门构建第一有向无环图方面，所述适配单元902，具体用于：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用相同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门中的任一个构建第一有向无环图。
在本申请的一实施例中，所述适配单元902，还用于：
若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用不同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门依次构建第一有向无环图。
在本申请的一实施例中，在所述遍历所述第一有向无环图得到最大子图序列方面，所述适配单元902，具体用于：
确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
基于所述第一节点生成第一子图；
删除所述第一节点得到第二有向无环图；
确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
将所述最大子图按照生成顺序排列，得到最大子图序列。
在本申请的一实施例中，在所述遍历所述第一有向无环图得到最大子图序列方面，所述适配单元902，还用于：
若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
基于所述第二节点的优先级和所述第二节点，生成最大子图。
在本申请一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，所述适配单元902，具体用于：
若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
删除所述第二节点，得到第三有向无环图；
将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
在本申请一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，所述适配单元902，还用于：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
在本申请一实施例中，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；在所述确定所述第二节点的优先级方面，所述适配单元902，具体用于：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
在本申请一实施例中，在所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台方面，所述适配单元902，具体用于：
确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；
确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
在本申请一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，所述适配单元902，具体用于：
确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000016
个消耗成本；
基于所述
Figure PCTCN2022087842-appb-000017
个消耗成本构建量子线路。
在本申请一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，所述适配单元902，具体用于：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
在本申请一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，所述适配单元902，具体用于：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
在本申请一实施例中，所述固定成本和所述交换成本基于保真度确定。
在本申请一实施例中，所述固定成本和所述交换成本基于CZ门的个数确定。
需要说明的是，获取单元901和适配单元902可通过处理器实现。
请参阅图10，图10为本申请实施例提供的一种量子线路构建装置的结构示意图，所述装置包括：
遍历单元1001，用于遍历量子程序的第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
构建单元1002，用于根据所述N个最大子图以及拓扑结构构建量子线路，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系。
在本申请的一实施例中，在所述根据所述N个最大子图以及拓扑结构构建量子线路方法，构建单元1002具体可以用于：确定所述N个最大子图在拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；基于所述N个同构子图集合构建量子线路。
在本申请的一实施例中，在遍历量子程序的第一有向无环图得到最大子图序列方面，遍历单元1001具体可以用于：
确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
基于所述第一节点生成第一子图；
删除所述第一节点得到第二有向无环图；
确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
将所述最大子图按照生成顺序排列，得到最大子图序列。
在本申请的一实施例中，在遍历量子程序的第一有向无环图得到最大子图序列方面，遍历单元1001还可以用于：
若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
基于所述第二节点的优先级和所述第二节点，生成最大子图。
在本申请的一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，遍历单元1001具体可以用于：
若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
删除所述第二节点，得到第三有向无环图；
将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
在本申请的一实施例中，在所述基于所述第二节点的优先级和所述第二节点，生成最大子图方面，遍历单元1001还可以用于：
若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
在本申请的一实施例中，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；在所述确定所述第二节点的优先级方面，遍历单元1001具体可以用于：
若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
需要说明的是，遍历单元1001和构建单元1002可通过处理器实现。
请参阅图11，图11是本申请实施例提供的一种量子线路构建装置的结构示意图，所述装置包括：
确定单元1101，用于确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N为大于或等于1的整数；
构建单元1102，用于确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
在本申请的一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，所述构建单元1102，具体用于：
确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
基于所述N个固定成本集合与所述N-1个交换成本集合确定
Figure PCTCN2022087842-appb-000018
个消耗成本；
基于所述
Figure PCTCN2022087842-appb-000019
个消耗成本构建量子线路。
在本申请的一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，所述构建单元1102，具体用于：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
在本申请的一实施例中，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；在所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路方面，所述构建单元1102，具体用于：
确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
在本申请的一实施例中，所述固定成本和所述交换成本基于保真度确定。
在本申请的一实施例中，所述固定成本和所述交换成本基于CZ门的个数确定。
需要说明的是，确定单元1101和构建单元1102可通过处理器实现。
本申请实施例还提供一种计算机可读存储介质，其中，该计算机可读存储介质存储用于电子数据交换的计算机程序，该计算机程序使得计算机执行如上述方法实施例中记载的任一方法的部分或全部步骤，上述计算机包括电子设备。
本申请实施例还提供一种计算机程序产品，上述计算机程序产品包括存储了计算机程序的非瞬时性计算机可读存储介质，上述计算机程序可操作来使计算机执行如上述方法实施例中记载的任一方法的部分或全部步骤。该计算机程序产品可以为一个软件安装包，上述计算机包括电子设备。
本申请实施例还提供一种量子计算机操作系统，该量子计算机操作系统根据上述方法实施例中记载的任一方法的部分或全部步骤实现所述量子计算平台的适配。
需要说明的是，对于前述的各方法实施例，为了简单描述，故将其都表述为一系列的动作组合，但是本领域技术人员应该知悉，本申请并不受所描述的动作顺序的限制，因为依据本申请，某些步骤可以采用其他顺序或者同时进行。其次，本领域技术人员也应该知悉，说明书中所描述的实施例均属于优选实施例，所涉及的动作和模块并不一定是本申请所必须的。
在上述实施例中，对各个实施例的描述都各有侧重，某个实施例中没有详述的部分，可以参见其他实施例的相关描述。
在本申请所提供的几个实施例中，应该理解到，所揭露的装置，可通过其它的方式实现。例如，以上所描述的装置实施例仅仅是示意性的，例如上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。另一点，所显示或讨论的相互之间的耦合或直接耦合或通信连接可以是通过一些接口，装置或单元的间接耦合或通信连接，可以是电性或其它的形式。
上述作为分离部件说明的单元可以是或者也可以不是物理上分开的，作为单元显示的部件可以是或者也可以不是物理单元，即可以位于一个地方，或者也可以分布到多个网络单元上。可以根据实际的需要选择其中的部分或者全部单元来实现本实施例方案的目的。
另外，在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
上述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储器中。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储器中，包括若干指令用以使得一台计算机设备(可为个人计算机、服务器或者网络设备等)执行本申请各个实施例上述方法的全部或部分步骤。而前述的存储器包括：U盘、只读存储器(ROM，Read-Only Memory)、随机存取存储器(RAM，Random Access Memory)、移动硬盘、磁碟或者光盘等各种可以存储程序代码的介质。
本领域普通技术人员可以理解上述实施例的各种方法中的全部或部分步骤是可以通过程序来指令相关的硬件来完成，该程序可以存储于一计算机可读存储器中，存储器可以包括：闪存盘、只读存储器(英文：Read-Only Memory，简称：ROM)、随机存取器(英文：Random Access Memory，简称：RAM)、磁盘或光盘等。
以上对本申请实施例进行了详细介绍，本文中应用了具体个例对本申请的原理及实施方式进行了阐述，以上实施例的说明只是用于帮助理解本申请的方法及其核心思想；同时，对于本领域的一般技术人员，依据本申请的思想，在具体实施方式及应用范围上均会有改变之处，综上所述，本说明书内容不应理解为对本申请的限制。

Claims (36)

  1. 一种量子计算平台适配方法，其特征在于，所述方法包括：
    获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；
    基于所述拓扑结构将所述量子程序适配至所述量子计算平台。
  2. 根据权利要求1所述的方法，其特征在于，所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台，包括：
    构建所述量子程序的第一有向无环图；
    遍历所述第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
    确定所述N个最大子图在所述拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
    基于所述N个同构子图集合构建量子线路，所述量子线路允许在所述量子计算平台上运行。
  3. 根据权利要求2所述的方法，其特征在于，所述构建所述量子程序的第一有向无环图，包括：
    获取所述量子程序中的量子逻辑门；
    基于所述量子逻辑门构建第一有向无环图，所述第一有向无环图包括节点和有向边；所述节点包括两个点和一条边，所述两个点用于表示所述量子逻辑门对应的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述有向边用于表示所述量子逻辑门按逻辑量子比特的量子态演化时序的依赖关系。
  4. 根据权利要求3所述的方法，其特征在于，所述量子逻辑门包括多量子逻辑门；所述基于所述量子逻辑门构建第一有向无环图，包括：
    将所述多量子逻辑门转化为单量子逻辑门与两量子逻辑门；
    删除所述单量子逻辑门，以及基于所述两量子逻辑门构建第一有向无环图。
  5. 根据权利要求3所述的方法，其特征在于，所述基于所述量子逻辑门构建第一有向无环图，包括：
    若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用相同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门中的任一个构建第一有向无环图。
  6. 根据权利要求5所述的方法，其特征在于，所述方法还包括：
    若所述量子逻辑门包括多个连续的两量子逻辑门，且所述多个连续的两量子逻辑门作用不同的两个逻辑量子比特上，则基于所述多个连续的两量子逻辑门依次构建第一有向无环图。
  7. 根据权利要求2所述的方法，其特征在于，所述遍历所述第一有向无环图得到最大子图序列，包括：
    确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
    基于所述第一节点生成第一子图；
    删除所述第一节点得到第二有向无环图；
    确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
    若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
    将所述最大子图按照生成顺序排列，得到最大子图序列。
  8. 根据权利要求7所述的方法，其特征在于，所述遍历所述第一有向无环图得到最大子图序列，还包括：
    若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
    基于所述第二节点的优先级和所述第二节点，生成最大子图。
  9. 根据权利要求8所述的方法，其特征在于，所述基于所述第二节点的优先级和所述第二节点，生成最大子图，包括：
    若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
    删除所述第二节点，得到第三有向无环图；
    将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
  10. 根据权利要求9所述的方法，其特征在于，所述基于所述第二节点的优先级和所述第二节点，生成最大子图，还包括：
    若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
  11. 根据权利要求10所述的方法，其特征在于，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；所述确定所述第二节点的优先级，包括：
    若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第四子优先级；
    若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
    若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
    若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
  12. 根据权利要求1所述的方法，其特征在于，所述基于所述拓扑结构将所述量子程序适配至所述量子计算平台，包括：
    确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；
    确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
  13. 根据权利要求12所述的方法，其特征在于，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路，包括：
    确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
    确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
    基于所述N个固定成本集合与所述N-1个交换成本集合确定
    Figure PCTCN2022087842-appb-100001
    个消耗成本；
    基于所述
    Figure PCTCN2022087842-appb-100002
    个消耗成本构建量子线路。
  14. 根据权利要求12所述的方法，其特征在于，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路，包括：
    确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
    确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
    确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
    基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
    确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述 k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
    将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
    将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
    令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
    在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
  15. 根据权利要求12所述的方法，其特征在于，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路，包括：
    确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
    确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
    确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
    基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
    确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
    将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
    将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
    令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
    在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
  16. 根据权利要求12至15任一项所述的方法，其特征在于，所述固定成本和所述交换成本基于保真度确定。
  17. 根据权利要求12至15任一项所述的方法，其特征在于，所述固定成本和所述交换成本基于CZ门的个数确定。
  18. 一种量子线路构建方法，其特征在于，所述方法包括：
    遍历量子程序的第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
    根据所述N个最大子图以及拓扑结构构建量子线路，所述拓扑结构用于表示电 子设备中的物理量子比特以及物理量子比特之间的连接关系。
  19. 根据权利要求18所述的方法，其特征在于，所述根据所述N个最大子图以及拓扑结构构建量子线路，包括：
    确定所述N个最大子图在拓扑结构中的同构子图，得到N个同构子图集合，所述N个同构子图集合与所述N个最大子图一一对应；
    基于所述N个同构子图集合构建量子线路。
  20. 根据权利要求18所述的方法，其特征在于，所述遍历量子程序的第一有向无环图得到最大子图序列，包括：
    确定所述第一有向无环图中的第一节点，所述第一节点的入度为0；
    基于所述第一节点生成第一子图；
    删除所述第一节点得到第二有向无环图；
    确定所述第二有向无环图中是否存在第二节点，所述第二节点的入度为0；
    若所述第二有向无环图中不存在所述第二节点，则将所述第一子图确定为最大子图；
    将所述最大子图按照生成顺序排列，得到最大子图序列。
  21. 根据权利要求20所述的方法，其特征在于，所述遍历量子程序的第一有向无环图得到最大子图序列，还包括：
    若所述第二有向无环图中存在所述第二节点，则确定所述第二节点的优先级，所述第二节点包括两个点和一条边，所述两个点用于表示量子程序中的两个逻辑量子比特，所述一条边用于表示作用在两个逻辑量子比特上的量子逻辑门；所述第二节点的优先级基于所述两个点和一条边、所述第一子图确定；
    基于所述第二节点的优先级和所述第二节点，生成最大子图。
  22. 根据权利要求21所述的方法，其特征在于，所述基于所述第二节点的优先级和所述第二节点，生成最大子图，包括：
    若所述第二节点的优先级为第一优先级，则基于所述第二节点，将所述第一子图拓展为第二子图，以及将所述第二子图作为新的第一子图；
    删除所述第二节点，得到第三有向无环图；
    将所述第三有向无环图作为新的第二有向无环图，然后执行步骤所述确定所述第二有向无环图中是否存在第二节点。
  23. 根据权利要求22所述的方法，其特征在于，所述基于所述第二节点的优先级和所述第二节点，生成最大子图，还包括：
    若所述第二节点的优先级为第二优先级，则将所述第二节点作为新的第一节点，然后执行步骤所述基于所述第一节点生成第一子图，所述第一优先级大于所述第二优先级。
  24. 根据权利要求23所述的方法，其特征在于，所述第一优先级包括第一子优先级、第二子优先级，所述第二优先级包括第三子优先级、第四子优先级；所述确定所述第二节点的优先级，包括：
    若所述第一子图中不存在所述两个点和所述一条边，则将所述第二节点的优先 级确定为第四子优先级；
    若所述第一子图中存在所述两个点且不存在所述一条边，则将所述第二节点的优先级确定为第三子优先级；
    若所述第一子图中存在所述两个点中的其中之一且不存在所述一条边，则将所述第二节点的优先级确定为第二子优先级；
    若所述第一子图中存在所述两个点和所述一条边，则将所述第二节点的优先级确定为第一子优先级；优先级从大到小依次为：所述第一子优先级、所述第二子优先级、所述第三子优先级、所述第四子优先级。
  25. 一种量子线路构建方法，其特征在于，包括：
    确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N个同构子图集合是所述N个最大子图基于电子设备中量子芯片的拓扑结构映射得到的在所述量子芯片上的比特关系图，所述N为大于或等于1的整数；
    确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
  26. 根据权利要求25所述的方法，其特征在于，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路，包括：
    确定所述N个同构子图集合中每个同构子图的固定成本，得到N个固定成本集合，所述N个固定成本集合与所述N个同构子图集合一一对应；
    确定所述N个同构子图集合中任意相邻同构子图集合中同构子图两两之间的交换成本，得到N-1个交换成本集合，每个所述交换成本集合包括k i·k i+1个交换成本；
    基于所述N个固定成本集合与所述N-1个交换成本集合确定
    Figure PCTCN2022087842-appb-100003
    个消耗成本；
    基于所述
    Figure PCTCN2022087842-appb-100004
    个消耗成本构建量子线路。
  27. 根据权利要求25所述的方法，其特征在于，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路，包括：
    确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
    确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成 本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
    确定所述第一同构子图集合中所有的第一同构子图与所述第二同构子图集合中每一个第二同构子图的交换成本，得到k i个交换成本集合，每个交换成本集合包括k 0个交换成本；
    基于所述第一固定成本集合、所述第二固定成本集合和所述k i个交换成本集合确定k i个消耗成本集合，每个消耗成本集合包括k 0个消耗成本；
    确定每个所述消耗成本集合中最小的消耗成本，得到k i个最小的消耗成本，所述k i个最小的消耗成本与所述第二同构子图集合中的k i个第二同构子图一一对应；
    将所述k i个第二同构子图中的每个第二同构子图及其对应的第一同构子图组成为新的第一同构子图，得到k i个新的第一同构子图；
    将所述k i个新的第一同构子图构成的集合确定为新的第一同构子图集合；
    令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
    在i＝N-1时，基于得到的k N-1个最小的消耗成本构建量子线路。
  28. 根据权利要求25所述的方法，其特征在于，所述N个最大子图构成最大子图序列，所述最大子图序列中的第i个最大子图对应的同构子图集合包括k i个同构子图，所述最大子图序列的编号从0开始，直至N-1；所述确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路，包括：
    确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述第一同构子图集合为所述第0个最大子图对应的同构子图集合；
    确定第二同构子图集合中每个第二同构子图的第二固定成本，得到第二固定成本集合，所述第二同构子图集合为所述第i个最大子图对应的同构子图集合；
    确定所述第二同构子图集合中所有的第二同构子图与所述第一同构子图集合中每一个第一同构子图的交换成本，得到k 0个交换成本集合，每个交换成本集合包括k i个交换成本；
    基于所述第一固定成本集合、所述第二固定成本集合和所述k 0个交换成本集合确定k 0个消耗成本集合，每个消耗成本集合包括k i个消耗成本；
    确定每个所述消耗成本集合中最小的消耗成本，得到k 0个最小的消耗成本，所述k 0个最小的消耗成本与所述第一同构子图集合中的k 0个第一同构子图一一对应；
    将所述k 0个第一同构子图中的每个第一同构子图及其对应的第二同构子图组成为新的第一同构子图，得到k 0个新的第一同构子图；
    将所述k 0个新的第一同构子图构成的集合确定为新的第一同构子图集合；
    令i＝i+1，以及执行步骤所述确定第一同构子图集合中每个第一同构子图的第一固定成本，得到第一固定成本集合，所述i的初始值为1；
    在i＝N-1时，基于得到的k 0个最小的消耗成本构建量子线路。
  29. 根据权利要求25至28任一项所述的方法，其特征在于，所述固定成本和所述交换成本基于保真度确定。
  30. 根据权利要求25至28任一项所述的方法，其特征在于，所述固定成本和所述交换成本基于CZ门的个数确定。
  31. 一种量子计算平台适配装置，其特征在于，所述装置包括：
    获取单元，用于获取待运行的量子程序和量子计算平台对应的量子芯片的拓扑结构，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系；
    适配单元，用于基于所述拓扑结构将所述量子程序适配至所述量子计算平台。
  32. 一种量子线路构建装置，其特征在于，所述装置包括：
    遍历单元，用于遍历量子程序的第一有向无环图得到最大子图序列，所述最大子图序列包括N个最大子图，所述N为大于或等于1的整数；
    构建单元，用于根据所述N个最大子图以及拓扑结构构建量子线路，所述拓扑结构用于表示电子设备中的物理量子比特以及物理量子比特之间的连接关系。
  33. 一种量子线路构建装置，其特征在于，所述装置包括：
    确定单元，用于确定量子程序的N个最大子图对应的N个同构子图集合，所述N个最大子图基于所述量子程序的有向无环图确定，所述N为大于或等于1的整数；
    构建单元，用于确定所述N个同构子图集合中每个同构子图的固定成本和任意相邻同构子图集合中同构子图两两之间的交换成本，以及基于所述固定成本和所述交换成本构建量子线路；所述固定成本基于所述同构子图对应的量子逻辑门确定，所述交换成本基于所述同构子图对应的量子逻辑门之间转化所需要的SWAP门确定。
  34. 一种电子设备，其特征在于，包括处理器、存储器、通信接口，以及一个或多个程序，所述一个或多个程序被存储在所述存储器中，并且被配置由所述处理器执行，所述程序包括用于执行如权利要求1-30任一项所述的方法中的步骤的指令。
  35. 一种计算机可读存储介质，其特征在于，所述计算机可读存储介质存储有计算机程序，所述计算机程序被处理器执行以实现权利要求1-30任一项所述的方法。
  36. 一种量子计算机操作系统，其特征在于，所述量子计算机操作系统根据权利要求1-30任一项所述的方法实现所述量子计算平台的适配。
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