WO2022222583A1 - 一种用于天线阻抗检测的校准装置及方法 - Google Patents

一种用于天线阻抗检测的校准装置及方法 Download PDF

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Publication number
WO2022222583A1
WO2022222583A1 PCT/CN2022/076085 CN2022076085W WO2022222583A1 WO 2022222583 A1 WO2022222583 A1 WO 2022222583A1 CN 2022076085 W CN2022076085 W CN 2022076085W WO 2022222583 A1 WO2022222583 A1 WO 2022222583A1
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Prior art keywords
reflection coefficient
load
probe
radio frequency
calibration
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PCT/CN2022/076085
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English (en)
French (fr)
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刘亮
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荣耀终端有限公司
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Publication of WO2022222583A1 publication Critical patent/WO2022222583A1/zh

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R35/00—Testing or calibrating of apparatus covered by the other groups of this subclass
    • G01R35/005—Calibrating; Standards or reference devices, e.g. voltage or resistance standards, "golden" references
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/04—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant in circuits having distributed constants, e.g. having very long conductors or involving high frequencies
    • G01R27/06—Measuring reflection coefficients; Measuring standing-wave ratio

Definitions

  • the present application relates to the field of radio frequency technology, and in particular, to a calibration device and method for antenna impedance detection.
  • the antenna of the terminal device needs to support the closed-loop tuning function or antenna scene detection.
  • the RF front-end circuit connected to the antenna needs to have the function of impedance detection. Due to the processing and manufacturing of RF devices in the RF front-end circuit, such as switches, couplers, and PCB traces, differences in RF performance may be brought about, such as fluctuations in the amplitude and phase of S-parameters, which make the impedance detected by different terminal equipment. have large fluctuations. To ensure the accuracy of impedance detection, different terminal devices need to be calibrated separately. How to achieve individual calibration of different terminal equipment and improve the accuracy of calibration is facing challenges.
  • the present application provides a calibration device and method for antenna impedance detection, so as to solve the problem of how to individually calibrate different terminal devices, and to improve the accuracy of antenna impedance detection after calibration.
  • the present application provides a calibration device for antenna impedance detection, where the calibration device is applied to test PCBs.
  • the test PCB includes a transceiver, an RF base, an RF front-end circuit and an impedance detection path.
  • the radio frequency seat is connected to the radio frequency front-end circuit, and the radio frequency front-end circuit is connected to the transceiver.
  • the transceiver includes an impedance detection interface, and the impedance detection interface is connected to the impedance detection path, and is used for measuring the reflection coefficient of the transceiver looking toward the impedance detection path.
  • the calibration device includes a jig PCB board, a calibration circuit and a probe set on the jig PCB board. Calibration circuit connection probe.
  • Probes are used to connect to a vector network analyzer or RF stand. When the probe is connected to the vector network analyzer, it is used to measure the first reflection coefficient of the probe looking at the calibration circuit. When the probe is connected to the radio frequency base, it is used to measure the second reflection coefficient of the transceiver looking at the calibration circuit, so as to complete the calibration of the antenna impedance detection according to the first reflection coefficient and the second reflection coefficient.
  • the antenna is connected to a radio frequency socket (eg, the main radio frequency socket) in the radio frequency chip.
  • a radio frequency socket eg, the main radio frequency socket
  • the impedance looking at the antenna from the radio base needs to be detected.
  • the antenna is connected to the RF base, in the RF chip, the reflection coefficient of the transceiver looking at the antenna can be detected through the impedance detection path, that is, the reflection coefficient of the transceiver looking at the impedance detection path, which can be recorded as the reflection coefficient ⁇ M .
  • the reflection coefficient ⁇ A from the radio frequency seat to the antenna can be calculated.
  • the reflection coefficient ⁇ A and the reflection coefficient ⁇ M have the following relationship: Among them, a, b and c are the network error model parameters from the transceiver to the radio frequency base.
  • the reflection coefficient ⁇ A viewed from the RF base to the antenna can be converted from the RF base to the antenna
  • the impedance Z in Specifically, after calculating the reflection coefficient ⁇ A looking from the radio frequency seat to the antenna, it can be calculated according to the formula Calculate the impedance Z in looking at the antenna from the radio base.
  • Z 0 is the characteristic impedance of the antenna, which is generally 50 ohms.
  • the probe on the fixture PCB board can be fastened with the radio frequency seat on the test PCB to be tested, so that the probe and the radio frequency can be fastened together.
  • the sockets are connected, so that the calibration device can calibrate different terminal equipment individually.
  • the probe is connected to the vector network analyzer, and the reflection coefficient of the probe looking at the calibration circuit can be measured as the reflection coefficient ⁇ A .
  • the reflection coefficient of the transceiver looking towards the impedance detection path can be detected as the reflection coefficient ⁇ M .
  • the impedance detection path on the PCB can be tested to detect the reflection coefficient ⁇ M of the transceiver looking at the antenna, and then combined with formula (2) and the calibration
  • the network error model parameters a, b and c are calculated to obtain the reflection coefficient ⁇ A from the radio frequency base to the antenna, so as to realize the accurate detection of the antenna impedance.
  • the calibration circuit may include a radio frequency switch, a first load, a second load and a third load.
  • the first load, the second load and the third load are connected to the probe through a radio frequency switch, so that the probe is connected to any one of the first load, the second load and the third load.
  • the radio frequency switch may be a single pole three throw (SP3T) switch.
  • SP3T single pole three throw
  • the RF switch When the RF switch is switched to the first load, the probe is connected to the first load; at this time, the reflection coefficient ⁇ A and the reflection coefficient ⁇ M when the probe is connected to the first load can be measured.
  • the RF switch When the RF switch is switched to the second load, the probe is connected to the second load; at this time, the reflection coefficient ⁇ A and the reflection coefficient ⁇ M when the probe is connected to the second load can be measured.
  • the RF switch When the RF switch is switched to the third load, the probe is connected to the third load; at this time, the reflection coefficient ⁇ A and the reflection coefficient ⁇ M when the probe is connected to the second load can be measured.
  • the network error model parameters a, b and c can be obtained by calculation according to the acquired three groups of reflection coefficients ⁇ A and ⁇ M .
  • the calibration circuit may further include a fourth load; the fourth load is connected to the probe through a radio frequency switch. After the test PCB board is calibrated by the first load, the second load and the third load in the calibration circuit, the accuracy of the calibrated network error model parameters can be checked through the fourth load to verify whether the network error model parameters meet the application requirements .
  • the calibration device may further include a comprehensive tester; the comprehensive tester is connected to a probe through a radio frequency switch for calibrating the transmit and receive power of the radio frequency front-end circuit.
  • the comprehensive tester can be connected to the probe through the RF switch.
  • the RF switch on the fixture PCB can be switched to the path connected to the comprehensive tester, so that the calibration device can not only calibrate the impedance of the RF front-end circuit, but also the RF transceiver power. Calibration is performed to improve the calibration efficiency of the RF front-end circuit in the terminal equipment and save costs.
  • the present application provides a calibration method for antenna impedance detection, the calibration method using the calibration device in any possible design of the first aspect above.
  • the calibration method includes: connecting a probe to a vector network analyzer, and measuring a first reflection coefficient of the probe looking at the calibration circuit. Connect the probe to the radio frequency base, and measure the second reflection coefficient of the transceiver looking at the calibration circuit through the impedance detection channel. According to the first reflection coefficient and the second reflection coefficient, the network error model parameters from the transceiver to the radio frequency base are calculated.
  • the above calibration method may further include: when the radio frequency base is connected to the antenna, measuring the third reflection coefficient ⁇ M of the transceiver looking at the antenna through the impedance detection channel. Through the network error model parameters and the third reflection coefficient ⁇ M , the fourth reflection coefficient ⁇ A of the radio frequency seat looking toward the antenna is calculated. According to the fourth reflection coefficient ⁇ A of the radio frequency base looking at the antenna, the impedance Z in of the radio frequency base looking at the antenna is obtained.
  • the relationship between the third reflection coefficient ⁇ M , the network error model parameters, and the fourth reflection coefficient and the third reflection coefficient ⁇ M is: Among them, the parameters a, b, and c are the network error model parameters.
  • the relationship between the impedance Z in of the radio frequency seat looking at the antenna and the fourth reflection coefficient ⁇ A is: Among them, Z0 is the characteristic impedance of the antenna.
  • the calibration circuit may include a radio frequency switch, a first load, a second load and a third load.
  • the first load, the second load and the third load are connected to the probe through a radio frequency switch, so that the probe is connected to any one of the first load, the second load and the third load.
  • Connecting the probe to the vector network analyzer and measuring the first reflection coefficient of the probe looking at the calibration circuit may include: configuring the probe to connect to the first load, and measuring the first reflection coefficient of the probe looking at the first load, which is recorded as reflection Coefficient ⁇ A1 .
  • the probe is configured to be connected to the second load, and the first reflection coefficient of the probe looking at the second load is measured, which is recorded as the reflection coefficient ⁇ A2 .
  • the probe is configured to connect to the third load, and the first reflection coefficient of the probe looking at the third load is measured, which is recorded as the reflection coefficient ⁇ A3 .
  • a possible design method is to connect the probe to the radio frequency base, and measure the second reflection coefficient of the transceiver looking at the calibration circuit through the impedance detection path.
  • the detection channel measures the second reflection coefficient of the transceiver looking at the first load, which is recorded as reflection coefficient ⁇ M1 .
  • the probe is configured to be connected to the second load, and the second reflection coefficient of the transceiver looking at the second load is measured through the impedance detection channel, which is recorded as reflection coefficient ⁇ M2 .
  • the probe is configured to be connected to the third load, and the second reflection coefficient of the transceiver looking at the second load is measured through the impedance detection channel, which is recorded as reflection coefficient ⁇ M3 .
  • a possible design method is to calculate the network error model parameters from the transceiver to the radio frequency base according to the first reflection coefficient and the second reflection coefficient, which may include:
  • the reflection coefficient ⁇ A1 and the reflection coefficient ⁇ M1 it is determined that the first reflection coefficient and the second reflection coefficient satisfy the relationship:
  • the reflection coefficient ⁇ A2 and the reflection coefficient ⁇ M2 it is determined that the first reflection coefficient and the second reflection coefficient satisfy the relationship:
  • the reflection coefficient ⁇ A2 and the reflection coefficient ⁇ M2 it is determined that the first reflection coefficient and the second reflection coefficient satisfy the relationship:
  • the parameters a, b and c are calculated; among them, the parameters a, b and c are the network error model parameters from the transceiver to the radio frequency base.
  • the calibration circuit may further include a fourth load; the fourth load is connected to the probe through a radio frequency switch.
  • the above calibration method may further include: verifying the accuracy of the calibrated network error model parameters through the fourth load.
  • verifying the accuracy of the calibrated network error model parameters through the fourth load may include: connecting the probe to the vector network analyzer, configuring the probe to connect to the fourth load, and measuring the probe to look at the first position of the fourth load.
  • the reflection coefficient is denoted as the reflection coefficient ⁇ ′ A4 .
  • Connect the probe to the radio frequency base configure the probe to connect to the fourth load, and measure the second reflection coefficient of the transceiver looking at the fourth load through the impedance detection channel, which is recorded as reflection coefficient ⁇ M4 . According to the reflection coefficient ⁇ ′ A4 and the reflection coefficient ⁇ M4 , the accuracy of the calibrated network error model parameters is verified.
  • verifying the accuracy of the calibrated network error model parameters may include: according to the reflection coefficient ⁇ M4 and the formula The reflection coefficient ⁇ A4 of the probe looking at the fourth load is calculated. Compare the reflection coefficient ⁇ ' A4 with the reflection coefficient ⁇ A4 . It is judged whether the error between the reflection coefficient ⁇ A4 and the reflection coefficient ⁇ ' A4 is less than the preset value, and when the error between the reflection coefficient ⁇ A4 and the reflection coefficient ⁇ ' A4 is less than the preset value, the network error model parameters meet the application requirements. .
  • a possible design method is that the calibration device may further include a comprehensive tester; the comprehensive tester is connected to a probe through a radio frequency switch to calibrate the transmit and receive power of the radio frequency front-end circuit.
  • the above calibration method may further include: configuring a probe to connect to a comprehensive tester to calibrate the transceiver power of the radio frequency front-end circuit.
  • the calibration method uses the calibration device provided in the first aspect, and the technical effect of the calibration method can refer to the calibration device provided in the first aspect, which will not be repeated here.
  • the present application provides an electronic device.
  • the electronic device includes one or more processors, one or more memories, and a communication interface. wherein one or more memories and a communication interface are coupled to one or more processors, the communication interface is used for wireless communication with other communication devices, the one or more memories are used to store computer program code, and the computer program code includes computer instructions, When one or more processors execute computer instructions, the electronic device performs the method of the second aspect and any possible design thereof.
  • the present application provides a chip system, which is applied to an electronic device including a memory.
  • the chip system includes one or more interface circuits and one or more processors.
  • the interface circuit and the processor are interconnected by wires.
  • the interface circuit is used to receive signals from the memory and send signals to the processor, the signals including computer instructions stored in the memory.
  • the processor executes the computer instructions, the electronic device performs the method of the second aspect and any possible design thereof.
  • embodiments of the present application provide a computer-readable storage medium, including computer instructions, when the computer instructions are executed on an electronic device, the electronic device is made to perform the method of the second aspect and any possible design methods thereof .
  • embodiments of the present application provide a computer program product, which, when the computer program product runs on a computer, causes the computer to execute the method of the second aspect and any possible design manner thereof.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a radio frequency front-end circuit provided by an embodiment of the present application.
  • Figure 3 is a graph showing the impedance fluctuations of different terminal devices at different antenna impedance amplitudes and phases without impedance calibration
  • Fig. 4 is the schematic diagram that the impedance fluctuation in Fig. 3 is represented by vector distance;
  • FIG. 5 is a schematic diagram of connection between a calibration device for antenna impedance detection and a test PCB provided by an embodiment of the present application;
  • FIG. 6 is a schematic structural diagram 1 of a calibration circuit provided by an embodiment of the present application.
  • FIG. 7 is a second schematic structural diagram of a calibration circuit provided by an embodiment of the present application.
  • FIG. 8 is a schematic diagram of a specific structure of the calibration circuit in FIG. 7;
  • FIG. 9 is a schematic diagram of the distribution of the reflection coefficient of the load in the calibration circuit in FIG. 8 on the Smith chart;
  • FIG. 10 is a flowchart of a calibration method for antenna impedance detection provided by an embodiment of the application.
  • FIG. 11 is a third schematic structural diagram of a calibration circuit provided by an embodiment of the present application.
  • FIG. 12 is a schematic diagram of a specific structure of the calibration circuit in FIG. 11;
  • Fig. 13 is a schematic diagram of the distribution of the reflection coefficient of the load in the calibration circuit in Fig. 12 on the Smith chart;
  • Figure 14 is a graph showing the impedance fluctuations of different terminal devices at different antenna impedance amplitudes and phases after impedance calibration
  • FIG. 15 is a schematic diagram of the impedance fluctuation in FIG. 14 represented by vector distance;
  • 16 is a schematic diagram of the connection between another calibration device for antenna impedance detection and a test PCB provided by an embodiment of the application;
  • FIG. 17 is a fourth schematic structural diagram of a calibration circuit provided by an embodiment of the present application.
  • FIG. 18 is a fifth structural schematic diagram of a calibration circuit provided by an embodiment of the present application.
  • FIG. 19 is a sixth schematic structural diagram of a calibration circuit provided by an embodiment of the present application.
  • At least one means one or more
  • plural means two or more.
  • And/or which describes the association relationship of the associated objects, indicates that there can be three kinds of relationships, for example, A and/or B, which can indicate: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A, B can be singular or plural.
  • At least one item(s) below or similar expressions thereof refer to any combination of these items, including any combination of single item(s) or plural items(s).
  • At least one (a) of a, b or c may represent: a, b, c, a-b, a-c, b-c or a-b-c, where a, b and c may be single or multiple.
  • the character "/" generally indicates that the associated objects are an "or” relationship.
  • words such as "first” and “second” do not limit the quantity and execution order.
  • connection should be understood in a broad sense.
  • connection may be a fixed connection, a detachable connection, or an integrated body; it may be directly connected, or Can be indirectly connected through an intermediary.
  • electrical connection may be a direct electrical connection or an indirect electrical connection through an intermediate medium.
  • FIG. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
  • the electronic device may be a terminal device in this embodiment of the present application, or may be a base station.
  • the electronic equipment may include an application subsystem, a memory, a mass storage, a baseband subsystem, a radio frequency integrated circuit (RFIC), a radio frequency front end, RFFE) devices, and antennas (antenna, ANT), these devices can be coupled through various interconnecting buses or other electrical connections.
  • RFIC radio frequency integrated circuit
  • RFFE radio frequency front end
  • antennas antennas
  • ANT_1 represents the first antenna
  • ANT_N represents the Nth antenna
  • N is a positive integer greater than 1.
  • Tx represents the transmit path
  • Rx represents the receive path
  • different numbers represent different paths.
  • FBRx represents the feedback receiving path
  • PRx represents the primary receiving path
  • DRx represents the diversity receiving path.
  • HB means high frequency
  • LB means low frequency, both refer to the relative high and low frequency.
  • BB stands for baseband.
  • the application subsystem can be used as the main control system or main computing system of the electronic device to run the main operating system and application programs, manage the hardware and software resources of the entire electronic device, and provide users with a user interface.
  • the application subsystem may include one or more processing cores.
  • the application subsystem may also include driver software related to other subsystems (eg, baseband subsystem).
  • the baseband subsystem may also include one or more processing cores, as well as hardware accelerators (HACs) and caches.
  • HACs hardware accelerators
  • the RFFE device, RFIC 1 can collectively form an RF subsystem.
  • the RF subsystem can be further divided into the RF receive path (RF receive path) and the RF transmit path (RF transmit path).
  • the RF receive channel can receive the RF signal through the antenna, process the RF signal (eg, amplify, filter and down-convert) to obtain the baseband signal, and transmit it to the baseband subsystem.
  • the RF transmit channel can receive the baseband signal from the baseband subsystem, perform RF processing (such as up-conversion, amplification and filtering) on the baseband signal to obtain the RF signal, and finally radiate the RF signal into space through the antenna.
  • the radio frequency subsystem may include an antenna switch, an antenna tuner, a low noise amplifier (LNA), a power amplifier (PA), a mixer (mixer), a local oscillator (LOO) ), filters and other electronic devices, which can be integrated into one or more chips as required. Antennas can also sometimes be considered part of the RF subsystem.
  • LNA low noise amplifier
  • PA power amplifier
  • mixer mixer
  • LEO local oscillator
  • the baseband subsystem can extract useful information or data bits from the baseband signal, or convert the information or data bits into the baseband signal to be transmitted. These information or data bits may be data representing user data or control information such as voice, text, video, etc.
  • the baseband subsystem can implement signal processing operations such as modulation and demodulation, encoding and decoding. Different radio access technologies, such as 5G NR and 4G LTE, tend to have different baseband signal processing operations. Therefore, in order to support the convergence of multiple mobile communication modes, the baseband subsystem may simultaneously include multiple processing cores, or multiple HACs.
  • the radio frequency signal is an analog signal
  • the signal processed by the baseband subsystem is mainly a digital signal
  • an analog-to-digital conversion device is also required in the electronic equipment.
  • the analog-to-digital conversion device includes an analog-to-digital converter (ADC) that converts an analog signal to a digital signal, and a digital-to-analog converter (DAC) that converts a digital signal to an analog signal.
  • ADC analog-to-digital converter
  • DAC digital-to-analog converter
  • the analog-to-digital conversion device may be disposed in the baseband subsystem, or may be disposed in the radio frequency subsystem.
  • the processing core may represent a processor, and the processor may be a general-purpose processor or a processor designed for a specific field.
  • the processor may be a central processing unit (center processing unit, CPU), or may be a digital signal processor (digital signal processor, DSP).
  • the processor may also be a microcontroller (micro control unit, MCU), a graphics processor (graphics processing unit, GPU), an image signal processor (image signal processing, ISP), an audio signal processor (audio signal processor, ASP) ), and processors specially designed for artificial intelligence (AI) applications.
  • AI processors include, but are not limited to, neural network processing units (NPUs), tensor processing units (TPUs), and processors called AI engines.
  • Hardware accelerators can be used to implement some sub-functions with high processing overhead, such as data packet assembly and parsing, data packet encryption and decryption, etc. These sub-functions can also be implemented using general-purpose processors, but hardware accelerators may be more appropriate due to performance or cost considerations. Therefore, the type and number of hardware accelerators can be specifically selected based on requirements. In a specific implementation manner, one or a combination of a field programmable gate array (FPGA) and an application specific integrated circuit (ASIC) can be used for implementation. Of course, one or more processing cores may also be used in a hardware accelerator.
  • FPGA field programmable gate array
  • ASIC application specific integrated circuit
  • Memory can be divided into volatile memory (volatile memory) and non-volatile memory (non-volatile memory, NVM).
  • Volatile memory refers to memory in which data stored inside is lost when the power supply is interrupted.
  • volatile memory is mainly random access memory (random access memory, RAM), including static random access memory (static RAM, SRAM) and dynamic random access memory (dynamic RAM, DRAM).
  • RAM random access memory
  • SRAM static random access memory
  • DRAM dynamic random access memory
  • Non-volatile memory refers to memory whose internal data will not be lost even if the power supply is interrupted.
  • Common non-volatile memories include read only memory (ROM), optical disks, magnetic disks, and various memories based on flash memory technology.
  • ROM read only memory
  • mass storage can choose non-volatile memory, such as magnetic disk or flash memory.
  • the baseband subsystem and the radio frequency subsystem together form a communication subsystem, which provides a wireless communication function for the electronic device.
  • the baseband subsystem is responsible for managing the hardware and software resources of the communication subsystem, and can configure the working parameters of the radio frequency subsystem.
  • One or more processing cores of the baseband subsystem may be integrated into one or more chips, which may be referred to as baseband processing chips or baseband chips.
  • RFICs may be referred to as radio frequency processing chips or radio frequency chips.
  • the functional division of the radio frequency subsystem and the baseband subsystem in the communication subsystem can also be adjusted.
  • the functions of part of the radio frequency subsystem are integrated into the baseband subsystem, or the functions of part of the baseband subsystem are integrated into the radio frequency subsystem.
  • electronic devices may employ combinations of different numbers and types of processing cores.
  • the radio frequency subsystem may include an independent antenna, an independent radio frequency front end (RF front end, RFFE) device, and an independent radio frequency chip.
  • a radio frequency chip is also sometimes referred to as a receiver, transmitter, or transceiver.
  • Antennas, RF front-end devices, and RF processing chips can all be manufactured and sold separately.
  • the RF subsystem can also use different devices or different integration methods based on power consumption and performance requirements. For example, some devices belonging to the radio frequency front-end are integrated into the radio frequency chip, and even the antenna and the radio frequency front-end device are integrated into the radio frequency chip, and the radio frequency chip can also be called a radio frequency antenna module or an antenna module.
  • the baseband subsystem may be used as an independent chip, and the chip may be called a modem chip.
  • the hardware components of the baseband subsystem can be manufactured and sold in units of modem chips. Modem chips are also sometimes called baseband chips or baseband processors.
  • the baseband subsystem can also be further integrated in the SoC chip, and the SoC chip is manufactured and sold as a unit.
  • the software components of the baseband subsystem can be built into the hardware components of the chip before the chip leaves the factory, or can be imported into the hardware components of the chip from other non-volatile memory after the chip leaves the factory, or can also be downloaded online through the network. and update these software components.
  • FIG. 2 is a schematic structural diagram of a radio frequency front-end circuit provided by an embodiment of the present application.
  • the RF front-end circuit is connected to the transceiver.
  • the transceiver may include a radio frequency processing chip or a baseband processing chip for processing transmitted signals and received information.
  • the RF front-end circuit includes a power amplifier (PA), a low noise amplifier (LNA), a duplexer, and a main RF base for connecting the main antenna.
  • PA power amplifier
  • LNA low noise amplifier
  • duplexer a duplexer
  • main RF base for connecting the main antenna.
  • the radio frequency front-end circuit can be divided into a radio frequency transmit path and a radio frequency receive path.
  • the transceiver In the radio frequency transmission path, the transceiver is connected to the duplexer through the power amplifier PA; in the radio frequency reception path, the transceiver is connected to the duplexer through the low noise amplifier; Connect to the antenna.
  • the duplexer is used to isolate the transmit signal and the receive signal, so as to ensure that the radio frequency transmit channel and the radio frequency receive channel connected to the transceiver can work normally at the same time.
  • a frequency band selection switch is also arranged to control the working frequency band of the radio frequency front-end circuit.
  • the radio frequency front-end circuit also includes a sub-radio base for connecting the diversity antenna, and the sub-radio base is used for connecting the diversity circuit to process the signal received by the diversity antenna. After the signal received by the diversity antenna is processed, it can be combined with the signal received by the main antenna, thereby improving the diversity gain of the received signal.
  • the main radio base and the branch radio base can pass a double pole double throw (DPDT)
  • the switch is connected to the duplexer and the diversity circuit, respectively.
  • the main radio base and the branch radio base may be collectively referred to as radio frequency bases.
  • the RF front-end circuit needs to support the function of impedance detection in order to achieve impedance matching. Therefore, in order to realize the impedance detection of the RF front-end device, the transceiver has an impedance detection function, and the transceiver includes an impedance detection interface, and an impedance detection path is connected to the impedance detection interface, which is used to measure the reflection coefficient of the transceiver looking at the impedance detection path.
  • the impedance detection path may include a bidirectional coupler and a detection switch (ie, a forward and reverse switch).
  • the forward power signal and the reverse power signal of the radio frequency transmission signal can be detected through the bidirectional coupler and the forward and reverse switches on the impedance detection path.
  • the forward power signal represents the signal transmitted by the radio frequency signal to the antenna
  • the reverse power signal represents the signal reflected back from the antenna.
  • the detected forward power signal and reverse power signal after frequency conversion of the impedance detection channel, are respectively processed with the corresponding radio frequency transmission signal.
  • the impedance detection channel of the transceiver can be obtained Reflection coefficient.
  • the antenna is connected to the radio frequency seat (such as the main radio frequency seat) in the radio frequency chip.
  • the impedance looking at the antenna from the radio base needs to be detected.
  • the reflection coefficient of the transceiver looking at the antenna can be detected through the impedance detection path, that is, the reflection coefficient of the transceiver looking at the impedance detection path, which can be recorded as the reflection coefficient ⁇ M .
  • the reflection coefficient ⁇ A from the radio frequency seat to the antenna can be calculated.
  • the reflection coefficient ⁇ A and the reflection coefficient ⁇ M have the relationship shown in the following formula (1):
  • a, b and c are the network error model parameters from the transceiver to the radio frequency base.
  • the reflection coefficient ⁇ A viewed from the RF base to the antenna can be converted from the RF base to the antenna
  • the impedance Z in Specifically, after the reflection coefficient ⁇ A viewed from the radio frequency seat to the antenna is calculated, the impedance Z in viewed from the radio frequency seat to the antenna can be calculated according to the following formula (2).
  • Z 0 is the characteristic impedance of the antenna, which is generally 50 ohms (Ohm).
  • the RF components in the RF front-end circuit such as detection switches, bidirectional couplers and transceivers, and the RF performance differences caused by PCB trace processing, it may cause the detection of antennas between different terminal equipment. Fluctuations in impedance (ie, the impedance looking at the antenna from the radio base). As shown in Figure 3, it is the impedance fluctuation situation of different terminal devices at different antenna impedance amplitudes and phases without impedance calibration.
  • the small black dots ( ⁇ ) in the figure are the terminals when the antenna impedance amplitude is divided into 0.2, 0.4, 0.6, 0.8, and the antenna impedance phase is 0, 45, 90, 135, 180, 225, 270, and 315.
  • the ideal antenna impedance value of the device, the circle ( ⁇ ) around the small black dot is the antenna impedance actually measured by different terminal devices.
  • point A in Figure 3 is an antenna impedance value with an antenna impedance amplitude of 0.2 and an antenna impedance phase of 45;
  • point B is an antenna impedance value with an antenna impedance amplitude of 0.4 and an antenna impedance phase of 45;
  • point C is the antenna impedance The amplitude is 0.6 and the antenna impedance phase is 45;
  • point D is the antenna impedance value with the antenna impedance amplitude of 0.8 and the antenna impedance phase of 45;
  • point E is the antenna impedance with the antenna impedance amplitude of 0.4 and the antenna impedance phase of 135 value. From Figure 3, comparing the small black dot ( ⁇ ) with the circle ( ⁇ ) around the small black dot, it can be seen that the antenna impedance actually measured by different terminal devices has large fluctuations.
  • FIG. 4 it is a schematic diagram of the impedance fluctuation in FIG. 3 represented by vector distance.
  • the abscissa of FIG. 4 is the measured number of samples of the antenna impedance of the terminal device, and the ordinate of FIG. 2 is the vector distance (distance).
  • the vector distance refers to the vector distance between the offset position caused by the tolerance and the ideal position between different terminal devices on the Smith chart shown in Figure 2, and the distance can be calculated by the following formula (3):
  • P1 is the ideal antenna impedance value of the terminal device
  • P2 is the antenna impedance value actually measured
  • P1 real refers to the resistance value of the P1 impedance
  • P2 real refers to the resistance value of the P2 impedance
  • P1 imag refers to the P1 impedance value.
  • Reactance value P2 imag refers to the reactance value of the P2 impedance.
  • the embodiments of the present application provide a calibration device and a calibration method for antenna impedance detection, which are used for the calibration of the terminal device. Antenna impedance detection for calibration.
  • the radio frequency front-end circuit is generally arranged on a PCB board of the terminal device.
  • the PCB board including the radio frequency front-end circuit is referred to as a test PCB.
  • FIG. 5 is a schematic diagram of the connection between a calibration device for antenna impedance detection and a test PCB according to an embodiment of the present application.
  • the test PCB includes transceivers, RF front-end circuits, and impedance detection paths.
  • the radio frequency front-end circuit may include a radio frequency transmit channel circuit including a power amplifier and a duplexer as shown in FIG. 2 , and may also include a radio frequency receive channel circuit including a low noise amplifier and a duplexer as shown in FIG. 2 .
  • the transceiver is connected to the radio frequency front-end circuit, and the radio frequency front-end circuit is connected to the antenna through the main radio frequency base, so that the transceiver transmits and receives radio frequency signals through the antenna.
  • the transceiver has an impedance detection function, and is connected to the impedance detection path through the impedance detection port. The reflection coefficient of the transceiver looking at the impedance detection path can be measured through the impedance detection function of the transceiver.
  • the calibration device includes a jig PCB, and a calibration circuit and probes arranged on the jig PCB board.
  • the calibration circuit is connected to the probe, which is used to connect the vector network analyzer.
  • the probe can also be used to connect the RF socket on the test PCB, so that the calibration circuit is connected with the RF front-end circuit to form a signal path.
  • the probe When the probe is connected to the vector network analyzer, it can be used to measure the first reflection coefficient of the probe looking at the calibration circuit.
  • the probe When the probe is connected to the RF seat on the test PCB, it can be used to measure the second reflection coefficient of the transceiver looking at the calibration circuit, so as to calculate the network error from the transceiver to the RF seat according to the first reflection coefficient and the second reflection coefficient model parameters to complete the calibration of the antenna impedance detection.
  • the probe on the fixture PCB can be fastened with the main RF seat on the test PCB, so that the probe is connected to the main RF seat.
  • the reflection coefficient of the transceiver looking at the impedance detection path can be detected as the reflection coefficient ⁇ M .
  • the reflection coefficient of the probe looking towards the calibration circuit can be measured.
  • the probe and the RF base can be regarded as the same position when the probe is connected to the RF base (such as the main RF base), when the probe on the fixture PCB is connected to the vector network analyzer, the measured probe looks towards the calibration
  • the first reflection coefficient of the circuit can be used as the reflection coefficient ⁇ A in the above formula (1).
  • the transceiver can be calculated according to formula (1).
  • Network error model parameters a, b, and c to the radio base.
  • the calculated network error model parameters a, b and c are used as the calibrated network error model parameters.
  • the impedance detection path on the PCB can be tested to detect the reflection coefficient ⁇ M of the transceiver looking at the antenna, and then combine the formula (1) and the calibrated
  • the network error model parameters a, b and c are calculated to obtain the reflection coefficient ⁇ A from the radio frequency base to the antenna, so as to realize the accurate detection of the antenna impedance.
  • the calibration circuit may include a radio frequency switch, a first load, a first Two loads and a third load; and the first load, the second load and the third load are connected to the probe through a radio frequency switch, so that the probe is connected to any one of the first load, the second load and the third load.
  • the radio frequency switch may be a single pole three throw (SP3T) switch.
  • the probe When the RF switch is switched to the second load, the probe is connected to the second load; at this time, the reflection coefficient ⁇ A and the reflection coefficient ⁇ M when the probe is connected to the second load can be measured.
  • the RF switch When the RF switch is switched to the third load, the probe is connected to the third load; at this time, the reflection coefficient ⁇ A and the reflection coefficient ⁇ M when the probe is connected to the second load can be measured. Then, the network error model parameters a, b and c can be obtained by calculation according to the acquired three groups of reflection coefficients ⁇ A and ⁇ M .
  • two radio frequency sockets can be set in the RF front-end circuit as shown in Figure 2, respectively the main radio frequency socket and the branch radio frequency socket, the main radio frequency socket
  • the radio base is used to connect the main set antenna
  • the branch radio base is used to connect the diversity antenna.
  • the path connecting the main set antenna through the main radio base is the main set path
  • the path connecting the diversity antenna through the branch radio base is the diversity path. Therefore, corresponding to the test PCB in FIG. 5 , the test PCB is provided with two radio frequency sockets, respectively the main radio frequency socket and the branch radio frequency socket.
  • the RF front-end circuit is connected to the main antenna through the main RF base
  • the diversity circuit is connected to the diversity antenna through the sub-RF base.
  • two probes are arranged on the fixture PCB, namely the main set probe and the diversity probe.
  • the main set probe can be fastened with the main radio frequency seat to realize signal connection.
  • the diversity probe can be snapped together with the splitter radio base to realize signal connection.
  • the RF switch needs to be connected to the main set probe and the diversity probe at the same time.
  • the radio frequency switch can be a double pole three throw (DP3T) switch.
  • the main set probe can be configured to be connected to the first load, the second load and the third load respectively through the radio frequency switch;
  • the diversity probe can also be configured to be connected to the first load, the second load and the third load respectively.
  • the impedances of the first load, the second load and the third load in the calibration circuit can be designed as three standard impedances of open circuit, short circuit and 50 ohms (Ohm). , or any other impedance.
  • the impedance positions of the first load, the second load, and the third load may be triangularly distributed on the Smith chart.
  • FIG. 8 is a structural example of a calibration circuit.
  • the calibration circuit shown in FIG. 8 includes a radio frequency switch using a double pole three throw (DP3T) switch, so that the main set probe can be The first load, the second load and the third load are respectively connected, and the diversity probe can also be connected to the first load, the second load and the third load respectively.
  • the first load uses a 65 ohm (Ohm) resistor
  • the second load uses a 1 Ohm resistor
  • the third load uses a 15 Ohm resistor and a 2.4 nanohenry (nH) inductance in series.
  • nH nanohenry
  • a PCB trace (MLIN) for impedance rotation is also connected to the first load and the third load, which can be used to rotate the impedance of the first load and the third load to a desired position.
  • FIG. 9 shows the reflection coefficients of the first load, the second load and the third load in the calibration circuit shown in FIG. 8 .
  • the impedance positions of the first load, the second load, and the third load are triangularly distributed on the Smith chart, and their frequency coverage ranges from 1.7 gigahertz (GHz) to 2.7 GHz.
  • the following describes the calibration method performed by applying the calibration apparatus shown in FIG. 5 by taking the main set probe connected to the main radio frequency base as an example.
  • FIG. 10 is a calibration method for antenna impedance detection provided by an embodiment of the present application. This calibration method is applied to the calibration device shown in FIG. 5 . Referring to Figure 10, the calibration method includes:
  • S1001 connect the probe to a vector network analyzer, and measure the first reflection coefficient of the probe looking toward the calibration circuit.
  • the RF switch in the calibration circuit can be configured to the first load, so that a path is formed between the first load and the main set probe, and then the vector network analyzer is used to obtain the main set probe looking at the first load.
  • the first reflection coefficient of denoted as reflection coefficient ⁇ A1 .
  • the radio frequency switch in the calibration circuit can be configured on the second load, so that a path is formed between the second load and the main set probe, and then measured by the vector network analyzer to obtain that the main set probe looks at the second load.
  • the first reflection coefficient of denoted as reflection coefficient ⁇ A2 .
  • the radio frequency switch in the calibration circuit can also be configured to the third load, so that a path is formed between the third load and the main set probe, and then measured by the vector network analyzer to obtain that the main set probe looks at the third load
  • the first reflection coefficient of denoted as reflection coefficient ⁇ A3 .
  • S1002 connect the probe to the radio frequency base, and measure the second reflection coefficient of the transceiver looking at the calibration circuit through the impedance detection channel.
  • the fixture PCB shown in FIG. 5 can be buckled with the test PCB, that is, the main set probe on the fixture PCB and the main RF seat on the test PCB can be buckled correspondingly, so that the main set probe and the RF front end are buckled.
  • the main RF sockets of the circuit are connected and form a signal path.
  • the radio frequency switch in the calibration circuit can be configured to the first load, the second load and the third load respectively, and the second reflection coefficient can be obtained by measuring the impedance detection path.
  • the radio frequency switch in the calibration circuit can be configured on the first load to form a path between the first load and the main set probe, thereby forming a path between the first load and the radio frequency front-end circuit.
  • the second reflection coefficient of the transceiver looking at the first load can be measured and obtained, which is recorded as the reflection coefficient ⁇ M1 .
  • the radio frequency switch in the calibration circuit can be configured on the second load, so that a path is formed between the second load and the main set probe, thereby forming a path between the second load and the radio frequency front-end circuit.
  • the second reflection coefficient of the transceiver looking at the second load can be measured and obtained, which is recorded as the reflection coefficient ⁇ M2 .
  • the radio frequency switch in the calibration circuit can be configured on the third load, so that a path is formed between the third load and the main set probe, and thus a path is formed between the third load and the radio frequency front-end circuit.
  • the second reflection coefficient of the transceiver looking at the third load can be measured and obtained, which is recorded as the reflection coefficient ⁇ M3 .
  • the reflection coefficient ⁇ A looking at the antenna from the main radio frequency seat is related to the reflection coefficient ⁇ M when the transceiver looks at the antenna. Since the RF seat on the test PCB is connected to the probe on the fixture PCB when calibrating the test PCB, the first reflection coefficient measured in step S1001 is equivalent to the reflection coefficient ⁇ A in formula (1). ; The second reflection coefficient measured in step S1002 is equivalent to the reflection coefficient ⁇ M in formula (1).
  • the network error model parameters a, b and c from the transceiver to the radio frequency base can be calculated.
  • the parameters a, b, and c can be stored in the terminal device for calculating the reflection coefficient of the radio frequency base looking at the antenna when the terminal device tunes the antenna.
  • the third reflection coefficient ⁇ M of the transceiver looking at the antenna is measured through the impedance detection channel.
  • the fourth reflection coefficient ⁇ A of the radio frequency seat looking toward the antenna can be calculated.
  • the impedance Z in of the radio frequency base looking at the antenna can be obtained.
  • the above calibration circuit may further include a fourth load, and the fourth load may be connected to the master probe through a radio frequency switch.
  • the radio frequency switch When the radio frequency switch is switched to the fourth load, the fourth load is connected to the main set probe.
  • FIG. 12 is another structural example of the calibration circuit.
  • the calibration circuit shown in FIG. 12 adds a fourth load on the basis of the calibration circuit shown in FIG. 8 .
  • the fourth load adopts a resistance of 15Ohm, and a short-circuit branch is designed on the fourth load.
  • the RF switch adopts a double pole four throw (DP4T) switch, so that the main set probe can be connected to the first load, the second load, the third load and the fourth load respectively, and the diversity
  • the probes may also be connected to the first load, the second load, the third load and the fourth load, respectively.
  • DSP4T double pole four throw
  • FIG. 13 shows the reflection coefficients of the first load, the second load, the third load and the fourth load in the calibration circuit shown in FIG. 12 .
  • the impedance positions of the first load, the second load, and the third load are triangularly distributed on the Smith chart, and their frequency coverage ranges from 1.7 gigahertz (GHz) to 2.7 GHz.
  • the fourth load can be used to verify the accuracy of the calibrated transceiver-to-RF base network error model parameters.
  • the parameters of the calibrated network error model can be verified through the fourth load, which may include the following steps:
  • the RF switch in the calibration circuit can be configured to the fourth load, so that a path is formed between the fourth load and the main set probe, thereby A path is formed between the fourth load and the RF front-end circuit, and by testing the impedance detection path on the PCB, the second reflection coefficient of the transceiver looking at the fourth load can be measured and recorded as reflection coefficient ⁇ M4 .
  • the accuracy of the calibrated network error model parameters can be verified. specifically:
  • the reflection coefficient ⁇ A4 can be calculated. Comparing the reflection coefficient ⁇ ' A4 obtained by the above measurement and the calculated reflection coefficient ⁇ A4 , it is judged whether the error between the reflection coefficient ⁇ A4 and the reflection coefficient ⁇ ' A4 meets the preset value, and the calibrated network error model parameter a can be verified. , b and c meet the application requirements.
  • the preset value may be 0.1. If the error range between the measured reflection coefficient ⁇ ′ A4 and the calculated reflection coefficient ⁇ A4 is less than 0.1, the calibrated parameters a, b and c meet the application requirements. In this case, the error occurs due to impedance (or reflection coefficient) fluctuations when the probe is in contact with the RF mount.
  • the fluctuations of the antenna impedance of different terminal equipment are shown in Figure 14.
  • the shaded parts in the figure are the antenna impedance amplitudes divided into 0.2, 0.4, 0.6, 0.8 , the antenna impedance fluctuation of the terminal device when the antenna impedance phase is 0, 45, 90, 135, 180, 225, 270 and 315.
  • the fluctuation of the antenna impedance value actually measured by different terminal devices in FIG. 14 is significantly reduced.
  • FIG. 15 it is a schematic diagram of the impedance fluctuation in FIG. 14 represented by vector distance.
  • the abscissa of FIG. 15 is the measured number of samples of the antenna impedance of the terminal device, and the ordinate of FIG. 15 is the distance.
  • the maximum fluctuation distance corresponding to the antenna impedance value actually measured by different terminal devices is about 0.08. Compared with the maximum fluctuation distance of 0.18 in Figure 4, there is a significant reduction.
  • the diversity probe and the splitter radio base when it is necessary to calibrate the diversity path on the splitter radio base, can be snapped together to achieve connection, and the diversity probe can be configured to be connected to the first load, the second load and the
  • the third load is configured with a sub-radio base to connect the RF front-end circuit, the transceiver and the impedance detection path, so as to realize the calibration of the antenna impedance detection on the sub-radio base and facilitate the subsequent impedance detection of the diversity antenna.
  • the specific calibration method for the calibration of the antenna impedance detection on the sub-radio base is similar to the method when the main set probe is connected to the main radio base, and will not be repeated here.
  • the calibration device shown in FIG. 5 and the calibration method described in FIG. 10 a set of calibration devices can be used to calibrate different terminal devices, which is more cost-effective.
  • the impedance (reflection coefficient) of each load in the calibration circuit can be obtained through the vector network analyzer. After the calibration, the accuracy of impedance detection can be greatly improved, that is, the fluctuation of the antenna impedance of different terminal equipment is reduced.
  • the calibration device shown in FIG. 5 may further include a comprehensive tester, and the comprehensive tester can be used to calibrate and test the transmit and receive power of the RF front-end circuit on the PCB, as shown in FIG. 16 .
  • the comprehensive tester can be connected to the probe through the RF switch.
  • the RF switch on the fixture PCB can be switched to the channel connected to the comprehensive tester.
  • the calibration circuit can be set as the calibration circuit shown in FIG. 17 , FIG. 18 and FIG. 19 .
  • the RF switch in the calibration circuit shown in Figure 17 uses a single pole four throw (SP4T) switch, so that the calibration circuit can be configured as The probe is connected to the comprehensive tester.
  • the RF switch in the calibration circuit shown in Figure 18 uses a double pole four throw (DP4T) switch, so that the calibration circuit can be configured Connect the tester for the probe.
  • Fig. 19 compared with the calibration circuit shown in Fig. 11, the RF switch in the calibration circuit shown in Fig.
  • the calibration circuit 19 adopts a single-pole four-throw switch, and a double-pole double-throw switch is also added, which can make
  • the calibration circuit is configured to connect the master probe to the comprehensive tester or the radio frequency switch, and the calibration circuit can also be configured to connect the diversity probe to the comprehensive tester or the radio frequency switch.
  • the RF front-end circuit can be calibrated by a comprehensive tester for the RF transceiver power, so that the calibration device shown in Fig. 16 can not only perform a calibration on the impedance of the RF front-end circuit It can also calibrate the RF transceiver power, thereby improving the calibration efficiency of the RF front-end circuit in the terminal equipment and saving costs.
  • the computer can communicate with the comprehensive tester, the fixture PCB and the test PCB, and the computer can control whether to enter the calibration state, whether to execute the steps in the above method, and whether to store the corresponding data.
  • the embodiment of the present application further provides a chip system, and the chip system can be applied to the electronic device in the foregoing embodiments.
  • the chip system includes at least one processor and at least one interface circuit.
  • the processor may be the processor in the electronic device described above.
  • the processor and interface circuits may be interconnected by wires.
  • the processor may receive and execute computer instructions from the memory of the electronic device described above through the interface circuit. When the computer instructions are executed by the processor, the electronic device can be caused to perform the various steps in the above method embodiments.
  • the chip system may also include other discrete devices, which are not specifically limited in this embodiment of the present application.
  • Embodiments of the present application further provide a computer storage medium, where the computer storage medium includes computer instructions, which, when the computer instructions are executed on an electronic device, cause the electronic device to perform various functions or steps in the foregoing method embodiments.
  • Embodiments of the present application further provide a computer program product, which, when the computer program product runs on a computer, enables the computer to execute each function or step in the foregoing method embodiments.
  • Each functional unit in each of the embodiments of the embodiments of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned integrated units may be implemented in the form of hardware, or may be implemented in the form of software functional units.
  • the integrated unit if implemented in the form of a software functional unit and sold or used as an independent product, may be stored in a computer-readable storage medium.
  • a computer-readable storage medium includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in the various embodiments of the present application.
  • the aforementioned storage medium includes: flash memory, removable hard disk, read-only memory, random access memory, magnetic disk or optical disk and other media that can store program codes.

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Abstract

一种用于天线阻抗检测的校准装置及方法，以解决如何对不同的终端设备进行单独校准的问题，并且提高校准后阻抗检测的精度。该校准装置应用于测试PCB。该测试PCB中，射频座通过射频前端电路连接收发机。收发机通过阻抗检测接口连接阻抗检测通路，用于测量收发机看向阻抗检测通路的反射系数。校准装置包括夹具PCB板以及设置在夹具PCB板上的校准电路和探针。校准电路连接探针。探针用于连接矢量网络分析仪或射频座。探针在连接矢量网络分析仪时，用于测量探针看向校准电路的第一反射系数；探针在连接射频座时，用于测量收发机看向校准电路的第二反射系数，以根据第一反射系数和第二反射系数，完成天线阻抗检测的校准。

Description

一种用于天线阻抗检测的校准装置及方法
本申请要求于2021年4月23日提交国家知识产权局、申请号为202110444395.4、申请名称为“一种用于天线阻抗检测的校准装置及方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及射频技术领域，尤其涉及一种用于天线阻抗检测的校准装置及方法。
背景技术
通常情况下，终端设备的天线需要支持闭环调谐功能或者天线场景检测。为实现天线的闭环调谐功能或天线场景检测，在与天线连接的射频前端电路中需要具有阻抗检测的功能。由于射频前端电路中的射频器件，如切换开关、耦合器以及PCB走线等加工制造，可能带来射频性能的差异，如S参数的幅度和相位的波动，使得不同的终端设备检测到的阻抗具有较大的波动。为保证阻抗检测的精度，不同的终端设备需要进行单独校准。如何实现不同的终端设备单独校准并提高校准的精度，面临着挑战。
发明内容
本申请提供了一种用于天线阻抗检测的校准装置及方法，以解决如何对不同的终端设备进行单独校准的问题，并且提高校准后天线阻抗检测的精度。
第一方面，本申请提供一种用于天线阻抗检测的校准装置，该校准装置应用于测试PCB。该测试PCB包括收发机、射频座、射频前端电路和阻抗检测通路。射频座连接射频前端电路，射频前端电路连接收发机。收发机包括阻抗检测接口，阻抗检测接口连接阻抗检测通路，用于测量收发机看向阻抗检测通路的反射系数。校准装置包括夹具PCB板以及设置在夹具PCB板上的校准电路和探针。校准电路连接探针。探针用于连接矢量网络分析仪或射频座。探针在连接矢量网络分析仪时，用于测量探针看向校准电路的第一反射系数。探针在连接射频座时，用于测量收发机看向校准电路的第二反射系数，以根据第一反射系数和第二反射系数，完成天线阻抗检测的校准。
可以理解地，在终端设备中，天线连接在射频芯片中的射频座(如主射频座)上。当对终端设备的天线进行调谐时，需要检测到从射频座看向天线的阻抗。当天线连接射频座时，在射频芯片中，可以通过阻抗检测通路检测到收发机看向天线的反射系数，也即收发机看向阻抗检测通路的反射系数，可以记为反射系数Γ M。根据反射系数Γ M可以计算得到从射频座看向天线的反射系数Γ A。反射系数Γ A和反射系数Γ M具有如下关系：
Figure PCTCN2022076085-appb-000001
其中，a、b和c为收发机到射频座的网络误差模型参数。
由于从射频座看向天线的阻抗Z in与从射频座看向天线的反射系数Γ A具有对应关系，通过从射频座看向天线的反射系数Γ A，可以换算得出从射频座看向天线的阻抗Z in。具体地，当计算得到从射频座看向天线的反射系数Γ A后，可以根据公式
Figure PCTCN2022076085-appb-000002
Figure PCTCN2022076085-appb-000003
计算得出从射频座看向天线的阻抗Z in。其中，Z 0为天线的特征阻抗，一般 为50欧姆。
基于上述用于天线阻抗检测的校准装置，在对测试PCB板进行阻抗检测校准时，可以将夹具PCB板上的探针与待测试的测试PCB上的射频座相扣合，实现探针与射频座相连，使得此校准装置能够对不同的终端设备进行单独校准。在阻抗校准的过程中，将探针与矢量网络分析仪相连，可以测量探针看向校准电路的反射系数，作为反射系数Γ A。并且，将探针与主射频座相连后，通过阻抗检测通路，可以检测到收发机看向阻抗检测通路的反射系数，作为反射系数Γ M。如此，在同一频率下，测量多组探针看向校准电路的第一反射系数Γ A，以及多组收发机看向阻抗检测通路的第二反射系数Γ M，便可以依据上述关系式计算出收发机到射频座的网络误差模型参数a、b和c。将计算得出的网络误差模型参数a、b和c，作为校准后的网络误差模型参数。当终端设备中的测试PCB连接天线后，需要对天线进行调谐时，可以通过测试PCB上阻抗检测通路，检测出收发机看向天线的反射系数Γ M，然后再结合公式(二)和校准后的网络误差模型参数a、b和c，计算得到从射频座到天线的反射系数Γ A，从而实现天线阻抗的精确检测。
结合第一方面，一种可能的设计方式是，校准电路可以包括射频切换开关、第一负载、第二负载和第三负载。第一负载、第二负载和第三负载通过射频切换开关与探针相连，使探针连接第一负载、第二负载和第三负载中的任意一个。
示例性地，射频切换开关可以是单刀三掷(single pole three throw，SP3T)切换开关。当射频切换开关切换到第一负载时，探针与第一负载相连；此时，可测量探针连接第一负载时的反射系数Γ A和反射系数Γ M。当射频切换开关切换到第二负载时，探针与第二负载相连；此时，可测量探针连接第二负载时的反射系数Γ A和反射系数Γ M。当射频切换开关切换到第三负载时，探针与第三负载相连；此时，可测量探针连接第二负载时的反射系数Γ A和反射系数Γ M。然后，可以根据获取的三组反射系数Γ A和反射系数Γ M，计算得到网络误差模型参数a、b和c。
结合第一方面，一种可能的设计方式是，校准电路还可以包括第四负载；第四负载通过射频切换开关与探针连接。当测试PCB板通过校准电路中的第一负载、第二负载和第三负载完成校准后，通过第四负载可以检验校准后的网络误差模型参数的精度，以验证网络误差模型参数是否符合应用要求。
结合第一方面，一种可能的设计方式是，上述校准装置还可以包括综测仪；综测仪通过射频切换开关连接探针，用于校准射频前端电路的收发功率。如此，综测仪可以通过射频切换开关连接探针。当需要实现射频收发功率的校准时，可以将夹具PCB上的射频切换开关切换到与综测仪相连的通路，使得该校准装置既能够对射频前端电路的阻抗进行校准，也能够对射频收发功率进行校准，从而提高终端设备中射频前端电路的校准效率，更加节约成本。
第二方面，本申请提供一种用于天线阻抗检测的校准方法，该校准方法使用如上第一方面中任一种可能的设计中的校准装置。该校准方法包括：将探针连接矢量网络分析仪，测量探针看向校准电路的第一反射系数。将探针连接射频座，通过阻抗检测通路测量收发机看向校准电路的第二反射系数。根据第一反射系数和第二反射系数，计算收发机到射频座的网络误差模型参数。
结合第二方面，一种可能的设计方式是，上述校准方法还可以包括：当射频座连接天线时，通过阻抗检测通路测量收发机看向天线的第三反射系数Γ M。通过网络误差模型参数和第三反射系数Γ M，计算得出射频座看向天线的第四反射系数Γ A。根据射频座看向天线的第四反射系数Γ A，获得射频座看向天线的阻抗Z in。
具体地，第三反射系数Γ M、网络误差模型参数以及第四反射系数第三反射系数Γ M之间的关系为：
Figure PCTCN2022076085-appb-000004
其中，参数a、b、c为网络误差模型参数。
具体地，射频座看向天线的阻抗Z in与第四反射系数Γ A之间的关系为：
Figure PCTCN2022076085-appb-000005
Figure PCTCN2022076085-appb-000006
其中，Z0为天线的特征阻抗。
结合第二方面，一种可能的设计方式是，校准电路可以包括射频切换开关、第一负载、第二负载和第三负载。第一负载、第二负载和第三负载通过射频切换开关与探针相连，使探针连接第一负载、第二负载和第三负载中的任意一个。将探针连接矢量网络分析仪，测量探针看向校准电路的第一反射系数，可以包括：配置探针连接第一负载，测量探针看向第一负载的第一反射系数，记为反射系数Γ A1。配置探针连接第二负载，测量探针看向第二负载的第一反射系数，记为反射系数Γ A2。配置探针连接第三负载，测量探针看向第三负载的第一反射系数，记为反射系数Γ A3。
结合第二方面，一种可能的设计方式是，将探针连接射频座，通过阻抗检测通路测量收发机看向校准电路的第二反射系数，可以包括：配置探针连接第一负载，通过阻抗检测通路测量收发机看向第一负载的第二反射系数，记为反射系数Γ M1。配置探针连接第二负载，通过阻抗检测通路测量收发机看向第二负载的第二反射系数，记为反射系数Γ M2。配置探针连接第三负载，通过阻抗检测通路测量收发机看向第二负载的第二反射系数，记为反射系数Γ M3。
结合第二方面，一种可能的设计方式是，根据第一反射系数和第二反射系数，计算收发机到射频座的网络误差模型参数，可以包括：
根据反射系数Γ A1和反射系数Γ M1，确定第一反射系数和第二反射系数满足关系：
Figure PCTCN2022076085-appb-000007
根据反射系数Γ A2和反射系数Γ M2，确定第一反射系数和第二反射系数满足关系：
Figure PCTCN2022076085-appb-000008
根据反射系数Γ A2和反射系数Γ M2，确定第一反射系数和第二反射系数满足关系：
Figure PCTCN2022076085-appb-000009
根据式(1)、式(2)和式(3)，计算得到参数a、b和c；其中，参数a、b和c为收发机到射频座的网络误差模型参数。
结合第二方面，一种可能的设计方式是，校准电路还可以包括第四负载；第四负载通过射频切换开关与探针连接。上述校准方法还可以包括：通过第四负载，验证校准后的网络误差模型参数的精度。
进一步地，通过第四负载，验证校准后的网络误差模型参数的精度，可以包括： 将探针连接矢量网络分析仪，配置探针连接第四负载，测量探针看向第四负载的第一反射系数，记为反射系数Γ′ A4。将探针连接射频座，配置探针连接第四负载，通过阻抗检测通路测量收发机看向第四负载的第二反射系数，记为反射系数Γ M4。根据反射系数Γ′ A4和反射系数Γ M4，验证校准后的网络误差模型参数的精度。
再进一步地，根据反射系数Γ′ A4和反射系数Γ M4，验证校准后的网络误差模型参数的精度，可以包括：根据反射系数Γ M4和公式
Figure PCTCN2022076085-appb-000010
计算得到探针看向第四负载的反射系数Γ A4。比较反射系数Γ′ A4与反射系数Γ A4。判断反射系数Γ A4与反射系数Γ′ A4之间的误差是否小于预设值，并且当反射系数Γ A4与反射系数Γ′ A4之间的误差小于预设值时，网络误差模型参数符合应用要求。
结合第二方面，一种可能的设计方式是，上述校准装置还可以包括综测仪；综测仪通过射频切换开关连接探针，用于校准射频前端电路的收发功率。上述校准方法还可以包括：配置探针连接综测仪，以校准射频前端电路的收发功率。
基于上述提供的天线阻抗检测的校准方法，该校准方法使用了上述第一方面提供的校准装置，该校准方法的技术效果可以参考上述第一方面提供的校准装置，此处不再赘述。
第三方面，本申请提供一种电子设备。该电子设备包括一个或多个处理器、一个或多个存储器以及通信接口。其中，一个或多个存储器和通信接口与一个或多个处理器耦合，通信接口用于与其他通信设备进行无线通信，一个或多个存储器用于存储计算机程序代码，计算机程序代码包括计算机指令，当一个或多个处理器执行计算机指令时，电子设备执行如第二方面及其任一种可能的设计方式的方法。
第四方面，本申请提供一种芯片系统，该芯片系统应用于包括存储器的电子设备。该芯片系统包括一个或多个接口电路和一个或多个处理器。该接口电路和处理器通过线路互联。该接口电路用于从存储器接收信号，并向处理器发送信号，该信号包括存储器中存储的计算机指令。当处理器执行计算机指令时，电子设备执行如第二方面及其任一种可能的设计方式的方法。
第五方面，本申请实施例提供一种计算机可读存储介质，包括计算机指令，当计算机指令在电子设备上运行时，使得电子设备执行如第二方面及其任一种可能的设计方式的方法。
第六方面，本申请实施例提供一种计算机程序产品，当该计算机程序产品在计算机上运行时，使得计算机执行如第二方面及其任一种可能的设计方式的方法。
可以理解地，上述提供的第三方面所述的电子设备，第四方面所述的芯片系统，第五方面所述的计算机可读存储介质，第六方面所述的计算机程序产品所能达到的有益效果，可参考如第二方面及其任一种可能的设计方式中的有益效果，此处不再赘述。
附图说明
图1为本申请实施例提供的一种电子设备的结构示意图；
图2为本申请实施例提供的一种射频前端电路的结构示意图；
图3为未经过阻抗校准时，不同的终端设备在不同的天线阻抗幅度和相位时的阻抗波动情况图；
图4为图3中的阻抗波动用矢量距离表示的示意图；
图5为本申请实施例提供的一种用于天线阻抗检测的校准装置与测试PCB的连接示意图；
图6为本申请实施例提供的校准电路的结构示意图一；
图7为本申请实施例提供的校准电路的结构示意图二；
图8为图7中的校准电路的一种具体结构示意图；
图9为图8中校准电路中负载的反射系数，在史密斯圆图上的分布情况示意图；
图10为本申请实施例提供的一种用于天线阻抗检测的校准方法的流程图；
图11为本申请实施例提供的校准电路的结构示意图三；
图12为图11中的校准电路的一种具体结构示意图；
图13为图12中校准电路中负载的反射系数，在史密斯圆图上的分布情况示意图；
图14为经过阻抗校准后，不同的终端设备在不同的天线阻抗幅度和相位时的阻抗波动情况图；
图15为图14中的阻抗波动用矢量距离表示的示意图；
图16为本申请实施例提供的另一种用于天线阻抗检测的校准装置与测试PCB的连接示意图；
图17为本申请实施例提供的校准电路的结构示意图四；
图18为本申请实施例提供的校准电路的结构示意图五；
图19为本申请实施例提供的校准电路的结构示意图六。
具体实施方式
本申请中，“至少一个”是指一个或者多个，“多个”是指两个或两个以上。“和/或”，描述关联对象的关联关系，表示可以存在三种关系，例如，A和/或B，可以表示：单独存在A，同时存在A和B，单独存在B的情况，其中A，B可以是单数或者复数。“以下至少一项(个)”或其类似表达，是指的这些项中的任意组合，包括单项(个)或复数项(个)的任意组合。例如，a，b或c中的至少一项(个)，可以表示：a，b，c，a-b，a-c，b-c或a-b-c，其中a、b和c可以是单个，也可以是多个。字符“/”一般表示前后关联对象是一种“或”的关系。另外，在本申请的实施例中，“第一”、“第二”等字样并不对数量和执行次序进行限定。
需要说明的是，本申请中，“示例性的”或者“例如”等词用于表示作例子、例证或说明。本申请中被描述为“示例性的”或者“例如”的任何实施例或设计方案不应被解释为比其他实施例或设计方案更优选或更具优势。确切而言，使用“示例性的”或者“例如”等词旨在以具体方式呈现相关概念。
在本申请中，除非另有明确的规定和限定，术语“连接”应做广义理解，例如，“连接”可以是固定连接，也可以是可拆卸连接，或成一体；可以是直接相连，也可以通过中间媒介间接相连。此外，术语“电连接”可以是直接的电性连接，也可以是通过中间媒介间接的电性连接。
图1为本申请实施例提供的一种电子设备的结构示意图。该电子设备可以是本申请实施例中的终端设备，也可以是基站。如图1所示，该电子设备可包括应用子系 统，内存(memory)，大容量存储器(massive storge)，基带子系统，射频集成电路(radio frequency intergreted circuit，RFIC)，射频前端(radio frequency front end，RFFE)器件，以及天线(antenna，ANT)，这些器件可以通过各种互联总线或其他电连接方式耦合。
图1中，ANT_1表示第一天线，ANT_N表示第N天线，N为大于1的正整数。Tx表示发射路径，Rx表示接收路径，不同的数字表示不同的路径。FBRx表示反馈接收路径，PRx表示主接收路径，DRx表示分集接收路径。HB表示高频，LB表示低频，两者是指频率的相对高低。BB表示基带。应理解，图1中的标记和组件仅为示意目的，仅作为一种可能的实现方式，本申请实施例还包括其他的实现方式。
其中，应用子系统可作为电子设备的主控制系统或主计算系统，用于运行主操作系统和应用程序，管理整个电子设备的软硬件资源，并可为用户提供用户操作界面。应用子系统可包括一个或多个处理核心。此外，应用子系统中也可包括与其他子系统(例如基带子系统)相关的驱动软件。基带子系统也可包括以及一个或多个处理核心，以及硬件加速器(hardware accelerator，HAC)和缓存等。
图1中，RFFE器件，RFIC 1(以及可选的RFIC 2)可以共同组成射频子系统。射频子系统可以进一步分为射频接收通道(RF receive path)和射频发射通道(RF transmit path)。射频接收通道可通过天线接收射频信号，对该射频信号进行处理(如放大、滤波和下变频)以得到基带信号，并传递给基带子系统。射频发射通道可接收来自基带子系统的基带信号，对基带信号进行射频处理(如上变频、放大和滤波)以得到射频信号，并最终通过天线将该射频信号辐射到空间中。具体地，射频子系统可包括天线开关，天线调谐器，低噪声放大器(low noise amplifier，LNA)，功率放大器(power amplifier，PA)，混频器(mixer)，本地振荡器(local oscillator，LO)、滤波器(filter)等电子器件，这些电子器件可以根据需要集成到一个或多个芯片中。天线有时也可以认为是射频子系统的一部分。
基带子系统可以从基带信号中提取有用的信息或数据比特，或者将信息或数据比特转换为待发射的基带信号。这些信息或数据比特可以是表示语音、文本、视频等用户数据或控制信息的数据。例如，基带子系统可以实现诸如调制和解调，编码和解码等信号处理操作。对于不同的无线接入技术，例如5G NR和4G LTE，往往具有不完全相同的基带信号处理操作。因此，为了支持多种移动通信模式的融合，基带子系统可同时包括多个处理核心，或者多个HAC。
此外，由于射频信号是模拟信号，基带子系统处理的信号主要是数字信号，电子设备中还需要有模数转换器件。模数转换器件包括将模拟信号转换为数字信号的模数转换器(analog to digital converter，ADC)，以及将数字信号转换为模拟信号的数模转换器(digital to analog converter，DAC)。本申请实施例中，模数转换器件可以设置在基带子系统中，也可以设置在射频子系统中。
应理解，本申请实施例中，处理核心可表示处理器，该处理器可以是通用处理器，也可以是为特定领域设计的处理器。例如，该处理器可以是中央处理单元(center processing unit，CPU)，也可以是数字信号处理器(digital signal processor，DSP)。该处理器也可以是微控制器(micro control unit，MCU)，图形 处理器(graphics processing unit，GPU)、图像信号处理器(image signal processing，ISP)，音频信号处理器(audio signal processor，ASP)，以及为人工智能(artificial intelligence，AI)应用专门设计的处理器。AI处理器包括但不限于神经网络处理器(neural network processing unit，NPU)，张量处理器(tensor processing unit，TPU)以及被称为AI引擎的处理器。
硬件加速器可用于实现一些处理开销较大的子功能，如数据包(data packet)的组装和解析，数据包的加解密等。这些子功能采用通用功能的处理器也可以实现，但是因为性能或成本的考量，采用硬件加速器可能更加合适。因此，硬件加速器的种类和数目可以基于需求来具体选择。在具体的实现方式中，可以使用现场可编程门阵列(field programmable gate array，FPGA)和专用集成电路(application specified intergated circuit，ASIC)中的一种或组合来实现。当然，硬件加速器中也可以使用一个或多个处理核心。
存储器可分为易失性存储器(volatile memory)和非易失性存储器(non-volatile memory，NVM)。易失性存储器是指当电源供应中断后，内部存放的数据便会丢失的存储器。目前，易失性存储器主要是随机存取存储器(random access memory，RAM)，包括静态随机存取存储器(static RAM，SRAM)和动态随机存取存储器(dynamic RAM，DRAM)。非易失性存储器是指即使电源供应中断，内部存放的数据也不会因此丢失的存储器。常见的非易失性存储器包括只读存储器(read only memory，ROM)、光盘、磁盘以及基于闪存(flash memory)技术的各种存储器等。通常来说，内存可以选用易失性存储器，大容量存储器可以选用非易失性存储器，例如磁盘或闪存。
本申请实施例中，基带子系统和射频子系统共同组成通信子系统，为电子设备提供无线通信功能。通常，基带子系统负责管理通信子系统的软硬件资源，并且可以配置射频子系统的工作参数。基带子系统的一个或多个处理核心可以集成为一个或多个芯片，该芯片可称为基带处理芯片或基带芯片。类似地，RFIC可以被称为射频处理芯片或射频芯片。此外，随着技术的演进，通信子系统中射频子系统和基带子系统的功能划分也可以有所调整。例如，将部分射频子系统的功能集成到基带子系统中，或者将部分基带子系统的功能集成到射频子系统中。在实际应用中，基于应用场景的需要，电子设备可采用不同数目和不同类型的处理核心的组合。
本申请实施例中，射频子系统可包括独立的天线，独立的射频前端(RF front end，RFFE)器件，以及独立的射频芯片。射频芯片有时也被称为接收机(receiver)、发射机(transmitter)或收发机(transceiver)。天线、射频前端器件和射频处理芯片都可以单独制造和销售。当然，射频子系统也可以基于功耗和性能的需求，采用不同的器件或者不同的集成方式。例如，将属于射频前端的部分器件集成在射频芯片中，甚至将天线和射频前端器件都集成射频芯片中，该射频芯片也可以称为射频天线模组或天线模组。
本申请实施例中，基带子系统可以作为独立的芯片，该芯片可被称调制解调器(modem)芯片。基带子系统的硬件组件可以按照modem芯片为单位来制造和销售。modem芯片有时也被称为基带芯片或基带处理器。此外，基带子系统也可以进 一步集成在SoC芯片中，以SoC芯片为单位来制造和销售。基带子系统的软件组件可以在芯片出厂前内置在芯片的硬件组件中，也可以在芯片出厂后从其他非易失性存储器中导入到芯片的硬件组件中，或者还可以通过网络以在线方式下载和更新这些软件组件。
图2为本申请实施例提供的射频前端电路的结构示意图。如图2所示，射频前端电路连接收发机。收发机可以包括射频处理芯片，也可以包括基带处理芯片，用于对发射的信号和接收的信息进行处理。射频前端电路包括功率放大器(power amplifier，PA)、低噪声放大器(low noise amplifier，LNA)、双工器以及用于连接主集天线的主射频座。其中，射频前端电路可以分为射频发射通路和射频接收通路。在射频发射通路中，收发机通过功率放大器PA连接双工器；在射频接收通路中，收发机通过低噪声放大器连接双工器；并且，上述双工器连接主射频座，以使射频前端电路与天线实现连接。双工器用于对发射信号和接收信号进行隔离，保证收发机连接的射频发射通道和射频接收通道能够同时正常工作。
此外，如图2所示，在主射频座与双工器之间，还设置有频段选择开关，用于控制射频前端电路的工作频段。为了提高信号的接收增益，在射频前端电路中还包括用于连接分集天线的分射频座，分射频座用于连接分集电路，对分集天线接收的信号进行处理。分集天线接收的信号经过处理后，可以与主集天线接收的信号进行合并处理，从而提高接收信号的分集增益。为使主集天线可以作为分集天线使用，而分集天线也可以作为主集天线使用，如图2所示，主射频座和分射频座可以通过一个双刀双掷(double pole double throw，DPDT)切换开关分别连接双工器和分集电路。应理解，主射频座和分射频座可以统称为射频座。
通常情况下，为了使终端设备的天线能够支持闭环调谐，射频前端电路需要支持阻抗检测的功能，以便实现阻抗匹配。因此，为实现射频前端器件的阻抗检测，收发机具有阻抗检测功能，并且收发机包括阻抗检测接口，该阻抗检测接口上连接有阻抗检测通路，用于测量收发机看向阻抗检测通路的反射系数。示例性地，阻抗检测通路可以包括双向耦合器和检测切换开关(即前向和反向切换开关)。收发机通过阻抗检测通路进行阻抗检测时，通过阻抗检测通路上的双向耦合器以及前向和反向切换开关，可以检测到射频发射信号的前向功率信号和反向功率信号。其中，前向功率信号表示射频信号向天线传输的信号，反向功率信号表示从天线反射回来的信号。检测到的前向功率信号和反向功率信号，经过的阻抗检测通路变频后，分别与对应的射频发射信号进行相关算法处理，经过收发机的处理后便可以得到收发机看向阻抗检测通路的反射系数。
在终端设备中，天线连接在射频芯片中的射频座(如主射频座)上。当对终端设备的天线进行调谐时，需要检测到从射频座看向天线的阻抗。当天线连接射频座时，在射频芯片中，可以通过阻抗检测通路检测到收发机看向天线的反射系数，也即收发机看向阻抗检测通路的反射系数，可以记为反射系数Γ M。根据反射系数Γ M可以计算得到从射频座看向天线的反射系数Γ A。反射系数Γ A和反射系数Γ M具有如下公式(一)所示的关系：
Figure PCTCN2022076085-appb-000011
其中，a、b和c为收发机到射频座的网络误差模型参数。
由于从射频座看向天线的阻抗Z in与从射频座看向天线的反射系数Γ A具有对应关系，通过从射频座看向天线的反射系数Γ A，可以换算得出从射频座看向天线的阻抗Z in。具体地，当计算得到从射频座看向天线的反射系数Γ A后，可以根据如下公式(二)，计算得出从射频座看向天线的阻抗Z in。
从射频座看向天线的阻抗Z in与从射频座看向天线的反射系数Γ A之间的关系为：
Figure PCTCN2022076085-appb-000012
其中，Z 0为天线的特征阻抗，一般为50欧姆(Ohm)。
需要说明的是，由于射频前端电路中的射频器件，如检测切换开关、双向耦合器和收发机，以及PCB走线加工带来的射频性能差异，可能会造成不同的终端设备之间检测的天线阻抗(即从射频座看向天线的阻抗)的波动。如图3所示，为未经过阻抗校准时，不同的终端设备在不同的天线阻抗幅度和相位时的阻抗波动情况。在图3中，图中的小黑点(●)为天线阻抗幅度分为为0.2、0.4、0.6、0.8，天线阻抗相位为0、45、90、135、180、225、270和315时终端设备的理想的天线阻抗值，小黑点周围的圆圈(○)为不同的终端设备实际测量得到的天线阻抗。具体地，图3中的A点为天线阻抗幅度为0.2，天线阻抗相位为45的天线阻抗值；B点为天线阻抗幅度为0.4，天线阻抗相位为45的天线阻抗值；C点为天线阻抗幅度为0.6，天线阻抗相位为45的天线阻抗值；D点为天线阻抗幅度为0.8，天线阻抗相位为45的天线阻抗值；E点为天线阻抗幅度为0.4，天线阻抗相位为135的天线阻抗值。从图3中，对比小黑点(●)与小黑点周围的圆圈(○)，可以看出不同的终端设备实际测量得到的天线阻抗具有较大的波动。
如图4所示，为图3中的阻抗波动用矢量距离表示的示意图。其中，图4的横坐标为测量到的终端设备的天线阻抗的样本数量，图2的纵坐标为矢量距离(distance)。矢量距离是指在图2所示的史密斯圆图上，不同的终端设备之间因为容差导致的偏移位置与理想位置的矢量距离，且距离可以通过如下公式(三)计算：
Figure PCTCN2022076085-appb-000013
其中，P1为终端设备的理想的天线阻抗值，P2为实际测量得到的天线阻抗值；P1 real是指P1阻抗的电阻值；P2 real是指P2阻抗的电阻值；P1 imag是指P1阻抗的电抗值；P2 imag是指P2阻抗的电抗值。
根据图4可知，不同的终端设备实际测量得到的天线阻抗具有较大的波动，最大的波动距离约为0.18。
为减小不同的终端设备之间检测的天线阻抗的波动，需要对进行天线阻抗检测的校准，本申请实施例提供一种用于天线阻抗检测的校准装置以及校准方法，用于对终端设备的天线阻抗检测进行校准。
在终端设备中，射频前端电路一般设置在终端设备的PCB板上，在本申请实施例中，将包括射频前端电路的PCB板称之为测试PCB。为了对测试PCB进行测试，图5为本申请实施例提供的一种用于天线阻抗检测的校准装置与测试PCB的连接示意图。
如图5所示，测试PCB包括收发机、射频前端电路和阻抗检测通路。其中，射频前端电路可以包括如图2所示的包含功率放大器和双工器的射频发射通道电路，还可以包括如图2所示的包含低噪声放大器和双工器的射频接收通道电路。收发机连接射频前端电路，射频前端电路通过主射频座连接天线，使得收发机通过天线发射射频信号和接收射频信号。收发机具有阻抗检测功能，并且通过阻抗检测端口与阻抗检测通路连接，通过收发机的阻抗检测功能可以测量收发机看向阻抗检测通路的反射系数。
如图5所示，校准装置包括夹具PCB，以及设置在夹具PCB板上的校准电路和探针。校准电路连接探针，探针用于连接矢量网络分析仪。探针还可以用于连接测试PCB上的射频座，使得校准电路与射频前端电路连接形成信号通路。当探针在连接矢量网络分析仪时，可以用于测量探针看向校准电路的第一反射系数。当探针在连接测试PCB上的射频座时，可以用于测量收发机看向校准电路的第二反射系数，以根据第一反射系数和第二反射系数，计算收发机到射频座的网络误差模型参数，从而完成天线阻抗检测的校准。
可以理解地，在对测试PCB板进行阻抗检测校准时，如图5所示，可以将夹具PCB上的探针与测试PCB上的主射频座相扣合，以使探针与主射频座相连。此时，通过阻抗检测通路，可以检测到收发机看向阻抗检测通路的反射系数，作为反射系数Γ M。此外，当夹具PCB上的探针与矢量网络分析仪连接时，可以测量得到探针看向校准电路的反射系数。由于当探针与射频座(如主射频座)时，探针和射频座可以看做同一位置，因此当夹具PCB上的探针与矢量网络分析仪连接时，测量得到的探针看向校准电路的第一反射系数可以作为上述公式(一)中的反射系数Γ A。如此，在同一频率下，测量多组探针到校准电路的反射系数Γ A，以及多组收发机看向阻抗检测通路的第二反射系数Γ M，便可以依据公式(一)计算出收发机到射频座的网络误差模型参数a、b和c。将计算得出的网络误差模型参数a、b和c，作为校准后的网络误差模型参数。
当终端设备中的测试PCB连接天线后，需要对天线进行调谐时，可以通过测试PCB上阻抗检测通路，检测出收发机看向天线的反射系数Γ M，然后再结合公式(一)和校准后的网络误差模型参数a、b和c，计算得到从射频座到天线的反射系数Γ A，从而实现天线阻抗的精确检测。
为了计算公式(一)中的参数a、b和c，需要至少三组反射系数Γ A和反射系数Γ M，因此，如图6所示，校准电路可以包括射频切换开关、第一负载、第二负载和第三负载；并且第一负载、第二负载和第三负载通过射频切换开关与探针相连，使探针连接第一负载、第二负载和第三负载中的任意一个。例如，射频切换开关可以是单刀三掷(single pole three throw，SP3T)切换开关。当射频切换开关切换到第一负载时，探针与第一负载相连；此时，可测量探针连接第一负载时的反射系数Γ A和反射系数Γ M。当射频切换开关切换到第二负载时，探针与第二负载相连；此时，可测量探针连接第二负载时的反射系数Γ A和反射系数Γ M。当射频切换开关切换到第三负载时，探针与第三负载相连；此时，可测量探针连接第二负载时的反射系数Γ A和反射系数Γ M。然后，可以根据获取的三组反射系数Γ A和反射系数Γ M，计算得到网络误差 模型参数a、b和c。
需要说明的是，通常情况下，为提高接收信号的增益，保证信号接收的质量，如图2所示的射频前端电路中可以设置两个射频座，分别为主射频座和分射频座，主射频座用于连接主集天线，分射频座用于连接分集天线。通过主射频座连接主集天线的通路为主集通路，通过分射频座连接分集天线的通路为分集通路。因此，对应于图5中的测试PCB，该测试PCB上设置有两个射频座，分别为主射频座和分射频座。在测试PCB上，射频前端电路通过主射频座连接主集天线，分集电路通过分射频座连接分集天线。
为适用于具有两个射频座的测试PCB的情况，如图5所示，在夹具PCB上设置有两个探针，分别为主集探针和分集探针。其中，主集探针可以与主射频座相扣合，实现信号连接。分集探针可以与分射频座相扣合，实现信号连接。
当夹具PCB上设置两个探针时，对于校准电路，如图7所示，射频切换开关需同时连接主集探针和分集探针。此时，射频切换开关可以为双刀三掷(double pole three throw，DP3T)切换开关。通过射频切换开关可以配置主集探针分别连接第一负载、第二负载和第三负载；还可以配置分集探针分别连接第一负载、第二负载和第三负载。
需要说明的是，对于图6和图7所示的校准电路，校准电路中第一负载、第二负载和第三负载的阻抗可以设计为在开路、短路以及50欧姆(Ohm)三个标准阻抗，也可以是其他任意阻抗。为了保证第一负载、第二负载和第三负载的阻抗点具有更加均匀的精度，第一负载、第二负载和第三负载的阻抗位置可以在史密斯圆图上呈三角分布。
示例性地，如图8为一种校准电路的结构示例，在图8所示的校准电路包括射频切换开关采用双刀三掷(double pole three throw，DP3T)切换开关，使得主集探针可以分别连接第一负载、第二负载和第三负载，并且分集探针也可以分别连接第一负载、第二负载和第三负载。其中，第一负载采用65欧姆(Ohm)的电阻，第二负载采用1Ohm的电阻，第三负载采用15Ohm的电阻和2.4纳亨(nH)的电感串联而成。如图8所示，第一负载和第三负载上还连接有用于阻抗旋转的PCB走线(MLIN)，可以用于将第一负载和第三负载的阻抗旋转到所需的位置。如图9所示为图8所示的校准电路中的第一负载、第二负载和第三负载的反射系数。请参考图9，第一负载、第二负载和第三负载的阻抗位置在史密斯圆图上呈三角分布，并且其频率覆盖范围在1.7吉赫兹(GHz)到2.7GHz。
下面以主集探针连接主射频座为例，对应用上述图5所示的校准装置执行的校准方法进行说明。
图10为本申请实施例提供的一种用于天线阻抗检测的校准方法。该校准方法应用于图5所示的校准装置。请参考图10，该校准方法包括：
S1001，将探针连接矢量网络分析仪，测量探针看向校准电路的第一反射系数。
测量时，可以将校准电路中的射频切换开关配置到第一负载上，使第一负载与主集探针之间形成通路，然后通过矢量网络分析仪测量得到主集探针看向第一负载的第一反射系数，记为反射系数Γ A1。
相应地，可以将校准电路中的射频切换开关配置到第二负载上，使第二负载与主集探针之间形成通路，然后通过矢量网络分析仪测量得到主集探针看向第二负载的第一反射系数，记为反射系数Γ A2。
接着，还可以将校准电路中的射频切换开关配置到第三负载上，使第三负载与主集探针之间形成通路，然后通过矢量网络分析仪测量得到主集探针看向第三负载的第一反射系数，记为反射系数Γ A3。
S1002，将探针连接射频座，通过阻抗检测通路测量收发机看向校准电路的第二反射系数。
此步骤中，可以将图5所示的夹具PCB与测试PCB相扣合，也即夹具PCB上的主集探针与测试PCB上的主射频座对应扣合，使得主集探针与射频前端电路的主射频座相连，并且形成信号通路。
完成夹具PCB与测试PCB的扣合之后，可以将校准电路中的射频切换开关分别配置到第一负载、第二负载和第三负载上，并且通过阻抗检测通路可以测量得到第二反射系数。
具体地，可以将校准电路中的射频切换开关配置到第一负载上，使第一负载与主集探针之间形成通路，从而使第一负载与射频前端电路之间形成通路。通过测试PCB上的阻抗检测通路，可以测量得到收发机看向第一负载的第二反射系数，记为反射系数Γ M1。
相应地，可以将校准电路中的射频切换开关配置到第二负载上，使第二负载与主集探针之间形成通路，从而使第二负载与射频前端电路之间形成通路。通过测试PCB上的阻抗检测通路，可以测量得到收发机看向第二负载的第二反射系数，记为反射系数Γ M2。
接着，可以将校准电路中的射频切换开关配置到第三负载上，使第三负载与主集探针之间形成通路，从而使第三负载与射频前端电路之间形成通路。通过测试PCB上的阻抗检测通路，可以测量得到收发机看向第三负载的第二反射系数，记为反射系数Γ M3。
S1003，根据第一反射系数和第二反射系数，计算收发机到射频座的网络误差模型参数。
在测试PCB板中，根据上述公式(一)可知，从主射频座看向天线的反射系数Γ A，与收发机看向天线的反射系数Γ M的关系。由于在对测试PCB板校准时，测试PCB上的射频座与夹具PCB上的探针相连，因此在S1001步骤中测量得到的第一反射系数，则相当于公式(一)中的反射系数Γ A；在S1002步骤中测量得到的第二反射系数，则相当于公式(一)中的反射系数Γ M。
当校准电路中的射频切换开关配置到第一负载时，依据上述公式(一)，根据所述反射系数Γ A1和反射系数Γ M1，确定所述第一反射系数和所述第二反射系数满足关系：
Figure PCTCN2022076085-appb-000014
当校准电路中的射频切换开关配置到第二负载时，依据上述公式(一)，根据所述反射系数Γ A2和反射系数Γ M2，确定所述第一反射系数和所述第二反射系数满足关 系：
Figure PCTCN2022076085-appb-000015
当校准电路中的射频切换开关配置到第三负载时，依据上述公式(一)，根据所述反射系数Γ A3和反射系数Γ M3，确定所述第一反射系数和所述第二反射系数满足关系：
Figure PCTCN2022076085-appb-000016
根据公式(四)、公式(五)和公式(六)，可以计算得到收发机到射频座的网络误差模型参数a、b和c。
当计算得到参数a、b和c后，可以将参数a、b和c保存在终端设备中，用于终端设备在对天线调谐时，计算射频座看向天线的反射系数。
具体地，当射频座连接天线时，通过阻抗检测通路测量收发机看向天线的第三反射系数Γ M。根据上述公式(一)，通过网络误差模型参数和第三反射系数Γ M，可以计算得出射频座看向天线的第四反射系数Γ A。然后，再根据上述公式(二)以及射频座看向天线的第四反射系数Γ A，便可以获得射频座看向天线的阻抗Z in。
可以理解地，通过上述S1001、S1002和S1003步骤执行在同一频率状态下，调整射频前端电路的频率，重复执行上述S1001、S1002和S1003步骤可以得到多个频点的校准参数，用于不同频率状态下，天线阻抗的计算。
一些实施例中，如图11所示，上述校准电路还可以包括第四负载，第四负载可以通过射频切换开关与主集探针连接。当射频切换开关切换到第四负载时，第四负载连接主集探针。当测试PCB板通过校准电路中的第一负载、第二负载和第三负载完成校准后，通过第四负载可以验证校准后的收发机到射频座的网络误差模型参数的精度。
示例性地，如图12所示为另一种校准电路的结构示例，图12所示的校准电路在图8所示的校准电路的基础上增加了第四负载。其中第四负载采用15Ohm的电阻，并且在第四负载上设计了短路枝节。在图12中，射频切换开关采用双刀四掷(double pole four throw，DP4T)切换开关，使得主集探针可以分别连接第一负载、第二负载、第三负载和第四负载，并且分集探针也可以分别连接第一负载、第二负载、第三负载和第四负载。
如图13所示为图12所示的校准电路中的第一负载、第二负载、第三负载和第四负载的反射系数。请参考图13，第一负载、第二负载和第三负载的阻抗位置在史密斯圆图上呈三角分布，并且其频率覆盖范围在1.7吉赫兹(GHz)到2.7GHz。第四负载可以用于验证校准后的收发机到射频座的网络误差模型参数的精度。
此时，若校准电路中设置有第四负载，通过第四负载，验证校准后的网络误差模型参数，可以包括如下步骤：
将探针连接矢量网络分析仪，并配置主集探针连接第四负载，即可以将校准电路中的射频切换开关配置到第四负载上，使第四负载与主集探针之间形成通路，然后通过矢量网络分析仪测量得到主集探针看向第四负载的第一反射系数，记为反射系数Γ′ A4。
将探针连接射频座，并配置主集探针连接第四负载，即可以将校准电路中的射频 切换开关配置到第四负载上，使第四负载与主集探针之间形成通路，从而使第四负载与射频前端电路之间形成通路，通过测试PCB上的阻抗检测通路，可以测量得到收发机看向第四负载的第二反射系数，记为反射系数Γ M4。
根据反射系数Γ′ A4和反射系数Γ M4，可以验证校准后的所述网络误差模型参数的精度。具体地：
依据上述公式(一)，根据所述反射系数Γ A4和反射系数Γ M4，确定所述第一反射系数和所述第二反射系数满足关系：
Figure PCTCN2022076085-appb-000017
根据上述测量得到的反射系数Γ M4以及公式(七)，可以计算得到反射系数Γ A4。比较上述测量得到的反射系数Γ′ A4和计算得到的反射系数Γ A4，判断反射系数Γ A4与反射系数Γ′ A4之间的误差是否满足预设值，可以验证校准后的网络误差模型参数a、b和c是否符合应用要求。例如，预设值可以为0.1，若测量得到的反射系数Γ′ A4和计算得到的反射系数Γ A4之间的误差范围小于0.1，则校准后的参数a、b和c符合应用要求。此时，出现误差的原因在于探针和射频座接触时的阻抗(或反射系数)波动。
通过上述装置和上述方法执行校准后，不同的终端设备的天线阻抗波动情况如图14所示，在图14中，图中的阴影部分分别为天线阻抗幅度分为为0.2、0.4、0.6、0.8，天线阻抗相位为0、45、90、135、180、225、270和315时终端设备的天线阻抗波动情况。与图3中的天线阻抗波动情况对比，图14中的不同终端设备实际测量得到的天线阻抗值的波动明显降低。
如图15所示，为图14中的阻抗波动用矢量距离表示的示意图。其中，图15的横坐标为测量到的终端设备的天线阻抗的样本数量，图15的纵坐标为距离(distance)。根据图15可知，不同的终端设备实际测量得到的天线阻抗值对应的最大的波动距离约为0.08。对比与图4的最大的波动距离0.18，具有明显降低。
一些实施例中，当需要对分射频座上的分集通路进行校准时，可以将分集探针和分射频座相互扣合，实现连接，并且配置分集探针分别连接第一负载、第二负载和第三负载，配置分射频座连接射频前端电路、收发机以及阻抗检测通路，实现分射频座上天线阻抗检测的校准，便于后续分集天线的阻抗检测。对分射频座上天线阻抗检测的校准的具体校准方法，与主集探针连接主射频座时的方法相似，此处不再赘述。
综上所述，应用图5所示的校准装置和图10所述的校准方法，可以使用一套校准装置，校准不同的终端设备，更加节约成本。此外在校准方法中，可以通过矢量网络分析仪得到校准电路中各负载的阻抗(反射系数)，完成校准后，可以大幅提高阻抗检测的精度，也即不同终端设备的天线阻抗的波动减小。
一些实施例中，上述图5所示的校准装置还可以包括综测仪，综测仪可以用来校准测试PCB板上射频前端电路的收发功率，如图16所示。此时，综测仪可以通过射频切换开关连接探针。当需要实现射频收发功率的校准时，可以将夹具PCB上的射频切换开关切换到与综测仪相连的通路。
示例性地，当校准装置包括综测仪时，对于校准电路，可以设置为如图17、图18和图19所示的校准电路。在图17中，与图6所示的校准电路相比，图17所示的校准电路中的射频切换开关，采用单刀四掷(single pole four throw，SP4T)切换开 关，使校准电路可以配置为探针连接综测仪。在图18中，与图7所示的校准电路相比，图18所示的校准电路中的射频切换开关，采用双刀四掷(double pole four throw，DP4T)切换开关，使校准电路可以配置为探针连接综测仪。在图19中，与图11所示的校准电路相比，图19所示的校准电路中的射频切换开关，采用单刀四掷切换开关，并且还增加了一个双刀双掷切换开关，可以使校准电路配置为主集探针连接综测仪或射频切换开关，还可以使校准电路配置为分集探针连接综测仪或射频切换开关。
通过上述图17、图18和图19所示的校准电路，可以通过综测仪对射频前端电路进行射频收发功率的校准，从而使得图16所示的校准装置既能够对射频前端电路的阻抗进行校准，也能够对射频收发功率进行校准，从而提高终端设备中射频前端电路的校准效率，更加节约成本。
可以理解地，上述图10所示的方法中，可以由另一电子设备控制执行，如可以通过计算机控制执行。在执行校准方法时，可以使计算机与综测仪、夹具PCB以及测试PCB进行通信，并通过计算机控制是否进入校准状态，以及是否执行上述方法中的各个步骤，是否储存相应的数据等。
本申请实施例还提供一种芯片系统，该芯片系统可以应用于前述实施例中的电子设备。该芯片系统包括至少一个处理器和至少一个接口电路。该处理器可以是上述电子设备中的处理器。处理器和接口电路可通过线路互联。该处理器可以通过接口电路从上述电子设备的存储器接收并执行计算机指令。当计算机指令被处理器执行时，可使得电子设备执行上述方法实施例中的各个步骤。当然，该芯片系统还可以包含其他分立器件，本申请实施例对此不作具体限定。
本申请实施例还提供一种计算机存储介质，该计算机存储介质包括计算机指令，当所述计算机指令在电子设备上运行时，使得该电子设备执行上述方法实施例中的各个功能或者步骤。
本申请实施例还提供一种计算机程序产品，当所述计算机程序产品在计算机上运行时，使得所述计算机执行上述方法实施例中的各个功能或者步骤。
通过以上的实施方式的描述，所属领域的技术人员可以清楚地了解到，为描述的方便和简洁，仅以上述各功能模块的划分进行举例说明，实际应用中，可以根据需要而将上述功能分配由不同的功能模块完成，即将装置的内部结构划分成不同的功能模块，以完成以上描述的全部或者部分功能。上述描述的系统，装置和单元的具体工作过程，可以参考前述方法实施例中的对应过程，在此不再赘述。
在本申请实施例各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。上述集成的单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
所述集成的单元如果以软件功能单元的形式实现并作为独立的产品销售或使用时，可以存储在一个计算机可读取存储介质中。基于这样的理解，本申请实施例的技术方案本质上或者说对现有技术做出贡献的部分或者该技术方案的全部或部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质中，包括若干指令用以使得一台计算机设备(可以是个人计算机，服务器，或者网络设备等)或处理器 执行本申请各个实施例所述方法的全部或部分步骤。而前述的存储介质包括：快闪存储器、移动硬盘、只读存储器、随机存取存储器、磁碟或者光盘等各种可以存储程序代码的介质。
以上所述，仅为本申请实施例的具体实施方式，但本申请实施例的保护范围并不局限于此，任何在本申请实施例揭露的技术范围内的变化或替换，都应涵盖在本申请实施例的保护范围之内。因此，本申请实施例的保护范围应以所述权利要求的保护范围为准。

Claims (17)

  1. 一种用于天线阻抗检测的校准装置，其特征在于，应用于测试PCB，所述测试PCB包括收发机、射频座、射频前端电路和阻抗检测通路；所述射频座连接所述射频前端电路；所述射频前端电路连接所述收发机，所述收发机包括阻抗检测接口，所述阻抗检测接口连接阻抗检测通路，用于测量收发机看向所述阻抗检测通路的反射系数；
    所述校准装置包括夹具PCB板以及设置在夹具PCB板上的校准电路和探针；
    所述校准电路连接所述探针；所述探针用于连接矢量网络分析仪或所述射频座；所述探针在连接矢量网络分析仪时，用于测量所述探针看向所述校准电路的第一反射系数；所述探针在连接所述射频座时，用于测量所述收发机看向所述校准电路的第二反射系数，以根据第一反射系数和第二反射系数，完成天线阻抗检测的校准。
  2. 根据权利要求1所述的校准装置，其特征在于，所述校准电路包括射频切换开关、第一负载、第二负载和第三负载；
    所述第一负载、所述第二负载和所述第三负载通过射频切换开关与所述探针相连，使所述探针连接所述第一负载、所述第二负载和所述第三负载中的任意一个。
  3. 根据权利要求2所述的校准装置，其特征在于，所述校准电路还包括第四负载；所述第四负载通过所述射频切换开关与所述探针连接，用于验证校准后的所述收发机到所述射频座的网络误差模型参数的精度。
  4. 根据权利要求2或3所述的校准装置，其特征在于，所述校准装置还包括综测仪；所述综测仪通过所述射频切换开关连接所述探针，用于校准所述射频前端电路的收发功率。
  5. 一种用于天线阻抗检测的校准方法，其特征在于，使用权利要求2至4任一项所述的校准装置；
    所述方法包括：
    将所述探针连接所述矢量网络分析仪，测量所述探针看向所述校准电路的第一反射系数；
    将所述探针连接所述射频座，通过所述阻抗检测通路测量所述收发机看向所述校准电路的第二反射系数；
    根据所述第一反射系数和所述第二反射系数，计算所述收发机到所述射频座的网络误差模型参数。
  6. 根据权利要求5所述的方法，其特征在于，所述方法还包括：
    当所述射频座连接天线时，通过所述阻抗检测通路测量所述收发机看向所述天线的第三反射系数Γ M；
    通过所述网络误差模型参数和所述第三反射系数Γ M，计算得出所述射频座看向所述天线的第四反射系数Γ A；
    根据所述第四反射系数Γ A，获得所述射频座看向所述天线的阻抗Z in。
  7. 根据权利要求6所述的方法，其特征在于，所述第三反射系数Γ M、所述网络误差模型参数以及所述第四反射系数第三反射系数Γ M之间的关系为：
    Figure PCTCN2022076085-appb-100001
    其中，参数a、b、c为所述网络误差模型参数。
  8. 根据权利要求6或7所述的方法，其特征在于，所述射频座看向所述天线的阻抗Z in与所述第四反射系数Γ A之间的关系为：
    Figure PCTCN2022076085-appb-100002
    其中，Z 0为所述天线的特征阻抗。
  9. 根据权利要求5至8任一项所述的方法，其特征在于，所述校准电路包括射频切换开关、第一负载、第二负载和第三负载；
    所述第一负载、所述第二负载和所述第三负载通过射频切换开关与所述探针相连，使所述探针连接所述第一负载、所述第二负载和所述第三负载中的任意一个；
    所述将所述探针连接所述矢量网络分析仪，测量所述探针看向所述校准电路的第一反射系数，包括：
    配置所述探针连接所述第一负载，测量所述探针看向所述第一负载的所述第一反射系数，记为反射系数Γ A1；
    配置所述探针连接所述第二负载，测量所述探针看向所述第二负载的所述第一反射系数，记为反射系数Γ A2；
    配置所述探针连接所述第三负载，测量所述探针看向所述第三负载的所述第一反射系数，记为反射系数Γ A3。
  10. 根据权利要求9所述的方法，其特征在于，将所述探针连接所述射频座，通过所述阻抗检测通路测量所述收发机看向所述校准电路的第二反射系数，包括：
    配置所述探针连接所述第一负载，通过所述阻抗检测通路测量所述收发机看向所述第一负载的第二反射系数，记为反射系数Γ M1；
    配置所述探针连接所述第二负载，通过所述阻抗检测通路测量所述收发机看向所述第二负载的第二反射系数，记为反射系数Γ M2；
    配置所述探针连接所述第三负载，通过所述阻抗检测通路测量所述收发机看向所述第二负载的第二反射系数，记为反射系数Γ M3。
  11. 根据权利要求10所述的方法，其特征在于，所述根据所述第一反射系数和所述第二反射系数，计算所述收发机到所述射频座的网络误差模型参数，包括：
    根据所述反射系数Γ A1和反射系数Γ M1，确定所述第一反射系数和所述第二反射系数满足关系：
    Figure PCTCN2022076085-appb-100003
    根据所述反射系数Γ A2和反射系数Γ M2，确定所述第一反射系数和所述第二反射系数满足关系：
    Figure PCTCN2022076085-appb-100004
    根据所述反射系数Γ A2和反射系数Γ M2，确定所述第一反射系数和所述第二反射系数满足关系：
    Figure PCTCN2022076085-appb-100005
    根据式(1)、式(2)和式(3)，计算得到参数a、b和c；其中，所述参数a、b和c为所述收发机到所述射频座的网络误差模型参数。
  12. 根据权利要求5至11任一项所述的方法，其特征在于，所述校准电路还包 括第四负载；所述第四负载通过所述射频切换开关与所述探针连接；
    所述方法还包括：
    通过所述第四负载，验证校准后的所述网络误差模型参数的精度。
  13. 根据权利要求12所述的方法，其特征在于，所述通过所述第四负载，验证校准后的所述网络误差模型参数的精度，包括
    将所述探针连接所述矢量网络分析仪，配置所述探针连接所述第四负载，测量所述探针看向所述第四负载的所述第一反射系数，记为反射系数Γ′ A4；
    将所述探针连接所述射频座，配置所述探针连接所述第四负载，通过所述阻抗检测通路测量所述收发机看向所述第四负载的第二反射系数，记为反射系数Γ M4；
    根据所述反射系数Γ′ A4和所述反射系数Γ M4，验证校准后的所述网络误差模型参数的精度。
  14. 根据权利要求13所述的方法，其特征在于，根据所述反射系数Γ′ A4和所述反射系数Γ M4，验证校准后的所述网络误差模型参数的精度，包括：
    根据所述反射系数Γ M4和公式
    Figure PCTCN2022076085-appb-100006
    计算得到所述探针看向所述第四负载的反射系数Γ A4；
    比较所述反射系数Γ′ A4与所述反射系数Γ A4；
    判断所述反射系数Γ A4与所述反射系数Γ′ A4之间的误差是否小于预设值，并且当所述反射系数Γ A4与所述反射系数Γ′ A4之间的误差小于预设值时，所述网络误差模型参数符合应用要求。
  15. 根据权利要求5至14任一项所述的方法，其特征在于，所述校准装置还包括综测仪；所述综测仪通过所述射频切换开关连接所述探针，用于校准所述射频前端电路的收发功率；
    所述方法还包括：
    配置所述探针连接所述综测仪，以校准所述射频前端电路的收发功率。
  16. 一种电子设备，其特征在于，包括：
    一个或多个处理器；
    存储器；
    通信模块；
    其中，所述存储器中存储有一个或多个计算机程序，所述一个或多个计算机程序包括指令，当所述指令被所述电子设备执行时，使得所述电子设备执行如权利要求5-15中任一项所述的方法。
  17. 一种计算机可读存储介质，所述计算机可读存储介质中存储有指令，其特征在于，当所述指令在电子设备上运行时，使得所述电子设备执行如权利要求5-15中任一项所述的方法。
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