WO2022222015A1 - Boîtier de semi-conducteur - Google Patents

Boîtier de semi-conducteur Download PDF

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Publication number
WO2022222015A1
WO2022222015A1 PCT/CN2021/088255 CN2021088255W WO2022222015A1 WO 2022222015 A1 WO2022222015 A1 WO 2022222015A1 CN 2021088255 W CN2021088255 W CN 2021088255W WO 2022222015 A1 WO2022222015 A1 WO 2022222015A1
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WO
WIPO (PCT)
Prior art keywords
redistribute
vias
layers
semiconductor package
semiconductor chip
Prior art date
Application number
PCT/CN2021/088255
Other languages
English (en)
Inventor
Akio Katsumata
Fei SHE
Qingshan TIAN
Original Assignee
Huawei Technologies Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co., Ltd. filed Critical Huawei Technologies Co., Ltd.
Priority to PCT/CN2021/088255 priority Critical patent/WO2022222015A1/fr
Priority to CN202180093671.5A priority patent/CN116897423A/zh
Publication of WO2022222015A1 publication Critical patent/WO2022222015A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures

Definitions

  • This invention relates to a semiconductor package.
  • Embodiments of the present invention have been made in view of the above circumstances, and provides a semiconductor package capable of efficiently recovering heat generated by a current flowing through a semiconductor chip and suppressing a temperature rise of the semiconductor chip.
  • this application employs the following means.
  • the semiconductor package according to one aspect of the present application comprises:
  • a semiconductor package comprising:
  • a semiconductor chip mounted on the substrate and having a plurality of first conductive regions on a surface of the semiconductor chip opposite to the substrate,
  • a first insulating layer disposed on the first redistribute layers and having an opening to expose at least a part of the first redistribute layer
  • a first heat-dissipating gel is preferably provided between the first redistribute layers.
  • the first heat-dissipating gel having a low thermal resistance is more preferable to use as an adhesive layer because the efficiency of heat release to the heat sink is increased.
  • a first heat-dissipating gel is preferably provided the first insulating layers and the heat sink.
  • the first heat-dissipating gel having a low thermal resistance is more preferable to use as an adhesive layer because the efficiency of heat release to the heat sink is increased.
  • the semiconductor chip has one or more second conductive regions on the surface of the semiconductor chip facing to the substrate.
  • the heat generated in the semiconductor chip can be released to the side of the heat sink as in the first embodiment, and also to the side of the substrate via the second vias and the second redistribute layer. Therefore, since the number of heat conduction paths is increased, the efficiency of heat dissipation is improved, and the temperature rise of the semiconductor chip can be further suppressed.
  • a plurality of first vias comprising at least
  • one of the first redistribute layers connects to the other end of the first group of vias and the other of the first redistribute layers connects to the other end of the second group of vias.
  • the opening to expose at least the part of the first redistribute layer has the maximum connection area with the other end of the first vias among the plurality of first redistribute layers.
  • the semiconductor package comprises one or more second vias connected to the second conductive region by one end of the second vias, and one or more second redistribute layers connected to the other end of the second vias.
  • the heat generated in the semiconductor chip can be released to the side of the heat sink as in the first embodiment, and also to the side of the substrate via the second vias and the second redistribute layer. Therefore, since the number of heat conduction paths is increased, the efficiency of heat dissipation is improved, and the temperature rise of the semiconductor chip can be further suppressed.
  • the semiconductor package comprises a plurality of second conductive regions and a plurality of second redistribute layers, the plurality of the second redistribute layers are separated from each other, one of the second redistribute layers connects to one end of a first group of the second vias formed on and connected to one of the second conductive regions by one end of the first group of the second vias, and the other of the second redistribute layers connects to a second group of the second vias formed on and connected to the other of the second conductive regions by one end of the second group of the second vias, and the semiconductor package comprises a second insulating layer disposed on the second redistribute layers and having an opening to expose at least a part of the second redistribute layer having the maximum connection area with the other end of the second vias among the plurality of second redistribute layers.
  • the heat generated in the semiconductor chip can be released to the side of the heat sink, and also to the side of the substrate via the second vias and the second redistribute layer. Therefore, since the number of heat conduction paths is increased, the efficiency of heat dissipation is improved, and the temperature rise of the semiconductor chip can be further suppressed.
  • the semiconductor package according to one aspect of the present application comprises:
  • a semiconductor chip mounted on the substrate and having a plurality of second conductive regions on a surface of the semiconductor chip facing to the substrate,
  • a second insulating layer disposed on the second redistribute layers and having an opening to expose at least a part of the second redistribute layer
  • the semiconductor package of the present aspect all the heat is released to the side of the heat sink via the interlayer insulating film, so that the efficiency of heat dissipation is lower than that of the above (1) .
  • a configuration such as the semiconductor package is effective.
  • a plurality of second vias comprising at least
  • one of the second redistribute layers connects to the other end of the first group of vias and the other of the second redistribute layers connects to the other end of the second group of vias.
  • the opening to expose at least the part of the second redistribute layer has the maximum connection area with the other end of the second vias among the plurality of second redistribute layers.
  • Figure 1A is a cross-sectional view of a semiconductor package according to the first embodiment of the present application.
  • Figure 1B is an enlarged view of a part of the semiconductor package of Figure 1A;
  • Figure 2A is a diagram showing an arrangement example of conductive regions and vias constituting the semiconductor package of Figure 1A;
  • Figure 2B is a diagram showing another arrangement example of conductive regions and vias constituting the semiconductor package of Figure 1A;
  • Figures 3a and 3b are cross-sectional views of an object to be processed in the process of manufacturing the semiconductor package of Figure 1A;
  • Figures 4a and 4b are cross-sectional views of an object to be processed in the process of manufacturing the semiconductor package of Figure 1A;
  • Figures 5a and 5b are cross-sectional views of an object to be processed in the process of manufacturing the semiconductor package of Figure 1A;
  • Figure 6 is a cross-sectional view of a semiconductor package according to the prior art
  • Figure 7A is a cross-sectional view of a semiconductor package according to a second embodiment of the present application.
  • Figure 7B is an enlarged view of a part of the semiconductor package of Figure 7A;
  • Figure 8A is a cross-sectional view of a semiconductor package according to a third embodiment of the present application.
  • Figure 8B is an enlarged view of a part of the semiconductor package of Figure 8A;
  • Figure 9A is a cross-sectional view of a semiconductor package according to a fourth embodiment of the present application.
  • Figure 9B is an enlarged view of a part of the semiconductor package of Figure 9A.
  • the terms “on” and “below” include the case that still another component is located between the components, in addition to the case that one component is located directly on or directly below another component, unless otherwise specified.
  • Figure 1A is a cross-sectional view schematically showing the configuration of the semiconductor package 100 according to the first embodiment of the present invention.
  • Figure 1B is an enlarged view of a part 100A of the semiconductor package.
  • the semiconductor package 100 mainly comprises a substrate 101, a semiconductor chip 102, a plurality of first vias 103, a plurality of first redistribute layers 104, a first insulating layer 105, and a heat sink 106.
  • the substrate 101 may be a mounting substrate (printed circuit board) on which the semiconductor chip 102 can be mounted on at least one main surface 101a, and has various configurations depending on the application of the semiconductor package 100.
  • the substrate 101 may be a multilayer wiring board that enables high-density wiring.
  • Figure 1A exemplifies a case where the redistribute layers on the two main surfaces 101a and 101b and the first redistribute layers 104 located at the heat sink side are electrically connected via the through wiring 118 penetrating in the thickness direction of the substrate 100, when the element or the like is also mounted on the side of the other main surface 101b of the substrate 100.
  • the semiconductor chip (IC chip) 102 is mounted (integrated) on one main surface 101a of the substrate 100. More specifically, the semiconductor chip (IC chip) 102 is adhered to the redistribute layer 112 formed on one main surface 101a of the substrate 100 via an adhesive layer (Die Attach Paste) 111.
  • the semiconductor chip 102 is provided with functional elements such as transistors and diodes on a base material made of a semiconductor material such as silicon, and a conductive region (electrode) for controlling the operation of each functional element is formed on the surface thereof.
  • the conductive region may be formed on either one of the surface 102a on the substrate 101 side and the surface 102b on the opposite side of the substrate 101, or may be formed on both. In this embodiment, the case where the conductive regions are formed on both the substrate 101 side and the side opposite to the substrate 101 will be illustrated.
  • first conductive region 107 the conductive region formed on the side opposite to the substrate 101
  • second conductive region 108 the conductive region formed on the side facing to substrate 101
  • Conductive impurities opposite to the base material are injected in the first conductive region 107 and the second conductive region 108 at a high concentration.
  • one or more conductive regions that function as gates, sources, and drains are formed in the MOS transistor portion that constitutes the semiconductor chip 102.
  • a first conductive region 107 that functions as a gate and a source is formed on the surface 102b opposite to the substrate 101, and a second conductive region 108 that functions as a drain is formed on the surface 102a of the semiconductor chip facing to the substrate 101 in the case of a MOS transistor for a power module for example, as shown in Figure 1B.
  • One or more first vias 103 are formed on each of the plurality of first conductive regions 107 on the surface of the semiconductor chip 102.
  • the first via 103 is formed of an electrically conductive material such as tungsten or copper, and one end 103a of the first via 103 is adhered to the surface 102a of the semiconductor chip via a barrier layer, an adhesive layer, or the like (not shown) and electrically connected to the first conductive region 107.
  • the side surface of the first via 103 excluding both end faces and the exposed surface of the semiconductor chip 102 are covered with an interlayer insulating film 109 such as BPSG.
  • the first redistribute layer 104 contains an electrically conductive material such as copper or aluminum as a main component, and the first redistribute layer 104A among the plurality of first redistribute layers 104 is connected to a first group of the first vias which shares one of the first conductive region 107A, and the second redistribute layer 104B among the plurality of first redistribute layers 104 is connected to a second group of the first vias which shares the other of the first conductive region 107B. That is, one of the first redistribute layers 104 is connected to one of the first conductive regions 107 via one or more first vias 103.
  • the first redistribute layer 104A connected to the first vias 103A formed on the first conductive region 107A is separated from the first redistribute layer 104B connected to the first vias 103B formed on the first conductive region 107B.
  • Figure 2A is a plan view of the semiconductor chip 102 viewed from the side opposite to the substrate 101, and shows an arrangement example of the two first conductive regions 107A and 107B.
  • the layers above the first redistribute layer 104 are not shown.
  • two first conductive regions 107A and 107B (indicated by broken lines) having different areas are formed.
  • the first conductive region 107A has a larger area than the first conductive region 107B, and a larger number of first vias 103 formed on the first conductive region 107A than the first conductive region 107B.
  • the first redistribute layer 104A connected to the first conductive region 107A via the first group of the first vias 103A has the maximum connection area with the other end 103b of the first group of the first vias among the plurality of first redistribute layers 104A, 104B.
  • the "connection area” here means the total area of the portion of the first redistribute layer 104 that comes into contact with the other end 103b of the first vias and becomes the inlet of the current flowing from the first vias 103. Therefore, the current flowing through the first redistribute layer 104A is the largest among the first redistribute layers 104A and 104B arranged here, and a large amount of heat proportional to the magnitude is generated.
  • Figure 2B is a plan view of an arrangement example of the first conductive regions 107C to 107E in which the semiconductor chip 102 is replaced with a semiconductor chip 102' in which the three first conductive regions 107C, 107D, and 107E are formed, and is viewed from the side opposite to the substrate 101, as in Figure 2A.
  • three first conductive regions 107C, 107D, and 107E having different areas are formed.
  • the first conductive region 107C has a larger area than the first conductive regions 107D and 107E, and the number of first vias 103 formed is the largest.
  • the first redistribute layer 104C connected to the first conductive region 107C via the first group of the first vias 103C has the maximum connection area with the other end 103b of the first group of the first vias 103c among the first three redistribute layers 104. Therefore, the current flowing through the first redistribute layer 104C is the largest among the first redistribute layers 104C, 104D, 104E arranged here, and a large amount of heat proportional to the magnitude is generated. Regarding the comparison of the connection areas, the case where three or more first conductive regions 104 are formed shall be considered in the same manner as the case where two are formed.
  • the first redistribute layer 104 has a spread that covers at least the other end 103b of the first vias and adds a margin 104a ( Figure 2A) specified by the design rule.
  • this spread is as large as the design rule allows.
  • the first insulating layer 105 is formed of an insulating material such as solder resist. Further, the first insulating layer 105 is disposed on the first redistribute layers 104, more specifically, on a portion of the surfaces of the first redistribute layers that is not in contact with the interlayer insulating film 109 to prevent the first redistribute layers 104 connected to different first conductive regions 107 from electrically conducting each other.
  • the first insulating layer 105 has an opening (through hole) 105a to expose at least a part of the first redistribute layer (the first redistribute layer 104A in Figures 1A and 2A, the first redistribute layer 104C in Figure 2B) having the maximum connection area with the other end 103b of the first vias among the plurality of first redistribute layers 104.
  • the "exposed” state here is a state in which it is exposed at least when the opening 105a is formed and is not covered with the first insulating layer 105 or is covered with a layer having a lower thermal resistance than the first insulating layer 105 in the final form.
  • the shape of the opening 105a is not limited, but the larger the opening area, the better, and there may be a plurality of openings 105a.
  • the first insulating layer 105 may not be disposed at all on the first redistribute layer 104 having the maximum connection area with the other end 103b of the first vias.
  • the opening 105a in the present embodiment does not need to be entirely surrounded by the first insulating layer 104, and the a part of the outer circumference of the opening 105a may be open, as in the case where the opening 105a is formed at the end of the first redistribute layer 104.
  • the opening 105a is formed only in the first insulating layer 105 formed in any one of them.
  • the heat sink 106 is made of a material having low thermal resistance such as metal, is arranged so as to cover the first redistribute layer 104 and the first insulating layer 105, and has the function of releasing heat generated from the first redistribute layer 104 to the outside.
  • the shape of the heat sink 106 is not particularly limited.
  • the first heat-dissipating gel 110 is preferably provided between the first insulating layer 105 and the heat sink 106 and/or between the first redistribute layer 104 exposed from the opening 105a of the first insulating layer and the heat sink 106.
  • One made of carbon, aluminum oxide, an organic material or the like can be used as the first heat-dissipating gel 110, for example.
  • Figures 3a, 3b, 4a, 4b, 5a, and 5b are cross-sectional views of the object to be processed in a process for manufacturing the semiconductor package 100.
  • the method for manufacturing the semiconductor package 100 mainly includes the following steps.
  • a substrate 101 on which the semiconductor chip 102 is mounted is prepared.
  • a plurality of third redistribute layers 112 and 116 are formed on both main surfaces 101a and 101b of the substrate 101, respectively.
  • the second insulating layer 113 is formed to cover the second redistribute layer 112 on which the semiconductor chip 102 is mounted and the exposed portion of the second redistribute layer 112 other than the portion connecting the predetermined wiring. Subsequently, the semiconductor chip 102 is adhered to the second redistribute layer 112, which is not covered with the second insulating layer 113, via the adhesive layer (Die Attach Paste) 111. Further, an interlayer insulating film 109 is formed on one main surface 101a of the substrate 101 by using ABF (Ajinomoto Built-up Film) , EMC (Epoxy molding compound) , or the like so that all the exposed portions at this time are covered. The interlayer insulating film 109 may be composed of a single layer or a plurality of layers made of different insulating materials.
  • a through hole is formed in the interlayer insulating film 109 by an etching method or a laser processing method to expose the first conductive region 107 of the semiconductor chip 102.
  • a conductive material such as copper or aluminum is filled in the through hole by using a known film forming method such as a sputtering or copper plating to form the first via 103.
  • the first redistribute layer 104 is formed by using a known film forming method such as sputtering or copper plating.
  • the first redistribute layer 104A is formed on the other end 103b of the first via formed in the first conductive region 107A
  • the first redistribute layer 104B is formed on the other end 103b of the first vias formed in the first conductive region 107B.
  • a solder resist or the like is used to form a first insulating layer 105 that covers the entire exposed surface of the first redistribute layer 104 at this time.
  • an opening (through hole) 105a is formed in the first insulating layer 105 by an etching method or the like so that at least a part of the first redistribute layer 104A is exposed.
  • a through hole connecting the first redistribute layer 104, the second redistribute layer 112, and the third redistribute layer 116 is formed, and electrically conductive materials such as copper and aluminum are filled in the through holes to form the through wiring 118.
  • electrically conductive materials such as copper and aluminum are filled in the through holes to form the through wiring 118.
  • connection method is not limited, and for example, a plurality of vias branching via the second redistribute layer 112 may be used for connection.
  • the semiconductor package 100 of the present embodiment can be obtained by covering at least the first insulating layer 105 and the first redistribute layer 104 exposed from the opening 105a of the first insulating layer with a heat sink 106.
  • the heat sink 106 preferably adheres to the first insulating layer 105 and the first redistribute layer 104 exposed from the opening 105a via an adhesive. It is more preferable to use the first heat-dissipating gel 110 having a low thermal resistance as an adhesive layer because the efficiency of heat release to the heat sink 106 is increased.
  • the first insulating layer 105 disposed on the first redistribute layer 104 has an opening 105a, and the portion of the first redistribute layer 105 exposed from the opening 105a is connected to the heat sink 106 without an insulator having a high thermal resistance. Therefore, since a path having a low thermal resistance is formed between the first redistribute layer 104 and the heat sink 106, the heat generated by the current flowing through the first redistribute layer 104 can be conducted along this path, efficiently collected by the heat sink 106, and discharged to the outside.
  • the first redistribute layer 104 exposed from the opening 105a has the maximum connection area with the other end 103b of the first vias. Therefore, as compared with the case where the other first redistribute layer 104 is exposed, the opening 105a can be formed larger, and thus, the area of the exposed first redistribute layer 104 can be expanded by that amount to conduct more heat toward the heat sink 106. Since the temperature rise of the semiconductor chip 102 can be avoided by the efficient heat dissipation in the first redistribute layer 104, the allowable current value of the semiconductor chip 102 can be increased. As a result, the semiconductor package 100 of the present embodiment can maintain a high allowable current value and can suppress a decrease in power density per unit volume even when it is miniaturized.
  • FIG. 6 is a cross-sectional view schematically showing the configuration of a conventional semiconductor package 500 such as a power module.
  • the semiconductor package 500 mainly comprises a printed circuit board 501, a semiconductor chip 502 mounted on the printed circuit board 501, a lead frame 503 for supporting the semiconductor chip 502 and connecting to the outside, a mold 504 that covers the semiconductor chip 502, and a heat sink 506 mounted on the mold 504.
  • the mold 504 having a low thermal conductivity exists between the semiconductor chip 502 and the heat sink 506, the heat generated from the semiconductor chip 502 does not easily reach the heat sink 506, and efficient cooling of the semiconductor chip 502 is prevented.
  • Figure 7A is a cross-sectional view schematically showing the configuration of the semiconductor package 200 according to the second embodiment of the present invention.
  • Figure 7B is an enlarged view of a part 200A of the semiconductor package.
  • the semiconductor package 200 of the present embodiment is different from the semiconductor package 100 of the first embodiment in that the second vias 119 are provided on the substrate 101 facing to the semiconductor chip 102.
  • One end 119a of the second vias is connected to the second conductive region 108 of the semiconductor chip 102, and the other end 119b of the second vias is connected to the second redistribute layer 112.
  • Other configurations are the same as those of the semiconductor package 100, and the corresponding parts are indicated by the same reference numerals regardless of the difference in shape.
  • the heat generated in the semiconductor chip 102 can be released to the side of the heat sink 106 as in the first embodiment, and also to the side of the substrate 101 via the second vias 119 and the second redistribute layer 112. Therefore, since the number of heat conduction paths is increased, the efficiency of heat dissipation is improved, and the temperature rise of the semiconductor chip 102 can be further suppressed.
  • Figure 8A is a cross-sectional view schematically showing the configuration of the semiconductor package 300 according to the second embodiment of the present invention.
  • Figure 8B is an enlarged view of a part 300A of the semiconductor package.
  • the semiconductor package 300 of the present embodiment there are a plurality of second conductive regions 108 having different areas, and there are also a plurality of corresponding second redistribute layers 112. Therefore, it is necessary to separate the second redistribute layers 112 from each other and electrically insulate them from each other.
  • the second conductive regions 108 and the second redistribute layer 112 have a one-to-one relationship, and one second redistribute layer 112 is connected to one second conductive region 108 via one or more second vias 119.
  • one second redistribute layer 112 is connected to the other end 119b of one or more second vias formed on the common second conductive regions 108.
  • Other configurations are the same as those of the semiconductor package 200, and the corresponding parts are indicated by the same reference numerals regardless of the difference in shape.
  • the efficiency is lower than in the side of the heat sink 106, but more heat can be released as compared with the case where heat is released only to the side of the heat sink 106.
  • Figure 9A is a cross-sectional view schematically showing the configuration of the semiconductor package 400 according to the fourth embodiment of the present invention.
  • Figure 9B is an enlarged view of a part 400A of the semiconductor package.
  • the semiconductor package 400 of the present embodiment is different from the semiconductor package 300 of the third embodiment in that the semiconductor chip 102 does not have a first via on the side opposite to the substrate 101 and has a second via 119 on the side facing the substrate 101.
  • Other configurations are the same as those of the semiconductor package 300, and the corresponding parts are indicated by the same reference numerals regardless of the difference in shape.
  • the semiconductor package 400 of the present embodiment all the heat is released to the side of the heat sink 106 via the interlayer insulating film 109, so that the efficiency of heat dissipation is lower than that of the first embodiment.
  • a configuration such as the semiconductor package 400 is effective.
  • the thermal resistances R jb and R jc generated between the semiconductor chip and the substrate and between the semiconductor chip and the heat sink were simulated.
  • a silicon substrate having a thickness of 100 ⁇ m and having a conductive region on one main surface was used as the semiconductor chip.
  • a semiconductor chip was mounted on the substrate so that the conductive region faces the heat sink.
  • As the first via connected to the conductive region one filled with copper was used.
  • the conductive region was connected to the heat sink via the first via.
  • a copper plate having a thickness of 70 ⁇ m was used as the substrate and the heat sink.
  • the thermal resistance R jb between the semiconductor chip and the substrate was 0.113 °C/W
  • the thermal resistance R jc between the semiconductor chip and the heat sink was 0.1154 °C/W.
  • the thermal resistances R jb and R jc generated between the semiconductor chip and the substrate and between the semiconductor chip and the heat sink were simulated when the conventional semiconductor package was operated.
  • the semiconductor chip, the substrate, and the heat sink those having the same configurations as those in the examples were used.
  • a semiconductor chip was mounted on the substrate so that the conductive regions face each other.
  • the surface of the semiconductor chip was covered with a mold so that the semiconductor chip was connected to the heat sink via the mold.
  • the thermal resistance R jb between the semiconductor chip and the substrate was 1 °C/W
  • the thermal resistance R jc between the semiconductor chip and the heat sink was 15 °C/W.
  • the thermal resistance between the semiconductor chip and the substrate is suppressed to about 1/9 of that of the comparative example, and the thermal resistance between the semiconductor chip and the heat sink is suppressed to about 1/130 of that of the comparative example.
  • the remarkable decrease in thermal resistance R jc in the examples is that the semiconductor chip is not covered with an insulating material (mold) , and the thermal resistance in the heat conduction path was significantly lower than that in the comparative example in which the mold having high heat resistance was sandwiched. From these results, the semiconductor package of the present application can suppress the temperature rise of the semiconductor chip in the operating state, and can raise the allowable current value of the semiconductor chip. Therefore, it is considered that a high allowable current value can be maintained and a decrease in power density per unit volume can be suppressed even when it is miniaturized.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

L'invention concerne un boîtier de semi-conducteur capable de récupérer efficacement la chaleur générée par un courant circulant à travers une puce à semi-conducteur et de supprimer une élévation de température de la puce à semi-conducteur. Le boîtier de semi-conducteur de la présente invention comprend un substrat, une puce à semi-conducteur montée sur le substrat et ayant une pluralité de premières régions conductrices sur une surface de la puce à semi-conducteur opposée au substrat, une pluralité de premières couches de redistribution séparées les unes des autres, une première couche isolante disposée sur les premières couches de redistribution et ayant une ouverture pour exposer au moins une partie de la première couche de redistribution, et un dissipateur thermique recouvrant les premières couches de redistribution et la première couche isolante.
PCT/CN2021/088255 2021-04-20 2021-04-20 Boîtier de semi-conducteur WO2022222015A1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
PCT/CN2021/088255 WO2022222015A1 (fr) 2021-04-20 2021-04-20 Boîtier de semi-conducteur
CN202180093671.5A CN116897423A (zh) 2021-04-20 2021-04-20 一种半导体封装

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Application Number Priority Date Filing Date Title
PCT/CN2021/088255 WO2022222015A1 (fr) 2021-04-20 2021-04-20 Boîtier de semi-conducteur

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WO2022222015A1 true WO2022222015A1 (fr) 2022-10-27

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