WO2022220450A1 - Semiconductor device having controlled threshold voltage and method for manufacturing same - Google Patents

Semiconductor device having controlled threshold voltage and method for manufacturing same Download PDF

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Publication number
WO2022220450A1
WO2022220450A1 PCT/KR2022/004478 KR2022004478W WO2022220450A1 WO 2022220450 A1 WO2022220450 A1 WO 2022220450A1 KR 2022004478 W KR2022004478 W KR 2022004478W WO 2022220450 A1 WO2022220450 A1 WO 2022220450A1
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cobalt
titanium
metal gate
semiconductor device
content
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PCT/KR2022/004478
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French (fr)
Korean (ko)
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최창환
이주현
최문석
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한양대학교 산학협력단
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    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
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    • C23C16/45553—Atomic layer deposition [ALD] characterized by the use of precursors specially adapted for ALD
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Definitions

  • the present invention relates to a semiconductor device with a controlled threshold voltage and a method for manufacturing the same, and more particularly, to a technical idea of controlling a work function of a metal gate by controlling the content of a metal gate material of the semiconductor device.
  • the metal gate has the advantage of being able to improve the high sheet resistance characteristic, which is a problem of the conventionally used polysilicon.
  • a pure metal having a high work function in order to apply the metal gate to a semiconductor device requiring a high work function, such as a PMOS transistor, a pure metal having a high work function must be used as the metal gate.
  • a pure metal having a high work function has difficulties in the etching process, There is a disadvantage that thermal stability may be poor, which may cause a diffusion problem into the gate insulating layer.
  • titanium nitride (TiN) used is the gate of the NMOS transistor and the PMOS transistor. It has a disadvantage in that it has an insufficient work function to be used as an electrode.
  • titanium nitride is a material having a mid-gap work function, and it is separately It is necessary to use the doping process of
  • An object of the present invention is to provide a semiconductor device having a metal gate having a work function required for a PMOS region by controlling the cobalt content in titanium-cobalt nitride (TiCoN), and a method for manufacturing the same.
  • TiCoN titanium-cobalt nitride
  • Another object of the present invention is to provide a semiconductor device capable of obtaining a low threshold voltage by applying a metal gate having a required work function to a PMOS region, and a method for manufacturing the same.
  • Another object of the present invention is to provide a semiconductor device capable of stably maintaining a work function corresponding to a PMOS region even after heat treatment, and a method for manufacturing the same.
  • Another object of the present invention is to provide a semiconductor device capable of securing excellent resistance characteristics (sheet resistance characteristics and resistivity characteristics) by providing a titanium-cobalt nitride-based metal gate with an optimized cobalt content, and a method for manufacturing the same.
  • a semiconductor device includes a substrate, a gate insulating layer formed on the substrate, and a metal gate formed on the gate insulating layer and including titanium-cobalt nitride (TiCoN), wherein the metal gate is titanium-cobalt.
  • TiCoN titanium-cobalt nitride
  • the work function may be adjusted according to the content of cobalt in the nitride.
  • the relative content of cobalt relative to titanium in titanium-cobalt nitride may be 0% ⁇ C Co /( Ti +Co) ⁇ 64%.
  • the titanium content (C Ti ) in the titanium-cobalt nitride is 13% ⁇ C Ti ⁇ 36%, and the cobalt content (C co ) may be 0% ⁇ C co ⁇ 23% .
  • the metal gate may have a work function of 4.8 eV to 5.3 eV.
  • the gate insulating layer is at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O 5 ) It may include a high-k dielectric material.
  • the gate insulating layer may be formed in a multi-layer structure of a first insulating layer corresponding to silicon oxide and a second insulating layer corresponding to at least one high-k material.
  • a method of manufacturing a semiconductor device includes forming a gate insulating film on a substrate and forming a metal gate including titanium-cobalt nitride (TiCoN) on the gate insulating film, wherein the metal
  • TiCoN titanium-cobalt nitride
  • the gate may have a work function adjusted according to the content of cobalt in the titanium-cobalt nitride.
  • the step of forming the metal gate is performed such that the relative content of cobalt relative to titanium (C Co /( Ti +Co) ) in titanium-cobalt nitride is 0% ⁇ C Co /( Ti +Co) ⁇ 64%.
  • a metal gate may be formed.
  • the titanium content (C Ti ) in the titanium-cobalt nitride becomes 13% ⁇ C Ti ⁇ 36%, and the cobalt content (C co ) is 0% ⁇ C co ⁇
  • a metal gate can be formed so as to be 23%.
  • the forming of the metal gate may control the content of cobalt in the titanium-cobalt nitride through atomic layer deposition (ALD).
  • ALD atomic layer deposition
  • the content of cobalt in the titanium-cobalt nitride may be controlled by adjusting the deposition ratio of the titanium nitride layer (TiN layer) and the cobalt layer (Co layer) through the atomic layer deposition method.
  • the step of forming the metal gate is to form a titanium nitride layer through an atomic layer deposition method based on a TiCl 4 precursor and NH 3 reaction gas, Co(MeCp) 2 Atomic layer based on the precursor and NH 3 reaction gas
  • a cobalt layer may be formed through a vapor deposition method.
  • the present invention may provide a semiconductor device including a metal gate having a work function required for a PMOS region by controlling the cobalt content in titanium-cobalt nitride (TiCoN).
  • a low threshold voltage can be obtained by applying a metal gate having a required work function to the PMOS region.
  • the present invention can stably maintain a work function corresponding to the PMOS region even after heat treatment.
  • the present invention can secure excellent resistance characteristics (sheet resistance characteristics and resistivity characteristics) by applying a titanium-cobalt nitride-based metal gate with an optimized cobalt content.
  • FIG. 1 is a view for explaining a semiconductor device according to an embodiment.
  • FIG. 2 is a view for explaining an example of controlling a composition ratio of a metal gate provided in a semiconductor device according to an embodiment.
  • FIG 3 is a view for explaining resistivity characteristics according to an increase in cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • FIG. 4 is a view for explaining capacitance characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • FIG. 5 is a diagram for explaining flat band voltage characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • FIG. 6 is a diagram for explaining effective work function characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • FIG. 7 is a view for explaining effective work function characteristics according to a cobalt content and a heat treatment temperature in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • FIGS. 8A to 8B are diagrams for explaining a TEM analysis result of a semiconductor device according to an exemplary embodiment.
  • FIG. 9 is a view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment.
  • an (eg, first) component When an (eg, first) component is referred to as being “(functionally or communicatively) connected” or “connected” to another (eg, second) component, that component is It may be directly connected to the element, or may be connected through another element (eg, a third element).
  • the expression “a device configured to” may mean that the device is “capable of” with other devices or components.
  • a processor configured (or configured to perform) A, B, and C refers to a dedicated processor (eg, an embedded processor) for performing the operations, or by executing one or more software programs stored in a memory device.
  • a dedicated processor eg, an embedded processor
  • a general-purpose processor eg, a CPU or an application processor
  • FIG. 1 is a view for explaining a semiconductor device according to an embodiment.
  • a semiconductor device 100 may include a metal gate having a work function required for a PMOS region by controlling the cobalt content in titanium-cobalt nitride (TiCoN).
  • TiCoN titanium-cobalt nitride
  • the semiconductor device 100 may obtain a low threshold voltage by applying a metal gate having a required work function to the PMOS region, and may stably maintain a work function corresponding to the PMOS region even after heat treatment.
  • the semiconductor device 100 includes a titanium-cobalt nitride-based metal gate with an optimized cobalt content, thereby securing excellent resistance characteristics (sheet resistance characteristics and resistivity characteristics).
  • the semiconductor device 100 may include a substrate 110 , a gate insulating layer 120 formed on the substrate 110 , and a metal gate 130 formed on the gate insulating layer 120 .
  • the semiconductor device 100 is a PMOS transistor
  • the substrate 110 includes an N-type well layer (N-well)
  • the gate insulating film 120 is formed in the center of the upper surface of the N-type well layer, and the gate insulating film ( A metal gate 130 may be formed on 130 .
  • the substrate 110 is silicon (silicon, Si), aluminum oxide (aluminum oxide, Al 2 O 3 ), magnesium oxide (magnesium oxide, MgO), silicon carbide (silicon carbide, SiC), silicon nitride (silicon nitride) , SiN), glass, quartz, sapphire, graphite, graphene, and polyimide (PI) may include at least one of, but preferably a substrate (100) may be a silicon substrate.
  • the gate insulating layer 120 may include at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O 5 ).
  • the gate insulating layer 120 may include hafnium oxide as a high-k material.
  • the gate insulating layer 120 when the gate insulating layer 120 includes a high-k material, it has an equivalent oxide thickness (EOT) electrically equal to that of silicon oxide and physically prevents tunneling while implementing a thick thin film. This is possible, and through this, the leakage current can be reduced.
  • EOT equivalent oxide thickness
  • the gate insulating layer 120 may be formed in a multilayer structure of a first insulating layer corresponding to silicon oxide and a second insulating layer corresponding to at least one high-k material.
  • the thickness of the first insulating layer may be reduced through a dry cleaning process using plasma.
  • a metal oxide film eg, HfO 2
  • PDA post-deposition annealing
  • the gate insulating layer 120 after forming the second insulating layer corresponding to the high-k material, activated fluorine through a dry cleaning process using plasma reacts with the first insulating layer corresponding to the silicon oxide Through this, the thickness of the first insulating layer can be reduced to obtain the effect of increasing the capacitance and reducing the leakage current.
  • the gate insulating layer 120 is activated using NH 4 F and HF as intermediate oxides.
  • fluorine (F) is formed, and fluorine diffuses through the first insulating layer (ie, HfO 2 layer) and reacts with the second insulating layer (ie, SiO 2 layer) to form highly volatile SiFx.
  • the decomposed oxygen is diffused into the first insulating layer to compensate for the oxygen deficiency, so that the thickness of the second insulating layer may be reduced and the film quality of the first insulating layer may be improved.
  • the metal gate 130 includes titanium-cobalt nitride (TiCoN), and the work function may be adjusted according to the content of cobalt in the titanium-cobalt nitride.
  • TiCoN titanium-cobalt nitride
  • the metal gate 130 may have a higher work function and a lower sheet resistance as the content of cobalt in the titanium-cobalt nitride increases.
  • the metal gate 130 includes titanium-cobalt nitride, but by optimizing the titanium content in the titanium-cobalt nitride, the sheet resistance of the TiAlN, TaAlN and TaSiN thin films provided in the metal gate of the existing PMOS transistor. This high problem can be solved.
  • the metal gate 130 is atomic layer deposition (ALD), vacuum deposition (vacuum deposition), chemical vapor deposition (chemical vapor deposition), physical vapor deposition (physical vapor deposition), sputtering (sputtering) And it may be formed through at least one method of spin coating (spincoating).
  • ALD atomic layer deposition
  • vacuum deposition vacuum deposition
  • chemical vapor deposition chemical vapor deposition
  • physical vapor deposition physical vapor deposition
  • sputtering sputtering
  • spincoating spin coating
  • the content of titanium, cobalt, and nitrogen in the titanium-cobalt nitride may be controlled through an atomic layer deposition method.
  • the work function of the metal gate 130 may be controlled by controlling the composition of titanium, cobalt, and nitrogen in the titanium-cobalt nitride using the atomic layer deposition method.
  • the cobalt content of the metal gate 130 may be controlled to have a work function of 4.8 eV to 5.3 eV through an atomic layer deposition method.
  • the metal gate 130 may have a work function of 5.1 eV suitable for a PMOS transistor.
  • the titanium content (C Ti ) in the titanium-cobalt nitride is 13% ⁇ C Ti ⁇ 36%
  • the cobalt content (C co ) is 0% ⁇ C co ⁇ 23%
  • the relative content of cobalt relative to titanium in the titanium-cobalt nitride may be 0% ⁇ C Co /( Ti +Co) ⁇ 64%.
  • the relative content of cobalt (C Co /( Ti +Co) ) may be 47% ⁇ C Co /( Ti +Co) ⁇ 64%.
  • the relative content of cobalt may mean the number of atoms of Co to the sum of the number of atoms of titanium and the number of atoms of cobalt (Ti + Co).
  • FIG. 2 is a view for explaining an example of controlling a composition ratio of a metal gate provided in a semiconductor device according to an embodiment.
  • reference numeral 200 denotes a titanium-cobalt nitride (TiCoN) based metal gate by controlling a deposition subcycle ratio (ie, deposition ratio) in a deposition process using an atomic layer deposition method, so that the relative content of cobalt in the gate.
  • a deposition subcycle ratio ie, deposition ratio
  • C Co /( Ti +Co) An example of controlling (C Co /( Ti +Co) ) is shown.
  • the titanium-cobalt nitride-based metal gate of the semiconductor device may be formed by alternately depositing a titanium nitride layer (TiN layer) and a cobalt layer (Co layer) using an atomic layer deposition method.
  • the content of cobalt in titanium-cobalt nitride (C Co ) can be adjusted in the range of 0% ⁇ C co ⁇ 23% by adjusting the deposition ratio (subcycle ratio), and the relative content of cobalt (C Co / ( Ti + Co) ) may be adjusted in the range of 0% ⁇ C Co/(Ti+Co) ⁇ 64%.
  • FIG 3 is a view for explaining resistivity characteristics according to an increase in cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • reference numeral 300 denotes a change in resistivity according to a change in the relative content of cobalt (C Co / ( Ti +Co) ) in a titanium-cobalt nitride (TiCoN)-based metal gate.
  • the cobalt content in the titanium-cobalt nitride based metal gate increases, and the content of titanium and nitrogen may decrease, in which case the cobalt content is As it increases, it can be seen that the resistivity of the titanium-cobalt nitride-based metal gate decreases.
  • FIG. 4 is a view for explaining capacitance characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • reference numeral 400 denotes a titanium-cobalt nitride (TiCoN) based metal gate with a relative content of cobalt (C Co / ( Ti +Co ) ) and a capacitance according to a change in the gate voltage. ) shows the change in characteristics.
  • the change in capacitance characteristic shown at reference numeral 400 is a silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ) on a substrate on a gate insulating film formed in a multilayered titanium-cobalt nitride-based metal gate electrode by depositing a metal gate electrode, and a metal gate electrode After tungsten was deposited on the tungsten, both ends of the substrate and the tungsten were connected and measured.
  • the titanium-cobalt nitride-based metal gate has little difference in the oxide capacitance (Co x ) value according to the change in the relative content of cobalt (C Co /( Ti +Co) ). have.
  • titanium-cobalt nitride-based metal gate can prevent unintentional change in equivalent oxide thickness (EOT) due to oxygen scavenging that occurs in the conventional Al-added electrodes such as TiAlN and TaAlN. it means.
  • EOT equivalent oxide thickness
  • FIG. 5 is a diagram for explaining flat band voltage characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • reference numeral 500 denotes a titanium-cobalt nitride (TiCoN) based metal gate with a relative content of cobalt (C Co / ( Ti +Co ) ) according to a change in flatband voltage (V FB ) Shows the change in characteristics.
  • TiCoN titanium-cobalt nitride
  • V FB flatband voltage
  • the change in the flat band voltage characteristic shown at reference numeral 500 is a silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ) on a substrate on a gate insulating film formed in a multilayered titanium-cobalt nitride-based metal gate electrode by depositing a metal gate electrode, After tungsten was deposited on the gate electrode, both ends of the substrate and the tungsten were connected and measured.
  • the flat band voltage is relatively positively shifted as the content of cobalt in the titanium-cobalt nitride-based metal gate increases.
  • Titanium-cobalt nitride according to an embodiment
  • the base metal gate can realize a flat band voltage shift of about 160 mV just by adjusting the cobalt content to 47% or more.
  • FIG. 6 is a diagram for explaining effective work function characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • reference numeral 600 denotes an effective work function according to a change in the relative content of cobalt (C Co / ( Ti +Co) ) in a titanium-cobalt nitride (TiCoN)-based metal gate. The results confirmed through the V FB -EOT plot method are shown.
  • silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ) When the same titanium-cobalt nitride based metal gate is used on two gate insulating layers, the relative content of cobalt (C Co / ( Ti + Co) ), it can be seen that the effective work function increases at a similar rate with little difference.
  • the titanium-cobalt nitride-based metal gate has a work function suitable for a PMOS transistor stably in both oxides.
  • FIG. 7 is a view for explaining effective work function characteristics according to a cobalt content and a heat treatment temperature in a metal gate provided in a semiconductor device according to an exemplary embodiment.
  • reference numeral 700 denotes a transistor device having a titanium-cobalt nitride (TiCoN)-based metal gate in a forming gas (H 2 5% + N 2 ) atmosphere for about 30 minutes at 400° C. and It shows effective work function characteristics when heat treated at a temperature of 500°C.
  • TiCoN titanium-cobalt nitride
  • the effective work function of the titanium-cobalt nitride-based metal gate decreases as the heat treatment temperature increases.
  • FIGS. 8A to 8B are diagrams for explaining a TEM analysis result of a semiconductor device according to an exemplary embodiment.
  • reference numeral 810 denotes a titanium-cobalt nitride (TiCoN)-based metal gate having a relative content of cobalt (C Co/(Ti+Co) ) of 47%, and then heat treatment is not performed.
  • a TEM (transmission electron microscope) image of a semiconductor device that has not been used is shown, and reference numeral 820 denotes a metal gate formed in the same manner as that of reference numeral 810, followed by heat treatment at a temperature of 500° C. for about 30 minutes in a forming gas atmosphere.
  • TEM of a semiconductor device show the image.
  • 'Si' denotes a substrate
  • 'HfO 2 ' denotes a gate insulating layer
  • 'TiCoN' denotes a metal gate
  • W denotes a low resistance material and a capping layer.
  • the titanium-cobalt nitride-based metal gate according to the embodiment can secure excellent thermal stability while having overall low sheet resistance, specific resistance, and high work function.
  • the titanium-cobalt nitride-based metal gate according to an embodiment can be applied to a metal gate in the PMOS region of a CMOS device requiring a high work function, and is used for all semiconductor devices requiring a high work function in addition to the CMOS device. It can also be applied to the gate.
  • the titanium-cobalt nitride-based metal gate according to an embodiment is applied to replace titanium nitride (TiN) and tantalum nitride (TaN), which are currently used as barrier metals, to lower specific resistance. can be used for
  • the titanium-cobalt nitride-based metal gate may be used in various devices requiring low resistivity in addition to the gate material.
  • FIG. 9 is a view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment.
  • FIG. 9 is a view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment described with reference to FIGS. 1 to 8B .
  • the contents described with reference to FIG. 9 below the contents described with reference to FIGS. 1 to 8B .
  • a description that overlaps with will be omitted.
  • a gate insulating layer may be formed on a substrate.
  • the substrate is silicon (silicon, Si), aluminum oxide (aluminum oxide, Al 2 O 3 ), magnesium oxide (magnesium oxide, MgO), silicon carbide (silicon carbide, SiC), silicon nitride (silicon nitride, SiN) , may include at least one of glass, quartz, sapphire, graphite, graphene, and polyimide (PI), but preferably the substrate is a silicon substrate can be
  • the gate insulating layer has a high dielectric constant of at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O 5 ). It may include a high-k dielectric material, but is not limited thereto, and may include various high-k dielectric materials in addition to the above-described materials.
  • the gate insulating layer may include hafnium oxide as a high-k material.
  • a metal gate including titanium-cobalt nitride may be formed on the gate insulating layer, wherein the metal gate according to the embodiment is titanium-cobalt nitride (TiCoN).
  • the work function may be adjusted according to the content of the cobalt material in the cobalt nitride.
  • the metal gate may have a higher work function and a lower sheet resistance as the content of cobalt in the titanium-cobalt nitride increases.
  • the method of manufacturing a semiconductor device may include atomic layer deposition (ALD), vacuum deposition, chemical vapor deposition, and physical vapor deposition.
  • the metal gate may be formed through at least one of vapor deposition, sputtering, and spin coating.
  • the content of titanium, cobalt, and nitrogen in the titanium-cobalt nitride may be controlled through an atomic layer deposition method.
  • step 920 the method of manufacturing a semiconductor device according to an embodiment adjusts the deposition ratio of a titanium nitride layer (TiN layer) and a cobalt layer (Co layer) through an atomic layer deposition method, thereby titanium-cobalt material in cobalt nitride. content can be controlled.
  • TiN layer titanium nitride layer
  • Co layer cobalt layer
  • a titanium nitride layer is formed through an atomic layer deposition method based on a TiCl 4 precursor and an NH 3 reaction gas, and a Co(MeCp) 2 precursor and an NH 3 reaction gas are formed.
  • a cobalt layer can be formed through an atomic layer deposition method based on
  • the content (C Ti ) of the titanium material in the titanium-cobalt nitride becomes 13% ⁇ C Ti ⁇ 36%, and the content of the cobalt material (C A metal gate may be formed such that co ) is 0% ⁇ C co ⁇ 23%.
  • the relative content (C Co /( Ti +Co) ) of the cobalt material relative to the titanium material in the titanium-cobalt nitride is 0% ⁇ C Co/(Ti+)
  • a metal gate may be formed such that Co) ⁇ 64%.
  • the method of manufacturing a semiconductor device according to an embodiment is such that the relative content of the cobalt material (C Co /( Ti +Co) ) is 47% ⁇ C Co /( Ti +Co) ⁇ 64%
  • a metal gate may be formed.
  • the present invention it is possible to provide a semiconductor device having a metal gate having a work function required for the PMOS region by controlling the cobalt content in the titanium-cobalt nitride (TiCoN).
  • a low threshold voltage can be obtained by applying a metal gate having a required work function to the PMOS region, and the work function corresponding to the PMOS region can be stably maintained even after heat treatment.

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Abstract

The present invention relates to a semiconductor device having a controlled threshold voltage and a method for manufacturing same. The semiconductor device according to an embodiment may comprise: a substrate; a gate insulating layer formed on the substrate; and a metal gate formed on the gate insulating layer and comprising titanium-cobalt nitride (TiCoN), wherein the metal gate has a work function which is controlled according to the content of cobalt in the titanium-cobalt nitride.

Description

문턱 전압이 제어된 반도체 소자 및 그 제조방법Semiconductor device with controlled threshold voltage and method for manufacturing the same
본 발명은 문턱 전압이 제어된 반도체 소자 및 그 제조방법에 관한 것으로, 보다 상세하게는 반도체 소자의 금속 게이트 물질의 함량을 제어하여 금속 게이트의 일함수를 조절하는 기술적 사상에 관한 것이다.The present invention relates to a semiconductor device with a controlled threshold voltage and a method for manufacturing the same, and more particularly, to a technical idea of controlling a work function of a metal gate by controlling the content of a metal gate material of the semiconductor device.
현재 반도체 소자는 도핑된 폴리실리콘 대신 금속 물질에 기반하는 금속 게이트를 적용하기 위한 연구가 지속되고 있다. 금속 게이트는 기존에 사용된 폴리실리콘의 문제점인 높은 면저항 특성을 개선할 수 있다는 장점이 있다. Currently, research to apply a metal gate based on a metal material instead of doped polysilicon for a semiconductor device is continuing. The metal gate has the advantage of being able to improve the high sheet resistance characteristic, which is a problem of the conventionally used polysilicon.
그러나, 금속 게이트는 PMOS 트랜지스터와 같이 높은 일함수를 필요로 하는 반도체 소자에 적용하려면 높은 일함수를 갖는 순수한 금속을 금속 게이트로 사용해야 하나, 높은 일함수를 갖는 순수한 금속은 식각 공정에서 어려움이 있고, 열적 안정성이 좋지 못해 게이트 절연막으로의 확산 문제를 야기할 수 있다는 단점이 있다. However, in order to apply the metal gate to a semiconductor device requiring a high work function, such as a PMOS transistor, a pure metal having a high work function must be used as the metal gate. However, a pure metal having a high work function has difficulties in the etching process, There is a disadvantage that thermal stability may be poor, which may cause a diffusion problem into the gate insulating layer.
또한, CMOS 구조에서는 대칭적이며 낮은 문턱전압을 얻기 위해 NMOS 트랜지스터와 PMOS 트랜지스터에서 이상적인 일함수를 갖는 두 개의 서로 다른 금속을 사용하는데, 이때 사용되는 티타늄 질화물(TiN)은 NMOS 트랜지스터와 PMOS 트랜지스터의 게이트 전극으로 사용하기에 충분치 못한 일함수를 가지고 있다는 단점이 있다. In addition, in the CMOS structure, two different metals having an ideal work function are used in the NMOS transistor and the PMOS transistor to obtain a symmetrical and low threshold voltage. In this case, titanium nitride (TiN) used is the gate of the NMOS transistor and the PMOS transistor. It has a disadvantage in that it has an insufficient work function to be used as an electrode.
구체적으로, 티타늄 질화물(TiN)은 미드 갭(mid gap) 일함수를 가지는 물질로, 각각의 밴드 엣지(band edge)에 가까운 일함수가 요구되는 NMOS 트랜지스터 및 PMOS 트랜지스터의 게이트 전극으로 사용되기 위해서는 별도의 도핑 과정을 이용하거나 다른 물질로 대체하는 방안이 필요하다.Specifically, titanium nitride (TiN) is a material having a mid-gap work function, and it is separately It is necessary to use the doping process of
본 발명은 티타늄-코발트 질화물(TiCoN) 내 코발트 함량의 제어를 통해 PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 구비하는 반도체 소자 및 그 제조방법을 제공하고자 한다. An object of the present invention is to provide a semiconductor device having a metal gate having a work function required for a PMOS region by controlling the cobalt content in titanium-cobalt nitride (TiCoN), and a method for manufacturing the same.
또한, 본 발명은 PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 적용하여 낮은 문턱전압을 얻을 수 있는 반도체 소자 및 그 제조방법을 제공하고자 한다.Another object of the present invention is to provide a semiconductor device capable of obtaining a low threshold voltage by applying a metal gate having a required work function to a PMOS region, and a method for manufacturing the same.
또한, 본 발명은 열처리 이후에도 PMOS 영역에 대응되는 일함수를 안정적으로 유지할 수 있는 반도체 소자 및 그 제조방법을 제공하고자 한다. Another object of the present invention is to provide a semiconductor device capable of stably maintaining a work function corresponding to a PMOS region even after heat treatment, and a method for manufacturing the same.
또한, 본 발명은 코발트 함량이 최적화된 티타늄-코발트 질화물에 기반한 금속 게이트를 구비하여 우수한 저항 특성(면저항 특성 및 비저항 특성)을 확보할 수 있는 반도체 소자 및 그 제조방법을 제공하고자 한다.Another object of the present invention is to provide a semiconductor device capable of securing excellent resistance characteristics (sheet resistance characteristics and resistivity characteristics) by providing a titanium-cobalt nitride-based metal gate with an optimized cobalt content, and a method for manufacturing the same.
본 발명의 일실시예에 따른 반도체 소자는 기판과, 기판 상에 형성된 게이트 절연막 및 게이트 절연막 상에 형성되고 티타늄-코발트 질화물(TiCoN)을 구비하는 금속 게이트를 포함하고, 여기서 금속 게이트는 티타늄-코발트 질화물 내의 코발트의 함량에 따라 일함수가 조절될 수 있다. A semiconductor device according to an embodiment of the present invention includes a substrate, a gate insulating layer formed on the substrate, and a metal gate formed on the gate insulating layer and including titanium-cobalt nitride (TiCoN), wherein the metal gate is titanium-cobalt. The work function may be adjusted according to the content of cobalt in the nitride.
일측에 따르면, 금속 게이트는 티타늄-코발트 질화물 내에서 티타늄 대비 코발트의 상대적 함량(CCo /( Ti +Co))이 0% < CCo /( Ti +Co) ≤ 64% 일 수 있다.According to one side, in the metal gate, the relative content of cobalt relative to titanium in titanium-cobalt nitride (C Co /( Ti +Co) ) may be 0% < C Co /( Ti +Co) ≤ 64%.
일측에 따르면, 금속 게이트는 티타늄-코발트 질화물 내에서 티타늄의 함량(CTi)이 13% ≤ CTi ≤ 36%이고, 코발트의 함량(Cco)이 0% < Cco ≤ 23%일 수 있다.According to one side, in the metal gate, the titanium content (C Ti ) in the titanium-cobalt nitride is 13% ≤ C Ti ≤ 36%, and the cobalt content (C co ) may be 0% < C co ≤ 23% .
일측에 따르면, 금속 게이트는 4.8eV 내지 5.3eV의 일함수를 갖을 수 있다.According to one side, the metal gate may have a work function of 4.8 eV to 5.3 eV.
일측에 따르면, 게이트 절연막은 하프늄 산화물(HfO2), 지르코늄 산화물(ZrO2), 티타늄 산화물(TiO2), 알루미늄 산화물(Al2O3) 및 탄탈럼 산화물(Ta2O5) 중 적어도 하나의 고유전율 물질(high-k dielectric material)을 포함할 수 있다. According to one side, the gate insulating layer is at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O 5 ) It may include a high-k dielectric material.
일측에 따르면, 게이트 절연막은 실리콘 산화물에 대응되는 제1 절연층과, 적어도 하나의 고유전율 물질에 대응되는 제2 절연층의 복층 구조로 형성될 수 있다.According to one side, the gate insulating layer may be formed in a multi-layer structure of a first insulating layer corresponding to silicon oxide and a second insulating layer corresponding to at least one high-k material.
본 발명의 일실시예에 따른 반도체 소자의 제조방법은 기판 상에 게이트 절연막을 형성하는 단계 및 게이트 절연막 상에 티타늄-코발트 질화물(TiCoN)을 구비하는 금속 게이트를 형성하는 단계를 포함하고, 여기서 금속 게이트는 티타늄-코발트 질화물 내의 코발트의 함량에 따라 일함수가 조절될 수 있다.A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming a gate insulating film on a substrate and forming a metal gate including titanium-cobalt nitride (TiCoN) on the gate insulating film, wherein the metal The gate may have a work function adjusted according to the content of cobalt in the titanium-cobalt nitride.
일측에 따르면, 금속 게이트를 형성하는 단계는 티타늄-코발트 질화물 내에서 티타늄 대비 코발트의 상대적 함량(CCo /( Ti +Co))이 0% < CCo /( Ti +Co) ≤ 64%가 되도록 금속 게이트를 형성할 수 있다.According to one side, the step of forming the metal gate is performed such that the relative content of cobalt relative to titanium (C Co /( Ti +Co) ) in titanium-cobalt nitride is 0% < C Co /( Ti +Co) ≤ 64%. A metal gate may be formed.
일측에 따르면, 금속 게이트를 형성하는 단계는 티타늄-코발트 질화물 내에서 티타늄의 함량(CTi)이 13% ≤ CTi ≤ 36%이 되고, 코발트의 함량(Cco)이 0% < Cco ≤ 23%가 되도록 금속 게이트를 형성할 수 있다.According to one side, in the step of forming the metal gate, the titanium content (C Ti ) in the titanium-cobalt nitride becomes 13% ≤ C Ti ≤ 36%, and the cobalt content (C co ) is 0% < C co ≤ A metal gate can be formed so as to be 23%.
일측에 따르면, 금속 게이트를 형성하는 단계는 원자층 증착법(atomic layer deposition, ALD)을 통해 티타늄-코발트 질화물 내의 코발트의 함량을 제어할 수 있다. According to one side, the forming of the metal gate may control the content of cobalt in the titanium-cobalt nitride through atomic layer deposition (ALD).
일측에 따르면, 금속 게이트를 형성하는 단계는 원자층 증착법을 통해 티타늄 질화물층(TiN layer)과 코발트층(Co layer)의 증착 비율을 조절하여 티타늄-코발트 질화물 내의 코발트의 함량을 제어할 수 있다. According to one side, in the forming of the metal gate, the content of cobalt in the titanium-cobalt nitride may be controlled by adjusting the deposition ratio of the titanium nitride layer (TiN layer) and the cobalt layer (Co layer) through the atomic layer deposition method.
일측에 따르면, 금속 게이트를 형성하는 단계는 TiCl4 전구체와 NH3 반응가스에 기초하는 원자층 증착법을 통해 티타늄 질화물층을 형성하고, Co(MeCp)2 전구체와 NH3 반응가스에 기초하는 원자층 증착법을 통해 코발트층을 형성할 수 있다.According to one side, the step of forming the metal gate is to form a titanium nitride layer through an atomic layer deposition method based on a TiCl 4 precursor and NH 3 reaction gas, Co(MeCp) 2 Atomic layer based on the precursor and NH 3 reaction gas A cobalt layer may be formed through a vapor deposition method.
일실시예에 따르면, 본 발명은 티타늄-코발트 질화물(TiCoN) 내 코발트 함량의 제어를 통해 PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 구비하는 반도체 소자를 제공할 수 있다. According to an embodiment, the present invention may provide a semiconductor device including a metal gate having a work function required for a PMOS region by controlling the cobalt content in titanium-cobalt nitride (TiCoN).
일실시예에 따르면, 본 발명은 PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 적용하여 낮은 문턱전압을 얻을 수 있다. According to an embodiment, in the present invention, a low threshold voltage can be obtained by applying a metal gate having a required work function to the PMOS region.
일실시예에 따르면, 본 발명은 열처리 이후에도 PMOS 영역에 대응되는 일함수를 안정적으로 유지할 수 있다.According to one embodiment, the present invention can stably maintain a work function corresponding to the PMOS region even after heat treatment.
일실시예에 따르면, 본 발명은 코발트 함량이 최적화된 티타늄-코발트 질화물에 기반한 금속 게이트를 적용하여 우수한 저항 특성(면저항 특성 및 비저항 특성)을 확보할 수 있다.According to one embodiment, the present invention can secure excellent resistance characteristics (sheet resistance characteristics and resistivity characteristics) by applying a titanium-cobalt nitride-based metal gate with an optimized cobalt content.
도 1은 일실시예에 따른 반도체 소자를 설명하기 위한 도면이다.1 is a view for explaining a semiconductor device according to an embodiment.
도 2는 일실시예에 따른 반도체 소자에 구비된 금속 게이트의 조성비를 제어하는 예시를 설명하기 위한 도면이다.2 is a view for explaining an example of controlling a composition ratio of a metal gate provided in a semiconductor device according to an embodiment.
도 3은 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량 증가에 따른 비저항 특성을 설명하기 위한 도면이다.3 is a view for explaining resistivity characteristics according to an increase in cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 4는 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량에 따른 커패시턴스 특성을 설명하기 위한 도면이다.4 is a view for explaining capacitance characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 5는 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량에 따른 평탄대역전압 특성을 설명하기 위한 도면이다.5 is a diagram for explaining flat band voltage characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 6은 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량에 따른 유효 일함수 특성을 설명하기 위한 도면이다. 6 is a diagram for explaining effective work function characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 7은 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량 및 열처리 온도에 따른 유효 일함수 특성을 설명하기 위한 도면이다.7 is a view for explaining effective work function characteristics according to a cobalt content and a heat treatment temperature in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 8a 내지 도 8b는 일실시예에 따른 반도체 소자의 TEM 분석 결과를 설명하기 위한 도면이다.8A to 8B are diagrams for explaining a TEM analysis result of a semiconductor device according to an exemplary embodiment.
도 9는 일실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 도면이다.9 is a view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment.
이하, 본 문서의 다양한 실시 예들이 첨부된 도면을 참조하여 기재된다.Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings.
실시 예 및 이에 사용된 용어들은 본 문서에 기재된 기술을 특정한 실시 형태에 대해 한정하려는 것이 아니며, 해당 실시 예의 다양한 변경, 균등물, 및/또는 대체물을 포함하는 것으로 이해되어야 한다.Examples and terms used therein are not intended to limit the technology described in this document to specific embodiments, and should be understood to include various modifications, equivalents, and/or substitutions of the embodiments.
하기에서 다양한 실시 예들을 설명에 있어 관련된 공지 기능 또는 구성에 대한 구체적인 설명이 발명의 요지를 불필요하게 흐릴 수 있다고 판단되는 경우에는 그 상세한 설명을 생략할 것이다.In the following, when it is determined that a detailed description of a known function or configuration related to various embodiments may unnecessarily obscure the gist of the present invention, a detailed description thereof will be omitted.
그리고 후술되는 용어들은 다양한 실시 예들에서의 기능을 고려하여 정의된 용어들로서 이는 사용자, 운용자의 의도 또는 관례 등에 따라 달라질 수 있다. 그러므로 그 정의는 본 명세서 전반에 걸친 내용을 토대로 내려져야 할 것이다.In addition, terms to be described later are terms defined in consideration of functions in various embodiments, which may vary according to intentions or customs of users and operators. Therefore, the definition should be made based on the content throughout this specification.
도면의 설명과 관련하여, 유사한 구성요소에 대해서는 유사한 참조 부호가 사용될 수 있다.In connection with the description of the drawings, like reference numerals may be used for like components.
단수의 표현은 문맥상 명백하게 다르게 뜻하지 않는 한, 복수의 표현을 포함할 수 있다.The singular expression may include the plural expression unless the context clearly dictates otherwise.
본 문서에서, "A 또는 B" 또는 "A 및/또는 B 중 적어도 하나" 등의 표현은 함께 나열된 항목들의 모든 가능한 조합을 포함할 수 있다.In this document, expressions such as “A or B” or “at least one of A and/or B” may include all possible combinations of items listed together.
"제1," "제2," "첫째," 또는 "둘째," 등의 표현들은 해당 구성요소들을, 순서 또는 중요도에 상관없이 수식할 수 있고, 한 구성요소를 다른 구성요소와 구분하기 위해 사용될 뿐 해당 구성요소들을 한정하지 않는다.Expressions such as "first," "second," "first," or "second," can modify the corresponding elements, regardless of order or importance, and to distinguish one element from another element. It is used only and does not limit the corresponding components.
어떤(예: 제1) 구성요소가 다른(예: 제2) 구성요소에 "(기능적으로 또는 통신적으로) 연결되어" 있다거나 "접속되어" 있다고 언급된 때에는, 어떤 구성요소가 상기 다른 구성요소에 직접적으로 연결되거나, 다른 구성요소(예: 제3 구성요소)를 통하여 연결될 수 있다.When an (eg, first) component is referred to as being “(functionally or communicatively) connected” or “connected” to another (eg, second) component, that component is It may be directly connected to the element, or may be connected through another element (eg, a third element).
본 명세서에서, "~하도록 구성된(또는 설정된)(configured to)"은 상황에 따라, 예를 들면, 하드웨어적 또는 소프트웨어적으로 "~에 적합한," "~하는 능력을 가지는," "~하도록 변경된," "~하도록 만들어진," "~를 할 수 있는," 또는 "~하도록 설계된"과 상호 호환적으로(interchangeably) 사용될 수 있다.As used herein, "configured to (or configured to)" according to the context, for example, hardware or software "suitable for," "having the ability to," "modified to ," "made to," "capable of," or "designed to," may be used interchangeably.
어떤 상황에서는, "~하도록 구성된 장치"라는 표현은, 그 장치가 다른 장치 또는 부품들과 함께 "~할 수 있는" 것을 의미할 수 있다.In some contexts, the expression “a device configured to” may mean that the device is “capable of” with other devices or components.
예를 들면, 문구 "A, B, 및 C를 수행하도록 구성된(또는 설정된) 프로세서"는 해당 동작을 수행하기 위한 전용 프로세서(예: 임베디드 프로세서), 또는 메모리 장치에 저장된 하나 이상의 소프트웨어 프로그램들을 실행함으로써, 해당 동작들을 수행할 수 있는 범용 프로세서(예: CPU 또는 application processor)를 의미할 수 있다.For example, the phrase “a processor configured (or configured to perform) A, B, and C” refers to a dedicated processor (eg, an embedded processor) for performing the operations, or by executing one or more software programs stored in a memory device. , may refer to a general-purpose processor (eg, a CPU or an application processor) capable of performing corresponding operations.
또한, '또는' 이라는 용어는 배타적 논리합 'exclusive or' 이기보다는 포함적인 논리합 'inclusive or' 를 의미한다.Also, the term 'or' means 'inclusive or' rather than 'exclusive or'.
즉, 달리 언급되지 않는 한 또는 문맥으로부터 명확하지 않는 한, 'x가 a 또는 b를 이용한다' 라는 표현은 포함적인 자연 순열들(natural inclusive permutations) 중 어느 하나를 의미한다.That is, unless stated otherwise or clear from context, the expression 'x employs a or b' means any one of natural inclusive permutations.
상술한 구체적인 실시 예들에서, 발명에 포함되는 구성 요소는 제시된 구체적인 실시 예에 따라 단수 또는 복수로 표현되었다.In the above-described specific embodiments, elements included in the invention are expressed in the singular or plural according to the specific embodiments presented.
그러나, 단수 또는 복수의 표현은 설명의 편의를 위해 제시한 상황에 적합하게 선택된 것으로서, 상술한 실시 예들이 단수 또는 복수의 구성 요소에 제한되는 것은 아니며, 복수로 표현된 구성 요소라 하더라도 단수로 구성되거나, 단수로 표현된 구성 요소라 하더라도 복수로 구성될 수 있다.However, the singular or plural expression is appropriately selected for the situation presented for convenience of description, and the above-described embodiments are not limited to the singular or plural component, and even if the component is expressed in plural, it is composed of a singular or , even a component expressed in a singular may be composed of a plural.
한편 발명의 설명에서는 구체적인 실시 예에 관해 설명하였으나, 다양한 실시 예들이 내포하는 기술적 사상의 범위에서 벗어나지 않는 한도 내에서 여러 가지 변형이 가능함은 물론이다.On the other hand, although specific embodiments have been described in the description of the invention, various modifications are possible without departing from the scope of the technical idea contained in the various embodiments.
그러므로 본 발명의 범위는 설명된 실시 예에 국한되어 정해져서는 아니되며 후술하는 청구범위뿐만 아니라 이 청구범위와 균등한 것들에 의해 정해져야 한다.Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims described below as well as the claims and equivalents.
도 1은 일실시예에 따른 반도체 소자를 설명하기 위한 도면이다. 1 is a view for explaining a semiconductor device according to an embodiment.
도 1을 참조하면, 일실시예에 따른 반도체 소자(100)는 티타늄-코발트 질화물(TiCoN) 내 코발트 함량의 제어를 통해 PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 구비할 수 있다. Referring to FIG. 1 , a semiconductor device 100 according to an exemplary embodiment may include a metal gate having a work function required for a PMOS region by controlling the cobalt content in titanium-cobalt nitride (TiCoN).
또한, 반도체 소자(100)는 PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 적용하여 낮은 문턱전압을 얻을 수 있으며, 열처리 이후에도 PMOS 영역에 대응되는 일함수를 안정적으로 유지할 수 있다. In addition, the semiconductor device 100 may obtain a low threshold voltage by applying a metal gate having a required work function to the PMOS region, and may stably maintain a work function corresponding to the PMOS region even after heat treatment.
또한, 반도체 소자(100)는 코발트 함량이 최적화된 티타늄-코발트 질화물에 기반한 금속 게이트를 구비하여 우수한 저항 특성(면저항 특성 및 비저항 특성)을 확보할 수 있다.In addition, the semiconductor device 100 includes a titanium-cobalt nitride-based metal gate with an optimized cobalt content, thereby securing excellent resistance characteristics (sheet resistance characteristics and resistivity characteristics).
이를 위해, 반도체 소자(100)는 기판(110)과, 기판(110) 상에 형성된 게이트 절연막(120) 및 게이트 절연막(120) 상에 형성된 금속 게이트(130)를 포함할 수 있다. To this end, the semiconductor device 100 may include a substrate 110 , a gate insulating layer 120 formed on the substrate 110 , and a metal gate 130 formed on the gate insulating layer 120 .
예를 들면, 반도체 소자(100)는 PMOS 트랜지스터로, 기판(110)은 N형 우물층(N-well)을 포함하고 N형 우물층 상면 중심부에 게이트 절연막(120)이 형성되며, 게이트 절연막(130) 상에 금속 게이트(130)가 형성될 수 있다. For example, the semiconductor device 100 is a PMOS transistor, the substrate 110 includes an N-type well layer (N-well), and the gate insulating film 120 is formed in the center of the upper surface of the N-type well layer, and the gate insulating film ( A metal gate 130 may be formed on 130 .
일측에 따르면, 기판(110)은 실리콘(silicon, Si), 산화알루미늄(aluminium oxide, Al2O3), 산화마그네슘(magnesium oxide, MgO), 탄화규소(silicon carbide, SiC), 질화규소(silicon nitride, SiN), 유리(glass), 석영(quartz), 사파이어(Sapphire), 그래파이트(graphite), 그래핀(graphene) 및 폴리이미드(polyimide, PI) 중 적어도 하나를 포함할 수 있으나, 바람직하게는 기판(100)은 실리콘 기판일 수 있다.According to one side, the substrate 110 is silicon (silicon, Si), aluminum oxide (aluminum oxide, Al 2 O 3 ), magnesium oxide (magnesium oxide, MgO), silicon carbide (silicon carbide, SiC), silicon nitride (silicon nitride) , SiN), glass, quartz, sapphire, graphite, graphene, and polyimide (PI) may include at least one of, but preferably a substrate (100) may be a silicon substrate.
또한, 게이트 절연막(120)은 하프늄 산화물(HfO2), 지르코늄 산화물(ZrO2), 티타늄 산화물(TiO2), 알루미늄 산화물(Al2O3) 및 탄탈럼 산화물(Ta2O5) 중 적어도 하나의 고유전율 물질(high-k dielectric material)을 포함할 수 있으나, 이에 한정되지 않고 상술한 물질 이외에 다양한 고유전율 물질을 포함할 수도 있다. In addition, the gate insulating layer 120 may include at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O 5 ). may include a high-k dielectric material, but is not limited thereto, and may include various high-k dielectric materials in addition to the above-described materials.
바람직하게는, 게이트 절연막(120)은 고유전율 물질로 하프늄 산화물을 포함할 수 있다. Preferably, the gate insulating layer 120 may include hafnium oxide as a high-k material.
구체적으로, 게이트 절연막(120)은 고유전율 물질을 포함하는 경우에, 실리콘 산화물과 비교하여 전기적으로 같은 등가 산화막 두께(equivalent oxide thickness, EOT)를 가지면서 물리적으로는 터널링이 방지되는 두꺼운 박막의 구현이 가능하며, 이를 통해 누설전류를 감소시킬 수 있다. Specifically, when the gate insulating layer 120 includes a high-k material, it has an equivalent oxide thickness (EOT) electrically equal to that of silicon oxide and physically prevents tunneling while implementing a thick thin film. This is possible, and through this, the leakage current can be reduced.
일측에 따르면, 게이트 절연막(120)은 실리콘 산화물에 대응되는 제1 절연층과, 적어도 하나의 고유전율 물질에 대응되는 제2 절연층의 복층 구조로 형성될 수 있다.According to one side, the gate insulating layer 120 may be formed in a multilayer structure of a first insulating layer corresponding to silicon oxide and a second insulating layer corresponding to at least one high-k material.
일측에 따르면, 복층 구조의 게이트 절연막(120)은 플라즈마를 이용한 건식 세정 공정을 통해 제1 절연층의 두께가 감소될 수 있다. According to one side, in the gate insulating layer 120 having a multilayer structure, the thickness of the first insulating layer may be reduced through a dry cleaning process using plasma.
구체적으로, 실리콘 기판 상에 고유전율 물질의 금속 산화막(일례로, HfO2)을 증착하고 후속 열처리(post-deposition annealing, PDA)를 수행하면, 후속 열처리 과정에서 산소가 확산하여 고유전율 물질의 금속 산화막과 실리콘 기판 사이에 실리콘 산화물(SiO2)이 형성될 수 있으며, 이러한 실리콘 산화물은 금속 산화막의 커패시턴스를 감소시키고 채널 전하 이동도를 저하시키는 문제를 야기할 수 있다. Specifically, when a metal oxide film (eg, HfO 2 ) of a high-k material is deposited on a silicon substrate and a post-deposition annealing (PDA) is performed, oxygen is diffused in the subsequent heat treatment process to the metal of the high-k material. Silicon oxide (SiO 2 ) may be formed between the oxide film and the silicon substrate, and such silicon oxide may cause a problem of reducing the capacitance of the metal oxide film and lowering the channel charge mobility.
이에, 일실시예에 따른 게이트 절연막(120)은 고유전율 물질에 대응되는 제2 절연층을 형성한 이후 플라즈마를 이용한 건식 세정 공정을 통해 활성화된 불소를 실리콘 산화물에 대응되는 제1 절연층과 반응시킬 수 있으며, 이를 통해 제1 절연층의 두께를 감소시켜 커패시턴스 증가 및 누설전류 감소의 효과를 얻을 수 있다. Accordingly, in the gate insulating layer 120 according to an embodiment, after forming the second insulating layer corresponding to the high-k material, activated fluorine through a dry cleaning process using plasma reacts with the first insulating layer corresponding to the silicon oxide Through this, the thickness of the first insulating layer can be reduced to obtain the effect of increasing the capacitance and reducing the leakage current.
보다 구체적으로, 게이트 절연막(120)은 고유전율 물질에 대응되는 제2 절연층을 형성한 이후 NF3와 NH3 가스를 이용한 건식 세정 공정을 수행하면, NH4F와 HF를 중간 산화물로 하여 활성화된 불소(F)가 형성되고, 불소가 제1 절연층(즉, HfO2층)을 통해 확산되어 제2 절연층(즉, SiO2층)과 반응하여 휘발성이 큰 SiFx를 형성할 수 있다. 이때 분해된 산소는 제1 절연층으로 확산되어 산소 결핍을 보충하여 줌으로써 제2 절연층은 그 두께가 감소하고 제1 절연층의 막질이 개선될 수 있다. More specifically, when a dry cleaning process using NF 3 and NH 3 gas is performed after forming the second insulating layer corresponding to the high-k material, the gate insulating layer 120 is activated using NH 4 F and HF as intermediate oxides. fluorine (F) is formed, and fluorine diffuses through the first insulating layer (ie, HfO 2 layer) and reacts with the second insulating layer (ie, SiO 2 layer) to form highly volatile SiFx. In this case, the decomposed oxygen is diffused into the first insulating layer to compensate for the oxygen deficiency, so that the thickness of the second insulating layer may be reduced and the film quality of the first insulating layer may be improved.
일실시예에 따른 금속 게이트(130)는 티타늄-코발트 질화물(TiCoN)을 구비하고, 티타늄-코발트 질화물 내의 코발트의 함량에 따라 일함수가 조절될 수 있다.The metal gate 130 according to an embodiment includes titanium-cobalt nitride (TiCoN), and the work function may be adjusted according to the content of cobalt in the titanium-cobalt nitride.
구체적으로, 금속 게이트(130)는 티타늄-코발트 질화물 내의 코발트의 함량이 높아질수록 높은 일함수 및 낮은 면저항을 갖을 수 있다. Specifically, the metal gate 130 may have a higher work function and a lower sheet resistance as the content of cobalt in the titanium-cobalt nitride increases.
다시 말해, 일실시예에 따른 금속 게이트(130)는 티타늄-코발트 질화물을 구비하되, 티타늄-코발트 질화물 내 티타늄 함량을 최적화함으로써, 기존 PMOS 트랜지스터의 금속 게이트에 구비된 TiAlN, TaAlN 및 TaSiN 박막의 면저항이 높다는 문제를 해결할 수 있다. In other words, the metal gate 130 according to an embodiment includes titanium-cobalt nitride, but by optimizing the titanium content in the titanium-cobalt nitride, the sheet resistance of the TiAlN, TaAlN and TaSiN thin films provided in the metal gate of the existing PMOS transistor. This high problem can be solved.
일측에 따르면, 금속 게이트(130)는 원자층 증착법(atomic layer deposition, ALD), 진공 증착법(vacuum deposition), 화학 기상 증착법(chemical vapor deposition), 물리 기상 증착법(physical vapor deposition), 스퍼터링(sputtering) 및 스핀 코팅(spincoating) 중 적어도 하나의 방법을 통해 형성될 수 있다.According to one side, the metal gate 130 is atomic layer deposition (ALD), vacuum deposition (vacuum deposition), chemical vapor deposition (chemical vapor deposition), physical vapor deposition (physical vapor deposition), sputtering (sputtering) And it may be formed through at least one method of spin coating (spincoating).
바람직하게는, 금속 게이트(130)는 원자층 증착법을 통해 티타늄-코발트 질화물 내의 티타늄, 코발트 및 질소의 함량이 제어될 수 있다. Preferably, in the metal gate 130 , the content of titanium, cobalt, and nitrogen in the titanium-cobalt nitride may be controlled through an atomic layer deposition method.
다시 말해, 금속 게이트(130)는 원자층 증착법을 이용한 티타늄-코발트 질화물 내의 티타늄, 코발트 및 질소의 조성 제어를 통해 일함수가 제어될 수 있다.In other words, the work function of the metal gate 130 may be controlled by controlling the composition of titanium, cobalt, and nitrogen in the titanium-cobalt nitride using the atomic layer deposition method.
일측에 따르면, 금속 게이트(130)는 원자층 증착법을 통해 4.8eV 내지 5.3eV의 일함수를 갖도록 코발트의 함량이 제어될 수 있다. 바람직하게는, 금속 게이트(130)는 PMOS 트랜지스터에 적합한 5.1eV의 일함수를 갖을 수 있다.According to one side, the cobalt content of the metal gate 130 may be controlled to have a work function of 4.8 eV to 5.3 eV through an atomic layer deposition method. Preferably, the metal gate 130 may have a work function of 5.1 eV suitable for a PMOS transistor.
일측에 따르면, 금속 게이트(130)는 티타늄-코발트 질화물 내에서 티타늄의 함량(CTi)이 13% ≤ CTi ≤ 36%이고, 코발트의 함량(Cco)이 0% < Cco ≤ 23%일 수 있다. According to one side, in the metal gate 130, the titanium content (C Ti ) in the titanium-cobalt nitride is 13% ≤ C Ti ≤ 36%, and the cobalt content (C co ) is 0% < C co ≤ 23% can be
또한, 금속 게이트(130)는 티타늄-코발트 질화물 내에서 티타늄 대비 코발트의 상대적 함량(CCo /( Ti +Co))이 0% < CCo /( Ti +Co) ≤ 64%일 수 있다. 바람직하게는 코발트의 상대적 함량(CCo /( Ti +Co))은 47% ≤ CCo /( Ti +Co) ≤ 64%일 수 있다.In addition, in the metal gate 130 , the relative content of cobalt relative to titanium in the titanium-cobalt nitride (C Co /( Ti +Co) ) may be 0% < C Co /( Ti +Co) ≤ 64%. Preferably, the relative content of cobalt (C Co /( Ti +Co) ) may be 47% ≤ C Co /( Ti +Co) ≤ 64%.
여기서, 코발트의 상대적 함량(CCo /( Ti +Co))은 티타늄의 원자수와 코발트의 원자수의 합(Ti+Co)에 대한 Co의 원자수를 의미할 수 있다. Here, the relative content of cobalt (C Co /( Ti + Co) ) may mean the number of atoms of Co to the sum of the number of atoms of titanium and the number of atoms of cobalt (Ti + Co).
도 2는 일실시예에 따른 반도체 소자에 구비된 금속 게이트의 조성비를 제어하는 예시를 설명하기 위한 도면이다. 2 is a view for explaining an example of controlling a composition ratio of a metal gate provided in a semiconductor device according to an embodiment.
도 2를 참조하면, 참조부호 200은 원자층 증착법을 이용한 증착 공정에서 증착 사이클비(subcycle ratio)(즉, 증착 비율)를 제어하여 티타늄-코발트 질화물(TiCoN) 기반의 금속 게이트 내 코발트의 상대적 함량(CCo /( Ti +Co))을 제어하는 예시를 도시한다. Referring to FIG. 2 , reference numeral 200 denotes a titanium-cobalt nitride (TiCoN) based metal gate by controlling a deposition subcycle ratio (ie, deposition ratio) in a deposition process using an atomic layer deposition method, so that the relative content of cobalt in the gate. An example of controlling (C Co /( Ti +Co) ) is shown.
참조부호 200에 따르면, 일실시예에 따른 반도체 소자의 티타늄-코발트 질화물 기반의 금속 게이트는 티타늄 질화물층(TiN layer)과 코발트층(Co layer)을 원자층 증착법을 이용하여 교대로 증착함으로써 형성될 수 있으며, 이때, 증착 비율(subcycle ratio)를 조절하여 티타늄-코발트 질화물 내의 코발트의 함량(CCo)을 0% < Cco ≤ 23%의 범위로 조절할 수 있고, 코발트의 상대적 함량(CCo /( Ti +Co))이 0% < CCo/(Ti+Co) ≤ 64%의 범위로 조절할 수도 있다.Referring to reference numeral 200, the titanium-cobalt nitride-based metal gate of the semiconductor device according to an embodiment may be formed by alternately depositing a titanium nitride layer (TiN layer) and a cobalt layer (Co layer) using an atomic layer deposition method. In this case, the content of cobalt in titanium-cobalt nitride (C Co ) can be adjusted in the range of 0% < C co ≤ 23% by adjusting the deposition ratio (subcycle ratio), and the relative content of cobalt (C Co / ( Ti + Co) ) may be adjusted in the range of 0% < C Co/(Ti+Co) ≤ 64%.
도 3은 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량 증가에 따른 비저항 특성을 설명하기 위한 도면이다. 3 is a view for explaining resistivity characteristics according to an increase in cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 3을 참조하면, 참조부호 300은 티타늄-코발트 질화물(TiCoN) 기반의 금속 게이트 내 코발트의 상대적 함량(CCo /( Ti +Co))의 변화에 따른 비저항(resistivity)의 변화를 도시한다. Referring to FIG. 3 , reference numeral 300 denotes a change in resistivity according to a change in the relative content of cobalt (C Co / ( Ti +Co) ) in a titanium-cobalt nitride (TiCoN)-based metal gate.
참조부호 300에 따르면, 티타늄 질화물층(TiN layer)에 대한 증착비율이 감소할수록 티타늄-코발트 질화물 기반의 금속 게이트 내의 코발트 함량이 증가하고, 티타늄과 질소의 함량은 감소할 수 있으며, 이때 코발트 함량이 증가함에 따라 티타늄-코발트 질화물 기반의 금속 게이트의 비저항이 감소하는 것을 확인할 수 있다. According to reference numeral 300, as the deposition rate for the titanium nitride layer (TiN layer) decreases, the cobalt content in the titanium-cobalt nitride based metal gate increases, and the content of titanium and nitrogen may decrease, in which case the cobalt content is As it increases, it can be seen that the resistivity of the titanium-cobalt nitride-based metal gate decreases.
도 4는 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량에 따른 커패시턴스 특성을 설명하기 위한 도면이다. 4 is a view for explaining capacitance characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 4를 참조하면, 참조부호 400은 티타늄-코발트 질화물(TiCoN) 기반의 금속 게이트 내 코발트의 상대적 함량(CCo /( Ti +Co))과 게이트 전압(Gate voltage)의 변화에 따른 커패시턴스(capacitance) 특성의 변화를 도시한다. Referring to FIG. 4 , reference numeral 400 denotes a titanium-cobalt nitride (TiCoN) based metal gate with a relative content of cobalt (C Co / ( Ti +Co ) ) and a capacitance according to a change in the gate voltage. ) shows the change in characteristics.
참조부호 400에 도시된 커패시턴스 특성의 변화는 기판 상에 실리콘 산화물(SiO2)과 하프늄 산화물(HfO2)이 복층으로 형성된 게이트 절연막 위에 티타늄-코발트 질화물 기반의 금속 게이트 전극을 증착하고, 금속 게이트 전극 상에 텅스텐을 증착한 후, 기판과 텅스텐의 양 끝단을 연결하여 측정하였다. The change in capacitance characteristic shown at reference numeral 400 is a silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ) on a substrate on a gate insulating film formed in a multilayered titanium-cobalt nitride-based metal gate electrode by depositing a metal gate electrode, and a metal gate electrode After tungsten was deposited on the tungsten, both ends of the substrate and the tungsten were connected and measured.
참조부호 400에 따르면, 티타늄-코발트 질화물 기반의 금속 게이트는 코발트의 상대적 함량(CCo /( Ti +Co)) 변화에 따른 산화물 커패시턴스(oxide capacitance : Cox)값의 차이가 거의 없는 것을 확인할 수 있다. According to reference numeral 400, it can be seen that the titanium-cobalt nitride-based metal gate has little difference in the oxide capacitance (Co x ) value according to the change in the relative content of cobalt (C Co /( Ti +Co) ). have.
이는, 티타늄-코발트 질화물 기반의 금속 게이트가 기존 TiAlN, TaAlN 등의 Al을 첨가한 전극에서 발생하는 산소 포집(oxygen scavenging) 현상에 의한 의도하지 않은 등가산화물두께(EOT) 변화를 방지할 수 있음을 의미한다. This indicates that the titanium-cobalt nitride-based metal gate can prevent unintentional change in equivalent oxide thickness (EOT) due to oxygen scavenging that occurs in the conventional Al-added electrodes such as TiAlN and TaAlN. it means.
도 5는 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량에 따른 평탄대역전압 특성을 설명하기 위한 도면이다. 5 is a diagram for explaining flat band voltage characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 5를 참조하면, 참조부호 500은 티타늄-코발트 질화물(TiCoN) 기반의 금속 게이트 내 코발트의 상대적 함량(CCo /( Ti +Co))의 변화에 따른 평탄대역전압(flatband voltage : VFB) 특성의 변화를 도시한다. Referring to FIG. 5 , reference numeral 500 denotes a titanium-cobalt nitride (TiCoN) based metal gate with a relative content of cobalt (C Co / ( Ti +Co ) ) according to a change in flatband voltage (V FB ) Shows the change in characteristics.
참조부호 500에 도시된 평탄대역전압 특성의 변화는 기판 상에 실리콘 산화물(SiO2)과 하프늄 산화물(HfO2)이 복층으로 형성된 게이트 절연막 위에 티타늄-코발트 질화물 기반의 금속 게이트 전극을 증착하고, 금속 게이트 전극 상에 텅스텐을 증착한 후, 기판과 텅스텐의 양 끝단을 연결하여 측정하였다. The change in the flat band voltage characteristic shown at reference numeral 500 is a silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ) on a substrate on a gate insulating film formed in a multilayered titanium-cobalt nitride-based metal gate electrode by depositing a metal gate electrode, After tungsten was deposited on the gate electrode, both ends of the substrate and the tungsten were connected and measured.
참조부호 500에 따르면, 티타늄-코발트 질화물 기반의 금속 게이트 내 코발트의 함량이 증가할수록 평탄대역전압이 상대적으로 양의 방향으로 쉬프트(positive shift)되는 것을 확인할 수 있다. Referring to reference numeral 500, it can be seen that the flat band voltage is relatively positively shifted as the content of cobalt in the titanium-cobalt nitride-based metal gate increases.
구체적으로, CMOS 공정 시 NMOS 트랜지스터는 음(negative)의 평탄대역전압 쉬프트가 요구 되어지고, PMOS 트랜지스터의 경우 양(positive)의 평탄대역전압 쉬프트가 요구 되어지는데, 일실시예에 따른 티타늄-코발트 질화물 기반의 금속 게이트는 코발트의 함량을 47% 이상으로 조절하는 것만으로 160 mV 정도의 양의 평탄대역전압 쉬프트를 구현할 수 있다. Specifically, in the CMOS process, a negative flat band voltage shift is required for an NMOS transistor, and a positive flat band voltage shift is required for a PMOS transistor. Titanium-cobalt nitride according to an embodiment The base metal gate can realize a flat band voltage shift of about 160 mV just by adjusting the cobalt content to 47% or more.
도 6은 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량에 따른 유효 일함수 특성을 설명하기 위한 도면이다. 6 is a diagram for explaining effective work function characteristics according to a cobalt content in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 6을 참조하면, 참조부호 600은 티타늄-코발트 질화물(TiCoN) 기반의 금속 게이트 내 코발트의 상대적 함량(CCo /( Ti +Co))의 변화에 따른 유효 일함수(effective work function) 특성을 VFB-EOT 플롯(plot) 방법을 통해 확인한 결과를 도시한다. Referring to FIG. 6 , reference numeral 600 denotes an effective work function according to a change in the relative content of cobalt (C Co / ( Ti +Co) ) in a titanium-cobalt nitride (TiCoN)-based metal gate. The results confirmed through the V FB -EOT plot method are shown.
참조부호 600에 따르면, 실리콘 산화물(SiO2)과 하프늄 산화물(HfO2) 두가지 게이트 절연막 위에 동일한 티타늄-코발트 질화물 기반의 금속 게이트를 사용하였을 때, 코발트의 상대적 함량(CCo /( Ti +Co))의 변화에 따른 유효 일함수는 차이가 거의 없이 유사한 비율로 증가하는 것을 확인할 수 있다. According to reference numeral 600, silicon oxide (SiO 2 ) and hafnium oxide (HfO 2 ) When the same titanium-cobalt nitride based metal gate is used on two gate insulating layers, the relative content of cobalt (C Co / ( Ti + Co) ), it can be seen that the effective work function increases at a similar rate with little difference.
다시 말해, 티타늄-코발트 질화물 기반의 금속 게이트는 두가지 산화물 모두에서 안정적으로 PMOS 트랜지스터에 적합한 일함수를 갖는 것을 확인할 수 있다. In other words, it can be confirmed that the titanium-cobalt nitride-based metal gate has a work function suitable for a PMOS transistor stably in both oxides.
도 7은 일실시예에 따른 반도체 소자에 구비된 금속 게이트에서 코발트 함량 및 열처리 온도에 따른 유효 일함수 특성을 설명하기 위한 도면이다.7 is a view for explaining effective work function characteristics according to a cobalt content and a heat treatment temperature in a metal gate provided in a semiconductor device according to an exemplary embodiment.
도 7을 참조하면, 참조부호 700은 티타늄-코발트 질화물(TiCoN) 기반의 금속 게이트를 구비하는 트랜지스터 소자를 포밍 가스(forming gas)(H2 5% + N2) 분위기에서 약 30분간 400℃ 및 500℃의 온도로 열처리 하였을 때 유효 일함수(effective work function) 특성을 도시한다. Referring to FIG. 7 , reference numeral 700 denotes a transistor device having a titanium-cobalt nitride (TiCoN)-based metal gate in a forming gas (H 2 5% + N 2 ) atmosphere for about 30 minutes at 400° C. and It shows effective work function characteristics when heat treated at a temperature of 500°C.
참조부호 700에 따르면, 티타늄-코발트 질화물 기반의 금속 게이트는 열처리 온도가 올라갈수록 유효 일함수의 감소가 발생하는 것을 확인할 수 있다. Referring to reference numeral 700, it can be seen that the effective work function of the titanium-cobalt nitride-based metal gate decreases as the heat treatment temperature increases.
그러나, 코발트의 상대적 함량(CCo /( Ti +Co))이 40% 이상에서는 감소한 유효 일함수도 5.0eV 이상을 유지하는 것을 확인할 수 있으며, 이는 티타늄-코발트 질화물 기반의 금속 게이트가 열처리 이후에도 PMOS 트랜지스터에 적합한 일함수를 갖는 것을 의미한다. However, when the relative content of cobalt (C Co /( Ti +Co) ) is 40% or more, it can be seen that the reduced effective work function also maintains 5.0 eV or more, which means that the titanium-cobalt nitride-based metal gate is PMOS even after heat treatment. It means having a work function suitable for the transistor.
도 8a 내지 도 8b는 일실시예에 따른 반도체 소자의 TEM 분석 결과를 설명하기 위한 도면이다. 8A to 8B are diagrams for explaining a TEM analysis result of a semiconductor device according to an exemplary embodiment.
도 8a 내지 도 8b를 참조하면, 참조부호 810은 코발트의 상대적 함량(CCo/(Ti+Co))이 47%인 티타늄-코발트 질화물(TiCoN) 기반의 금속 게이트를 형성한 후 열처리를 수행하지 않은 반도체 소자의 TEM(transmission electron microscope) 이미지를 도시하고, 참조부호 820은 참조부호 810과 동일한 방식으로 금속 게이트를 형성한 후 포밍 가스 분위기에서 약 30분간 500℃의 온도로 열처리한 반도체 소자의 TEM 이미지를 도시한다. 8A to 8B, reference numeral 810 denotes a titanium-cobalt nitride (TiCoN)-based metal gate having a relative content of cobalt (C Co/(Ti+Co) ) of 47%, and then heat treatment is not performed. A TEM (transmission electron microscope) image of a semiconductor device that has not been used is shown, and reference numeral 820 denotes a metal gate formed in the same manner as that of reference numeral 810, followed by heat treatment at a temperature of 500° C. for about 30 minutes in a forming gas atmosphere. TEM of a semiconductor device show the image.
또한, 참조부호 810 내지 820에서 'Si'는 기판, 'HfO2'는 게이트 절연막, 'TiCoN'은 금속 게이트, W는 저저항(low resistance) 물질로 캡핑층(capping layer)을 의미한다. In addition, in reference numerals 810 to 820, 'Si' denotes a substrate, 'HfO 2 ' denotes a gate insulating layer, 'TiCoN' denotes a metal gate, and W denotes a low resistance material and a capping layer.
참조부호 810 내지 820에 따르면, 일실시예에 따른 반도체 소자는 열처리 전후에 상태 변화(즉, 금속 게이트의 특성 변화)가 거의 나타나지 않는 것을 확인할 수 있으며, 이는 PMOS 반도체 소자의 제작 공정에서 열적 안정성 확보 및 신뢰성 향상에 도움이 된다는 것을 의미한다. Referring to reference numerals 810 to 820, it can be seen that, in the semiconductor device according to an embodiment, there is almost no state change (that is, a change in properties of the metal gate) before and after heat treatment, which ensures thermal stability in the manufacturing process of the PMOS semiconductor device. and to help improve reliability.
다시 말해, 일실시예에 따른 티타늄-코발트 질화물 기반의 금속 게이트는 전체적으로 낮은 면저항 및 비저항, 높은 일함수를 가지면서도 열안정성이 우수한 특성을 확보할 수 있다는 것을 확인할 수 있다. In other words, it can be confirmed that the titanium-cobalt nitride-based metal gate according to the embodiment can secure excellent thermal stability while having overall low sheet resistance, specific resistance, and high work function.
따라서, 일실시예에 따른 티타늄-코발트 질화물 기반의 금속 게이트는 높은 일함수를 요구하는 CMOS 소자의 PMOS 영역의 금속 게이트에 적용할 수 있으며, CMOS 소자 외에도 높은 일함수를 필요로하는 모든 반도체 소자의 게이트에 적용될 수도 있다. Therefore, the titanium-cobalt nitride-based metal gate according to an embodiment can be applied to a metal gate in the PMOS region of a CMOS device requiring a high work function, and is used for all semiconductor devices requiring a high work function in addition to the CMOS device. It can also be applied to the gate.
보다 구체적으로, 일실시예에 따른 티타늄-코발트 질화물 기반의 금속 게이트는 현재 배리어 금속(barrier metal)로 사용되고 있는 티타늄 질화물(TiN)과 탄탈럼 질화물(TaN) 등을 대체하여 적용되어, 비저항을 낮추는 용도로 사용될 수 있다. More specifically, the titanium-cobalt nitride-based metal gate according to an embodiment is applied to replace titanium nitride (TiN) and tantalum nitride (TaN), which are currently used as barrier metals, to lower specific resistance. can be used for
다시 말해, 일실시예에 따른 티타늄-코발트 질화물 기반의 금속 게이트는 게이트 물질 이외에도 낮은 비저항을 필요로 하는 다양한 소자에 활용될 수 있다. In other words, the titanium-cobalt nitride-based metal gate according to an embodiment may be used in various devices requiring low resistivity in addition to the gate material.
도 9는 일실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 도면이다. 9 is a view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment.
다시 말해, 도 9는 도 1 내지 도 8b를 통해 설명한 일실시예에 따른 반도체 소자의 제조방법을 설명하기 위한 도면으로, 이하에서 도 9를 통해 설명하는 내용 중 도 1 내지 도 8b를 통해 설명한 내용과 중복되는 설명은 생략 하기로 한다. In other words, FIG. 9 is a view for explaining a method of manufacturing a semiconductor device according to an exemplary embodiment described with reference to FIGS. 1 to 8B . Among the contents described with reference to FIG. 9 below, the contents described with reference to FIGS. 1 to 8B . A description that overlaps with will be omitted.
도 9를 참조하면, 910 단계에서 일실시예에 따른 반도체 소자의 제조방법은 기판 상에 게이트 절연막을 형성할 수 있다. Referring to FIG. 9 , in step 910 , in the method of manufacturing a semiconductor device according to an embodiment, a gate insulating layer may be formed on a substrate.
일측에 따르면, 기판은 실리콘(silicon, Si), 산화알루미늄(aluminium oxide, Al2O3), 산화마그네슘(magnesium oxide, MgO), 탄화규소(silicon carbide, SiC), 질화규소(silicon nitride, SiN), 유리(glass), 석영(quartz), 사파이어(Sapphire), 그래파이트(graphite), 그래핀(graphene) 및 폴리이미드(polyimide, PI) 중 적어도 하나를 포함할 수 있으나, 바람직하게는 기판은 실리콘 기판일 수 있다.According to one side, the substrate is silicon (silicon, Si), aluminum oxide (aluminum oxide, Al 2 O 3 ), magnesium oxide (magnesium oxide, MgO), silicon carbide (silicon carbide, SiC), silicon nitride (silicon nitride, SiN) , may include at least one of glass, quartz, sapphire, graphite, graphene, and polyimide (PI), but preferably the substrate is a silicon substrate can be
또한, 게이트 절연막은 하프늄 산화물(HfO2), 지르코늄 산화물(ZrO2), 티타늄 산화물(TiO2), 알루미늄 산화물(Al2O3) 및 탄탈럼 산화물(Ta2O5) 중 적어도 하나의 고유전율 물질(high-k dielectric material)을 포함할 수 있으나, 이에 한정되지 않고 상술한 물질 이외에 다양한 고유전율 물질을 포함할 수도 있다. In addition, the gate insulating layer has a high dielectric constant of at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O 5 ). It may include a high-k dielectric material, but is not limited thereto, and may include various high-k dielectric materials in addition to the above-described materials.
바람직하게는, 게이트 절연막은 고유전율 물질로 하프늄 산화물을 포함할 수 있다.Preferably, the gate insulating layer may include hafnium oxide as a high-k material.
다음으로, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 게이트 절연막 상에 티타늄-코발트 질화물(TiCoN)을 구비하는 금속 게이트를 형성할 수 있으며, 여기서 일실시예에 따른 금속 게이트는 티타늄-코발트 질화물 내의 코발트 물질의 함량에 따라 일함수가 조절될 수 있다. Next, in step 920 , in the method of manufacturing a semiconductor device according to an embodiment, a metal gate including titanium-cobalt nitride (TiCoN) may be formed on the gate insulating layer, wherein the metal gate according to the embodiment is titanium-cobalt nitride (TiCoN). The work function may be adjusted according to the content of the cobalt material in the cobalt nitride.
구체적으로, 금속 게이트는 티타늄-코발트 질화물 내의 코발트의 함량이 높아질수록 높은 일함수 및 낮은 면저항을 갖을 수 있다.Specifically, the metal gate may have a higher work function and a lower sheet resistance as the content of cobalt in the titanium-cobalt nitride increases.
일측에 따르면, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 원자층 증착법(atomic layer deposition, ALD), 진공 증착법(vacuum deposition), 화학 기상 증착법(chemical vapor deposition), 물리 기상 증착법(physical vapor deposition), 스퍼터링(sputtering) 및 스핀 코팅(spincoating) 중 적어도 하나의 방법을 통해 금속 게이트를 형성할 수 있다. According to one side, in step 920 , the method of manufacturing a semiconductor device according to an embodiment may include atomic layer deposition (ALD), vacuum deposition, chemical vapor deposition, and physical vapor deposition. The metal gate may be formed through at least one of vapor deposition, sputtering, and spin coating.
바람직하게는, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 원자층 증착법을 통해 티타늄-코발트 질화물 내의 티타늄, 코발트 및 질소의 함량을 제어할 수 있다. Preferably, in step 920, in the method of manufacturing a semiconductor device according to an embodiment, the content of titanium, cobalt, and nitrogen in the titanium-cobalt nitride may be controlled through an atomic layer deposition method.
보다 구체적으로, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 원자층 증착법을 통해 티타늄 질화물층(TiN layer)과 코발트층(Co layer)의 증착 비율을 조절하여 티타늄-코발트 질화물 내의 코발트 물질의 함량을 제어할 수 있다. More specifically, in step 920, the method of manufacturing a semiconductor device according to an embodiment adjusts the deposition ratio of a titanium nitride layer (TiN layer) and a cobalt layer (Co layer) through an atomic layer deposition method, thereby titanium-cobalt material in cobalt nitride. content can be controlled.
또한, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 TiCl4 전구체와 NH3 반응가스에 기초하는 원자층 증착법을 통해 티타늄 질화물층을 형성하고, Co(MeCp)2 전구체와 NH3 반응가스에 기초하는 원자층 증착법을 통해 코발트층을 형성할 수 있다.In addition, in step 920, in the method of manufacturing a semiconductor device according to an embodiment, a titanium nitride layer is formed through an atomic layer deposition method based on a TiCl 4 precursor and an NH 3 reaction gas, and a Co(MeCp) 2 precursor and an NH 3 reaction gas are formed. A cobalt layer can be formed through an atomic layer deposition method based on
일측에 따르면, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 티타늄-코발트 질화물 내에서 티타늄 물질의 함량(CTi)이 13% ≤ CTi ≤ 36%이 되고, 코발트 물질의 함량(Cco)이 0% < Cco ≤ 23%가 되도록 금속 게이트를 형성할 수 있다. According to one side, in the method of manufacturing a semiconductor device according to an embodiment in step 920, the content (C Ti ) of the titanium material in the titanium-cobalt nitride becomes 13% ≤ C Ti ≤ 36%, and the content of the cobalt material (C A metal gate may be formed such that co ) is 0% < C co ≤ 23%.
또한, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 티타늄-코발트 질화물 내에서 티타늄 물질 대비 코발트 물질의 상대적 함량(CCo /( Ti +Co))이 0% < CCo/(Ti+Co) ≤ 64%가 되도록 금속 게이트를 형성할 수 있다.In addition, in step 920 , in the method of manufacturing a semiconductor device according to an embodiment, the relative content (C Co /( Ti +Co) ) of the cobalt material relative to the titanium material in the titanium-cobalt nitride is 0% < C Co/(Ti+) A metal gate may be formed such that Co) ≤ 64%.
바람직하게는, 920 단계에서 일실시예에 따른 반도체 소자의 제조방법은 코발트 물질의 상대적 함량(CCo /( Ti +Co))이 47% ≤ CCo /( Ti +Co) ≤ 64%가 되도록 금속 게이트를 형성할 수 있다.Preferably, in step 920, the method of manufacturing a semiconductor device according to an embodiment is such that the relative content of the cobalt material (C Co /( Ti +Co) ) is 47% ≤ C Co /( Ti +Co) ≤ 64% A metal gate may be formed.
결국, 본 발명을 이용하면, 티타늄-코발트 질화물(TiCoN) 내 코발트 함량의 제어를 통해 PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 구비하는 반도체 소자를 제공할 수 있다. As a result, by using the present invention, it is possible to provide a semiconductor device having a metal gate having a work function required for the PMOS region by controlling the cobalt content in the titanium-cobalt nitride (TiCoN).
또한, PMOS 영역에 요구되는 일함수를 갖는 금속 게이트를 적용하여 낮은 문턱전압을 얻을 수 있으며, 열처리 이후에도 PMOS 영역에 대응되는 일함수를 안정적으로 유지할 수 있다.In addition, a low threshold voltage can be obtained by applying a metal gate having a required work function to the PMOS region, and the work function corresponding to the PMOS region can be stably maintained even after heat treatment.
또한, 코발트 함량이 최적화된 티타늄-코발트 질화물에 기반한 금속 게이트를 적용하여 우수한 저항 특성(면저항 특성 및 비저항 특성)을 확보할 수 있다. In addition, excellent resistance characteristics (sheet resistance characteristics and resistivity characteristics) can be secured by applying a titanium-cobalt nitride-based metal gate with an optimized cobalt content.
이상과 같이 실시예들이 비록 한정된 도면에 의해 설명되었으나, 해당 기술분야에서 통상의 지식을 가진 자라면 상기의 기재로부터 다양한 수정 및 변형이 가능하다. 예를 들어, 설명된 기술들이 설명된 방법과 다른 순서로 수행되거나, 및/또는 설명된 시스템, 구조, 장치, 회로 등의 구성요소들이 설명된 방법과 다른 형태로 결합 또는 조합되거나, 다른 구성요소 또는 균등물에 의하여 대치되거나 치환되더라도 적절한 결과가 달성될 수 있다.Although the embodiments have been described with reference to the limited drawings as described above, various modifications and variations are possible by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or the described components of the system, structure, apparatus, circuit, etc. are combined or combined in a different form than the described method, or other components Or substituted or substituted by equivalents may achieve an appropriate result.
그러므로, 다른 구현들, 다른 실시예들 및 특허청구범위와 균등한 것들도 후술하는 특허청구범위의 범위에 속한다.Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

Claims (12)

  1. 기판; Board;
    상기 기판 상에 형성된 게이트 절연막 및 a gate insulating film formed on the substrate; and
    상기 게이트 절연막 상에 형성되고, 티타늄-코발트 질화물(TiCoN)을 구비하는 금속 게이트A metal gate formed on the gate insulating layer and including titanium-cobalt nitride (TiCoN)
    를 포함하고, including,
    상기 금속 게이트는, The metal gate is
    상기 티타늄-코발트 질화물 내의 코발트의 함량에 따라 일함수가 조절되는 것을 특징으로 하는 The titanium- characterized in that the work function is adjusted according to the content of cobalt in the cobalt nitride
    반도체 소자.semiconductor device.
  2. 제1항에 있어서, According to claim 1,
    상기 금속 게이트는, The metal gate is
    상기 티타늄-코발트 질화물 내에서 티타늄 대비 코발트의 상대적 함량(CCo/(Ti+Co))이 0% < CCo/(Ti+Co) ≤ 64%인 것을 특징으로 하는 In the titanium-cobalt nitride, the relative content of cobalt compared to titanium (C Co/(Ti+Co) ) is 0% < C Co/(Ti+Co) ≤ 64%
    반도체 소자.semiconductor device.
  3. 제1항에 있어서, According to claim 1,
    상기 금속 게이트는, The metal gate is
    상기 티타늄-코발트 질화물 내에서 티타늄의 함량(CTi)이 13% ≤ CTi ≤ 36%이고, 코발트의 함량(Cco)이 0% < Cco ≤ 23%인 것을 특징으로 하는 In the titanium-cobalt nitride, the content of titanium (C Ti ) is 13% ≤ C Ti ≤ 36%, and the content of cobalt (C co ) is 0% < C co ≤ 23%
    반도체 소자.semiconductor device.
  4. 제1항에 있어서, According to claim 1,
    상기 금속 게이트는, The metal gate is
    4.8eV 내지 5.3eV의 상기 일함수를 갖는 것을 특징으로 하는 characterized in that it has the work function of 4.8 eV to 5.3 eV
    반도체 소자.semiconductor device.
  5. 제1항에 있어서, According to claim 1,
    상기 게이트 절연막은,The gate insulating film is
    하프늄 산화물(HfO2), 지르코늄 산화물(ZrO2), 티타늄 산화물(TiO2), 알루미늄 산화물(Al2O3) 및 탄탈럼 산화물(Ta2O5) 중 적어도 하나의 고유전율 물질(high-k dielectric material)을 포함하는 High-k material (high-k) of at least one of hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), titanium oxide (TiO 2 ), aluminum oxide (Al 2 O 3 ), and tantalum oxide (Ta 2 O 5 ) dielectric material)
    반도체 소자.semiconductor device.
  6. 제5항에 있어서, 6. The method of claim 5,
    상기 게이트 절연막은, The gate insulating film is
    실리콘 산화물에 대응되는 제1 절연층과, 상기 적어도 하나의 고유전율 물질에 대응되는 제2 절연층의 복층 구조로 형성되는 것을 특징으로 하는 characterized in that it is formed in a multilayer structure of a first insulating layer corresponding to silicon oxide and a second insulating layer corresponding to the at least one high-k material
    반도체 소자.semiconductor device.
  7. 기판 상에 게이트 절연막을 형성하는 단계 및 forming a gate insulating film on the substrate; and
    상기 게이트 절연막 상에 티타늄-코발트 질화물(TiCoN)을 구비하는 금속 게이트를 형성하는 단계forming a metal gate including titanium-cobalt nitride (TiCoN) on the gate insulating layer;
    를 포함하고, including,
    상기 금속 게이트는, The metal gate is
    상기 티타늄-코발트 질화물 내의 코발트의 함량에 따라 일함수가 조절되는 것을 특징으로 하는 The titanium- characterized in that the work function is adjusted according to the content of cobalt in the cobalt nitride
    반도체 소자의 제조방법.A method of manufacturing a semiconductor device.
  8. 제7항에 있어서, 8. The method of claim 7,
    상기 금속 게이트를 형성하는 단계는, Forming the metal gate comprises:
    상기 티타늄-코발트 질화물 내에서 티타늄 대비 코발트의 상대적 함량(CCo/(Ti+Co))이 0% < CCo /( Ti +Co) ≤ 64%가 되도록 상기 금속 게이트를 형성하는 것을 특징으로 하는 In the titanium-cobalt nitride, the relative content of cobalt compared to titanium (C Co/(Ti+Co) ) is 0% < C Co /( Ti +Co) ≤ 64%, characterized in that the metal gate is formed
    반도체 소자의 제조방법.A method of manufacturing a semiconductor device.
  9. 제7항에 있어서, 8. The method of claim 7,
    상기 금속 게이트를 형성하는 단계는, Forming the metal gate comprises:
    상기 티타늄-코발트 질화물 내에서 티타늄의 함량(CTi)이 13% ≤ CTi ≤ 36%이 되고, 코발트의 함량(Cco)이 0% < Cco ≤ 23%가 되도록 상기 금속 게이트를 형성하는 것을 특징으로 하는 In the titanium-cobalt nitride, the content of titanium (C Ti ) becomes 13% ≤ C Ti ≤ 36%, and the content of cobalt (C co ) forms the metal gate such that 0% < C co ≤ 23% characterized by
    반도체 소자의 제조방법.A method of manufacturing a semiconductor device.
  10. 제7항에 있어서, 8. The method of claim 7,
    상기 금속 게이트를 형성하는 단계는, Forming the metal gate comprises:
    원자층 증착법(atomic layer deposition, ALD)을 통해 상기 티타늄-코발트 질화물 내의 코발트의 함량을 제어하는 것을 특징으로 하는Characterized in controlling the content of cobalt in the titanium-cobalt nitride through atomic layer deposition (ALD)
    반도체 소자의 제조방법.A method of manufacturing a semiconductor device.
  11. 제10항에 있어서, 11. The method of claim 10,
    상기 금속 게이트를 형성하는 단계는,Forming the metal gate comprises:
    상기 원자층 증착법을 통해 티타늄 질화물층(TiN layer)과 코발트층(Co layer)의 증착 비율을 조절하여 상기 티타늄-코발트 질화물 내의 코발트의 함량을 제어하는 것을 특징으로 하는Controlling the deposition ratio of the titanium nitride layer (TiN layer) and the cobalt layer (Co layer) through the atomic layer deposition method to control the content of cobalt in the titanium-cobalt nitride
    반도체 소자의 제조방법.A method of manufacturing a semiconductor device.
  12. 제11항에 있어서, 12. The method of claim 11,
    상기 금속 게이트를 형성하는 단계는,Forming the metal gate comprises:
    TiCl4 전구체와 NH3 반응가스에 기초하는 상기 원자층 증착법을 통해 상기 티타늄 질화물층을 형성하고, Co(MeCp)2 전구체와 상기 NH3 반응가스에 기초하는 상기 원자층 증착법을 통해 상기 코발트층을 형성하는 것을 특징으로 하는The titanium nitride layer is formed through the atomic layer deposition method based on the TiCl 4 precursor and the NH 3 reaction gas, and the cobalt layer is formed through the atomic layer deposition method based on the Co(MeCp) 2 precursor and the NH 3 reaction gas. characterized by forming
    반도체 소자의 제조방법.A method of manufacturing a semiconductor device.
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