WO2022218253A1 - 图像块的处理方法、装置、电子设备、可读存储介质 - Google Patents

图像块的处理方法、装置、电子设备、可读存储介质 Download PDF

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Publication number
WO2022218253A1
WO2022218253A1 PCT/CN2022/086096 CN2022086096W WO2022218253A1 WO 2022218253 A1 WO2022218253 A1 WO 2022218253A1 CN 2022086096 W CN2022086096 W CN 2022086096W WO 2022218253 A1 WO2022218253 A1 WO 2022218253A1
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Prior art keywords
image block
overlapping area
image
coordinates
module
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PCT/CN2022/086096
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English (en)
French (fr)
Inventor
张兴进
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维沃移动通信有限公司
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Publication of WO2022218253A1 publication Critical patent/WO2022218253A1/zh

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0625—Power saving in storage systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0638—Organizing or formatting or addressing of data
    • G06F3/064—Management of blocks
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the present application relates to the technical field of data transmission, and in particular, to an image block processing method, an image block processing apparatus, an electronic device, a readable storage medium, and a chip.
  • the image distortion correction algorithm often needs to be processed in units of image blocks to obtain a corrected corrected image.
  • the cache memory can only write the image into the DDR (Double Rate Synchronous Dynamic Random Access Memory) first, then read the required image block from the DDR, and send it to the memory for interpolation to obtain the corrected image.
  • DDR Double Rate Synchronous Dynamic Random Access Memory
  • the cache memory enables direct memory access (DMA)
  • DMA direct memory access
  • the image blocks read from the DDR may overlap due to image distortion, which will result in direct memory access to duplicate image data, which gives the DDR bus Bandwidth causes a certain pressure, and there is a waste of power consumption.
  • Embodiments of the present application provide an image block processing method, apparatus, electronic device, and readable storage medium, which can effectively reduce the bandwidth and power consumption required for reading, and reduce the memory requirement for computing power.
  • an embodiment of the present application provides an image block processing method, including:
  • the first read request includes acquiring the coordinates of the first image block and the coordinates of the second image block in the target image;
  • an image block processing apparatus including:
  • a first request module configured to receive a first read request for the target image, where the first read request includes acquiring the coordinates of the first image block and the coordinates of the second image block in the target image;
  • a calculation module for obtaining the overlapping area of the first image block and the second image block according to the coordinates of the first image block and the coordinates of the second image block;
  • the writing module is configured to write the pixel block data corresponding to the non-overlapping area in the first image block into the cache module according to the overlapping area, or give up writing the pixel block data corresponding to the first image block into the cache module.
  • an embodiment of the present application provides an electronic device, including a processor, a memory, and a program or instruction stored in the memory and executable on the processor.
  • the program or instruction is executed by the processor, the first aspect is implemented Provides the steps of the image block processing method.
  • an embodiment of the present application provides a readable storage medium on which a program or an instruction is stored, and when the program or instruction is executed by a processor, implements the steps of the image block processing method provided in the first aspect .
  • an embodiment of the present application provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled with the processor, and the processor is used to run a program or an instruction to implement the image block processing method provided in the first aspect. step.
  • pixels are read from the memory module (DDR) according to the coordinates of each image block of the target image that needs to be processed in the received first read request. block data, and write the pixel block data into the cache module for use in subsequent processing.
  • a second image block adjacent to the first image block is determined by using the coordinates, and an overlapping area between adjacent image blocks is determined by using the coordinates of the first image block and the coordinates of the second image block. If there is an overlapping area, it means that there is a problem of repeated writing of some pixel block data. At this time, the pixel block data corresponding to the non-overlapping area in the first image block is written into the cache module through the overlapping area.
  • FIG. 1 shows one of the flow charts of an image block processing method according to an embodiment of the present application
  • FIG. 2 shows the second flowchart of a method for processing an image block according to an embodiment of the present application
  • FIG. 3 shows the third flowchart of a method for processing an image block according to an embodiment of the present application
  • FIG. 4 shows a fourth flowchart of a method for processing an image block according to an embodiment of the present application
  • Fig. 5 shows the fifth flow chart of the image block processing method according to an embodiment of the present application
  • FIG. 6 shows a schematic structural diagram of a cache module according to an embodiment of the present application.
  • FIG. 7 shows a structural block diagram of an apparatus for processing an image block according to an embodiment of the present application.
  • FIG. 8 shows a logical block diagram of an apparatus for processing image blocks according to an embodiment of the present application
  • FIG. 9 shows one of the structural block diagrams of an electronic device according to an embodiment of the present application.
  • FIG. 10 shows the second structural block diagram of an electronic device according to an embodiment of the present application.
  • FIG. 11 shows a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application.
  • the following describes an image block processing method, an image block processing apparatus, an electronic device, a readable storage medium, and a chip according to some embodiments of the present application with reference to FIGS. 1 to 11 .
  • an image block processing method including:
  • Step 102 receiving a first read request to the target image
  • the first read request includes acquiring the coordinates of the first image block and the coordinates of the second image block in the target image.
  • the lens module of the electronic device is usually configured with default lens distortion parameters.
  • image processing such as correction processing
  • the image processor can calculate the processed image according to the distortion algorithm and these lens distortion parameters.
  • the coordinates of each image block in the corrected image corresponding to the image block in the target image to be processed are corrected, and the image processor generates a first read request according to the coordinates to read the required pixel block data in the memory module.
  • the coordinates of the image block are the coordinates of any pixel in the image block in the entire target image.
  • all image blocks in the target image use pixels in the same position to determine the coordinates of the image blocks. For example, set the coordinates of the image block to the coordinates of the upper left pixel of the image block in the target image.
  • the coordinate dimensions of the image block are the width and height of the image block.
  • Step 104 according to the coordinates of the first image block and the coordinates of the second image block, obtain the overlapping area of the first image block and the second image block;
  • Step 106 write the pixel block data corresponding to the non-overlapping area in the first image block into the cache module, or give up writing the pixel block data corresponding to the first image block into the cache module.
  • pixel blocks are read from the memory module (DDR) according to the coordinates of each image block of the target image to be processed in the received first read request. data, and write the pixel block data into the cache module for use in subsequent processing.
  • a second image block adjacent to the first image block is determined by using the coordinates, and an overlapping area between adjacent image blocks is determined by using the coordinates of the first image block and the coordinates of the second image block. If there is an overlapping area, it means that there is a problem of repeated writing of some pixel block data. At this time, the pixel block data corresponding to the non-overlapping area in the first image block is written into the cache module through the overlapping area.
  • the memory module (DDR) is used to store the data required for the operation of the electronic device.
  • the cache module can be random access memory (RAM), such as static random access memory (SRAM), which includes multiple memory banks (banks), so that they can be read from the memory banks simultaneously in one clock cycle Multiple pixel block data.
  • RAM random access memory
  • SRAM static random access memory
  • the target image that needs to be corrected is processed by the distortion correction algorithm to obtain a corrected image, wherein the corrected image is composed of multiple image blocks, that is, each image block in the corrected image is It is obtained by algorithm from the corresponding area in the target image. Due to the distortion of the image, the size and coordinates of the corresponding area in the target image are different from the image blocks of the target image, so the adjacent areas in the target image corresponding to the image blocks of the adjacent corrected image may overlap.
  • step 106 writing the pixel block data corresponding to the non-overlapping area in the first image block into the cache module according to the overlapping area, including:
  • Step 202 when the size of the overlapping area is smaller than the size of the first image block, determine a non-overlapping area in the first image block according to the overlapping area;
  • Step 204 read pixel block data corresponding to the non-overlapping area from the memory module
  • Step 206 Write the pixel block data corresponding to the non-overlapping area into the cache module.
  • the positional relationship (coordinates) of the first image block and the second image block it can be determined whether there is an overlapping area between the two image blocks before and after, and the size of the overlapping area can be determined. If the size of the overlapping area is smaller than the size of the first image block, it means that the second image block only contains part of the pixel block data of the first image block, or does not contain the pixel block data of the first image block at all.
  • the non-overlapping area in the first image block is determined by the overlapping area, and the pixel block data corresponding to the non-overlapping area in the memory module is written into the cache module according to the size of the non-overlapping area. .
  • the required data can be read from the memory module through a memory bus (cacheline).
  • the second image block may be a previous image block or a subsequent image block of the first image block.
  • the second image block does not completely cover the first image block, indicating that the first image block needs to be converted from the DDR Then switch to the next image block in RAM to fetch the number.
  • step 106 abandoning writing the pixel block data corresponding to the first image block into the cache module, including:
  • Step 302 in the case that the size of the overlapping area is equal to the size of the first image block, give up reading the pixel block data corresponding to the first image block from the memory module, and give up writing the pixel block data corresponding to the first image block into the cache module.
  • the size of the overlapping area can be determined. If the size of the overlapping area is not smaller than the size of the first image block, that is, the size of the overlapping area is equal to the size of the first image block, it means that the second image block contains all the pixel block data of the first image block, that is, the second image block contains all the pixel block data of the first image block.
  • all pixel block data of the first image block can be written into the cache module, then after receiving the first read request, it will give up reading all the pixels corresponding to the first image block from the memory module block data, and at the same time, all pixel block data corresponding to the first image block will not be written into the cache module. This ensures that when the target image is cached, it is avoided to repeatedly read the same pixel block data from the memory module, thereby minimizing the bandwidth waste caused by the displacement of the image block in the y-direction, and reducing the memory module's bandwidth. power consumption.
  • the size of the overlapping area is equal to the size of the first image block, that is, the second image block completely covers the first image block. If the pixel block data corresponding to the second image block has been written into the RAM, the first image block data already exists in the RAM completely. At this time, it is not necessary to read the pixel block data corresponding to the first image block from the DDR and write it into the RAM. However, tag information is still required when reading pixel block data corresponding to the image block from RAM, so as to instruct to fetch data from the second image block when reading the first image block from RAM.
  • step 204 read pixel block data corresponding to the non-overlapping area from the memory module, including:
  • Step 402 according to the size of the non-overlapping area, the preset read size and the preset row coordinate threshold, determine the target row of the first image block and the target row coordinates corresponding to the target row in the memory module;
  • the preset read size is used to align the data coordinates to avoid reading incomplete data.
  • the size of the pixel block data to be read in the image block is determined according to the sum of the size of the non-overlapping area and the preset read size. Read the coordinates. Therefore, when determining the pixel block data to be read, the calculation is performed according to the sum of the size of the non-overlapping area and the preset reading size, so that the pixel block data actually read out is more than the pixels included in the size range of the non-overlapping area. Block data, avoid data loss caused by problems in the reading process and affect subsequent data writing, prevent the target image cache from being incomplete, and enhance the read fault tolerance rate.
  • the width of the overlapping area It is MAX(0, (x1+w1+x_ext-x2)), and the height of the overlap is MAX(0, (y1+h1+y_ext-y2)). If the width and height of the overlapping area are equal to the width and height of the first image block, then The first image block is hit.
  • x_ext refers to the prefetch part of the cache module, that is, the preset read size, which is calculated according to the preset read size, so that the actual read pixel block data is more than the pixels included in the size range of the non-overlapping area. block data. In this way, data loss caused by a problem during the reading process is avoided and subsequent data writing is affected, the target image cache is prevented from being incomplete, and the read fault tolerance rate is enhanced.
  • a row coordinate threshold is preconfigured, and the read coordinate and row coordinate threshold are used to take multiple adjacent pixel block data with a small distance between the coordinates as a target row, that is, multiple adjacent pixel block data in one row of the image block.
  • the row coordinate threshold can also be adjusted according to the configuration of the memory.
  • the cacheline is dynamically adaptive. Since too small AXIburst is not friendly to DDR, the cacheline here gives a minimum limit.
  • the maximum pixel block read out is 4 ⁇ 4 as an example.
  • the SRAMarray (cache module) is divided into 8 banks (memory bank of the cache module), 2 banks in the horizontal direction and 4 banks in the vertical direction, and the storage bit width of each bank is 4 pixel bit widths.
  • the lower 2 bits of the Y-axis coordinate in the read and write coordinates select 4 rows of banks in the vertical direction, so that 8 pixels can be written in each clock cycle, and the coordinates of these 8 pixels in the target image are aligned.
  • 4 pixels are written into the bank in the left column, and the lower 4 pixels are written into the bank in the right column.
  • the write address of each bank is spliced by the X and Y axis coordinates in the label information.
  • the area required for the SRAM (the size of the four largest image blocks) can be reduced.
  • Step 404 generating a second read request according to the target row and the target row coordinates
  • Step 406 Read pixel block data corresponding to the non-overlapping area from the memory module according to the second read request.
  • a second read request is generated according to the target row and the target row coordinates, so as to read the pixel block data of the required non-overlapping area from the memory module.
  • the pixel block data corresponding to the read out non-overlapping area is written into the cache module, so that when the target image is processed, the required pixel block data can be obtained from the cache module at any time.
  • a method for processing an image block further includes:
  • Step 502 generating label information of the first image block according to the overlapping area
  • the tag information includes: the size of the overlapping area, the size of the first image block, and the read and write coordinates of the first image block in the cache module.
  • the label information of the first image block is generated according to the overlapping area, so as to provide overlap for writing and reading of the cache module
  • the cache module may include multiple memory banks, and the target memory bank for writing pixel block data may be determined according to the width and height of the pixel block data read from the memory module as required. For example, take the pixel block read out with a maximum size of 4 ⁇ 4 as an example.
  • the SRAMarray (composed of multiple SRAMs) is divided into 8 banks, 2 banks in the horizontal direction and 4 banks in the vertical direction, and the SRAM bit width of each bank is 4 pixel bit widths. Among them, the four rows of banks in the vertical direction are the first row of bank00 and bank01, the second row of bank10 and bank11, the third row of bank20 and bank21, and the fourth row of bank30 and bank31.
  • p0, p1, p2, and p3 in FIG. 6 refer to a storage bit width of 4 pixels.
  • read and write information is calculated according to the target row coordinates of the DDR to be read in the first image block.
  • Each first read request generates a set of tag information, and the tag information includes whether it is hit or not, that is, whether the overlap size is 0, the width and height of the first image block, the width and height of the overlapping area of the first image block and the second image block, and the read and write coordinates in the SRAM (cache module).
  • Step 504 receiving the third read request for the target pixel block data of the first image block in the cache module
  • the third read request includes the pixel bit width and target coordinates indicating the target pixel block data.
  • Step 506 output the target pixel block data from the cache module according to the pixel bit width, target coordinates and tag information in the third read request.
  • a third read request for the target pixel block data of the first image block in the cache module exists is received.
  • the target pixel block data is read and output from the cache module using the storage bit width, target coordinates and the tag information generated by the cache target image indicated by the third read request.
  • the image processor For subsequent image processors to process the target pixel block data according to the specified algorithm. For example, to correct the image, the image processor corrects the target pixel block data according to the correction algorithm to obtain the corrected corrected image block, and then the corrected image can be output through the corrected image block.
  • an image block processing apparatus 700 including: a first request module 702, where the first request module 702 is configured to receive a first reading of a target image request, the first read request includes acquiring the coordinates of the first image block and the coordinates of the second image block in the target image; the calculation module 704, the calculation module 704 is used to obtain the coordinates of the first image block and the coordinates of the second image block according to the , to obtain the overlapping area of the first image block and the second image block; the writing module 706, the writing module 706 is used to write the pixel block data corresponding to the non-overlapping area in the first image block into the cache module according to the overlapping area, Or give up writing the pixel block data corresponding to the first image block into the cache module.
  • the calculation module 704 is further configured to determine the non-overlapping area in the first image block according to the overlapping area when the size of the overlapping area is smaller than the size of the first image block; the processing of the image block
  • the device 700 further includes: an access module 708, the access module 708 is used to read the pixel block data corresponding to the non-overlapping area from the memory module; the writing module 706 is further used to write the pixel block data corresponding to the non-overlapping area into the cache module .
  • the writing module 706 is further configured to give up reading the pixel block data corresponding to the first image block from the memory module, and give up writing the first image block when the size of the overlapping area is equal to the size of the first image block.
  • the pixel block data corresponding to the image block is written into the cache module.
  • the calculation module 704 is further configured to determine the target row of the first image block and the target in the memory module according to the size of the non-overlapping area, the preset read size and the preset row coordinate threshold.
  • the image block processing device 700 further includes: a first generation module 710, the first generation module 710 is configured to generate a second read request according to the target row and the target row coordinates; an access module 708, an access module 708 is further configured to read pixel block data corresponding to the non-overlapping area from the memory module according to the second read request.
  • the image block processing apparatus further includes: a second generation module, the second generation module is configured to generate label information of the first image block according to the overlapping area, and the label information includes: the size of the overlapping area, the size of the first image block Size and read/write coordinates of the first image block in the cache module;
  • the second request module is configured to receive a third read request for the target pixel block data of the first image block in the cache module, where the third read request includes the storage bit width and target coordinates of the target pixel block data;
  • the output module is used for outputting the target pixel block data from the cache module according to the storage bit width, target coordinates and label information.
  • each module of the image block processing apparatus 700 implements the steps of the image block processing method in any of the above embodiments when performing their respective functions. Therefore, the image block processing apparatus 700 also includes any of the above-mentioned steps. All the beneficial effects of the image block processing apparatus and method in one embodiment will not be repeated here.
  • the image block processing apparatus in this embodiment of the present application may be an apparatus, or may be a component, an integrated circuit, or a chip in a terminal.
  • the apparatus may be a mobile electronic device or a non-mobile electronic device.
  • the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant).
  • UMPC ultra-mobile personal computer
  • netbook or a personal digital assistant
  • non-mobile electronic devices can be servers, network attached storage (Network Attached Storage, NAS), personal computer (personal computer, PC), television (television, TV), teller machine or self-service machine, etc., this application Examples are not specifically limited.
  • Network Attached Storage NAS
  • personal computer personal computer, PC
  • television television
  • teller machine or self-service machine etc.
  • the image block processing apparatus in this embodiment of the present application may be an apparatus having an operating system.
  • the operating system may be an Android (Android) operating system, an ios operating system, or other possible operating systems, which are not specifically limited in the embodiments of the present application.
  • an electronic device 1000 including: a processor 1004, a memory 1002, and programs or instructions stored in the memory 1002 and executable on the processor 1004, When the program or instruction is executed by the processor 1004, the steps of the image block processing method provided in any of the above embodiments are implemented. Therefore, the electronic device 1000 includes all of the image block processing methods provided in any of the above embodiments. The beneficial effects will not be repeated here.
  • the memory 1002 further includes: a memory module 1006, connected to the processor 1004; a cache module 1008, connected to the processor 1004; the electronic device 1000 further includes: an image processor 1010, connected with the memory 1002 and the processor 1004, the image processor 1010 is used for processing the target image.
  • the cache module 1008 may include a first cache module and a second cache module.
  • the first cache module is used for storing data.
  • the second cache module is used to cache tag information. If the first image block is hit, that is, the size of the overlapping area is equal to the size of the first image block, at this time, it is not necessary to read the corresponding pixel block data from the memory module 1006 and write it into the first cache module, but it is necessary to The tag information is written into the second cache module, so that when the first image block is read, it can be read according to the second image block.
  • the second buffer module may adopt a first-in, first-out (FIFO) principle.
  • the electronic device to be electronic in this embodiment of the present application may be a mobile electronic device or a non-mobile electronic device.
  • the mobile electronic device may be a mobile phone, a tablet computer, a notebook computer, a palmtop computer, an in-vehicle electronic device, a wearable device, an ultra-mobile personal computer (UMPC), a netbook, or a personal digital assistant (personal digital assistant).
  • assistant, PDA personal digital assistant
  • the non-mobile electronic device can be a server, a network attached storage module (Network Attached Storage, NAS), a personal computer (personal computer, PC), a television (television, TV), an ATM or a self-service machine, etc.
  • NAS Network Attached Storage
  • NAS Network Attached Storage
  • personal computer personal computer
  • TV television
  • ATM self-service machine
  • FIG. 11 is a schematic diagram of a hardware structure of an electronic device 1200 implementing an embodiment of the present application.
  • the electronic device 1200 includes but is not limited to: a radio frequency unit 1202, a network module 1204, an audio output unit 1206, an input unit 1208, a sensor 1210, a display unit 1212, a user input unit 1214, an interface unit 1216, a memory 1218, a processor 1220 and other components .
  • the electronic device 1200 may also include a power source (such as a battery) for supplying power to various components, and the power source may be logically connected to the processor 1220 through a power management system, so as to manage charging, discharging, and power management through the power management system. consumption management and other functions.
  • a power source such as a battery
  • the structure of the electronic device shown in FIG. 11 does not constitute a limitation to the electronic device, and the electronic device may include more or less components than shown, or combine some components, or arrange different components.
  • electronic devices include, but are not limited to, mobile terminals, tablet computers, notebook computers, handheld computers, vehicle-mounted electronic devices, wearable devices, and pedometers.
  • the processor 1220 is configured to receive a first read request for the target image, where the first read request includes acquiring the coordinates of the first image block and the coordinates of the second image block in the target image; according to the coordinates of the first image block and the coordinates of the second image block to obtain the overlapping area of the first image block and the second image block; according to the overlapping area, write the pixel block data corresponding to the non-overlapping area in the first image block into the cache module, or give up the The pixel block data corresponding to an image block is written into the cache module.
  • the processor 1220 is further configured to, when the size of the overlapping area is smaller than the size of the first image block, determine the non-overlapping area in the first image block according to the overlapping area; read the non-overlapping area from the memory module The corresponding pixel block data; write the pixel block data corresponding to the non-overlapping area into the cache module.
  • the processor 1220 is further configured to, in the case that the size of the overlapping area is equal to the size of the first image block, give up reading the pixel block data corresponding to the first image block from the memory module, and give up reading the pixel block data corresponding to the first image block from the memory module.
  • the pixel block data corresponding to the block is written into the cache module.
  • the processor 1220 is further configured to determine the target row of the first image block and the target row coordinates corresponding to the target row in the memory module according to the size of the non-overlapping area, the preset reading size and the preset row coordinate threshold; The target row and the target row coordinates are used to generate a second read request; the pixel block data corresponding to the non-overlapping area is read from the memory module according to the second read request.
  • the processor 1220 is further configured to generate label information of the first image block according to the overlapping area, where the label information includes: the size of the overlapping area, the size of the first image block, and the read and write coordinates of the first image block in the cache module ; Receive the 3rd read request for the target pixel block data of the first image block in the cache module, the 3rd read request includes the storage bit width and target coordinates of the target pixel block data; According to the storage bit width , the target coordinates and the label information, and output the target pixel block data from the cache module.
  • the radio frequency unit 1202 may be used to send and receive information or send and receive signals during a call, and specifically, receive downlink data from the base station or send uplink data to the base station.
  • the radio frequency unit 1202 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like.
  • the network module 1204 provides users with wireless broadband Internet access, such as helping users to send and receive emails, browse web pages, and access streaming media.
  • the audio output unit 1206 may convert audio data received by the radio frequency unit 1202 or the network module 1204 or stored in the memory 1218 into audio signals and output as sound. Also, the audio output unit 1206 may also provide audio output related to a specific function performed by the electronic device 1200 (eg, call signal reception sound, message reception sound, etc.).
  • the audio output unit 1206 includes a speaker, a buzzer, a receiver, and the like.
  • the input unit 1208 is used to receive audio or video signals.
  • the input unit 1208 may include a graphics processor (Graphics Processing Unit, GPU) 5082 and a microphone 5084.
  • the graphics processor 5082 monitors the pixels of a still picture or video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. block data for processing.
  • the processed image frames may be displayed on the display unit 1212, or stored in the memory 1218 (or other storage medium), or transmitted via the radio frequency unit 1202 or the network module 1204.
  • the microphone 5084 can receive sound, and can process the sound into audio data, and the processed audio data can be converted into a format that can be sent to a mobile communication base station via the radio frequency unit 1202 for output in the case of a phone call mode.
  • the electronic device 1200 also includes at least one sensor 1210, such as a fingerprint sensor, pressure sensor, iris sensor, molecular sensor, gyroscope, barometer, hygrometer, thermometer, infrared sensor, light sensor, motion sensor, and other sensors.
  • a sensor 1210 such as a fingerprint sensor, pressure sensor, iris sensor, molecular sensor, gyroscope, barometer, hygrometer, thermometer, infrared sensor, light sensor, motion sensor, and other sensors.
  • the display unit 1212 is used to display information input by the user or information provided to the user.
  • the display unit 1212 may include a display panel 5122, which may be configured in the form of a liquid crystal display, an organic light emitting diode, or the like.
  • the user input unit 1214 may be used to receive input numerical or character information, and generate key signal input related to user settings and function control of the electronic device.
  • the user input unit 1214 includes a touch panel 5142 and other input devices 5144 .
  • the touch panel 5142 also referred to as a touch screen, collects the user's touch operations on or near it.
  • the touch panel 5142 may include two parts, a touch detection device and a touch controller. Among them, the touch detection device detects the user's touch orientation, detects the signal brought by the touch operation, and transmits the signal to the touch controller; the touch controller receives the touch information from the touch detection device, converts it into contact coordinates, and then sends it to the touch controller.
  • Other input devices 5144 may include, but are not limited to, physical keyboards, function keys (such as volume control keys, switch keys, etc.), trackballs, mice, and joysticks, which are not described herein again.
  • the touch panel 5142 can be covered on the display panel 5122.
  • the touch panel 5142 detects a touch operation on or near it, it transmits it to the processor 1220 to determine the type of the touch event, and then the processor 1220 determines the type of the touch event according to the touch
  • the type of event provides corresponding visual output on display panel 5122.
  • the touch panel 5142 and the display panel 5122 can be used as two independent components, or can be integrated into one component.
  • the interface unit 1216 is an interface for connecting an external device to the electronic device 1200 .
  • external devices may include wired or wireless headset ports, external power (or battery charger) ports, wired or wireless data ports, memory card ports, ports for connecting devices with identification modules, audio input/output (I/O) ports, video I/O ports, headphone ports, etc.
  • the interface unit 1216 may be used to receive input (eg, data information, power, etc.) from external devices and transmit the received input to one or more elements within the electronic device 1200 or may be used between the electronic device 1200 and external Transfer data between devices.
  • Memory 1218 may be used to store application programs and various data.
  • the memory 1218 may mainly include a stored program area and a stored data area, wherein the stored program area may store an operating system, an application program (such as a sound playback function, an image playback function, etc.) required for at least one function, and the like; Data (such as audio data, phone book, etc.) created by the use of the mobile terminal, etc.
  • memory 1218 may include a high-speed random access cache module, and may also include a non-volatile cache module, such as at least one disk cache module, flash memory device, or other volatile solid state cache module.
  • the processor 1220 executes various functions of the electronic device 1200 and processes data by running or executing the application programs and/or modules stored in the memory 1218, and calling the data stored in the memory 1218, so as to perform the overall operation of the electronic device 1200. monitor.
  • the processor 1220 may include one or more processing units; the processor 1220 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface and application programs, etc., and the modem processor mainly processes communication operations.
  • a readable storage medium is provided on which programs or instructions are stored, and when the program or instructions are executed by a processor, the image block processing method provided in any of the foregoing embodiments is implemented A step of.
  • the readable storage medium can implement each process of the image block processing method provided by the embodiment of the present application, and can achieve the same technical effect, which is not repeated here in order to avoid repetition.
  • the processor is the processor in the communication device in the above embodiment.
  • the readable storage medium includes a computer-readable storage medium, such as a computer read-only cache module (Read-Only Memory, ROM), a random access cache module (Random Access Memory, RAM), a magnetic disk or an optical disk, and the like.
  • An embodiment of the present application further provides a chip, where the chip includes a processor and a communication interface, the communication interface is coupled to the processor, and the processor is used for running programs or instructions to implement the various processes of the above image block processing method embodiments, and can achieve The same technical effect, in order to avoid repetition, will not be repeated here.
  • the chip mentioned in the embodiments of the present application may also be referred to as a system-on-chip, a system-on-chip, a system-on-a-chip, or a system-on-a-chip, or the like.
  • the method of the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is better implementation.
  • the technical solution of the present application can be embodied in the form of a software product in essence or in a part that contributes to the prior art, and the computer software product is stored in a storage medium (such as ROM/RAM, magnetic disk, CD-ROM), including several instructions to enable a terminal (which may be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to execute the methods of the various embodiments of the present application.
  • a storage medium such as ROM/RAM, magnetic disk, CD-ROM

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Abstract

本申请实施例提供了一种图像块的处理方法、装置、电子设备、可读存储介质。其中，图像块的处理方法包括：接收对目标图像的第一读取请求，第一读取请求包括获取目标图像中的第一图像块的坐标和第二图像块的坐标；根据第一图像块的坐标和第二图像块的坐标，得到第一图像块和第二图像块的重叠区域；根据重叠区域，将第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将第一图像块对应的像素块数据写入缓存模块。

Description

图像块的处理方法、装置、电子设备、可读存储介质
相关申请的交叉引用
本申请主张在2021年04月16日在中国提交的中国专利申请号No.202110413137.X的优先权，其全部内容通过引用包含于此。
技术领域
本申请涉及数据传输技术领域，具体而言，涉及一种图像块的处理方法、一种图像块的处理装置、一种电子设备、一种可读存储介质和一种芯片。
背景技术
在设置有超广角摄像头的手持设备上，通常会存在图像畸变的问题。相关技术中，但图像畸变矫正算法往往需要以图像块为单位来处理，以得到矫正后的矫正图像。高速缓冲存储器(Cache)只能先将图像写入DDR(双倍速率同步动态随机存储器)，再从DDR读取所需的图像块，并输送至存储器做插值运算得到矫正的图像。虽然高速缓冲存储器能够实现直接存储器访问(DMA)，但是由于图像畸变使得从DDR中读取的图像块之间有可能是重叠的，这将导致直接存储器访问重复的图像数据，这给DDR总线的带宽造成一定压力，同时存在功耗浪费。
发明内容
本申请实施例提供了一种图像块的处理方法、装置、电子设备、可读存储介质，能够有效减小读取时所需的带宽和功耗，降低存储器对运算能力的需求。
第一方面，本申请实施例提供了一种图像块的处理方法，包括：
接收对目标图像的第一读取请求，第一读取请求包括获取目标图像中的第一图像块的坐标和第二图像块的坐标；
根据第一图像块的坐标和第二图像块的坐标，得到第一图像块和第二图像块的重叠区域；
根据重叠区域，将第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将第一图像块对应的像素块数据写入缓存模块。
第二方面，本申请实施例提供了一种图像块的处理装置，包括：
第一请求模块，用于接收对目标图像的第一读取请求，第一读取请求包括获取目标图像中的第一图像块的坐标和第二图像块的坐标；
计算模块，用于根据第一图像块的坐标和第二图像块的坐标，得到第一图像块和第二图像块的重叠区域；
写入模块，用于根据重叠区域，将第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将第一图像块对应的像素块数据写入缓存模块。
第三方面，本申请实施例提供了一种电子设备，包括处理器，存储器及存储在存储器上并可在处理器上运行的程序或指令，程序或指令被处理器执行时实现如第一方面提供的图像块的处理方法的步骤。
第四方面，本申请实施例提供了一种可读存储介质，可读存储介质上存储程序或指令，该程序或指令被处理器执行时实现如第一方面提供的图像块的处理方法的步骤。
第五方面，本申请实施例提供了一种芯片，芯片包括处理器和通信接口，通信接口和处理器耦合，处理器用于运行程序或指令，实现如第一方面提供的图像块的处理方法的步骤。
在本申请实施例中，在需要进行图像数据处理时，根据接收到的第一读取请求中需要被处理的目标图像的各个图像块的坐标，从内存模组(DDR)中的读取像素块数据，并将像素块数据写入缓存模块，以便于后续处理时使用。另外，利用坐标确定与第一图像块相邻的第二图像块，并利用第一图像块的坐标和第二图像块的坐标，确定出相邻图像块之间的重叠区域。若存在重叠区域，说明存在部分像素块数据重复写入的问题，此时通过重叠区域将第一图像块中非重叠区域对应的像素块数据写入缓存模块。若不存在重叠区域，说明第一图像块对应的像素块数据和第二图像块对应的像素块数据并不相同，则放弃将第一图像块对应的像素块数据写入缓存模块。一方面，避免重复读取和写入重叠区域，有效减小读取时所需的带宽和功耗，降低缓存模块对运算能力的需求，另一方面，使用图像块的坐标作为定位依据，便于与后续与图像处理 器对接时，提高图像块的处理效率。
附图说明
图1示出了根据本申请的一个实施例的图像块的处理方法的流程图之一；
图2示出了根据本申请的一个实施例的图像块的处理方法的流程图之二；
图3示出了根据本申请的一个实施例的图像块的处理方法的流程图之三；
图4示出了根据本申请的一个实施例的图像块的处理方法的流程图之四；
图5示出了根据本申请的一个实施例的图像块的处理方法的流程图之五；
图6示出了根据本申请的一个实施例的缓存模块的结构示意图；
图7示出了根据本申请的一个实施例的图像块的处理装置的结构框图；
图8示出了根据本申请的一个实施例的图像块的处理装置的逻辑框图；
图9示出了根据本申请的一个实施例的电子设备的结构框图之一；
图10示出了根据本申请的一个实施例的电子设备的结构框图之二；
图11示出了根据本申请的一个实施例的电子设备的硬件结构示意图。
具体实施方式
为了能够更清楚地理解本申请的上述目的、特征和优点，下面结合附图和具体实施方式对本申请进行进一步的详细描述。需要说明的是，在不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本申请，但是，本申请还可以采用其他不同于在此描述的其他方式来实施，因此，本申请的保护范围并不受下面公开的具体实施例的限制。
下面参照图1至图11描述根据本申请一些实施例图像块的处理方法、图像块的处理装置、电子设备、可读存储介质和芯片。
如图1所示，在本申请的一个实施例中，提出了一种图像块的处理方法，包括：
步骤102，接收对目标图像的第一读取请求；
其中，第一读取请求包括获取目标图像中的第一图像块的坐标和第二图像块的坐标。
在该实施例中，电子设备的镜头模组通常会配置有默认的镜头畸变参数，在进行图像 处理，例如矫正处理时，图像处理器能够根据畸变算法和这些镜头畸变参数，计算出处理后的矫正图像中每一个图像块在需要被处理的目标图像中图像块对应的坐标，图像处理器根据该坐标生成第一读取请求，以读取内存模组中所需的像素块数据。
可以理解的是，图像块的坐标为图像块中任一像素点在整幅目标图像中的坐标。为了便于统计，目标图像中所有的图像块均采用处于同一位置的像素点来确定图像块的坐标。例如，设置图像块的坐标为图像块左上角像素点在目标图像中的坐标。图像块的坐标尺寸为图像块的宽度和高度。
步骤104，根据第一图像块的坐标和第二图像块的坐标，得到第一图像块和第二图像块的重叠区域；
步骤106，根据重叠区域，将第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将第一图像块对应的像素块数据写入缓存模块。
在该实施例中，在需要进行图像数据处理时，根据接收到的第一读取请求中需要被处理的目标图像的各个图像块的坐标，从内存模组(DDR)中的读取像素块数据，并将像素块数据写入缓存模块，以便于后续处理时使用。另外，利用坐标确定与第一图像块相邻的第二图像块，并利用第一图像块的坐标和第二图像块的坐标，确定出相邻图像块之间的重叠区域。若存在重叠区域，说明存在部分像素块数据重复写入的问题，此时通过重叠区域将第一图像块中非重叠区域对应的像素块数据写入缓存模块。若不存在重叠区域，说明第一图像块对应的像素块数据和第二图像块对应的像素块数据并不相同，则放弃将第一图像块对应的像素块数据写入缓存模块。一方面，避免重复读取和写入重叠区域，有效减小读取时所需的带宽和功耗，降低缓存模块对运算能力的需求，另一方面，使用图像块的坐标作为定位依据，便于与后续与图像处理器对接时，提高图像块的处理效率。
其中，内存模组(DDR)用于存储电子设备运行所需的数据。缓存模块可以是随机存取存储器(RAM)，例如，静态随机存取存储器(SRAM)，随机存取存储器中包括多个内存库(bank)，从而能够在一个时钟周期同时从内存库读取出多个像素块数据。
需要说明的是，需要被矫正处理的目标图像，也即原图图像，通过畸变矫正算法处理后得到矫正图像，其中，矫正图像由多个图像块组成，也即矫正图像中每一个图像块都是从目标图像中对应的区域经过算法得到的。由于图像有畸变，使得目标图像中对应的区域 的尺寸和坐标不同于目标图像的图像块，所以相邻的矫正图像的图像块对应的目标图像中相邻的区域可能出现重叠。
如图2所示，步骤106，根据重叠区域将第一图像块中的非重叠区域对应的像素块数据写入缓存模块，包括：
步骤202，在重叠区域的尺寸小于第一图像块的尺寸的情况下，根据重叠区域确定第一图像块中的非重叠区域；
步骤204，从内存模组中读取非重叠区域对应的像素块数据；
步骤206，将非重叠区域对应的像素块数据写入缓存模块。
在该实施例中，根据第一图像块和第二图像块的位置关系(坐标)，能够判断前后两个图像块之间是否存在重叠区域，并确定出重叠区域的尺寸。若重叠区域的尺寸小于第一图像块的尺寸，说明第二图像块仅包含第一图像块的部分像素块数据，或者完全不包含第一图像块的像素块数据，此时，需要正常进行第一图像块的像素块数据的读写，则通过重叠区域确定第一图像块中的非重叠区域，并按照非重叠区域的尺寸将内存模组中非重叠区域对应的像素块数据写入缓存模块。从而保证在进行目标图像缓存时，即使出现图像块之间的重叠问题，也不会从内存模组中读取重叠区域的像素块数据，进而能最大程度减小由于图像块在y方向上的位移造成的带宽浪费，同时降低内存模组的功耗。
具体地，可通过存储器总线(cacheline)从内存模组中读取所需的数据。
可以理解的是，按照读取的先后顺序，第二图像块可以是第一图像块的前一个图像块，也可以是后一个图像块。
具体举例来说，如果第一图像块未命中，也即重叠区域的尺寸小于第一图像块的尺寸，此时，第二图像块未完全覆盖第一图像块，说明第一图像块需要从DDR中取数，然后再切换到RAM中的下一个图像块中取数。
如图3所示，步骤106，根据重叠区域放弃将第一图像块对应的像素块数据写入缓存模块，包括：
步骤302，在重叠区域的尺寸等于第一图像块的尺寸的情况下，放弃从内存模组中读取第一图像块对应的像素块数据，以及放弃将第一图像块对应的像素块数据写入缓存模块。
在该实施例中，根据第一图像块和第二图像块的位置关系(坐标)，能够判断前后两个图像块之间是否存在重叠区域，并确定出重叠区域的尺寸。若重叠区域的尺寸不小于第一图像块的尺寸，也即重叠区域的尺寸等于第一图像块的尺寸，说明第二图像块包含第一图像块的所有像素块数据，也即在写入第二图像块时，能够将第一图像块的所有像素块数据写入缓存模块中，则在接收到第一读取请求后，放弃将从内存模组中读取第一图像块对应的全部像素块数据，同时也不会将第一图像块对应的全部像素块数据写入缓存模块。从而保证在进行目标图像缓存时，避免从内存模组中重复读取相同的像素块数据，进而能最大程度减小由于图像块在y方向上的位移造成的带宽浪费，同时降低内存模组的功耗。
具体举例来说，如果第一图像块被命中，也即重叠区域的尺寸等于第一图像块的尺寸，也就是说，第二图像块完全覆盖第一图像块。若第二图像块对应的像素块数据已经写入RAM，则第一图像块数据在RAM中已经完全存在。此时，不需要从DDR中读取第一图像块相应的像素块数据并写入RAM。但是在从RAM读取该图像块对应的像素块数据时还是需要标签信息的，以在从RAM读取第一图像块时指示从第二图像块中取数。
如图4所示，步骤204，按照非重叠区域从内存模组中读取非重叠区域对应的像素块数据，包括：
步骤402，根据非重叠区域的尺寸、预设读取尺寸和预设行坐标阈值，确定第一图像块的目标行和内存模组中目标行对应的目标行坐标；
其中，预设读取尺寸用于对齐数据坐标，以避免读取不完整的数据。
在该实施例中，在第二图像块未完全覆盖第一图像块的情况下，根据非重叠区域的尺寸与预设读取尺寸的和，确定需要读取的像素块数据在图像块中的读取坐标。从而在确定需要读取的像素块数据时，按照非重叠区域的尺寸与预设读取尺寸的和进行计算，使得实际读取出的像素块数据多于非重叠区域的尺寸范围内包含的像素块数据，避免读取过程中处于出现问题导致的数据丢失而影响后续的数据写入，防止目标图像缓存不完整，增强读取容错率。
具体举例来说，假设第二图像块的坐标和宽高为(x1，y1，w1，h1)第一图像块的坐标和宽高为(x2，y2，w2，h2)，那么重叠区域的宽度就是MAX(0，(x1+w1+x_ext-x2))，重叠的高度为MAX(0，(y1+h1+y_ext-y2))，如果重叠区域宽高等于第一图像块的宽 高，则第一图像块被命中。其中，x_ext是指缓存模块的预取部分，也即预设读取尺寸，按照预设读取尺寸进行计算，使得实际读取出的像素块数据多于非重叠区域的尺寸范围内包含的像素块数据。从而避免读取过程中处于出现问题导致的数据丢失而影响后续的数据写入，防止目标图像缓存不完整，增强读取容错率。
进一步地，由于需要读取的像素块数据的坐标密集且非连续，若每一个非连续的像素块数据均生成一个第二读取请求(AXIburst)，将生成较多的AXIburst，那么就需要从内存模组中进行较多次数的读取，容易降低内存模组的使用寿命。所以预先配置一个行坐标阈值，利用该读取坐标和行坐标阈值，将坐标之间的间距较小的多个相邻的像素块数据作为一个目标行，也即在图像块的一行中多个像素块数据的坐标之间的距离小于行坐标阈值的情况下，可以将多个像素块数据的坐标生成一个AXIburst。然后再计算出内存模组中目标行对应的目标行坐标，以便于对需要从内存模组中读取的像素块数据进行定位。从而减少从内存模组中读取数据的次数，延长内存模组的使用寿命。具体地，行坐标阈值还可以根据存储器的配置调整大小。例如，如果第一图像块没有命中，则计算出第一图像块中哪些行需要读取DDR以及每一行读取的起始坐标和对齐的结束坐标，一行对应一个AXIburst命令，也就是说，存储器总线(cacheline)的大小是动态自适应的，由于太小的AXIburst对DDR不友好，所以这里cacheline给出一个最小值的限定。
具体举例来说，如图6所示，以读取出像素块最大为4×4为例。SRAMarray(缓存模块)分为8个bank(缓存模块的内存库)，水平方向2个bank，垂直方向4个bank，每个bank的存储位宽为4个像素位宽。根据读写坐标中Y轴坐标的低2bit选择垂直方向上的4行bank，这样在每个时钟周期能够写入8个像素，这8个像素在目标图像中的坐标是对齐的，其中，高4个像素写入左边一列bank，低4个像素写入右边一列bank，每个bank的写入地址都是由标签信息中的X和Y轴坐标拼接成。从而能够缩小SRAM所需面积大小(4个最大图像块的大小)。
步骤404，根据目标行和目标行坐标，生成第二读取请求；
步骤406，按照第二读取请求从内存模组中读取非重叠区域对应的像素块数据。
在该实施例中，根据目标行和目标行坐标，生成第二读取请求，以从内存模组中读取所需的非重叠区域的像素块数据。最后将读取出的非重叠区域对应的像素块数据写入缓存 模块，以便于对目标图像进行处理时，能够随时从缓存模块获得所需的像素块数据。
如图5所示，在本申请的一个实施例中，一种图像块的处理方法，还包括：
步骤502，根据重叠区域，生成第一图像块的标签信息；
其中，标签信息包括：重叠区域的尺寸、第一图像块的尺寸、第一图像块在缓存模块中的读写坐标。
在该实施例中，在得到第一图像块和第二图像块之间的重叠区域之后，根据重叠区域生成第一图像块的标签信息，以便于为缓存模块的写入和读取，提供重叠区域的尺寸、第一图像块的尺寸、像素块数据写入缓存模块中的缓存模块的读写坐标等读写信息，以便于为存储器的读写控制提供可靠的定位数据。从而需要从缓存模块读取像素块数据时，能够通过读写坐标快速、准确定位到所需的像素块数据，有利于提升写入和读取速度，进而提高图像块处理的效率。
需要说明的是，缓存模块可以包括多个内存库，用于写入像素块数据的目标内存库可根据需要从内存模组中读取的像素块数据的宽高来确定。例如，以读取出像素块最大为4×4为例。SRAMarray(由多块SRAM构成)分为8个bank，水平方向2个bank，垂直方向4个bank，每个bank的SRAM位宽为4个像素位宽。其中，垂直方向上的4行bank，为第一行为bank00和bank01，第二行为bank10和bank11，第三行为bank20和bank21，第四行为bank30和bank31。图6中的p0、p1、p2、p3是指存储位宽为4个pixel的宽度。
具体举例来说，根据第一图像块需要读取DDR的目标行坐标计算出读写信息，每个第一读取请求产生一组标签信息，标签信息包括是否命中，也即重叠的尺寸是否为0，第一图像块的宽和高，第一图像块和第二图像块重叠区域的宽和高，以及在SRAM(缓存模块)中的读写坐标。
步骤504，接收针对缓存模块中第一图像块的目标像素块数据的第三读取请求；
其中，第三读取请求包括指示目标像素块数据的像素位宽和目标坐标。
步骤506，按照第三读取请求中的像素位宽、目标坐标和标签信息，从缓存模块中输出目标像素块数据。
在该实施例中，在目标图像的第一图像块的像素块数据已经写入缓存模块之后，接收缓存模块存在的中第一图像块的目标像素块数据的第三读取请求。利用第三读取请求指示 的存储位宽、目标坐标以及缓存目标图像生成的标签信息，从缓存模块中读取并输出该目标像素块数据。以供后续的图像处理器按照指定的算法对目标像素块数据进行处理。例如，对图像进行矫正处理，图像处理器按照矫正算法对目标像素块数据进行矫正，得到矫正后的矫正图像块，进而可通过矫正图像块输出矫正图像。
具体举例来说，如图6所示，读取SRAM时需要在一个时钟周期内从8个bank中读取最大为4×4的像素块。以读取4×4像素块为例，像素块坐标可以是随机的，4×4像素块的四行分别从4个不同的bank行中读取，4×4像素块的每行4个像素可能只需要读其中一列bank，也可能每个bank行中两个bank都读取，然后再从读取的8个像素中取出需要的4个像素块，读取出的4×4像素块在同一个时钟周期返回至图像处理器。
在本申请的一个实施例中，如图7所示，提供了一种图像块的处理装置700，包括：第一请求模块702，第一请求模块702用于接收对目标图像的第一读取请求，第一读取请求包括获取目标图像中的第一图像块的坐标和第二图像块的坐标；计算模块704，计算模块704用于根据第一图像块的坐标和第二图像块的坐标，得到第一图像块和第二图像块的重叠区域；写入模块706，写入模块706用于根据重叠区域，将第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将第一图像块对应的像素块数据写入缓存模块。
可选的，如图8所示，计算模块704还用于在重叠区域的尺寸小于第一图像块的尺寸的情况下，根据重叠区域确定第一图像块中的非重叠区域；图像块的处理装置700还包括：访问模块708，访问模块708用于从内存模组中读取非重叠区域对应的像素块数据；写入模块706还用于将非重叠区域对应的像素块数据写入缓存模块。
可选的，写入模块706还用于在重叠区域的尺寸等于第一图像块的尺寸的情况下，放弃从内存模组中读取第一图像块对应的像素块数据，以及放弃将第一图像块对应的像素块数据写入缓存模块。
可选的，如图8所示，计算模块704，还用于根据非重叠区域的尺寸、预设读取尺寸和预设行坐标阈值，确定第一图像块的目标行和内存模组中目标行对应的目标行坐标；图像块的处理装置700还包括：第一生成模块710，第一生成模块710用于根据目标行和目标行坐标，生成第二读取请求；访问模块708，访问模块708还用于按照第二读取请求从 内存模组中读取非重叠区域对应的像素块数据。
可选的，图像块的处理装置还包括：第二生成模块，第二生成模块用于根据重叠区域，生成第一图像块的标签信息，标签信息包括：重叠区域的尺寸、第一图像块的尺寸和第一图像块在缓存模块中的读写坐标；
第二请求模块，第二请求模块用于接收针对缓存模块中第一图像块的目标像素块数据的第三读取请求，第三读取请求包括目标像素块数据的存储位宽和目标坐标；输出模块，输出模块用于按照存储位宽、目标坐标和标签信息，从缓存模块中输出目标像素块数据。
在该实施例中，图像块的处理装置700的各模块执行各自功能时实现如上述任一实施例中的图像块的处理方法的步骤，因此，图像块的处理装置700同时也包括如上述任一实施例中的图像块的处理装置方法的全部有益效果，在此不再赘述。
本申请实施例中的图像块的处理装置可以是装置，也可以是终端中的部件、集成电路、或芯片。该装置可以是移动电子设备，也可以为非移动电子设备。示例性的，移动电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，非移动电子设备可以为服务器、网络附属存储器(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
本申请实施例中的图像块的处理装置可以为具有操作系统的装置。该操作系统可以为安卓(Android)操作系统，可以为ios操作系统，还可以为其他可能的操作系统，本申请实施例不作具体限定。
在本申请的一个实施例中，如图9所示，提供了一种电子设备1000，包括：处理器1004，存储器1002及存储在存储器1002上并可在处理器1004上运行的程序或指令，程序或指令被处理器1004执行时实现如上述任一实施例中提供的图像块的处理方法的步骤，因此，该电子设备1000包括如上述任一实施例中提供的图像块的处理方法的全部有益效果，在此不再赘述。
在本申请的一个实施例中，如图10所示，存储器1002还包括：内存模组1006，与处理器1004连接；缓存模块1008，与处理器1004连接；电子设备1000还包括：图像处理 器1010，与存储器1002和处理器1004连接，图像处理器1010用于对目标图像进行处理。
此外，在一些实施例中，缓存模块1008可以包括第一缓存模块和第二缓存模块。其中，第一缓存模块用于存储数据。第二缓存模块用于缓存标签信息。如果第一图像块被命中，也即重叠区域的尺寸等于第一图像块的尺寸，此时，不需要从内存模组1006中读取相应的像素块数据写入第一缓存模块，但需要将标签信息写入第二缓存模块，以便于读取第一图像块时，根据第二图像块读数。一方面，能够避免像素点数据读写时的信息混乱，进而提高数据读取的准确性，有利于提升图像处理效率，保证处理后的图像质量，另一方面，减小第一缓存模块的内存占用，降低产品的存储要求，有利于降低产品的制造成本。
值得一提的是，第二缓存模块可采用先进先出(FIFO)原则。
本申请实施例中的待电子设备可以是移动电子设备，也可以为非移动电子设备。示例性的，移动电子设备可以为手机、平板电脑、笔记本电脑、掌上电脑、车载电子设备、可穿戴设备、超级移动个人计算机(ultra-mobile personal computer，UMPC)、上网本或者个人数字助理(personal digital assistant，PDA)等，非移动电子设备可以为服务器、网络附属缓存模块(Network Attached Storage，NAS)、个人计算机(personal computer，PC)、电视机(television，TV)、柜员机或者自助机等，本申请实施例不作具体限定。
图11为实现本申请实施例的一种电子设备1200的硬件结构示意图。该电子设备1200包括但不限于：射频单元1202、网络模块1204、音频输出单元1206、输入单元1208、传感器1210、显示单元1212、用户输入单元1214、接口单元1216、存储器1218、处理器1220等部件。
本领域技术人员可以理解，电子设备1200还可以包括给各个部件供电的电源(比如电池)，电源可以通过电源管理系统与处理器1220逻辑相连，从而通过电源管理系统实现管理充电、放电、以及功耗管理等功能。图11中示出的电子设备结构并不构成对电子设备的限定，电子设备可以包括比图示更多或更少的部件，或者组合某些部件，或者不同的部件布置。在本申请实施例中，电子设备包括但不限于移动终端、平板电脑、笔记本电脑、掌上电脑、车载电子设备、可穿戴设备、以及计步器等。
其中，处理器1220用于接收对目标图像的第一读取请求，第一读取请求包括获取目标图像中的第一图像块的坐标和第二图像块的坐标；根据第一图像块的坐标和第二图像块 的坐标，得到第一图像块和第二图像块的重叠区域；根据重叠区域，将第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将第一图像块对应的像素块数据写入缓存模块。
进一步地，处理器1220还用于，在重叠区域的尺寸小于第一图像块的尺寸的情况下，根据重叠区域确定第一图像块中的非重叠区域；从内存模组中读取非重叠区域对应的像素块数据；将非重叠区域对应的像素块数据写入缓存模块。
进一步地，处理器1220还用于，在重叠区域的尺寸等于第一图像块的尺寸的情况下，放弃从内存模组中读取第一图像块对应的像素块数据，以及放弃将第一图像块对应的像素块数据写入缓存模块。
进一步地，处理器1220还用于根据非重叠区域的尺寸、预设读取尺寸和预设行坐标阈值，确定第一图像块的目标行和内存模组中目标行对应的目标行坐标；根据目标行和目标行坐标，生成第二读取请求；按照第二读取请求从内存模组中读取非重叠区域对应的像素块数据。
进一步地，处理器1220还用于根据重叠区域，生成第一图像块的标签信息，标签信息包括：重叠区域的尺寸、第一图像块的尺寸和第一图像块在缓存模块中的读写坐标；接收针对所述缓存模块中所述第一图像块的目标像素块数据的第三读取请求，第三读取请求包括目标像素块数据的存储位宽和目标坐标；按照所述存储位宽、所述目标坐标和所述标签信息，从所述缓存模块中输出所述目标像素块数据。
应理解的是，本申请实施例中，射频单元1202可用于收发信息或收发通话过程中的信号，具体的，接收基站的下行数据或向基站发送上行数据。射频单元1202包括但不限于天线、至少一个放大器、收发信机、耦合器、低噪声放大器、双工器等。
网络模块1204为用户提供了无线的宽带互联网访问，如帮助用户收发电子邮件、浏览网页和访问流式媒体等。
音频输出单元1206可以将射频单元1202或网络模块1204接收的或者在存储器1218中存储的音频数据转换成音频信号并且输出为声音。而且，音频输出单元1206还可以提供与电子设备1200执行的特定功能相关的音频输出(例如，呼叫信号接收声音、消息接收声音等等)。音频输出单元1206包括扬声器、蜂鸣器以及受话器等。
输入单元1208用于接收音频或视频信号。输入单元1208可以包括图形处理器(Graphics Processing Unit，GPU)5082和麦克风5084，图形处理器5082对在视频捕获模式或图像捕获模式中由图像捕获装置(如摄像头)获得的静态图片或视频的像素块数据进行处理。处理后的图像帧可以显示在显示单元1212上，或者存储在存储器1218(或其它存储介质)中，或者经由射频单元1202或网络模块1204发送。麦克风5084可以接收声音，并且能够将声音处理为音频数据，处理后的音频数据可以在电话通话模式的情况下转换为可经由射频单元1202发送到移动通信基站的格式输出。
电子设备1200还包括至少一种传感器1210，比如指纹传感器、压力传感器、虹膜传感器、分子传感器、陀螺仪、气压计、湿度计、温度计、红外线传感器、光传感器、运动传感器以及其他传感器。
显示单元1212用于显示由用户输入的信息或提供给用户的信息。显示单元1212可包括显示面板5122，可以采用液晶显示器、有机发光二极管等形式来配置显示面板5122。
用户输入单元1214可用于接收输入的数字或字符信息，以及产生与电子设备的用户设置以及功能控制有关的键信号输入。具体地，用户输入单元1214包括触控面板5142以及其他输入设备5144。触控面板5142也称为触摸屏，可收集用户在其上或附近的触摸操作。触控面板5142可包括触摸检测装置和触摸控制器两个部分。其中，触摸检测装置检测用户的触摸方位，并检测触摸操作带来的信号，将信号传送给触摸控制器；触摸控制器从触摸检测装置上接收触摸信息，并将它转换成触点坐标，再送给处理器1220，接收处理器1220发来的命令并加以执行。其他输入设备5144可以包括但不限于物理键盘、功能键(比如音量控制按键、开关按键等)、轨迹球、鼠标、操作杆，在此不再赘述。
进一步的，触控面板5142可覆盖在显示面板5122上，当触控面板5142检测到在其上或附近的触摸操作后，传送给处理器1220以确定触摸事件的类型，随后处理器1220根据触摸事件的类型在显示面板5122上提供相应的视觉输出。触控面板5142与显示面板5122可作为两个独立的部件，也可以集成为一个部件。
接口单元1216为外部装置与电子设备1200连接的接口。例如，外部装置可以包括有线或无线头戴式耳机端口、外部电源(或电池充电器)端口、有线或无线数据端口、存储卡端口、用于连接具有识别模块的装置的端口、音频输入/输出(I/O)端口、视频I/O端口、 耳机端口等等。接口单元1216可以用于接收来自外部装置的输入(例如，数据信息、电力等等)并且将接收到的输入传输到电子设备1200内的一个或多个元件或者可以用于在电子设备1200和外部装置之间传输数据。
存储器1218可用于存储应用程序程序以及各种数据。存储器1218可主要包括存储程序区和存储数据区，其中，存储程序区可存储操作系统、至少一个功能所需的应用程序(比如声音播放功能、图像播放功能等)等；存储数据区可存储根据移动终端的使用所创建的数据(比如音频数据、电话本等)等。此外，存储器1218可以包括高速随机存取缓存模块，还可以包括非易失性缓存模块，例如至少一个磁盘缓存模块件、闪存器件、或其他易失性固态缓存模块件。
处理器1220通过运行或执行存储在存储器1218内的应用程序程序和/或模块，以及调用存储在存储器1218内的数据，执行电子设备1200的各种功能和处理数据，从而对电子设备1200进行整体监控。处理器1220可包括一个或多个处理单元；处理器1220可集成应用处理器和调制解调处理器，其中，应用处理器主要处理操作系统、用户界面和应用程序等，调制解调处理器主要通信的操作。
在本申请的一个实施例中，提供了一种可读存储介质，其上存储有程序或指令，该程序或指令被处理器执行时实现如上述任一实施例中提供的图像块的处理方法的步骤。
在该实施例中，可读存储介质能够实现本申请的实施例提供的图像块的处理方法的各个过程，并能达到相同的技术效果，为避免重复，这里不再赘述。
其中，处理器为上述实施例中的通信设备中的处理器。可读存储介质，包括计算机可读存储介质，如计算机只读缓存模块(Read-Only Memory，ROM)、随机存取缓存模块(Random Access Memory，RAM)、磁碟或者光盘等。
本申请实施例还提供了一种芯片，芯片包括处理器和通信接口，通信接口和处理器耦合，处理器用于运行程序或指令，实现上述图像块的处理方法实施例的各个过程，且能达到相同的技术效果，为避免重复，这里不再赘述。
应理解，本申请实施例提到的芯片还可以称为系统级芯片、系统芯片、芯片系统或片上系统芯片等。
需要说明的是，在本文中，术语“包括”、“包含”或者其任何其他变体意在涵盖非 排他性的包含，从而使得包括一系列要素的过程、方法、物品或者装置不仅包括那些要素，而且还包括没有明确列出的其他要素，或者是还包括为这种过程、方法、物品或者装置所固有的要素。在没有更多限制的情况下，由语句“包括一个……”限定的要素，并不排除在包括该要素的过程、方法、物品或者装置中还存在另外的相同要素。此外，需要指出的是，本申请实施方式中的方法和装置的范围不限按示出或讨论的顺序来执行功能，还可包括根据所涉及的功能按基本同时的方式或按相反的顺序来执行功能，例如，可以按不同于所描述的次序来执行所描述的方法，并且还可以添加、省去、或组合各种步骤。另外，参照某些示例所描述的特征可在其他示例中被组合。
通过以上的实施方式的描述，本领域的技术人员可以清楚地了解到上述实施例方法可借助软件加必需的通用硬件平台的方式来实现，当然也可以通过硬件，但很多情况下前者是更佳的实施方式。基于这样的理解，本申请的技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来，该计算机软件产品存储在一个存储介质(如ROM/RAM、磁碟、光盘)中，包括若干指令用以使得一台终端(可以是手机，计算机，服务器，空调器，或者网络设备等)执行本申请各个实施例的方法。
上面结合附图对本申请的实施例进行了描述，但是本申请并不局限于上述的具体实施方式，上述的具体实施方式仅仅是示意性的，而不是限制性的，本领域的普通技术人员在本申请的启示下，在不脱离本申请宗旨和权利要求所保护的范围情况下，还可做出很多形式，均属于本申请的保护之内。
以上仅为本申请的优选实施例而已，并不用于限制本申请，对于本领域的技术人员来说，本申请可以有各种更改和变化。凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (15)

  1. 一种图像块的处理方法，包括：
    接收对目标图像的第一读取请求，所述第一读取请求包括获取所述目标图像中的第一图像块的坐标和第二图像块的坐标；
    根据所述第一图像块的坐标和所述第二图像块的坐标，得到所述第一图像块和所述第二图像块的重叠区域；
    根据所述重叠区域，将所述第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将所述第一图像块对应的像素块数据写入缓存模块。
  2. 根据权利要求1所述的图像块的处理方法，其中，所述根据所述重叠区域，将所述第一图像块中的非重叠区域对应的像素块数据写入缓存模块，包括：
    在所述重叠区域的尺寸小于所述第一图像块的尺寸的情况下，根据所述重叠区域确定所述第一图像块中的非重叠区域；
    从内存模组中读取所述非重叠区域对应的像素块数据；
    将所述非重叠区域对应的像素块数据写入所述缓存模块。
  3. 根据权利要求1所述的图像块的处理方法，其中，所述根据所述重叠区域放弃将所述第一图像块对应的像素块数据写入缓存模块，包括：
    在所述重叠区域的尺寸等于所述第一图像块的尺寸的情况下，放弃从内存模组中读取所述第一图像块对应的像素块数据，以及放弃将所述第一图像块对应的像素块数据写入所述缓存模块。
  4. 根据权利要求2所述的图像块的处理方法，其中，所述按照所述非重叠区域从内存模组中读取所述非重叠区域对应的像素块数据，包括：
    根据所述非重叠区域的尺寸、预设读取尺寸和预设行坐标阈值，确定所述第一图像块的目标行和内存模组中所述目标行对应的目标行坐标；
    根据所述目标行和所述目标行坐标，生成第二读取请求；
    按照所述第二读取请求从所述内存模组中读取所述非重叠区域对应的像素块数据。
  5. 根据权利要求1所述的图像块的处理方法，其中，还包括：
    根据所述重叠区域，生成所述第一图像块的标签信息，所述标签信息包括：所述重叠区域的尺寸、所述第一图像块的尺寸和所述第一图像块在缓存模块中的读写坐标；
    接收针对所述缓存模块中所述第一图像块的目标像素块数据的第三读取请求，所述第三读取请求包括所述目标像素块数据的存储位宽和目标坐标；
    按照所述存储位宽、所述目标坐标和所述标签信息，从所述缓存模块中输出所述目标像素块数据。
  6. 一种图像块的处理装置，包括：
    第一请求模块，用于接收对目标图像的第一读取请求，所述第一读取请求包括获取所述目标图像中的第一图像块的坐标和第二图像块的坐标；
    计算模块，用于根据所述第一图像块的坐标和所述第二图像块的坐标，得到所述第一图像块和所述第二图像块的重叠区域；
    写入模块，用于根据所述重叠区域，将所述第一图像块中的非重叠区域对应的像素块数据写入缓存模块，或放弃将所述第一图像块对应的像素块数据写入缓存模块。
  7. 根据权利要求6所述的图像块的处理装置，其中，
    所述计算模块，还用于在所述重叠区域的尺寸小于所述第一图像块的尺寸的情况下，根据所述重叠区域确定所述第一图像块中的所述非重叠区域；
    所述图像块的处理装置还包括：
    访问模块，用于从内存模组中读取所述非重叠区域对应的像素块数据；
    所述写入模块，还用于将所述非重叠区域对应的像素块数据写入所述缓存模块。
  8. 根据权利要求6所述的图像块的处理装置，其中，
    所述写入模块，还用于在所述重叠区域的尺寸等于所述第一图像块的尺寸的情况下，放弃从内存模组中读取所述第一图像块对应的像素块数据，以及放弃将所述第一图像块对应的像素块数据写入所述缓存模块。
  9. 根据权利要求7所述的图像块的处理装置，其中，
    所述计算模块，还用于根据所述非重叠区域的尺寸、预设读取尺寸和预设行坐标阈值，确定所述第一图像块的目标行和内存模组中所述目标行对应的目标行坐标；
    所述图像块的处理装置还包括：
    第一生成模块，用于根据所述目标行和所述目标行坐标，生成第二读取请求；
    所述访问模块，还用于按照所述第二读取请求从所述内存模组中读取所述非重叠区域对应的像素块数据。
  10. 根据权利要求6所述的图像块的处理装置，其中，还包括：
    第二生成模块，用于根据所述重叠区域，生成所述第一图像块的标签信息，所述标签信息包括：所述重叠区域的尺寸、所述第一图像块的尺寸和所述第一图像块在缓存模块中的读写坐标；
    第二请求模块，用于接收针对所述缓存模块中所述第一图像块的目标像素块数据的第三读取请求，所述第三读取请求包括所述目标像素块数据的存储位宽和目标坐标；
    输出模块，用于按照所述存储位宽、所述目标坐标和所述标签信息，从所述缓存模块中输出所述目标像素块数据。
  11. 一种电子设备，包括处理器，存储器及存储在所述存储器上并可在所述处理器上运行的程序或指令，所述程序或指令被所述处理器执行时实现如权利要求1至5中任一项所述的图像块的处理方法的步骤。
  12. 一种可读存储介质，所述可读存储介质上存储程序或指令，所述程序或指令被处理器执行时实现如权利要求1至5中任一项所述的图像块的处理方法的步骤。
  13. 一种芯片，包括处理器和通信接口，通信接口和处理器耦合，处理器用于运行程序或指令，实现权利要求1至5中任一项所述的图像块的处理方法的步骤。
  14. 一种图像块的处理装置，包括所述装置被配置成用于执行如权利要求1至5中任一项所述的图像块的处理方法。
  15. 一种计算机程序产品，所述程序产品被至少一个处理器执行以实现如权利要求1至5任一项所述的图像块的处理方法。
PCT/CN2022/086096 2021-04-16 2022-04-11 图像块的处理方法、装置、电子设备、可读存储介质 WO2022218253A1 (zh)

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