WO2022215665A1 - Passive part - Google Patents

Abstract

In the present invention, on an insulating surface of a substrate is disposed an inductor containing two patterned conductors which are mutually layered with an insulating film sandwiched therebetween. The two patterned conductors constituting the inductor each have a spiral form in plan view. The two patterned conductors are connected in series so that current flows in identical directions relative to the circuiting direction, and contain side-by-side running sections that are disposed in parallel adjoining each other in plan view. Both the side-by-side running sections of the two patterned conductors have portions that do not overlap each other relative to a width direction that is orthogonal to the direction in which the conductors extend in parallel. Between the two patterned conductors constituting the inductor, the patterned conductor that is farther from the substrate has a surface facing toward the substrate, and such surface is disposed in a position which is farther from the substrate than a surface which is of the patterned conductor that is nearer to the substrate and which is facing away from the substrate side.

Description

passive components

The present invention relates to passive components.

With the rapid spread of electronic devices with wireless communication functions, an extremely large number of high frequency bands have come to be used in wireless communication. In order to support a large number of high frequency bands, multi-bands and multi-modes are being used in one communication module. In addition, in order to suppress an increase in module size, the components mounted in communication modules are becoming smaller, thinner, and more highly integrated.

Technologies for realizing high integration of communication modules include technologies such as three-dimensional mounting and embedding components in package substrates. Integrated passive components such as noise filters and bandpass filters are also required to be smaller and thinner, or to be embedded in package substrates. Integrated passive components have been proposed in which passive components are formed on a substrate using thin film technology (see Patent Document 1). For example, Patent Literature 1 discloses a spiral inductor composed of conductor patterns arranged on a plurality of conductor layers.

Japanese Patent Publication No. 2018-534763

In an inductor having a structure in which conductor patterns are laminated, the lower conductor pattern and the upper conductor pattern face each other in the vertical direction. Since a parasitic capacitance is generated between the two conductor patterns facing each other in the vertical direction, the high-frequency characteristics of the inductor, such as the Q value, are degraded. Insulating films must be made thick in order to dispose a plurality of conductor layers sufficiently apart in the vertical direction in order to reduce parasitic capacitance. However, it is difficult to unconditionally increase the thickness of the insulating film due to restrictions on the manufacturing process.

An object of the present invention is to provide a passive component capable of reducing the parasitic capacitance of an inductor including laminated conductor patterns.

According to one aspect of the invention,
a substrate having an insulating surface;
an inductor including two conductor patterns stacked on the insulating surface of the substrate with an insulating film sandwiched therebetween;
each of the two conductor patterns forming the inductor has a spiral shape in plan view,
The two conductor patterns that make up the inductor are connected in series so that current flows in the same direction with respect to the winding direction, and include parallel running portions that are arranged in parallel and adjacent to each other in a plan view,
Both of the parallel running portions of the two conductor patterns that constitute the inductor have portions that do not overlap each other in the width direction orthogonal to the direction extending in parallel,
Of the two conductor patterns forming the inductor, the surface of the conductor pattern farther from the substrate facing the substrate faces the side opposite to the substrate of the conductor pattern closer to the substrate. Passive components are provided that are positioned farther from the substrate than the plane.

Both of the parallel running portions of the two conductor patterns that make up the inductor have portions that do not overlap each other in the width direction. , the parasitic capacitance of the inductor can be reduced.

FIG. 1A is a plan view of an inductor included in a passive component according to the first embodiment, and FIG. 1B is a cross-sectional view taken along dashed-dotted line 1B-1B in FIG. 1A. 2A is a plan view of an inductor included in a passive component according to the second embodiment, and FIG. 2B is a cross-sectional view taken along dashed-dotted line 2B-2B in FIG. 2A. 3A is a plan view of an inductor included in a passive component according to the third embodiment, and FIG. 3B is a cross-sectional view taken along dashed-dotted line 3B-3B in FIG. 3A. FIG. 4A is a plan view of an inductor included in a passive component according to a fourth embodiment, and FIG. 4B is a cross-sectional view taken along dashed-dotted line 4B-4B in FIG. 4A. 5A is a plan view of an inductor included in a passive component according to the fifth embodiment, and FIG. 5B is a cross-sectional view taken along dashed-dotted line 5B-5B in FIG. 5A. 6A is a plan view of an inductor included in a passive component according to the sixth embodiment, and FIG. 6B is a cross-sectional view taken along dashed-dotted line 6B-6B in FIG. 6A. FIG. 7 is an equivalent circuit diagram of a passive component according to the seventh embodiment. FIG. 8A is a plan view of the passive component according to the seventh embodiment at an intermediate stage of manufacturing, and FIG. 8B is a cross-sectional view taken along dashed-dotted line 8B-8B in FIG. 8A. FIG. 9A is a plan view of the passive component according to the seventh embodiment at an intermediate stage of manufacturing, and FIG. 9B is a cross-sectional view taken along dashed-dotted line 9B-9B in FIG. 9A. 10A is a plan view of the passive component according to the seventh embodiment in the middle of manufacturing, and FIG. 10B is a cross-sectional view taken along the dashed-dotted line 10B-10B in FIG. 10A. FIG. 11A is a plan view of the passive component according to the seventh embodiment at an intermediate stage of manufacturing, and FIG. 11B is a cross-sectional view taken along dashed-dotted line 11B-11B in FIG. 11A. FIG. 12A is a plan view of the passive component according to the seventh embodiment at an intermediate stage of manufacturing, and FIG. 12B is a cross-sectional view taken along dashed-dotted line 12B-12B in FIG. 12A. 13A is a plan view of a passive component according to the seventh embodiment, and FIG. 13B is a cross-sectional view taken along dashed-dotted line 13B-13B in FIG. 13A. FIG. 14 is a cross-sectional view of part of a passive component according to an eighth embodiment. 15A is a plan view of an inductor included in a passive component according to the ninth embodiment, and FIG. 15B is a cross-sectional view taken along dashed-dotted line 15B-15B in FIG. 15A. 16A and 16B are cross-sectional views of inductors of passive components according to the tenth embodiment and its modification, respectively.

[First embodiment]
A passive component according to a first embodiment will be described with reference to FIGS. 1A and 1B.
FIG. 1A is a plan view of an inductor 30 included in the passive component according to the first embodiment, and FIG. 1B is a cross-sectional view taken along dashed-dotted line 1B-1B in FIG. 1A. A passive component according to the first embodiment includes a substrate 20 having an insulating surface and an inductor 30 disposed over the insulating surface of substrate 20 . The thickness of the substrate 20 is, for example, within the range of 50 μm or more and 300 μm or less, and the thickness of the substrate 20 is determined according to the height requirements of the passive components.

The inductor 30 includes a lower layer conductor pattern 31 and an upper layer conductor pattern 32 . In FIG. 1A, the lower layer conductor pattern 31 is hatched relatively darkly, and the upper layer conductor pattern 32 is relatively lightly hatched. 2A to 6A, which will be described later, are also hatched in the same manner. The underlying conductor pattern 31 is disposed on the insulating surface of the substrate 20 . A first insulating film 21 is arranged on the substrate 20 so as to cover the conductor pattern 31 in the lower layer. The upper conductor pattern 32 is arranged on the first insulating film 21 . A second-layer insulating film 22 is arranged on the first-layer insulating film 21 so as to cover the upper-layer conductor pattern 32 . The bottom surface of the upper conductor pattern 32 farther from the substrate 20 (the surface facing the substrate 20) is lower than the upper surface of the lower conductor pattern 31 closer to the substrate 20 (the surface facing away from the substrate 20). , are located far from the substrate 20 .

Each of the conductor patterns 31 and 32 has a spiral shape in plan view. For example, each of the conductor patterns 31 and 32 is arranged along the perimeter of a square or rectangle in plan view. In other words, each of the conductor patterns 31 and 32 is composed of a plurality of straight line portions bent at right angles.

The two conductor patterns 31 and 32 are connected in series so that current flows in the same direction with respect to the winding direction. Each of the conductor patterns 31 and 32 has about two turns, and one end of the upper conductor pattern 32 is connected to one end of the lower conductor pattern 31 through a via hole 35 .

The two conductor patterns 31 and 32 include linear portions arranged side by side in parallel in plan view. Here, "arranged in parallel" means that they are arranged side by side and extend in the same direction. The linear portions that are adjacent to each other and arranged in parallel are referred to as “parallel portions”. Current flows in the same direction in the two straight portions that constitute the parallel running portion. The direction (horizontal direction in FIG. 1B) perpendicular to the direction in which the two conductor patterns 31 and 32 run in parallel in plan view (the direction perpendicular to the paper surface of FIG. 1B) is defined as the width direction. do.

The "parallel running part" will be explained in more detail below. For example, in the cross section taken along the dashed-dotted line 1B-1B in FIG. 1A, two portions 31A and 31B of the lower layer conductor pattern 31 are located on both sides of the inner peripheral portion 32A of the upper layer conductor pattern 32 in plan view. arranged in parallel. As shown in FIG. 1B, the center-to-center spacing in the width direction between the inner peripheral portion 32A of the upper conductive pattern 32 and the inner peripheral portion 31A of the lower conductive pattern 31 is denoted by P1. The center-to-center spacing in the width direction between the inner peripheral portion 32A of the conductor pattern 32 and the outer peripheral portion 31B of the underlying conductor pattern 31 is denoted by P2.

Of the two portions 31A and 31B of the lower layer conductor pattern 31, the portion with the narrower center-to-center spacings P1 and P2 and the inner peripheral side portion 32A of the upper layer conductor pattern 32 constitute parallel running portions. . For example, when P1<P2, the inner peripheral side portion 32A of the upper layer conductor pattern 32 and the inner peripheral side portion 31A of the lower layer conductor pattern 31 constitute a parallel running portion. The inner peripheral side portion 32A and the outer peripheral side portion 31B of the underlying conductive pattern 31 do not constitute a parallel running portion. That is, when focusing on a portion of one conductor pattern, the portion of the other conductor pattern that has the narrowest center-to-center distance from the focused portion and the focused portion constitute the parallel running portion. When P1=P2, the inner peripheral portion 32A of the upper conductive pattern 32 forms parallel portions with both the inner peripheral portion 31A and the outer peripheral portion 31B of the lower conductive pattern 31. FIG.

The parallel running portions of the two conductor patterns 31 and 32 do not overlap in plan view. At a location (crossing location) where one conductor pattern 31 crosses the other conductor pattern 32 in the width direction, both have an overlapping portion.

Next, examples of materials for each component of the passive component will be described.
As the substrate 20, for example, an oxide insulating layer or nitride insulating layer is laminated on a ceramic substrate such as silicon nitride or aluminum oxide, a glass substrate made of a glass material containing silicon oxide as a main component, or a semiconductor substrate such as Si or GaAs. A substrate or the like is used. The oxide insulating layer is formed by thermal oxidation, chemical vapor deposition (CVD), or the like, for example. The nitride insulating layer is formed by CVD, for example.

A resin material with a low Young's modulus such as epoxy or polyimide is used for the insulating films 21 and 22 . In order to bring the coefficient of linear expansion of the insulating films 21 and 22 close to that of the substrate 20 , an inorganic material may be mixed in the resin material of the insulating films 21 and 22 .

For the conductor patterns 31 and 32, a metal material with high conductivity such as Au, Cu, Al is used. Metal materials containing these metals or alloys containing these metals as main materials may also be used. When the content of component A is 50% by weight or more, it can be said that component A is contained as the main material. It is preferable to use a metal containing Cu or a Cu alloy as a main material for the conductor patterns 31 and 32 because it is relatively inexpensive and can be easily thickened.

A metal layer may be arranged between the conductor pattern 31 and the substrate 20 and the insulating film 21 and between the conductor pattern 32 and the insulating films 21 and 22 for the purpose of improving adhesion. For example, Ti, Ni, W, Ta, and alloys containing these metals can be used for the metal layer intended to improve adhesion. An example alloy is TiW. When Cu is used as the conductor patterns 31 and 32, the Cu surface may be roughened.

Next, the excellent effects of the first embodiment will be described.
In plan view, if the lower layer conductor pattern 31 and the upper layer conductor pattern 32 overlap each other, a parasitic capacitance is generated between them. In the first embodiment, the parallel running portions of the two conductor patterns 31 and 32 do not overlap in plan view. Therefore, the parasitic capacitance in the parallel running portion is smaller than in the configuration in which the two overlap each other. This suppresses deterioration of the high-frequency characteristics of the inductor 30 . Although the two conductor patterns 31 and 32 overlap at the intersection, the area of the overlapping portion at the intersection is small compared to the total area of the conductor patterns 31 and 32 . Therefore, the parasitic capacitance generated at the intersection is sufficiently smaller than the parasitic capacitance when the parallel running portions overlap.

Furthermore, in the first embodiment, the bottom surface of the upper conductor pattern 32 is located farther from the substrate 20 than the upper surface of the lower conductor pattern 31 . Therefore, the distance between the upper conductor pattern 32 and the lower conductor pattern 31 becomes wider than in the configuration in which the bottom surface of the upper conductor pattern 32 is positioned closer to the substrate 20 than the upper surface of the lower conductor pattern 31. . Thereby, the parasitic capacitance between the lower layer conductor pattern 31 and the upper layer conductor pattern 32 can be reduced.

Next, a modification of the first embodiment will be described.
In the first embodiment, each of the two conductor patterns 31 and 32 includes a straight portion, but may include only curved portions without including straight portions. In this case, the parallel running portions are formed by the curved portions that are arranged adjacent to each other in parallel. In the two curved portions forming the parallel running portion, the tangential directions of the two curved lines are substantially parallel. In plan view, the direction orthogonal to the tangential direction of the curved portion corresponds to the width direction of the curved portion.

In the first embodiment, each of the two conductor patterns 31 and 32 has about 2 turns, but the number of turns may be other than 2, and the number of turns need not be an integer. The number of turns may be less than one. Moreover, it is not necessary to make the number of turns of one conductor pattern 31 and the number of turns of the other conductor pattern 32 the same.

Although the inductor 30 includes two conductor patterns 31 and 32 in the first embodiment, the inductor 30 may include three or more conductor patterns. In the first embodiment, the two conductor patterns 31 and 32 are arranged on the insulating surface of the substrate 20 and on the first insulating film 21, respectively. The arrangement of the patterns 31 and 32 is not limited to this configuration. For example, each of the two conductor patterns 31 and 32 may be arranged on the first insulating film 21 and on the second insulating film 22 . In other words, the two conductor patterns 31 and 32 may be conductor patterns laminated with an insulating film interposed between them, and are not necessarily on the insulating surface of the substrate 20 and on the first insulating film 21 . Doesn't have to be in place.

[Second embodiment]
Next, a passive component according to a second embodiment will be described with reference to FIGS. 2A and 2B. Hereinafter, descriptions of configurations common to the passive components (FIGS. 1A and 1B) according to the first embodiment will be omitted.

FIG. 2A is a plan view of an inductor 30 included in a passive component according to the second embodiment, and FIG. 2B is a cross-sectional view taken along dashed-dotted line 2B-2B in FIG. 2A. In the first embodiment, each of the two conductor patterns 31, 32 forming the inductor 30 is composed only of linear portions. On the other hand, in the second embodiment, each of the two conductor patterns 31 and 32 is composed of a straight portion and an arcuate curved portion.

The number of turns of the lower conductor pattern 31 is about 2, and the number of turns of the upper conductor pattern 32 is about 1.5. In the cross-sectional view shown in FIG. 2B, the right portion 32A of the upper conductive pattern 32 overlaps the inner peripheral portion 31A of the lower conductive pattern 31 in plan view, but does not overlap the outer peripheral portion 31B. do not have. Therefore, in FIG. 2B, the widthwise center-to-center spacing P1 between the right side portion 32A of the upper layer conductor pattern 32 and the inner peripheral side portion 31A of the lower layer conductor pattern 31 is equal to the right side portion 32A of the upper layer conductor pattern 32. is narrower than the center-to-center interval P2 in the width direction between the portion 32A and the portion 31B on the outer peripheral side of the conductor pattern 31 in the lower layer.

Focusing on the right portion 32A of the upper-layer conductor pattern 32, the right-hand portion 32A of the upper-layer conductor pattern 32 constitutes a portion running parallel to the inner peripheral side portion 31A of the lower-layer conductor pattern 31, but the upper-layer conductor The right portion 32A of the pattern 32 does not run parallel to the outer peripheral portion 31B of the underlying conductor pattern 31 . Focusing on the outer peripheral side portion 31B of the lower layer conductor pattern 31, the center-to-center distance from the focused portion 31B to the right portion 32A of the upper layer conductor pattern 32 is the narrowest. Therefore, the portion 31B on the outer peripheral side of the conductor pattern 31 in the lower layer constitutes a portion running parallel to the portion 32A on the right side of the conductor pattern 32 in the upper layer.

Next, the excellent effects of the second embodiment will be described.
In the second embodiment, part of the parallel running portions of the lower layer conductor pattern 31 and the upper layer conductor pattern 32 partially overlap in plan view, and each of the two mutually overlapping parallel running portions is It has a portion that does not overlap with respect to the width direction. In other words, the parallel running portions of the two conductor patterns 31 and 32 are mutually shifted in the width direction. For this reason, compared to a configuration in which one of the two parallel running portions is included in the other, an excellent effect is obtained in that the parasitic capacitance generated between the two parallel running portions is reduced. In addition, since the two parallel portions partially overlap in plan view, an excellent effect is obtained that the area occupied by the inductor 30 is reduced.

Next, a preferable relationship between the widths W1 and W2 of the conductor patterns 31 and 32 and the width Wov of the portion where the two parallel running portions overlap in plan view will be described. When the widthwise positions of the two parallel running portions match in plan view, the relationship of W1=W2=Wov is established. In the second embodiment, since the two parallel running portions are shifted in the width direction, the relationships Wov<W1 and Wov<W2 are established. In the inductor 30 designed so that W1=W2=Wov, the relationships of Wov<W1 and Wov<W2 are established even when a positional deviation within the process tolerance occurs.

Even if the two parallel running portions are misaligned in the width direction in plan view, if the amount of positional misalignment is within the allowable range for the process, a sufficient effect of reducing the parasitic capacitance cannot be obtained. In order to obtain a sufficient effect of reducing the parasitic capacitance, it is preferable to make the amount of deviation in the width direction of the two parallel running portions larger than the amount of deviation allowed in the process. For example, it is preferable to set the amount of deviation between the centers of the two parallel running portions in the width direction to 5 μm or more. At this time, both W1-Wov and W2-Wov are 5 μm or more.

[Third embodiment]
Next, a passive component according to a third embodiment will be described with reference to FIGS. 3A and 3B. Hereinafter, descriptions of configurations common to the passive components (FIGS. 2A and 2B) according to the second embodiment will be omitted.

3A is a plan view of an inductor 30 included in a passive component according to the third embodiment, and FIG. 3B is a cross-sectional view taken along dashed-dotted line 3B-3B in FIG. 3A. In the second embodiment, the lower layer conductor pattern 31 has about 2 turns, and the upper layer conductor pattern 32 has about 1.5 turns. On the other hand, in the third embodiment, the number of turns of the conductor pattern 31 in the lower layer is approximately 1.5, and the number of turns of the conductor pattern 32 in the upper layer is approximately 2.

Also, in the second embodiment, portions of the parallel running portions of the two conductor patterns 31 and 32 overlap each other in plan view. On the other hand, in the third embodiment, as in the first embodiment (FIGS. 1A and 1B), the parallel running portions of the two conductor patterns 31 and 32 do not overlap each other, and the two conductor patterns 31 and 32 do not overlap each other. 32 are overlapped in plan view only at the intersections of the two. The width W1 of the conductor pattern 31 in the lower layer is equal to the width W2 of the conductor pattern 32 in the upper layer.

In a plan view, one of the two conductor patterns 31 and 32 is arranged between the inner circumference side portion and the outer circumference side portion of the other conductor pattern. The distances G1 and G2 between the inner and outer peripheral portions of the two conductor patterns 31 and 32 are equal to the widths W1 and W2 of the two conductor patterns 31 and 32, respectively. Therefore, the parallel running portions of the two conductor patterns 31 and 32 are in contact with each other in plan view.

One of the two conductor patterns 31 and 32 intersects with the other conductor pattern approximately every half turn, and the positions of the two conductor patterns 31 and 32 in the width direction are exchanged at the crossing point.

In one cross section cut in the width direction at the linear portions of the two conductor patterns 31 and 32, for example, in the cross section shown in FIG. , the distance between the innermost two portions of the upper-layer conductor pattern 32 is denoted by L2. At this time, the interval L1 and the interval L2 are equal.

Next, the excellent effects of the third embodiment will be described.
In the third embodiment, since the parallel running portions of the two conductor patterns 31 and 32 do not overlap in plan view, the parallel running portions partially overlap with the second embodiment (FIGS. 2A and 2B). In comparison, the parasitic capacitance of inductor 30 is further reduced. Since the parallel running portions of the two conductor patterns 31 and 32 are in contact with each other in a plan view, the area occupied by the inductor 30 is smaller than in a configuration in which the two parallel running portions are spaced apart in the width direction. An excellent effect is obtained.

[Fourth embodiment]
Next, a passive component according to a fourth embodiment will be described with reference to FIGS. 4A and 4B. Hereinafter, descriptions of configurations common to the passive components (FIGS. 3A and 3B) according to the third embodiment will be omitted.

4A is a plan view of an inductor included in a passive component according to a fourth embodiment, and FIG. 4B is a cross-sectional view taken along dashed-dotted line 4B-4B in FIG. 4A. In the third embodiment, the lower layer conductor pattern 31 has about 1.5 turns, and the upper layer conductor pattern 32 has about 2 turns. In contrast, in the third embodiment, the number of turns of the conductor pattern 31 in the lower layer is approximately 2, and the number of turns of the conductor pattern 32 in the upper layer is approximately 1.5.

One of the two conductor patterns 31 and 32 intersects with the other conductor pattern about every turn. Counting from the inner circumference side of the inductor 30 in plan view, the lower layer conductor pattern 31 is arranged on the first and third turns, and the upper layer conductor pattern 32 is arranged on the second and fourth turns. there is Therefore, in the cross-section shown in FIG. 4B, the interval L1 between the two inner peripheral portions of the lower conductive pattern 31 is narrower than the interval L2 between the two inner peripheral portions of the upper conductive pattern 32 .

The parallel running portions of the two conductor patterns 31 and 32 are in contact with each other without overlapping in plan view, as in the third embodiment.

Next, the excellent effects of the fourth embodiment will be described.
Also in the fourth embodiment, similar to the third embodiment, the excellent effect of further reducing the parasitic capacitance of the inductor 30 can be obtained. Furthermore, an excellent effect is obtained that the area occupied by the inductor 30 is reduced.

[Fifth embodiment]
Next, a passive component according to a fifth embodiment will be described with reference to FIGS. 5A and 5B. Hereinafter, descriptions of configurations common to the passive components (FIGS. 2A and 2B) according to the second embodiment will be omitted.

FIG. 5A is a plan view of an inductor 30 included in a passive component according to the fifth embodiment, and FIG. 5B is a cross-sectional view taken along dashed-dotted line 5B-5B in FIG. 5A. In the second embodiment (FIGS. 2A and 2B), the widths W1 and W2 of the two conductor patterns 31 and 32 are equal. In contrast, in the fifth embodiment, the width W1 of the conductor pattern 31 in the lower layer is narrower than the width W2 of the conductor pattern 32 in the upper layer. The conductor pattern 31 in the lower layer is thicker than the conductor pattern 32 in the upper layer.

In plan view, the parallel running portions of the two conductor patterns 31 and 32 are in contact with each other without overlapping, as in the third embodiment (FIGS. 3A and 3B). Therefore, in the cross-sectional view shown in FIG. 5B, the interval G1 between the inner peripheral portion and the outer peripheral portion of the lower layer conductor pattern 31 is equal to the width W2 of the upper layer conductor pattern 32 . Similarly, the distance G2 between the inner peripheral portion and the outer peripheral portion of the upper layer conductor pattern 32 is equal to the width W1 of the lower layer conductor pattern 31 .

Next, the excellent effects of the fifth embodiment will be described.
Also in the fifth embodiment, the excellent effect of reducing the parasitic capacitance of the inductor 30 can be obtained. It is not necessary to make the widths W1 and W2 of the two conductor patterns 31 and 32 equal as in the fifth embodiment. Since the lower conductor pattern 31 having a smaller width is made thicker than the upper conductor pattern 32, an increase in parasitic resistance due to the narrower conductor pattern is suppressed.

The insulating surface of the substrate 20, which serves as the base surface of the lower conductor pattern 31, is substantially flat, but the upper surface of the insulating film 21, which serves as the base surface of the upper conductor pattern 32, reflects the shape of the lower conductor pattern 31. unevenness may appear. When the conductor pattern is formed, disconnection is likely to occur if the underlying surface has unevenness. In the fifth embodiment, since the width W2 of the upper layer conductor pattern 32 is relatively large, the occurrence of disconnection can be suppressed.

When the dielectric constant of the substrate 20 is higher than the dielectric constant of the insulating film 21 , the electric lines of force extending in the lateral direction between the inner peripheral side portion and the outer peripheral side portion of the underlying conductor pattern 31 preferentially enter the substrate 20 . occurs in Therefore, the substrate 20 having a high dielectric constant becomes a factor that increases the parasitic capacitance generated between the inner peripheral side portion and the outer peripheral side portion of the underlying conductor pattern 31 . In the fifth embodiment, the width of the lower conductor pattern 31 is relatively narrow, and the width of the upper conductor pattern 32 is relatively wide. The interval G1 with the side portion is widened. Therefore, it is possible to suppress an increase in the parasitic capacitance generated between the inner peripheral portion and the outer peripheral portion of the underlying conductor pattern 31 .

Next, a modified example of the fifth embodiment will be described.
In the fifth embodiment, the width W1 of the lower conductor pattern 31 is smaller than the width W2 of the upper conductor pattern 32; It can be thinner. In this case, the conductor pattern 31 in the lower layer should be thinner than the conductor pattern 32 in the upper layer. When the dielectric constant of the substrate 20 is approximately the same as the dielectric constant of the insulating film 21, the electric lines of force extending laterally between the inner peripheral side portion and the outer peripheral side portion of the underlying conductive pattern 31 are It does not preferentially occur within the substrate 20 . Therefore, even if the upper-layer conductor pattern 32 is made thinner and the lower-layer conductor pattern 31 is brought closer to the inner peripheral portion and the outer peripheral portion thereof, the influence of the increase in the parasitic capacitance can be reduced. In addition, since the conductor pattern 31 of the lower layer is thin, the height of the unevenness generated on the underlying surface of the conductor pattern 32 of the upper layer is reduced. Therefore, disconnection of the conductor pattern 32 in the upper layer does not tend to occur.

[Sixth embodiment]
Next, a passive component according to a sixth embodiment will be described with reference to FIGS. 6A and 6B. Hereinafter, descriptions of configurations common to the passive components (FIGS. 2A and 2B) according to the second embodiment will be omitted.

6A is a plan view of an inductor 30 included in a passive component according to the sixth embodiment, and FIG. 6B is a cross-sectional view taken along dashed-dotted line 6B-6B in FIG. 6A. In the second embodiment (FIGS. 2A and 2B), the width of each of the conductor patterns 31, 32 is uniform. On the other hand, in the sixth embodiment, the widths W1o and W2o of the outer peripheral portions of the conductor patterns 31 and 32 are larger than the widths W1i and W2i of the inner peripheral portions. The thicknesses of the conductor patterns 31 and 32 are the same on the inner peripheral side and the outer peripheral side.

Next, the excellent effects of the sixth embodiment will be described.
In a spiral conductor pattern having more than one turn, the length of one turn of the outer peripheral portion is longer than the length of one turn of the inner peripheral portion. In the sixth embodiment, since the width of the outer peripheral portion of the conductor patterns 31 and 32 is wider than the width of the inner peripheral portion, the resistance per unit length of the outer peripheral portion is greater than that of the inner peripheral side. Lower than the resistance per unit length of the part. Therefore, the difference in resistance per turn between the outer peripheral portion and the inner peripheral portion is reduced. The widths of the conductor patterns 31 and 32 are preferably set so that the resistance per turn is substantially equal between the outer peripheral portion and the inner peripheral portion.

Next, a modification of the sixth embodiment will be described. In the sixth embodiment, the widths of the conductor patterns 31 and 32 are changed for each turn in the winding direction, but the widths of the conductor patterns 31 and 32 may be changed at arbitrary positions in the winding direction. . For example, of the two conductor patterns 31 and 32 that make up the inductor 30, the dimension in the width direction of the conductor pattern with more than one turn monotonously decreases from the end on the outer circumference side toward the end on the inner circumference side. may be configured. As used herein, "monotonically decreasing" means "monotonically decreasing" in a broad sense. That is, on the path from the outer end to the inner end along the conductor pattern, is the width dimension at a certain position narrower than the width at a position closer to the outer end than that position? , or equal to or greater than or equal to the width at a position closer to the inner edge than that position. Even if the configuration according to this modified example is employed, the difference in resistance per turn between the outer peripheral portion and the inner peripheral portion can be reduced.

[Seventh embodiment]
Next, a passive component according to a seventh embodiment will be described with reference to FIGS. 7 to 13B. Hereinafter, descriptions of configurations common to the passive components (FIGS. 2A and 2B) according to the second embodiment will be omitted. A passive component according to the seventh embodiment is an integrated passive component (IPD) in which a plurality of inductors and a plurality of capacitors are integrated, and has a bandpass filter function.

FIG. 7 is an equivalent circuit diagram of a passive component according to the seventh embodiment.
A capacitor C1, an inductor L1, and a capacitor C2 are inserted in series in this order between the input terminal In and the output terminal Out. A series circuit of the capacitor C3 and the inductor L2 and a series circuit of the capacitor C4 and the inductor L3 are connected between the input terminal In and the ground GND. A series circuit of the capacitor C5 and the inductor L4 and a series circuit of the capacitor C6 and the inductor L5 are connected between the output terminal Out and the ground GND.

Next, a method of manufacturing a passive component according to the seventh embodiment will be described with reference to FIGS. 8A to 13B. 8A, 9A, 10A, 11A, and 12A are plan views of the passive component in the middle of manufacturing according to the seventh embodiment. FIG. 13A is a plan view of a passive component according to the seventh embodiment; Figures 8B, 9B, 10B, 11B, 12B, and 13B are shown in Figures 8A, 9A, 10A, 11A, 12A, and 13A, respectively. 10B-10B, 11B-11B, 12B-12B, and 13B-13B. FIG.

As shown in FIGS. 8A and 8B, conductive patterns 51 under the inductors L1, L2, L3, L4, and L5 (hereinafter referred to as inductors L1 to L5) are formed on the insulating surface of the substrate 40, and Intermediate electrodes 52 of capacitors C1, C2, C3, C4, C5 and C6 (hereinafter referred to as capacitors C1 to C6) are formed. In FIG. 8A, the underlying conductor pattern 51 and the intermediate electrode 52 are hatched.

The conductor pattern 51 under the inductor L1 has about two turns, and the conductor patterns 51 under the inductors L2, L3, L4, and L5 have about one turn. The lower conductor pattern 51 and the intermediate electrode 52 include a metal layer 61 for enhancing adhesion and a metal layer 62 disposed thereon. The metal layer 61 for enhancing adhesion is made of high-melting-point metals such as Ti, Ni, W, and Ta, or alloys containing these metals. Cu or the like is used for the metal layer 62 .

For the substrate 40, it is preferable to use a highly insulating material such as silicon oxide or silicon nitride. Since silicon nitride has good thermal conductivity, it is suitably used as the substrate 40 of passive components for applications where a relatively large amount of power is applied. The thickness of the substrate 40 is, for example, 50 μm or more and 300 μm or less.

Next, a method for forming the lower layer conductor pattern 51 and the intermediate electrode 52 will be described. A metal layer 61 is formed on the insulating surface of the substrate 40 by sputtering or the like. A Cu film, which is used as a power supply electrode for electroplating, is formed on the metal layer 61 by a sputtering method or the like. The upper surface of the Cu film is covered with a photoresist film, and openings are formed in this photoresist film so as to match the underlying conductor pattern 51 and the intermediate electrode 52 . A Cu film is deposited in the opening by electroplating. After removing the photoresist film, the exposed portion of the Cu film used for power supply and the unnecessary metal layer 61 are removed. A Cu film for power supply and a Cu film formed by electrolytic plating constitute the metal layer 62 .

A dielectric film 41 is formed on the entire surface of the substrate 40 by plasma-enhanced chemical vapor deposition (P-CVD) or the like so as to cover the underlying conductor pattern 51 and the intermediate electrode 52 . Dielectric film 41 is used as a dielectric film between electrodes of capacitors C1 to C6. The thickness of the dielectric film 41 is determined so as to meet quality requirements such as the capacitance value of the capacitor, withstand voltage, and moisture resistance. As an example, the thickness of the dielectric film 41 is 30 nm or more and 500 nm or less. As a material of the dielectric film 41, for example, a dielectric material containing silicon nitride, silicon oxide, aluminum oxide, aluminum nitride, tantalum oxide, etc. as a main material is used.

It should be noted that it is preferable to use a dielectric material containing the same material as the main material of the substrate 40 as the dielectric film 41 . When the main materials of the substrate 40 and the dielectric film 41 are the same, the difference in coefficient of linear expansion between the substrate 40 and the dielectric film 41 becomes small. This suppresses the occurrence of defects such as cracks due to concentration of thermal stress.

As shown in FIGS. 9A and 9B, a plurality of via holes H1 are formed in the dielectric film 41 by reactive ion etching (RIE) or the like. The plurality of via holes H1 are arranged at both ends of the conductor pattern 51 under the inductors L1 to L5 and are included in the conductor pattern 51. As shown in FIG. Furthermore, the dielectric film 41 in unnecessary regions is also removed at the same time.

Next, on the dielectric film 41, a pair of electrodes 53 for each of the capacitors C1 to C6 are formed. In FIG. 9A, the underlying conductor pattern 51 and the intermediate electrode 52 are represented by outline figures, and the electrodes 53 are hatched. A pair of electrodes 53 of each of capacitors C1-C6 is included in intermediate electrode 52 in plan view. The electrode 53 on one side, the dielectric film 41, the intermediate electrode 52, the dielectric film 41, and the electrode 53 on the other side constitute an MIM capacitor.

A pair of electrodes 53 of each of the capacitors C1 to C6 is made of a highly conductive metal such as Al, Au, Cu, or an alloy containing these metals. A metal layer may be provided on at least one of the lower surface and the upper surface of the pair of electrodes to improve adhesion. As the metal layer for improving adhesion, a high-melting-point metal such as Ti, Ni, W, or Ta, or an alloy containing these metals can be used. This metal layer also functions as a diffusion prevention layer that prevents metal from diffusing into the insulating film.

Next, a method for forming the electrodes 53 will be described. First, a photoresist pattern is formed by the image reverse method. After forming the photoresist pattern, a Ti film and an Au film are formed by vacuum deposition or sputtering. The thicknesses of the Ti film and the Au film are set to 50 nm and 100 nm, respectively. After that, the photoresist pattern and the Ti film and Au film thereon are removed by a lift-off method.

As shown in FIGS. 10A and 10B, an insulating film 42 is formed on the dielectric film 41 so as to cover the electrodes 53 . After that, a plurality of via holes H2 are formed in the insulating film 42. Next, as shown in FIG. The plurality of via holes H2 are arranged at positions overlapping with the via holes H1 formed in the dielectric film 41 and at positions included in the pair of electrodes 53 of each of the capacitors C1 to C6.

Next, a method for forming the insulating film 42 and the via hole H2 will be described. First, a B-stage epoxy resin film processed into a film and mixed with a photosensitive material is laminated by a vacuum lamination method. After forming a photosensitive portion and a non-photosensitive portion by photolithography, the via hole H2 is formed by developing using an alkaline solution. After that, heat treatment is performed to harden the epoxy resin film.

As shown in FIGS. 11A and 11B, on the insulating film 42, a conductor pattern 56, a plurality of wirings 55, and a plurality of pads 57 are formed on the inductors L1 to L5. In FIG. 11A, the conductor pattern 56, the plurality of wirings 55, and the plurality of pads 57 on the upper layer of the inductors L1 to L5 are hatched. In addition, the conductor pattern 51 in the lower layer, the intermediate electrode 52, and the electrodes 53 of the capacitors C1 to C6 are indicated by outline figures. The plurality of conductor patterns 56, the plurality of wirings 55, and the plurality of pads 57 are composed of two layers, a metal layer 63 made of Ti or the like arranged for the purpose of improving adhesion, and a metal layer 64 made of Cu or the like thereon. consists of

The number of turns of the conductive pattern 56 on the upper layer of the inductors L1, L2, L4 is about 1.5, and the number of turns of the conductive pattern 56 on the upper layer of the inductors L3, L5 is about 1. The lower-layer conductor pattern 51 and the upper-layer conductor pattern 56 of the inductor L1 are similar to the relationship between the lower-layer conductor pattern 31 and the upper-layer conductor pattern 32 of the inductor 30 according to the third embodiment (FIGS. 3A and 3B). The parallel running portions do not overlap each other. In the other inductors L2 to L5, most of the conductor pattern 51 in the lower layer and the conductor pattern 56 in the upper layer are substantially aligned in the width direction.

One end of each upper layer conductor pattern 56 is connected to the lower layer conductor pattern 51 through via holes H2 and H1. The other end of conductor pattern 56 on the upper layer of inductor L1 is connected to one electrode 53 of capacitor C1 through via hole H2. The other end of the conductor pattern 56 on the upper layer of the inductors L2 to L5 is continuous with a pad 57 for ground GND.

A plurality of wirings 55 connect one end of the conductor pattern 51 under the inductors L1 to L5 and one electrode 53 of each of the capacitors C2 to C6. Three wirings 55 extending from a pad 57 for the input terminal In are connected to one electrodes 53 of the capacitors C1, C3 and C4, respectively. Three wirings 55 extending from a pad 57 for the output terminal Out are connected to one electrodes 53 of the capacitors C2, C5 and C6, respectively.

Next, a method for forming the plurality of conductor patterns 56, the plurality of wirings 55, and the plurality of pads 57 will be described. First, a Ti film and a Cu film are formed by sputtering. A photoresist film is formed on the Cu film, and openings matching the conductor pattern 56 , the wiring 55 and the pad 57 are formed in the photoresist film. Using a Cu film as a seed layer, a Cu film is deposited in the opening by electroplating. After that, the photoresist film is removed with an organic solvent. Furthermore, the exposed portion of the Cu film used as the seed layer and the unnecessary Ti film are removed by wet etching.

As shown in FIGS. 12A and 12B, an insulating film 43 is formed on the insulating film 42 so as to cover the conductor pattern 56, the wiring 55, and the pad 57, and a plurality of via holes H3 are formed in the insulating film 43. The method of forming the insulating film 43 and the via hole H3 is the same as the method of forming the insulating film 42 and the via hole H2. A plurality of via holes H3 are each included in a plurality of pads 57 in plan view.

As shown in FIGS. 13A and 13B, a plurality of external connection terminals 58 are formed on the insulating film 43 and their surfaces are covered with an anti-oxidation film 59. As shown in FIGS. In FIG. 13A, the external connection terminals 58 are hatched. A plurality of external connection terminals 58 are connected to pads 57 through via holes H3. Two external connection terminals 58 are ground terminals, another external connection terminal 58 is an input terminal In, and the remaining one external connection terminal 58 is an output terminal Out.

A low resistance metal such as Cu, Al or Au is used for the external connection terminal 58 . NiAu, NiPdAu, or the like is used for the antioxidant film 59 . The anti-oxidation film 59 prevents oxidation of the external connection terminals 58 and ensures sufficient solder connectivity. A solder layer such as NiSn or NiSnAg may be added on the anti-oxidation film 59 .

Next, a method for forming the external connection terminals 58 and the anti-oxidation film 59 will be described. An external connection terminal 58 is formed by a method similar to the method of forming the conductor pattern 56 , the pad 57 and the wiring 55 . An antioxidant film 59 made of NiAu is formed on the surface of the external connection terminal 58 by electroless plating.

After forming the external connection terminals 58 and the anti-oxidation film 59, the substrate 40 is ground (back-grinded) from the rear surface to reduce the thickness of the substrate 40 to a desired thickness. Finally, the substrate 40 is diced to singulate the passive components.

Next, the excellent effects of the seventh embodiment will be described.
Parasitic capacitance between the lower-layer conductor pattern 51 and the upper-layer conductor pattern 56 is reduced because the parallel-running portions of the lower-layer conductor pattern 51 and the upper-layer conductor pattern 56 of the inductor L1 do not overlap in plan view. be able to.

Further, the intermediate electrodes 52 (FIGS. 8A and 8B) of the capacitors C1 to C6 are arranged in the same layer as the conductor patterns 51 (FIGS. 8A and 8B) under the inductors L1 to L5, and the same film formation is performed. Formed in the process. Therefore, the manufacturing process can be simplified.

The wiring 55 (FIGS. 12A and 12B) connected to the inductors L1 to L5 and the pad 57 is arranged in the same layer as the conductor pattern 56 on the upper layer of the inductors L1 to L5. Conductive patterns 56 on the upper layer of inductors L1 to L5 are usually formed thick in order to suppress an increase in electrical resistance. Since the wiring 55 arranged in the same layer as the conductor pattern 56 is also thickened, the equivalent series resistance (ESR) of the capacitors C1 to C6 can be reduced. Therefore, the Q value of the filter is improved, and it becomes possible to reduce the filter loss.

Next, a modified example of the seventh embodiment will be described.
In the seventh embodiment, the conductor pattern 51 in the lower layer and the conductor pattern 56 in the upper layer do not overlap each other in the inductor L1. A configuration in which two parallel running portions partially overlap each other may also be used. Also, in the other inductors L2 to L5, the parallel running portions of the lower layer conductor pattern 51 and the upper layer conductor pattern 56 may not overlap, or may partially overlap in the width direction.

Also, in the seventh embodiment, the conductor patterns 51 in the lower layer of the inductors L1 to L5 and the intermediate electrodes 52 of the capacitors C1 to C6 are arranged in the same layer. As another configuration, at least one electrode of capacitors C1 to C6 and at least one conductor pattern of inductors L1 to L5 may be arranged in the same layer.

[Eighth embodiment]
Next, an inductor according to an eighth embodiment will be described with reference to FIG. Hereinafter, descriptions of configurations common to the passive components (FIGS. 2A and 2B) according to the second embodiment will be omitted.

FIG. 14 is a cross-sectional view of part of the passive component according to the eighth embodiment. In the second embodiment (FIGS. 2A and 2B), the conductor patterns 31 and 32 of the inductor 30 have a substantially rectangular cross-sectional shape perpendicular to the winding direction (hereinafter simply referred to as cross-sectional shape). In contrast, in the eighth embodiment, the cross-sectional shape of the lower layer conductor pattern 31 is trapezoidal, and the cross-sectional shape of the upper layer conductor pattern 32 is an inverted trapezoid. Here, "trapezoidal" and "inverted trapezoidal" do not mean geometrically strict trapezoids or inverted trapezoids. A cross-sectional shape in which the side surface of the conductor pattern is inclined and the width gradually narrows in the direction away from the substrate 20 is called a “trapezoid”, and the cross-sectional shape in which the width gradually widens in the direction away from the substrate 20 is called a “trapezoid”. It is called "inverted trapezoidal shape".

The width of the surface of the lower conductor pattern 31 facing the substrate 20 is denoted by W1b, and the width of the surface facing away from the substrate 20 is denoted by W1t. The width of the surface of the upper conductor pattern 32 facing the substrate 20 is denoted by W2b, and the width of the surface facing away from the substrate 20 is denoted by W2t. In the eighth embodiment, the relationships W1b>W1t and W2t>W2b are established.

The width of the overlapping portion in plan view of the parallel running portions of the conductor patterns 31 and 32 is denoted as Wova. The width of the overlapped portion of the parallel running portions of the conductor patterns 31 and 32 is denoted by Wovb.

In the eighth embodiment, as in the second embodiment (FIGS. 2A and 2B), the parallel running portions of the two conductor patterns 31 and 32 have portions that do not overlap each other in the width direction. That is, the relationships Wova<W1b and Wova<W2t are established. Furthermore, the relationships Wovb<W1t and Wovb<W2b are established.

Next, a method for forming the conductor patterns 31 and 32 having trapezoidal or inverted trapezoidal cross-sectional shapes will be described. The basic process of forming conductor patterns 31 and 32 is common to the process of forming conductor pattern 51 (FIGS. 8A and 8B) in the lower layer of the passive component according to the seventh embodiment. In the eighth embodiment, the cross-sectional shape of the opening of the photoresist film used as a mask when depositing the Cu film by electrolytic plating is trapezoidal or inverted trapezoidal. Such an opening can be formed by intentionally shifting the focus position in the thickness direction when exposing the photoresist film. By depositing a Cu film in this opening, the conductor patterns 31 and 32 having a trapezoidal or inverted trapezoidal cross section can be formed.

Next, another method for forming the conductor pattern 31 having a trapezoidal cross-sectional shape will be described. A Ti film and a Cu film are formed on the entire insulating surface of the substrate 20 by sputtering. After that, using the Cu film as a seed layer, a Cu film is formed on the entire insulating surface of the substrate 20 by electroplating. After that, the portion where the conductor pattern 31 is to be formed is covered with a photoresist pattern. Using this photoresist pattern as an etching mask, the Cu film is etched using an aqueous copper chloride solution or an aqueous iron chloride solution. Since this etching progresses isotropically in the depth direction and the lateral direction, a conductor pattern 31 having a substantially trapezoidal cross-sectional shape is formed. Instead of the Ti film, a film made of a high-melting-point metal such as Ni, W, or Ta, or a film made of an alloy containing a high-melting-point metal such as Ti, Ni, W, or Ta may be used.

Next, the excellent effects of the eighth embodiment will be described.
In the eighth embodiment, of the surfaces on which the parallel running portions of the two conductor patterns 31 and 32 face each other, the area of the overlapping portion in plan view becomes smaller than when the cross-sectional shape is rectangular. In other words, the width Wovb of the overlapping portion is narrower than the width Wova of the overlapping portion. Therefore, the parasitic capacitance between the two conductor patterns 31 and 32 is further reduced. Thereby, the Q value of the inductor 30 can be made higher.

When the cross-sectional shape of the lower layer conductor pattern 31 is triangular or rounded triangle, and the cross-sectional shape of the upper layer conductor pattern 32 is inverted triangle or rounded inverted triangle, the width Wovb of the overlapping portion can be made almost zero. However, in this configuration, the current tends to concentrate near the upward ridgeline of the lower conductor pattern 31 and near the downward ridgeline of the upper conductor pattern 32 . When the current concentrates in such a narrow region, dielectric breakdown is likely to occur. On the other hand, in the eighth embodiment, the range in which the current concentrates is composed of planes. As a result, the local concentration of current is alleviated, and an excellent effect is obtained that dielectric breakdown is less likely to occur. In order to suppress concentration of current, it is preferable that the areas where the lower-layer conductor pattern 31 and the upper-layer conductor pattern 32 face each other are configured as planes.

Furthermore, in the eighth embodiment, compared to the configuration in which the conductor patterns 31 and 32 have rectangular cross-sectional shapes, the distance between the inner and outer peripheral portions of the conductor patterns 31 and 32 can be narrowed. can. Thereby, it is possible to reduce the size of the inductor 30 .

Next, a modified example of the eighth embodiment will be described.
In the eighth embodiment, the cross-sectional shapes of the conductor patterns 31 and 32 are both trapezoidal with corners, but they may be trapezoids with rounded corners. For example, the cross-sectional shape of the conductor patterns 31 and 32 may be a rounded trapezoid depending on the conditions of the manufacturing process. Even in this case, when the regions in which the lower-layer conductor pattern 31 and the upper-layer conductor pattern 32 face each other are composed of planes, an excellent effect that dielectric breakdown is less likely to occur can be obtained.

In the eighth embodiment, the cross-sectional shape of the lower conductor pattern 31 is trapezoidal, and the cross-sectional shape of the upper conductive pattern 32 is an inverted trapezoid. As another configuration, if the cross-sectional shape of the parallel running portion of the lower layer conductor pattern 31 (that is, the conductor pattern closer to the substrate 20 of the two conductor patterns 31 and 32) is trapezoidal, the other conductor pattern 32 may be rectangular or trapezoidal. Conversely, if the cross-sectional shape of the parallel running portion of the upper conductor pattern 32 (that is, the conductor pattern of the two conductor patterns 31, 32 farther from the substrate 20) is an inverted trapezoid, the other conductor pattern 31 is , a rectangular shape, or an inverted trapezoidal shape.

[Ninth embodiment]
Next, a passive component according to the ninth embodiment will be described with reference to FIGS. 15A and 15B. Hereinafter, descriptions of configurations common to the passive components according to the fifth embodiment (FIGS. 5A and 5B) will be omitted.

15A is a plan view of an inductor 30 included in a passive component according to the ninth embodiment, and FIG. 15B is a cross-sectional view taken along dashed-dotted line 15B-15B in FIG. 15A. The planar view shape of the inductor 30 shown in FIG. 15A is the same as the planar view shape of the inductor 30 of the fifth embodiment (FIG. 5A).

The detailed structure of the substrate 20 is not mentioned in the fifth embodiment (FIG. 5B). A substrate 20 used for passive components according to the ninth embodiment includes a base substrate 20A made of a semiconductor such as silicon, and an insulating layer 20B made of silicon oxide, silicon nitride, or the like disposed thereon. A lower layer conductor pattern 31 is arranged on the insulating layer 20B.

In the ninth embodiment, as in the fifth embodiment (FIG. 5B), the width W1 of the lower layer conductor pattern 31 is narrower than the width W2 of the upper layer conductor pattern 32 . In the fifth embodiment (FIG. 5B), the conductor pattern 31 in the lower layer is thicker than the conductor pattern 32 in the upper layer. On the other hand, in the ninth embodiment, the lower layer conductor pattern 31 and the upper layer conductor pattern 32 have substantially the same thickness. Here, "thickness" means a dimension in the height direction when the direction perpendicular to the insulating surface of the substrate 20 is defined as the height direction.

Next, the excellent effects of the ninth embodiment will be described.
When the substrate 20 includes a base substrate 20A made of a semiconductor and an insulating layer 20B disposed thereon, parasitic capacitance is generated between the conductor patterns 31, 32 forming the inductor 30 and the base substrate 20A. In particular, the parasitic capacitance between the underlying conductor pattern 31 and the underlying substrate 20A tends to increase. In the ninth embodiment, since the lower-layer conductor pattern 31 is thinner than the upper-layer conductor pattern 32, the lower-layer conductor pattern 31 is thinner than the upper-layer conductor pattern 32, compared to the configuration in which the lower-layer conductor pattern 31 has the same width as the upper-layer conductor pattern 32. and the underlying substrate 20A can be reduced.

The parasitic capacitance is greatly affected by the area of the region where the underlying conductor pattern 31 and the base substrate 20A face each other, and is hardly affected by the thickness of the underlying conductor pattern 31. Therefore, in the ninth embodiment, the lower layer conductor pattern 31 may be thicker than the upper layer conductor pattern 32, as in the fifth embodiment (FIG. 5A).

[Tenth embodiment]
Next, the passive component according to the tenth embodiment will be described with reference to FIG. 16A. Hereinafter, descriptions of configurations common to the passive components (FIGS. 1A and 1B) according to the first embodiment will be omitted.

FIG. 16A is a cross-sectional view of the passive component inductor 30 according to the tenth embodiment. In the first embodiment (FIG. 1B), the distance between the inner peripheral side portion and the outer peripheral side portion of the two conductor patterns 31 and 32 adjacent to each other in the width direction, the lower layer conductor pattern 31 and the upper layer conductor pattern 32 No mention is made of the vertical spacing between and . The tenth embodiment defines the preferred relationship of these intervals.

The distance in the height direction between the two conductor patterns 31 and 32 forming the inductor 30 is denoted by H. The distance between the outer peripheral side portion and the inner peripheral side portion of the lower layer conductor pattern 31 adjacent in the width direction is denoted by G1, and the distance between the outer peripheral side portion and the inner peripheral side portion of the upper layer conductive pattern 32 adjacent in the width direction is denoted by G1. The distance between the parts is labeled as G2. In the tenth embodiment, the heightwise interval H is wider than both the widthwise intervals G1 and G2.

Next, the excellent effects of the tenth embodiment will be described. In order to reduce the parasitic capacitance of the conductor patterns 31, 32 forming the inductor 30, it is preferable to widen the intervals G1, G2, H. However, if the upper limit of the area occupied by the inductor 30 on the surface of the substrate 20 is determined, the widthwise intervals G1 and G2 cannot be widened without limit. Even if the interval H in the height direction is widened, the area occupied by the inductor 30 does not increase. Even if the gaps G1 and G2 cannot be widened due to restrictions imposed by the upper limit of the area of the region where the inductor 30 is arranged, by making the gap H in the height direction wider than the gaps G1 and G2, the parasitic capacitance A certain effect of reducing the It should be noted that the interval H in the height direction may be wider than at least one of the intervals G1 and G2 in the width direction. Also in this configuration, a certain effect of reducing the parasitic capacitance can be obtained.

Next, a passive component according to a modification of the tenth embodiment will be described with reference to FIG. 16B. FIG. 16B is a cross-sectional view of the passive component inductor 30 according to the modification of the tenth embodiment. In this modification, both the widthwise intervals G1 and G2 are wider than the heightwise interval H. FIG. Due to restrictions imposed by the upper limit of the height of passive components, it may not be possible to widen the dimension H in the height direction. On the other hand, there may be a margin in the region where the inductor 30 is arranged. In such a case, by making the gaps G1 and G2 in the width direction wider than the gap H in the height direction, a certain effect of reducing the parasitic capacitance can be obtained. At least one of the gaps G1 and G2 in the width direction may be wider than the gap H in the height direction. Also in this configuration, a certain effect of reducing the parasitic capacitance can be obtained.

It goes without saying that each of the above-described embodiments is an example, and partial replacement or combination of configurations shown in different embodiments is possible. Similar actions and effects due to similar configurations of multiple embodiments will not be sequentially referred to for each embodiment. Furthermore, the invention is not limited to the embodiments described above. For example, it will be obvious to those skilled in the art that various changes, improvements, combinations, etc. are possible.

20 substrate 20A base substrate 20B insulating layer 21 first-layer insulating film 22 second-layer insulating film 30 inductor 31 lower- layer conductor patterns 31A and 31B constituting inductor part of lower-layer conductor pattern 32 constituting inductor upper-layer conductor pattern 32A, part 35 of the upper-layer conductor pattern constituting the inductor, via-hole 40, substrate 41, dielectric films 42, 43, insulating film 51, lower-layer conductor pattern 52, which constitutes the inductor, intermediate electrode 53 of the capacitor, and pair of electrodes 55 of the capacitor. Wiring 56 Upper conductor pattern 57 constituting the inductor Pad 58 External connection terminal 59 Anti-oxidation films 61, 62, 63, 64 Metal layer

Claims (17)

1. a substrate having an insulating surface;
   an inductor including two conductor patterns stacked on the insulating surface of the substrate with an insulating film sandwiched therebetween;
   each of the two conductor patterns forming the inductor has a spiral shape in plan view,
   The two conductor patterns that make up the inductor are connected in series so that current flows in the same direction with respect to the winding direction, and include parallel running portions that are arranged in parallel and adjacent to each other in a plan view,
   Both of the parallel running portions of the two conductor patterns that constitute the inductor have portions that do not overlap each other in the width direction orthogonal to the direction extending in parallel,
   Of the two conductor patterns forming the inductor, the surface of the conductor pattern farther from the substrate facing the substrate faces the side opposite to the substrate of the conductor pattern closer to the substrate. A passive component located farther from the substrate than the plane.
2. In a plan view, two parallel running portions of one of the two conductor patterns forming the inductor are arranged on both sides of the parallel running portion of the other conductor pattern. 2. Passive component according to claim 1, wherein the part is arranged between two parallel parts of the other conductor pattern.
3. The passive component according to claim 1 or 2, wherein the parallel running portions of the two conductor patterns forming the inductor do not overlap in the width direction when viewed from above.
4. The passive component according to claim 1 or 2, wherein the parallel running portions of the two conductor patterns forming the inductor have mutually different dimensions in the width direction.
5. Of the parallel running portions of the two conductor patterns forming the inductor, the width direction dimension of the parallel running portion located on the side of the substrate is smaller than the width direction dimension of the parallel running portion located on the far side from the substrate. A passive component according to claim 4 .
6. When the direction perpendicular to the insulating surface of the substrate is defined as the height direction, of the parallel running portions of the two conductor patterns forming the inductor, the height direction of the parallel running portion located on the substrate side. 6. The passive component according to claim 5, wherein the dimension of is greater than the dimension in the height direction of the parallel running portion located on the far side from the substrate.
7. At least one of the two conductor patterns forming the inductor has more than one turn, and the widthwise dimension of the relatively outer peripheral portion is larger than the widthwise dimension of the relatively inner peripheral portion. 3. A passive component according to claim 1 or 2.
8. 8. The method according to claim 7, wherein, of the two conductor patterns forming the inductor, the widthwise dimension of the conductor pattern having more than one turn monotonically decreases from the outer peripheral end to the inner peripheral end. Passive components as described.
9. Of the parallel running portions of the two conductor patterns forming the inductor, the parallel running portion of the conductor pattern closer to the substrate has a dimension in the width direction of the surface facing the opposite side of the substrate, the surface facing the substrate. 3. The passive component according to claim 1, wherein the cross-sectional shape is smaller than the dimension in the width direction.
10. 3. A cross-sectional shape of a parallel running portion of the conductor pattern closer to the substrate, of the parallel running portions of the two conductor patterns forming the inductor, is trapezoidal in cross section, the width of which narrows in the direction away from the substrate. 9. Passive component according to 9.
11. Of the parallel running portions of the two conductor patterns forming the inductor, the parallel running portion of the conductor pattern farther from the substrate has a dimension in the width direction of the surface facing the substrate facing the opposite side of the substrate. 3. The passive component according to claim 1 or 2, which is smaller than the dimension in the width direction of the .
12. The cross-sectional shape of the parallel running portion of the two conductor patterns that constitute the inductor, which is farther from the substrate, is an inverted trapezoid whose width increases in a direction away from the substrate. Item 12. The passive component according to Item 11.
13. further comprising a capacitor disposed over the insulating surface of the substrate;
    3. The passive component according to claim 1, wherein at least one electrode included in said capacitor is arranged in the same layer as one of two conductor patterns forming said inductor.
14. The passive component according to claim 1 or 2, wherein the two conductor patterns forming the inductor contain Au, Cu, Al, or an alloy of these metals as main components.
15. insulation between at least a partial region of the surfaces of the two conductor patterns forming the inductor and the insulating film, and between the conductor pattern closer to the substrate and the substrate among the two conductor patterns forming the inductor; 3. The passive component according to claim 1, further comprising a metal layer made of Ti, Ni, W, Ta, or an alloy containing these metals, on at least one of the surfaces of the passive component.
16. When the direction perpendicular to the insulating surface of the substrate is taken as the height direction, at least one of the two conductor patterns constituting the inductor has a height-direction interval between the two conductor patterns constituting the inductor. 3. The passive component according to claim 1, wherein the space between the inner peripheral side portion and the outer peripheral side portion adjacent to each other in the width direction is wider than the interval.
17. When the direction perpendicular to the insulating surface of the substrate is taken as the height direction, at least one of the two conductor patterns forming the inductor has an inner peripheral portion and an outer peripheral portion adjacent to each other in the width direction. 3. The passive component according to claim 1, wherein the distance between and is wider than the distance in the height direction between the two conductor patterns forming said inductor.
    

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