CN100423264C - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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- CN100423264C CN100423264C CNB2005100834790A CN200510083479A CN100423264C CN 100423264 C CN100423264 C CN 100423264C CN B2005100834790 A CNB2005100834790 A CN B2005100834790A CN 200510083479 A CN200510083479 A CN 200510083479A CN 100423264 C CN100423264 C CN 100423264C
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Abstract
A semiconductor device includes a semiconductor substrate having an electrode formed above a surface thereof; a first insulating resin layer that is provided over the semiconductor substrate and has a first opening defined at a position corresponding to the electrode; a first wiring layer that is provided on the first insulating resin layer and is connected to the electrode through the first opening; a second insulating resin layer provided over the first insulating resin layer and the first wiring layer, the second insulating resin layer having a second opening that is defined at a position different from the position of the first opening in a direction of the surface of the semiconductor substrate; and a second wiring layer that is provided on the second insulating resin layer and is connected to the first wiring layer through the second opening, wherein the second wiring layer includes an induction element, and a sum of a thickness of the first insulating resin layer and a thickness of the second insulating resin layer is not less than 5 mum and not more than 60 mum.
Description
Technical field
The present invention relates to a kind of semiconductor device and manufacture method thereof, wherein have the semi-conductive formation that is formed on as the sensing element on the semiconductor chip of silicon wafer and finish with its encapsulation.
Japanese patent application No.2004-221785 that submitted on July 29th, 2004 and the Japanese patent application No.2004-302696 that submitted on October 18th, 2004 are required priority, and its content is hereby incorporated by.
Background technology
In recent years, in the manufacturing of high-frequency semiconductor element,, on semiconductor chip, form sensing element, as spiral inductor for guaranteeing its impedance matching etc.Yet in such semiconductor element, because the parasitic capacitance between wiring and the semiconductor chip, the electromagnetic energy that part is produced by sensing element is lost in substrate or constitutes in the wiring of this sensing element.Such energy loss discloses among the first announcement No.2003-86690 in for example Japanese unexamined patent.
A reason of such electromagnetic energy loss be wiring with semiconductor chip between relative near vertical range, it makes that the influence of parasitic capacitance is remarkable.For eliminating such loss, a kind of technology is proposed, wherein between semiconductor chip and sensing element, provide thick resin bed, with the loss (seeing for example NIKKEI MICRODEVICES, in March, 2002,125-127 page or leaf) that prevents electromagnetic energy.
Fig. 1,2A and 2B illustrate the example of the conventional semiconductor device with helical coil.Fig. 1 is a plane graph, and Fig. 2 A is exploded (broken) perspective view, and Fig. 2 B is the viewgraph of cross-section of being got along the line B-B shown in Fig. 1.
In semiconductor device 20, semiconductor chip 1 comprises integrated circuit formed thereon (IC) 2, and the electrode 3 of integrated circuit 2 and passivating film 4 (insulator film) are provided on the surface of semiconductor chip 1.
In addition, the following wiring layer 21 that is connected to electrode 3 is formed on the passivating film 4 on the semiconductor chip 1, and insulating resin layer 22 is formed on semiconductor chip 1 and the following wiring layer 21.On insulating resin layer 22, the last wiring layer 23 with helical coil 24 provides as dielectric element (dielectricelement).Helical coil 24 is connected to the electrode 3 of integrated circuit 2 via following wiring layer 21.
Fig. 3 A-3D is a schematic cross-sectional view, and substep illustrates the illustrative methods that is used for the semiconductor device shown in shop drawings 1,2A and the 2B.
At first, as shown in Figure 3A, provide to have integrated circuit 2 semiconductor chip 1 of electrode 3 and passivating film 4.Semiconductor chip 1 is a silicon wafer for example, provides aluminium pad (aluminumpad) as electrode 3 thereon, and it has been capped by SiN, SiO
2Deng the passivating film of making 4.In passivating film 4, opening 5 is limited at the position corresponding to electrode 3, and electrode 3 exposes from opening 5.Can for example use any well-known method, passivating film 4 is formed into for example thickness between the 0.1 μ m and 0.5 μ m as low-pressure chemical vapor deposition (LPCVD) technology.
Secondly shown in Fig. 3 B, following wiring layer 21 is formed on the passivating film 4 on the semiconductor chip 1.Following wiring layer 21 is the redistributing layers (redistribution layer) (following path (under path)) that are connected between electrode 3 and the helical coil 24, and its first end 21a is connected to electrode 3, and the second end 21b is connected to end 23a and the 23b (seeing Fig. 3 D) that is provided at down the last wiring layer 23 on the wiring layer 21.The material of following wiring layer 21 can be for example aluminium or copper, and its thickness can be between for example 0.1 μ m and 10 μ m.Can use any well-known method, for example sputter, evaporation, plating wait and form down wiring layer 21.
Then shown in Fig. 3 C, insulating resin layer 22 is formed on the passivating film 4 and following wiring layer 21 on the semiconductor chip 1.Insulating resin layer 22 can be made by for example polyimide resin, epoxy resin, silicones (silicon resin) etc., and its thickness can be between for example 0.1 μ m and 10 μ m.Can use any well-known method to form insulating resin layer 22, for example spin coating method, printing process, laminating method etc.In insulating resin layer 22, opening 25 is limited at the position (at two openings shown in Fig. 3 A-3D) corresponding to the second end 21b of following wiring layer 21.Can use patterning techniques etc., for example limit opening 25 by means of photoetching.
Shown in Fig. 3 D, the last wiring layer 23 with helical coil 24 forms on insulating resin layer 22 subsequently.The end 23a of last wiring layer 23 and 23b pass opening 25 that is limited in the insulating resin layer 22 and the second end 21b that is connected to down wiring layer 21 by opening 25.The material of last wiring layer 23 can be a copper for example, and its thickness can be between for example 1 μ m and 20 μ m.Can for example use any well-known technology, as electroplate and form wiring layer 23.
Although helical coil 24 is formed in the wiring layer 23 in the conventional example shown in Fig. 3 A-3D, helical coil 24 can be formed on down on the wiring layer 21 shown in Fig. 4 A-4D.The process that is used for making the semiconductor device that helical coil 24 wherein forms at wiring layer 21 down is described below with reference to Fig. 4 A-4D.
At first shown in Fig. 4 A, provide have integrated circuit 2, the semiconductor chip 1 of electrode 3 and passivating film 4.Description to the semiconductor chip 1 shown in Fig. 4 A-4D is omitted, because it is similar to the semiconductor chip 1 shown in Fig. 3 A.
Secondly shown in Fig. 4 B, following wiring layer 21 is formed on the passivating film 4 on the semiconductor chip 1.Following wiring layer 21 comprises interconnect conductive layers 26 and the helical coil 24 that is connected to electrode 3.In the stage afterwards, helical coil 24 will be connected to interconnect conductive layers 26 and electrode 3.
The material of following wiring layer 21 can be for example aluminium or copper, and its thickness can be between for example 0.1 μ m and 10 μ m.Can be with any well-known method, for example sputter, evaporation, plating wait and form down wiring layer 21.
Then shown in Fig. 4 C, insulating resin layer 22 is formed on the passivating film 4 and following wiring layer 21 on the semiconductor chip 1.Insulating resin layer 22 can be made by for example polyimide resin, epoxy resin, silicones etc., and its thickness can be between for example 0.1 μ m and 10 μ m.Can form insulating resin layer 22 with any well-known method, for example spin coating method, printing process, laminating method etc.In insulating resin layer 22, opening 25 is limited at corresponding to the position of the end 24a of interconnect conductive layers 26 and helical coil 24 (at two openings shown in Fig. 4 C and the 4D).Can use patterning techniques etc., for example limit opening 25 by means of photoetching.
Shown in Fig. 4 D, last wiring layer 23 is formed on the insulating resin layer 22 subsequently.The two ends 23a of last wiring layer 23 and 23b pass the opening 25 that is limited in the insulating resin layer 22, and are connected respectively to the end 24a of interconnect conductive layers 26 and helical coil 24.By this way, helical coil 24 is connected to electrode 3 via last wiring layer 23 (upper pathway (over path)) and interconnect conductive layers 26.
The material of last wiring layer 23 can be a copper for example, and its thickness can be between for example 1 μ m and 20 μ m.Can be for example with any well-known technology, as electroplate and form wiring layer 23.
But the conventional semiconductor device 20 shown in Fig. 3 A-3D and Fig. 4 A-4D still has following shortcoming.
With reference to figure 5, be depicted as the equivalent electric circuit of conventional semiconductor device.In Fig. 5, C
SBe the electric capacity of helical coil, R
SBe the resistance of helical coil, and L
SIt is the inductance of helical coil.C
(OX+Resin)Be the electric capacity of passivating film and insulating resin layer, C
SiBe the electric capacity of semiconductor chip (silicon chip), and R
SBe the resistance of semiconductor chip (silicon chip).
Being shown in as Fig. 3 A-3D provides helical coil 24 that following shortcoming (1) and (2) are arranged on the wiring layer 23.
(1) because of wiring layer 21 and semiconductor chip 1 are approaching down, C
SiOwing to parasitic capacitance increases, thereby cause energy loss.
(2) because of wiring layer 21 and last wiring layer 23 (helical coil 24) are approaching down, C
SIncrease, cause energy loss.
Being shown in down as Fig. 4 A-4D provides helical coil 24 that following shortcoming (1) and (2) are arranged on the wiring layer 21.
(1) because of wiring layer 24 and semiconductor chip 1 are approaching down, R
SiOwing to eddy current loss increases, thereby cause energy loss.
(2) because of wiring layer 21 and last wiring layer 23 (helical coil 24) are approaching down, C
SIncrease, cause energy loss.
As discussed previously, in recent years, in the manufacturing of high-frequency semiconductor element,, on semiconductor chip, form sensing element (see for example Japanese unexamined patent, first announces No.2003-86690) such as spiral inductor for guaranteeing its impedance matching etc.Therefore propose a kind of technology, thick resin bed wherein is provided between semiconductor chip and sensing element, to reduce the electromagnetic energy loss.
Yet in conventional semiconductor device, may need multi-layer wiring structure.In this case, impedance mismatching occurs in the wiring that is connected to form in different layers and the knot (contact hole) of sensing element is located, and this can cause the reduction of figure of merit value (Q value).
Summary of the invention
The present invention conceives according to above-mentioned background, and its purpose provides a kind of low energy loss and high performance semiconductor device with sensing element formed thereon.
For overcoming the above problems, first aspect provides a kind of semiconductor device, comprising: semiconductor chip, and it has and is formed at its lip-deep electrode; First insulating resin layer, it is provided on this semiconductor chip and has first opening that is limited to corresponding to the position of this electrode; The first wiring layer, it is provided on first insulating resin layer and by first opening and is connected to electrode; Second insulating resin layer, it is provided on first insulating resin layer and the first wiring layer, and this second insulating resin layer has second opening, and it is defined to the position that is different from first aperture position on the surface of semiconductor chip direction; And the second wiring layer, it is provided on second insulating resin layer and by second opening and is connected to the first wiring layer, wherein this second wiring layer comprises sensing element, and the first insulating resin layer thickness and the second insulating resin layer thickness sum are not less than 5 μ m and are not more than 60 μ m.
According to a second aspect of the invention, in above-mentioned semiconductor device, can be between 0.3 and 0.5 by the value that the first wiring layer thickness is obtained divided by the second wiring layer thickness.
According to a third aspect of the invention we, described sensing element can be a helical coil.
In addition, a fourth aspect of the present invention provides a kind of method of making semiconductor device, may further comprise the steps: first insulating resin layer is provided on the semiconductor chip with the electrode that provides thereon; In first insulating resin layer, limit first opening, make electrode be exposed; Form the first wiring layer on first insulating resin layer, it is connected to electrode by first opening; On first insulating resin layer and the first wiring layer, form second insulating resin layer; The position that is different from first aperture position on the direction of surface of semiconductor chip forms second opening, and the position of this second opening is corresponding to the position of the first wiring layer; And on the two or two insulating resin layer, form the second wiring layer, the effect that it is connected to the first wiring layer and plays sensing element by second opening, wherein the first insulating resin layer thickness and the second insulating resin layer thickness sum are not less than 5 μ m and are not more than 60 μ m.
According to a fifth aspect of the invention, in the method for above-mentioned manufacturing semiconductor device, can be between 0.3 and 0.5 by the value that the first wiring layer thickness is obtained divided by the second wiring layer thickness.
According to the present invention, because first insulating resin layer and second insulating resin layer are provided between the sensing element and semiconductor chip such as helical coil, sensing element and semiconductor chip are spaced apart with enough distances by described two insulating resin layers.By this way, can reduce such as the energy loss of eddy current loss, and can obtain to have the semiconductor device of the dielectric element that shows high Q value (quality factor) and good characteristic.
In addition, the present invention conceives according to above-mentioned background, and its another purpose provides the semiconductor device with the sensing element that shows high Q value.
A sixth aspect of the present invention provides a kind of semiconductor device, comprising: semiconductor chip, and it has and is formed on its lip-deep electrode; First insulating resin layer, it is provided on the semiconductor chip, and has first opening that is limited to corresponding to the position of electrode; The first wiring layer, it is formed on first insulating resin layer and by first opening and is connected to electrode; Second insulating resin layer, it is formed on first insulating resin layer and the first wiring layer corresponding to the position of the first wiring layer, and this second insulating resin layer has second opening; And the second wiring layer, it is formed on second insulating resin layer and has sensing element, wherein the second wiring layer is connected to the first wiring layer via the knot that is provided in second opening, and the width of knot is equal to or greater than the live width of the second wiring layer that constitutes sensing element.
According to a seventh aspect of the invention, in above-mentioned semiconductor device, first contact mat and second contact mat can be provided to the first wiring layer and the second wiring layer respectively, knot can be provided between second contact mat of first contact mat of the first wiring layer and the second wiring layer, and in second contact mat of first contact mat of the first wiring layer and the second wiring layer at least one width C and poor (C-A) between the width A of knot can be 30 μ m or following.
According to an eighth aspect of the invention, in above-mentioned semiconductor device, sensing element can be a helical coil.
According to a ninth aspect of the invention, in above-mentioned semiconductor device, first contact mat and second contact mat can be one of shape, the almost circular shape of basic rectangle or the polygonal shape with five or more a plurality of limits.
According to the present invention, because knot is formed and makes its width be same as or greater than the width of the second wiring layer that constitutes sensing element, the flowing of electric current do not blocked at this knot place and loss can be reduced.Especially, can prevent the impedance mismatching in the sensing element under the high frequency situations.
Therefore, can obtain to have the semiconductor device of high Q value (quality factor) sensing element.
Description of drawings
Fig. 1 is a plane graph, and the example of conventional semiconductor device is shown;
Fig. 2 A is the partial, exploded perspective view of described conventional semiconductor device example;
Fig. 2 B is the viewgraph of cross-section of obtaining along the line B-B among Fig. 1, and the example according to semiconductor device of the present invention is shown;
Fig. 3 A-3D is a schematic cross-sectional view, and substep illustrates the method example that is used to make semiconductor device shown in Figure 1;
Fig. 4 A-4D is a schematic cross-sectional view, and substep illustrates the method example that is used to make another routine conventional semiconductor device;
Fig. 5 is a circuit diagram, and the equivalent electric circuit of conventional semiconductor device is shown;
Fig. 6 is a plane graph, and an example according to semiconductor device of the present invention is shown;
Fig. 7 A is a partial, exploded perspective view, and an example according to semiconductor device of the present invention is shown;
Fig. 7 B is the viewgraph of cross-section of being got along Fig. 6 center line A-A, and the example according to semiconductor device of the present invention is shown;
Fig. 8 A-8E is a schematic cross-sectional view, and substep illustrates the method example that is used to make semiconductor device shown in Figure 6;
Fig. 9 is a curve chart, illustrates at the example with relation between the frequency of the semiconductor device of the sensing element of all places and Q value;
Figure 10 is a curve chart, and the example of relation between the layer thickness sum (gross thickness of all resin beds) of first insulating resin layer and second insulating resin layer and the Q value is shown;
Figure 11 is a curve chart, and the example of relation between the first wiring layer thickness and the semiconductor device Q value is shown;
Figure 12 is a curve chart, and the example of the relation between the distance of the first wiring layer thickness and the first wiring layer and the second wiring interlayer is shown;
Figure 13 is the diagram that illustrates according to the replaceable example of semiconductor device of the present invention;
Figure 14 is the partial, exploded perspective view of semiconductor device shown in Figure 13;
Figure 15 is a plane graph, and the major part of semiconductor device shown in Figure 13 is shown;
Figure 16 is a perspective view, and the major part of semiconductor device shown in Figure 13 is shown;
Figure 17 is a perspective view, and the major part of semiconductor device shown in Figure 13 is shown;
Figure 18 A-18E is a schematic cross-sectional view, and substep illustrates the method example that is used to make semiconductor device shown in Figure 13;
Figure 19 is a viewgraph of cross-section, and the variation of second knot is shown;
Figure 20 is a plane graph, and the variation of contact mat is shown;
Figure 21 is a plane graph, and another variation of contact mat is shown; And
Figure 22 is the curve chart that test result is shown.
Embodiment
Based on preferred embodiment the present invention is described below with reference to accompanying drawing.
Fig. 6 and Fig. 7 A and 7B illustrate the example according to semiconductor device of the present invention.Fig. 6 is a plane graph, and Fig. 7 A is a partial, exploded perspective view, and Fig. 7 B is the viewgraph of cross-section of being got along line A-A shown in Figure 6.
In semiconductor device 110, semiconductor chip 101 has integrated circuit formed thereon (IC) 102, and the electrode 103 of integrated circuit 102 and passivating film 104 are provided on the surface of semiconductor chip 101.
First insulating resin layer 111 that provides on the passivating film 104 of semiconductor chip 101 further is provided this semiconductor device 110, the first wiring layer 112 that on first insulating resin layer 111, forms, second insulating resin layer 113 that on first insulating resin layer 111 and the first wiring layer 112, forms, and the second wiring layer 114 that on second insulating resin layer 113, forms.
In the present embodiment, the wiring layer that will have a helical coil 115 electrode 103 that is connected to integrated circuit 102 is provided at semiconductor chip 101 lip-deep two positions.
According to the present invention, semiconductor chip can be a semiconductor wafer, as silicon wafer, perhaps can be to obtain semiconductor chip by semiconductor wafer is cut into die size.At semiconductor chip is in the situation of semiconductor chip, and a plurality of semiconductor chips can be cut into die size to semiconductor wafer and obtain then by form the group of various semiconductor elements, IC or sensing element on semiconductor wafer.
Be formed at semiconductor device part on the semiconductor chip although a sensing element has been shown in Fig. 6 and Fig. 7 A and 7B, should point out that the present invention is applicable on such as the semiconductor chip of semiconductor wafer to form a plurality of sensing elements.Also should point out that various structures are provided in addition according to semiconductor device of the present invention, as be used to seal the sealant of the second wiring layer 114, to the lead-out terminal of outer member, as projection (bump) etc., although these other structures do not illustrate in the drawings.
First insulating resin layer 111 has first opening 116, and it is limited at the position corresponding to each electrode 103.First insulating resin layer 111 can be made by for example polyimide resin, epoxy resin, silicones etc., and its thickness can be between for example 1 μ m and 30 μ m.
Can use any well-known method, for example spin coating method, printing process, laminating method wait and form first insulating resin layer 111.In addition, can use patterning techniques etc., for example limit first opening 116 by means of photoetching.
Second insulating resin layer 113 has second opening 117, and it is limited at the position that is different from first opening, 116 positions on semiconductor chip 101 surface direction.Second opening 117 is limited at corresponding to the end 114a of the second wiring layer 114 and the position of 114b.
The first wiring layer 112 is redistributing layers, and it is connected between electrode 103 and the helical coil 115.The first end 112a of the first wiring layer 112 passes first insulating resin layer 111 through first opening 116, and is connected to electrode 103.In addition, the second end 112b of the first wiring layer 112 extends so that in alignment with second opening 117.
The material of the first wiring layer 112 can be a copper for example, and its thickness can be between for example 1 μ m and 20 μ m.This has guaranteed good conductivity.Can use for example coating technology, as the copper plating etc., sputter, any two or more combination of evaporation or these methods forms the first wiring layer 112.
The second wiring layer 114 comprises the helical coil 115 as dielectric element.The end 114a of the second wiring layer 114 and 114b pass second insulating resin layer 113 through second opening 117, and are connected to the corresponding second end 112b of the first wiring layer 112.
The material of the second wiring layer 114 can be a copper for example, and its thickness can be between for example 1 μ m and 20 μ m.This has guaranteed good conductivity.Can use for example coating technology, as the copper plating etc., sputter, any two or more combination of evaporation or these methods forms the second wiring layer 114.
As required, the sealant (not shown) can be provided on second insulating resin layer 113 and the second wiring layer 114, covers the second wiring layer 114 at least.
Sealant can be made by for example polyimide resin, epoxy resin, silicones etc., and its thickness can be between for example 10 μ m and 150 μ m.The opening that is used for being connected to the outer member terminal can be limited to sealant.
In the semiconductor device 110 of this external present embodiment, the layer thickness sum of the layer thickness of first insulating resin layer 111 and second insulating resin layer 113 is not less than 5 μ m and is not more than 60 μ m.Can obtain to have the semiconductor device of the dielectric element that shows high Q value and good characteristic thus, as describing subsequently.
In the semiconductor device of present embodiment, the layer thickness of the first wiring layer 112 is preferably less than the layer thickness of the second wiring layer 114.Especially, by value that the layer thickness of the first wiring layer 112 is obtained divided by the layer thickness of the second wiring layer 114 preferably between 0.3 and 0.5.
In addition, the thickness of the first wiring layer 112 is preferably less than the thickness of second insulating resin layer 113.
Next the method that explanation is used for the semiconductor device shown in shop drawings 6 and Fig. 7 A and Fig. 7 B.
Fig. 8 A-8E is a schematic cross-sectional view, and substep illustrates the method example of making above-mentioned semiconductor device.Viewgraph of cross-section among Fig. 8 A-8E is to get along line A-A shown in Figure 6.
At first shown in Fig. 8 A, provide have integrated circuit 102, the semiconductor chip 101 of electrode 103 and passivating film 104.
As previously discussed, semiconductor chip 101 is the semiconductor wafers that are formed with electrode 103 and passivating film 104 on its surface, and opening 105 is limited in the passivating film 104 position corresponding to electrode 103.
Next, shown in Fig. 8 B, first insulating resin layer 111 with first opening 116 is formed on the passivating film 104 of semiconductor chip 101.
First insulating resin layer 111 can for example form by following steps: use any well-known method, for example spin coating method, printing process, laminating method etc. form the film of being made by one or more above-mentioned resins (first insulating resin layer forms step) on the whole surface of passivating film 104; Use patterning techniques etc. then, for example first opening 116 is limited to position corresponding to electrode 103 (first opening forms step) by means of photoetching.
Then, shown in Fig. 8 C, the first wiring layer 112 is formed on (the first wiring layer forms step) on first insulating resin layer 111.The concrete grammar that is used for forming in the precalculated position the first wiring layer 112 is not done special restriction, and for example can adopt the method that discloses in PCT international application published No.WO00/077844.
Here explanation is used to form the example of the method for optimizing of the first wiring layer 112.
At first, thin Seed Layer (seed layer) (not shown) of the plating that on the whole surface of first insulating resin layer 111 or its favored area, is formed for carrying out afterwards by means of sputtering technology etc.Seed Layer is for example to comprise by means of the copper layer of sputter formation and the stacked body of chromium (Cr) layer, or comprises the stacked body of copper layer and titanium (Ti) layer.In addition, Seed Layer can be to use the combination in any of evaporation, painting method, chemical vapor deposition (CVD) etc. or above-mentioned metal level formation technology and the thin metal layer that forms or do not have electrolytic copper coating.
Then on Seed Layer, be formed for the trapping layer (not shown) electroplated.Opening is limited in the zone that will form the first wiring layer 112 in this trapping layer, and Seed Layer exposes from this opening.Can for example pass through laminated film inhibitor (film resist), spin coating liquid inhibitor (liquid resist), or form trapping layer by any other appropriate method.
Then, use trapping layer on Seed Layer, to form the first wiring layer 112 by means of electroplating to wait as mask.After the first wiring layer 112 was formed on desired zone, the unnecessary part by etch stopper and Seed Layer removed them, and the insulating resin layer 111 of winning is exposed, and (sees Fig. 8 C) except the zone that forms the first wiring layer 112.
Then shown in Fig. 8 D, second insulating resin layer 113 is formed on first insulating resin layer 111 and the first wiring layer 112.
Second insulating resin layer 113 can for example form by following steps: use any well-known method, for example spin coating method, printing process, laminating method etc. form the film of being made by one or more above-mentioned resins (second insulating resin layer forms step) on the whole surface of first insulating resin layer 111 and the first wiring layer 112; Use patterning techniques etc. then, for example second opening 117 is limited to position corresponding to the second end 112b of the first wiring layer 112 (second opening forms step) by means of photoetching.
Next shown in Fig. 8 E, on second insulating resin layer 113, form the second wiring layer 114 (the second wiring layer forms step) with helical coil 115.Be used for providing the concrete grammar of the second wiring layer 114 to be similar to the method that is used to provide the first wiring layer 112, and therefore will omit detailed description in presumptive area.
In sealant was provided at situation on the second wiring layer 114, sealant can be for example by using photoetching come the photosensitive resin of patterning such as photosensitive polyimide resin to form so that opening is limited to the precalculated position.Should point out that the concrete grammar that is used to form sealant is not limited to this method, and can use various technology.
After forming sealant, can be by being cut into the semiconductor chip that pre-sizing obtains wherein to be packaged with sensing element etc. with having semiconductor wafer such as the various structures of sensing element on it.
The operation and the effect of the semiconductor device of present embodiment will be described down.
Because first resin bed and second resin bed are inserted between semiconductor chip and the dielectric element, dielectric element and semiconductor chip are by spaced apart with enough distances.As a result, the resistance of semiconductor chip reduces (R shown in Figure 5
Si), reduce eddy current loss thus.In addition, be the interconnecting cable that is connected between electrode and the dielectric element near the first wiring layer the semiconductor chip, and dielectric element is provided in the second wiring layer away from semiconductor chip.Like this, because dielectric element and semiconductor chip be by spaced apart with enough distances, the eddy current loss that the magnetic flux that can reduce to produce owing to dielectric element causes.
In addition, first insulating resin layer and second insulating resin layer are inserted between semiconductor chip and the dielectric element, and the thickness sum of these insulating resin layers is set to be not less than 5 μ m and is not more than 60 μ m.Can obtain preferred semiconductor device thus, it has various advantages, as the bigger increase of Q value, and less size, and the manufacturing cost that reduces.If the thickness sum of two insulating resin layers is less than 5 μ m, then the improvement of Q value is less, and this is undesirable.In addition, the thickness sum of two insulating resin layers greater than 60 μ m in manufacturing cost or be disadvantageous aspect creating conditions, because the further increase (see figure 10) of expectability Q value not.In order to use this device as dielectric element, the Q value be preferably 20 or more than.
In the semiconductor device of present embodiment, inductor is made by the first wiring layer and the second wiring layer, wherein the first wiring layer is following path, and it is connected between the electrode and dielectric element (coil) on the semiconductor chip, and the second wiring layer has dielectric element (coil).
In this structure, the resistance of the second wiring layer is at inductor resistance (R
S) in become to take as the leading factor.
In addition, when the thickness of first insulating resin layer and second insulating resin layer was identical, if the thickness of second insulating resin layer is too small, then the distance between the first wiring layer and the second wiring layer reduced.As a result, because the inductor electric capacity (C that increases
S), it is remarkable that the energy loss effect becomes.This is because second insulating resin layer (seeing Fig. 7 A and 7B) has two different parts: one is formed directly on first insulating resin layer and another is formed on the first wiring layer.If the first wiring layer is blocked up, then resin can be moving from the first wiring laminar flow during second insulating resin layer forms, and the resin thickness on the first wiring layer trends towards becoming littler than required.
If the thickness of the first wiring layer is too small, then resistance is owing to the cross-sectional area of the first wiring layer reduces, and this is undesirable.
Be not less than 0.3 and be not more than 0.5, the electric capacity (C of increase by keeping the value that the layer thickness of the first wiring layer is obtained divided by the layer thickness of the second wiring layer
S) influence reduced, and can realize having the more semiconductor device of good characteristic.
Example
Make semiconductor device, and assess its characteristic.Silicon chip is used as semiconductor chip.Form first insulating resin layer and second insulating resin layer with polyimide resin.The first wiring layer is provided between first insulating resin layer and second insulating resin layer, and the second wiring layer is provided on second insulating resin layer.Dielectric element is formed the helical coil of 3.5 circles.Use the material of copper (Cu) as the first wiring layer and the second wiring layer.
The position of sensing element
As work example of the present invention (working example), make have as interconnecting cable (following path) be positioned near the semiconductor chip the first wiring layer and as the semiconductor device away from the second wiring layer of semiconductor chip of dielectric element.As a comparative example, make have as dielectric element be positioned near the semiconductor chip the first wiring layer and as the semiconductor device away from the second wiring layer of semiconductor chip of interconnecting cable (upper pathway).For these semiconductor devices, the relation between assessment frequency and the Q value.
Except the position as above-mentioned sensing element, the semiconductor element of this work example and the semiconductor element of comparative example are made under the same terms of work example, as identical insulating resin layer thickness.
In Fig. 9, solid line illustrates the Q value of the semiconductor element of work example, and wherein dielectric element is provided in the second wiring layer.In addition, be shown in dotted line the Q value of the semiconductor element of comparative example, wherein dielectric element is provided in the first wiring layer.
The result of Fig. 9 shows when two wiring layers are provided and can be set to the inductor of realizing having high Q value away from semiconductor chip by dielectric element.
The thickness of insulating resin layer
As shown in table 1, when changing the layer thickness sum of first insulating resin layer and second insulating resin layer, make a plurality of semiconductor devices, and measure the Q value of these semiconductor devices at 2GHz frequency place.
In these semiconductor devices, near the first wiring layer that is positioned at the semiconductor chip is interconnecting cable (following path), and is dielectric element away from the second wiring layer of semiconductor chip.
The layer thickness sum (gross thickness of all resin beds) of first insulating resin layer and second insulating resin layer and the relation between the Q value have been shown in Figure 10 and table 1.These results show, have obtained 20 or above Q value when the layer thickness sum of first insulating resin layer and second insulating resin layer is not less than 5 μ m and is not more than 60 μ m.In this case, the effect that improves the Q value is favourable, but will prevent that the gross thickness of insulating resin layer from unnecessarily increasing.
Table 1
| The thickness sum of first and second insulating resin layers (μ m) | Q value (at 2GHz) |
| 1 | 12.2 |
| 2 | 14.2 |
| 5 | 22.4 |
| 10 | 26.5 |
| 20 | 34.0 |
| 30 | 29.8 |
| 40 | 37.1 |
| 50 | 36.0 |
| 60 | 36.3 |
| 80 | 37.1 |
| 100 | 36.1 |
The thickness of conductive layer
Make a plurality of semiconductor devices at the thickness that the fixed thickness of the second wiring layer is changed the first wiring layer during to 10 μ m.
In these semiconductor devices, near the first wiring layer that is positioned at the semiconductor chip is interconnecting cable (following path), and is dielectric element away from the second wiring layer of semiconductor chip.
Figure 11 is illustrated in the Q value of the semiconductor device of measuring at 2GHz frequency place, and wherein the thickness of the first wiring layer is 1 μ m, 3 μ m, and 5 μ m, or 9 μ m, and the thickness of the second wiring layer is 10 μ m.In this was measured, the thickness of first insulating resin layer was 10 μ m, and the thickness of second insulating resin layer is 10 μ m.
The result of Figure 11 shows, the value that obtains divided by the thickness of the second wiring layer when the thickness with the first wiring layer is between 0.3 and 0.5 the time, the semiconductor device that can realize having higher Q value.
Figure 12 illustrate the first wiring layer of semiconductor device and the range finding between the second wiring layer from, wherein the thickness of second insulating resin layer (the just in time thickness on first insulating resin layer) is 10 μ m and the thickness of the first wiring layer is 3 μ m, 5 μ m, or 10 μ m.According to measurement shown in Figure 12, the thickness of first insulating resin layer is 10 μ m, and the thickness of the second wiring layer is 10 μ m.
As indicated in the curve chart of Figure 12, when the ratio of the thickness of the first wiring layer and the thickness of second insulating resin layer reduced, the distance between the first wiring layer and the second wiring layer increased.This shows when the ratio of the thickness of the first wiring layer and the thickness of second insulating resin layer reduces, the defect semiconductor device that has obtained to have high Q value.
Below with reference to accompanying drawing alternative embodiment of the present invention is described.
Figure 13-17 illustrates the alternative embodiment according to semiconductor device of the present invention.Figure 13 is a viewgraph of cross-section, and Figure 14 is a partial, exploded perspective view, and Figure 15 is the plane graph of major part, and Figure 16 and Figure 17 are the perspective views of major part.Figure 13 is the viewgraph of cross-section of being got along line D-D shown in Figure 15.
As shown in figure 13, this semiconductor device comprises semiconductor chip 201, be provided at first insulating resin layer 210 on the semiconductor chip 201, be provided at the first wiring layer 211 and 212 on first insulating resin layer 210, be provided at second insulating resin layer 213 on first insulating resin layer 210 and the first wiring layer 211 and 212, and be provided at the second wiring layer 214 on second insulating resin layer 213.
In passivating film 204, opening 205 is limited at the position corresponding to electrode 203, and electrode 203 exposes from opening 205.
Can for example use any well-known method, form passivating film 204, and its film thickness is between for example 0.1 μ m and 0.5 μ m as the LPCVD technology.
According to the present invention, semiconductor chip can be the semiconductor wafer such as silicon wafer, perhaps can be semiconductor chip.Semiconductor chip can be cut into die size with semiconductor wafer and obtain then by form the group of various semiconductor elements, IC or sensing element on semiconductor wafer.
First insulating resin layer 210 has first opening 216, and it is defined as opening corresponding to the position of each electrode 203.
First insulating resin layer 210 can be made by for example polyimide resin, epoxy resin, silicones etc., and its thickness can be between for example 1 μ m and 30 μ m.
Second insulating resin layer 213 has opening 217, and it is limited at the position corresponding to two ends of the second wiring layer 214.
Second insulating resin layer 213 can be made by for example polyimide resin, epoxy resin, silicones etc.
Since the thickness by second insulating resin layer 213 be set to 10 μ m or more than, the first wiring layer 211 and the 212 and second wiring layer 214 are by spaced apart with enough distances, so might reduce energy loss and increase the Q value.The thickness of second insulating resin layer 213 is preferably between 10 μ m and 20 μ m.
Can use any well-known method, for example spin coating method, printing process, laminating method wait and form insulating resin layer 210 and 213. Opening 216 and 217 can use patterning techniques etc., for example limits by means of photoetching.
The first wiring layer 211 and 212 (first conductive layer) is the redistributing layer that is connected between the electrode 203 and the second wiring layer 214.The first wiring layer 211 and 212 the first end 211a and 212a are connected to electrode 203 via being formed on the knot of first in first opening 216 218.
Shown in Figure 13,16 and 17, contact mat 211b and 212b with plate shape of basic rectangle are provided on the first wiring layer 211 and 212.
The first wiring layer 211 and 212 material can be for example aluminium or copper, and its thickness can be between for example 1 μ m and 20 μ m.Can use any well-known method, for example sputter, evaporation, plating wait and form the first wiring layer 211 and 212.
Shown in Figure 13-15, the second wiring layer 214 (second conductive layer) comprises the helical coil 215 as sensing element.
The material of the second wiring layer 214 can be a copper for example, and its thickness can be between for example 1 μ m and 20 μ m.Can use for example coating technology, as the copper plating etc., sputter, evaporation waits and forms the second wiring layer 214.
The contact mat 214a of the plate shape of basic rectangle and the two ends that 214b is provided to the second wiring layer 214.
Aspect ratio (aspect ratio), promptly the ratio (width/height) of the minimum widith of second opening 217 and length (thickness of second insulating resin layer 213) is too little, not exclusively be filled in second opening 217 at 219 o'clock metal materials of qualification second knot, cause the deformity of second knot 219.Owing to above reason, aspect ratio is preferably 1 or bigger.
Second knot, 219 walls along second opening 217 limit.
In the example shown in the figure, second knot 219 is the prism shapes with rectangular cross section, and its four parallel sided are in each limit of contact mat 214a, 214b, 211b or 212b.
Second knot, 219 width (the width A shown in Figure 13,16 and 17) is configured to be same as or greater than the live width (width B of the helical coil 215 shown in Figure 13,16 and 17) of the second wiring layer 214 that constitutes helical coil 215.
By the width of second knot 219 is arranged to drop within the above-mentioned scope, can prevents the impedance mismatching in the helical coil 215 and can realize high Q value.
Poor (A-B) between the live width of the second wiring layer 214 of the width of second knot 219 and formation helical coil 215 preferably is set to 10 μ m or following.
Poor (C-A) between the width (the width A shown in Figure 13,16 and 17) of the width of contact mat 214a, 214b, 211b and 212b (width C shown in Figure 13,16 and 17) and second knot 219 is preferably 30 μ m or following.Be set to drop within the above-mentioned scope by the difference between the described width, can realize high Q value.
Difference between the described width be preferably 10 μ m or more than, even so that can prevent to connect fault when forming when second knot 219 misalignments.
The ratio (C/A) of the width C of contact mat 214a, 214b, 211b and 212b and second knot, 219 width A be preferably 2 or below.By ratio (C/A) is set to drop within this scope, can realize high Q value.
Described ratio (C/A) be preferably 1.33 or more than, even because can prevent to connect fault when forming in second knot 219 misalignments.
Difference between the cross-sectional area of the area of contact mat 214a, 214b, 211b or 212b and second knot 219 is preferably 2700 μ m
2Or below.Difference by area is set to drop in the above scope, can realize high Q value.
Above-mentioned area difference is preferably 700 μ m
2Or more than, even so that can prevent to connect fault when forming when second knot 219 misalignments.
The ratio of the area of contact mat 214a, 214b, 211b or 212b and second knot, 219 cross-sectional area be preferably 4 or below.Be set to drop in the above-mentioned scope by area difference, can realize high Q value.
Above-mentioned area than preferably 1.78 or more than, even so that tie 219 misalignments and can prevent to connect fault when forming when second.
The stand out of contact mat 214a, 214b, 211b or 212b and second knot 219, the width ratio, area difference and area are than preferably all contact mat 214a, 214b, 211b and 212b being satisfied.Yet, even when any one that is connected to second knot, 219 contact mat meets above-mentioned condition, also can realize above-mentioned advantageous effects.
Should point out that the width that constitutes the second wiring layer 214 of helical coil 215 as used herein refers to the mean breadth of helical coil 215.
In addition, the width of contact mat 214a, 214b, 211b and 212b and second knot 219 refers to Breadth Maximum as used herein.
As required, the sealant (not shown) can be provided on second insulating resin layer 213 and the second wiring layer 214, covers the second wiring layer 214 at least.
Sealant can be made by for example polyimide resin, epoxy resin, silicones etc., and its thickness can be for example between 5 μ m and 20 μ m.The opening (not shown) that is used for being connected to the outer member terminal can be limited at sealant.
Next use description to make the method for above-mentioned semiconductor device.
Figure 18 A-18E is a schematic cross-sectional view, and the example of the method that is used to make above-mentioned semiconductor device is shown.Figure 18 A-18E is the viewgraph of cross-section of being got along line D-D shown in Figure 15.
Next shown in Figure 18 A and 18B, first insulating resin layer 210 with first opening 216 is formed on the passivating film 204 of semiconductor chip 201.
First insulating resin layer 210 can for example use following method to form.
Second insulating resin layer 210 can be for example by with the formation of getting off: use any well-known method, for example spin coating method, printing process, laminating method etc. form the film of being made by one or more above-mentioned resins (first insulating resin layer forms step) on the whole surface of passivating film 204.
Then can use patterning techniques etc., for example limit first opening 216 (first opening forms step) in position corresponding to electrode 203 by means of photoetching.
Shown in Figure 18 C, the first wiring layer 211 and 212 is formed on (the first wiring layer forms step) on first insulating resin layer 210.
The first wiring layer 211 and 212 can for example use following method to form.
Use sputtering technology etc. forms Seed Layer on first insulating resin layer 210.Seed Layer is the stacked body that for example comprises copper layer and chromium (Cr) layer, or comprises the stacked body of copper layer and titanium (Ti) layer.
Next the trapping layer (not shown) that is used to electroplate is formed on Seed Layer.Trapping layer is formed on the zone except the zone that will be provided the first wiring layer 211 and 212.
Use to electroplate and wait the first wiring layer 211 and 212 that will for example be made of copper to be formed on the Seed Layer, and first knot 218 is formed in first opening 216.After forming the first wiring layer 211 and 212 and first knot 218, the unnecessary part by etch stopper and Seed Layer removes them.
Shown in Figure 18 D, second insulating resin layer 213 is formed on first insulating resin layer 210 and the first wiring layer 211 and 212.
Second insulating resin layer 213 can for example use following method to form.
Use any well-known method, for example spin coating method, printing process, laminating method etc. form the film of being made by one or more above-mentioned resins (second insulating resin layer forms step) on the whole surface of first insulating resin layer 210 and the first wiring layer 211 and 212.
Then use patterning techniques etc., for example limiting second opening 217 (second opening forms step) corresponding to the contact mat 211b of the first wiring layer 211 and 212 and the position of 212b by means of photoetching.
Shown in Figure 18 E, the second wiring layer 214 with helical coil 215 is formed on (the second wiring layer forms step) on second insulating resin layer 213.
Can use the method identical to form the second wiring layer 214 with the method that forms the first wiring layer 211 and 212.
In other words, Seed Layer and trapping layer are formed on second insulating resin layer 213.Use to electroplate wait then on Seed Layer, to form the second wiring layer of making by copper etc. 214, and in second opening 217, form second knot 219.
In sealant is provided at situation on the second wiring layer 214, can be for example by using photoetching come the photosensitive resin of patterning such as photosensitive polyimide resin to form sealant in the precalculated position, to form sealant.
The operation and the effect of the semiconductor device of present embodiment will be described below.
(1) is set to be same as by second knot, 219 width A or greater than the live width B of the second wiring layer 214 (helical coil 215), flowing of electric current do not blocked by second knot 219.Therefore loss can remain on low-level.Especially, can prevent the impedance mismatching in the helical coil 215 when high-frequency.
Therefore can obtain to have the semiconductor device of the helical coil 215 that shows high Q value (quality factor).
(2) send out by poor (C-A) with the width of the width of contact mat 214a, 214b, 211b and 212b and second knot 219 and be changed to 30 μ m or following, can further improve the Q value of helical coil 215.
By described stand out (C-A) being set to reason that above-mentioned scope obtains high Q value is considered to can reduce CURRENT DISTRIBUTION when electric current flows in contact mat variation.
(3) because contact mat 214a, 214b, 211b or 212b are shaped as the shape of basic rectangle, so, be connected also seldom generation of fault between second knot 219 and contact mat 214a, 214b, 211b and the 212b even when forming when second knot 219 misalignments.
Although in semiconductor device shown in Figure 13, second knot 219 has substantially invariable width on depth direction, the invention is not restricted to such embodiment.
Semiconductor device shown in Figure 19 is different from semiconductor device part shown in Figure 13 and is, the width of second knot 229 increases along with the distance with the surface and reduces gradually.
In having second knot, 229 semiconductor device, wait when forming second knot 229 when using to electroplate, metal material is evenly distributed not to be filled in second opening 227 with having the space.
Therefore can prevent the deformity of second knot 229.
Figure 20 and 21 illustrates other embodiment of contact mat.
Contact mat 234b shown in Figure 21 is polygonal in plane graph, and it is different from contact mat 214a, 214b, 211b and 212b.
Contact mat 234b preferably has polygonal shape, has five (pentagons) or more sides.In example shown in Figure 21, this spacer has octagon-shaped.
In the semiconductor device with contact mat 224b and 234b, the Q value of helical coil 215 can be able to further raising.Especially, having basically, the semiconductor device of the contact mat 224b of circle shows high Q value.
Realize that the reason of high Q value is considered to can reduce the variation of CURRENT DISTRIBUTION in contact mat when electric current flows.
Example
Test case 2-1 is to 2-5
Make semiconductor device as shown in figure 13, it comprises the semiconductor chip 201 as silicon chip, first insulating resin layer of making by polyimide resin 210, the first wiring layer 211 and 212 that is made of copper, second insulating resin layer of making by polyimide resin 213, and the second wiring layer 214 that is made of copper.
The thickness of first insulating resin layer and second insulating resin layer 210 and 213 is 10 μ m.
The first wiring layer 211 and 212 width are 30 μ m.
Second knot, 219 cross section and its width that form square shape are set to the value shown in the table 2.
Measure the Q value of helical coil 215 at 2GHz frequency place.The results are shown in the table 2.
Table 2
| The second knot width (μ m) | Helical coil width (μ m) | Q value (at 2GHz) | |
| Test case 2-1 | 20 | 30 | 25.5 |
| Test case 2-2 | 25 | 30 | 25.8 |
| Test case 2-3 | 30 | 30 | 27.0 |
| Test case 2-4 | 35 | 30 | 27.4 |
| Test case 2-5 | 40 | 30 | 28.0 |
The result of table 2 shows, the width by second knot 219 is set to be equal to or greater than the width of helical coil 215 and has realized high Q value.
Test case 2-6 is to 2-10
Make the semiconductor device shown in Figure 13.
The Q value of helical coil 215 is measured at frequency place between 0.1GHz and 20GHz.The result is shown in Figure 22.
Result among Figure 22 shows, compares between 70 μ m and 80 μ m the time with width, when the width of contact mat 214a, 214b, 211b and 212b is between 40 μ m and 60 μ m, realized higher Q value.
Because the width of contact mat is 30 μ m, so be 30 μ m or realized favourable result when following when the width of contact mat and the difference between second width of tying.
The present invention is applicable to the various semiconductor devices with sensing element, and as for example being used for the semiconductor device of non-contact type IC tag, wherein sensing element plays the effect of aerial coil.
Although below described and shown the preferred embodiments of the present invention, should be appreciated that these be example of the present invention and should not be considered to the restriction.Can in the spirit or scope of the present invention, add, abridge, replace and other modifications.Therefore the present invention should not be considered to be limited by above description, but is only limited by appended claim.
Claims (7)
1. semiconductor device comprises:
Semiconductor chip, it has the electrode that forms in its surface;
First insulating resin layer, it is provided on the described semiconductor chip, and has first opening that is limited to corresponding to the position of described electrode;
The first wiring layer, it is provided on described first insulating resin layer, and is connected to described electrode by described first opening;
Second insulating resin layer, it is provided on described first insulating resin layer and the described first wiring layer, and this second insulating resin layer has second opening, and it is limited at the position that is different from described first aperture position on the described surface of semiconductor chip direction; And
The second wiring layer, it is provided on described second insulating resin layer, and is connected to the described first wiring layer by described second opening,
Wherein this second wiring layer comprises sensing element, and the thickness sum of the thickness of described first insulating resin layer and described second insulating resin layer is not less than 5 μ m and is not more than 60 μ m,
Wherein by value that the thickness of the described first wiring layer is obtained divided by the thickness of the described second wiring layer between 0.3 and 0.5.
2. according to the semiconductor device of claim 1, wherein said sensing element is a helical coil.
3. method that is used to make semiconductor device may further comprise the steps:
First insulating resin layer is provided on the semiconductor chip with the electrode that provides thereon;
In described first insulating resin layer, limit first opening, make described electrode be exposed;
Form the first wiring layer on described first insulating resin layer, it is connected to described electrode by described first opening;
On described first insulating resin layer and the described first wiring layer, form second insulating resin layer;
The position that is different from described first aperture position on the surface of semiconductor chip direction forms second opening, and the position of this second opening is corresponding to the position of the described first wiring layer; And
Form the second wiring layer on described second insulating resin layer, it is connected to the described first wiring layer by described second opening, and plays the effect of sensing element,
The thickness sum of the thickness of wherein said first insulating resin layer and described second insulating resin layer is not less than 5 μ m and is not more than 60 μ m,
Wherein by the thickness of the described first wiring layer is set between 0.3 and 0.5 divided by the value that the thickness of the described second wiring layer obtains.
4. semiconductor device comprises:
Semiconductor chip, it has the electrode that forms in its surface;
First insulating resin layer, it is provided on the described semiconductor chip, and has first opening that is limited to corresponding to the position of described electrode;
The first wiring layer, it is formed on described first insulating resin layer, and is connected to described electrode by described first opening;
Second insulating resin layer, it is formed on described first insulating resin layer and the described first wiring layer corresponding to the position of the described first wiring layer, and this second insulating resin layer has second opening; And
The second wiring layer, it is formed on described second insulating resin layer, and has sensing element,
The wherein said second wiring layer is connected to the described first wiring layer via the knot that is provided in described second opening, and
The width of described knot is equal to or greater than the live width of the described second wiring layer that constitutes described sensing element.
5. according to the semiconductor device of claim 4, wherein first contact mat and second contact mat are provided to described first wiring layer and the described second wiring layer respectively,
Described knot is provided between second contact mat of first contact mat of the described first wiring layer and the described second wiring layer, and
Poor (C-A) between the width C of at least one in second contact mat of first contact mat of the described first wiring layer and the described second wiring layer and the width A of described knot is 30 μ m or following.
6. according to the semiconductor device of claim 4, wherein said sensing element is a helical coil.
7. according to the semiconductor device of claim 5, shape, the almost circular shape that wherein said first contact mat and described second contact mat are basic rectangles and have one of the polygonal shape on five or more a plurality of limits.
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| JP2004221785A JP2006041357A (en) | 2004-07-29 | 2004-07-29 | Semiconductor device and its manufacturing method |
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| JP2007243676A (en) * | 2006-03-09 | 2007-09-20 | Fujikura Ltd | Semiconductor device and manufacturing method therefor |
| JP5044353B2 (en) * | 2007-10-10 | 2012-10-10 | 株式会社テラミクロス | Manufacturing method of semiconductor device |
| JP2010232230A (en) * | 2009-03-25 | 2010-10-14 | Casio Computer Co Ltd | Semiconductor device and manufacturing method thereof |
| JP5370216B2 (en) * | 2010-03-04 | 2013-12-18 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| JP5083360B2 (en) * | 2010-04-02 | 2012-11-28 | セイコーエプソン株式会社 | Electronic substrate, semiconductor device and electronic equipment |
| JP2012190854A (en) | 2011-03-08 | 2012-10-04 | Toshiba Corp | Semiconductor device and formation method for wire thereof |
| DE112012003318T5 (en) * | 2011-08-11 | 2014-04-30 | Flipchip International, Llc | Thin-film structure for high-density inductors and rewiring in wafer-level packaging |
| JP5831498B2 (en) * | 2013-05-22 | 2015-12-09 | Tdk株式会社 | Coil component and manufacturing method thereof |
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| JP3755453B2 (en) * | 2001-11-26 | 2006-03-15 | 株式会社村田製作所 | Inductor component and method for adjusting inductance value thereof |
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| US6133079A (en) * | 1999-07-22 | 2000-10-17 | Chartered Semiconductor Manufacturing Ltd. | Method for reducing substrate capacitive coupling of a thin film inductor by reverse P/N junctions |
| CN1338779A (en) * | 2000-08-11 | 2002-03-06 | Iep技术株式会社 | Semiconductor device |
| CN1377217A (en) * | 2001-03-23 | 2002-10-30 | 株式会社藤仓 | Multi-layer circuit board assembly, unit thereof and manufacture thereof |
| CN1396797A (en) * | 2001-07-10 | 2003-02-12 | 株式会社藤仓 | Multilayer terminal plate assembly, multilayer terminal plate assembly unit and its manufacturing method |
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| CN101271895A (en) | 2008-09-24 |
| CN1728384A (en) | 2006-02-01 |
| JP2006041357A (en) | 2006-02-09 |
| CN101271895B (en) | 2010-06-02 |
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