WO2022213873A1 - 存储装置和处理数据的方法 - Google Patents

存储装置和处理数据的方法 Download PDF

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Publication number
WO2022213873A1
WO2022213873A1 PCT/CN2022/084338 CN2022084338W WO2022213873A1 WO 2022213873 A1 WO2022213873 A1 WO 2022213873A1 CN 2022084338 W CN2022084338 W CN 2022084338W WO 2022213873 A1 WO2022213873 A1 WO 2022213873A1
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Prior art keywords
information
data
processing
storage
storage medium
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PCT/CN2022/084338
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English (en)
French (fr)
Inventor
朱晓明
陈一峰
廖宇
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华为技术有限公司
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Application filed by 华为技术有限公司 filed Critical 华为技术有限公司
Priority to EP22783940.4A priority Critical patent/EP4293672A4/en
Publication of WO2022213873A1 publication Critical patent/WO2022213873A1/zh
Priority to US18/480,355 priority patent/US20240028263A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/0284—Multiple user address space allocation, e.g. using different base addresses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0604—Improving or facilitating administration, e.g. storage management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/061—Improving I/O performance
    • G06F3/0613—Improving I/O performance in relation to throughput
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0658—Controller construction arrangements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
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    • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
    • G06F3/0671—In-line storage system
    • G06F3/0683—Plurality of storage devices
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    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
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    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7208—Multiple device management, e.g. distributing data over multiple flash devices

Definitions

  • the present application relates to the field of computer technology, and in particular, to a storage device and a method for processing data.
  • a computer device includes various elements, and a storage medium is one of the various elements.
  • data is stored in the form of multiple storage units, and the storage unit is the smallest operation unit for data processing.
  • an instruction is sent to a storage medium through a controller in a computer device, and each instruction is directed to a storage unit in the storage medium. Therefore, when data processing needs to be performed based on multiple storage units, the controller needs to send multiple processing instructions to the storage medium.
  • This method requires the controller to consume more processing resources, resulting in waste of resources and low data processing efficiency.
  • Embodiments of the present application provide a storage device and a method for processing data to solve the problems provided by related technologies, and the technical solutions are as follows:
  • a storage device in a first aspect, includes a controller and a storage medium, the storage medium includes an instruction decoder and a plurality of storage units, and the controller is connected to the instruction decoder of the storage medium.
  • the controller is used to send a first processing instruction to the instruction decoder of the storage medium.
  • the first processing instruction includes first information and second information, the first information is used to indicate the processing mode, and the second information is used to indicate the need The data length of the processed data.
  • the instruction decoder of the storage medium is configured to receive the first processing instruction sent by the controller. Based on the data length indicated by the second information in the first processing instruction, at least two target storage units are determined from the plurality of storage units of the storage medium. After that, based on the at least two target storage units, data processing is performed according to the processing mode indicated by the first information in the first processing instruction.
  • the controller only needs to send one processing instruction, so that the instruction decoder of the storage medium can perform continuous data processing based on at least two storage units.
  • the storage device provided in this embodiment can reduce the number of processing instructions that the controller needs to send. Therefore, not only the processing resources that the controller needs to consume during the data processing process are reduced, the waste of resources is avoided, but also the efficiency of data processing is improved.
  • multiple storage units of the storage medium are located in at least one storage row, and an instruction decoder of the storage medium is used to determine the starting address of the data to be processed, based on the second information, the multiple storage
  • the length of the unit, the length of at least one storage row, and the start address of the data to be processed determine at least two target storage units from a plurality of storage units in the storage medium.
  • An exemplary implementation of determining at least two target storage units is provided, thereby enabling an instruction decoder of a storage medium to perform data processing based on the determined at least two target storage units.
  • the first processing instruction further includes third information, where the third information is used to indicate an address, and an instruction decoder of the storage medium is used to determine the address indicated by the third information as the address of the data to be processed.
  • the starting address, the addresses of at least two target storage units are consecutive.
  • the instruction decoder of the storage medium directly uses the address indicated by the third information as the starting address of the data to be processed. Therefore, in the subsequent process, the storage unit where the starting address of the data to be processed is located can be used as the first target storage unit, and the continuous storage units including the first target storage unit can be determined as at least two target storage units. unit.
  • the instruction decoder of the storage medium is configured to determine the starting address of the data to be processed based on multiple storage units of the storage medium, and the addresses of at least two target storage units are continuous or discontinuous.
  • the instruction decoder of the storage medium is also used to encapsulate the instruction identifier of the first processing instruction and the addresses of at least two target storage units, obtain a response message, and send the response message to the controller; the controller is also used to receive the response information.
  • the instruction decoder of the storage medium randomly determines the starting address of the data to be processed among the multiple storage units, and randomly determines at least two target storage units, then the at least two target storage units may be continuous or may Discontinuous. Since the at least two target storage units are randomly determined, the instruction decoder also needs to return the addresses of the at least two target storage units to the controller, so that the controller can determine which target storage units the instruction decoder is based on. data processing.
  • the processing manner indicated by the first information includes a first processing manner
  • the first processing manner includes a processing manner of storing data in a storage unit
  • the controller is further configured to send data.
  • the instruction decoder of the storage medium is configured to store the data sent by the controller in at least two target storage units according to the first processing manner.
  • the first processing manner is, for example, writing and overwriting.
  • the data processing process performed by the instruction decoder refers to the data storage process.
  • the processing manner indicated by the first information includes a second processing manner
  • the second processing manner includes a manner of performing data processing based on a storage unit that has stored data
  • an instruction decoder of the storage medium is used to In the second processing manner, the data stored in the at least two target storage units is processed.
  • the second processing method is, for example, reading and erasing.
  • the data processing process performed by the instruction decoder refers to the processing process of the stored data.
  • the instruction decoder of the storage medium is further configured to send the data stored in the at least two target storage units to the controller according to the address sequence of the at least two target storage units.
  • the controller is further configured to receive the data stored in the at least two target storage units sent by the instruction decoder of the storage medium. For example, when the processing mode is read, the instruction decoder of the storage medium needs to return the read data to the controller. Among them, the instruction decoder completes the transmission of data through multiple transmission processes, and the length of the data sent in each transmission process depends on the bit width of the transmission interface.
  • the first processing instruction further includes fourth information, where the fourth information is used to indicate a data grouping requirement, and the data grouping requirement includes grouping at least two target storage units in units of storage behaviors, or
  • the storage column groups the at least two target storage units in units
  • the instruction decoder of the storage medium is configured to group the at least two target storage units according to the data grouping requirements indicated by the fourth information to obtain at least one grouping, based on each grouping
  • the target storage unit in performs data processing according to the processing mode indicated by the first information.
  • the instruction decoder of the storage medium can store the row unit for data processing, that is, after completing the data processing of each target storage unit in one storage row, switch to another storage row, and correct the Other target storage units that store rows perform data processing.
  • data processing may also be performed in units of storage columns, and after data processing of each target storage unit in one storage column is completed, switching to other storage columns is performed.
  • the fourth information makes the data processing process of the instruction decoder more flexible.
  • the instruction decoder of the storage medium is configured to, for any group, execute parallel execution of the target storage unit in any group, and execute the parallel execution of any group according to the processing method indicated by the first information.
  • the enabled target storage units perform data processing so that the difference between the processing times of the parallel enabled target storage units in any group is less than a threshold value. Performing parallel enabling and data processing on target storage units within the same group reduces the time required for enabling and data processing, thereby reducing the overall time required for data processing.
  • At least two target storage units are located in the same logical unit number, and the target storage unit is the smallest unit for data processing.
  • one storage medium is one logical unit number, so at least two target storage units determined from multiple storage units of the storage medium are located in the same logical unit number.
  • the instruction decoder of the storage medium is further configured to parse the first processing instruction to obtain the first information and the second information.
  • the instruction decoder obtains the first information and the second information by parsing the first processing instruction.
  • the sum of the lengths of the at least two target storage units is not less than the data length indicated by the second information. Since the target storage unit is the smallest unit for data processing, the sum of the lengths of at least two target storage units may be equal to the data length indicated by the second information, or may be greater than the data length indicated by the second information. For example, when the data length cannot divide the length of the storage unit, the sum of the lengths of at least two target storage units is greater than the data length indicated by the second information.
  • the number of storage media is multiple, and the controller is configured to receive the storage medium identifier, and send the first processing instruction to the instruction decoder of the storage medium indicated by the storage medium identifier.
  • the controller determines to which instruction decoder of the storage medium to send the first processing instruction based on the storage medium identifier. For example, if the storage medium is identified as a logical address sent by the processor, the controller uses the instruction decoder indicated by the physical address corresponding to the logical address as the instruction decoder for receiving the first processing instruction.
  • a method for processing data is provided, the method is applied to a storage device, the storage device includes a controller and a storage medium, the storage medium includes an instruction decoder and a plurality of storage units, and the method includes:
  • the instruction decoder of the storage medium receives the first processing instruction sent by the controller, the first processing instruction includes first information and second information, the first information is used to indicate the processing mode, and the second information is used to indicate the data of the data to be processed length;
  • the instruction decoder of the storage medium determines at least two target storage units from the plurality of storage units of the storage medium based on the data length indicated by the second information;
  • the instruction decoder of the storage medium performs data processing according to the processing mode indicated by the first information based on the at least two target storage units.
  • multiple storage units of the storage medium are located in at least one storage row, and an instruction decoder of the storage medium determines at least two storage units from the multiple storage units of the storage medium based on the data length indicated by the second information.
  • a target storage unit including: the instruction decoder of the storage medium determines the starting address of the data to be processed; the instruction decoder of the storage medium determines the starting address of the data to be processed based on the second information, the length of the plurality of storage units, the length of at least one storage row, and the need to process The starting address of the data, and at least two target storage units are determined from the plurality of storage units of the storage medium.
  • the first processing instruction further includes third information
  • the third information is used to indicate an address
  • the instruction decoder of the storage medium determines the starting address of the data to be processed, including: instruction decoding of the storage medium
  • the controller determines the address indicated by the third information as the starting address of the data to be processed, and the addresses of at least two target storage units are consecutive.
  • the instruction decoder of the storage medium determines the starting address of the data to be processed, including: determining the starting address of the data to be processed based on multiple storage units of the storage medium, and at least two target storage The addresses of the units are consecutive or non-consecutive.
  • the method further includes: the instruction decoder of the storage medium encapsulates the instruction identifier of the first processing instruction and the at least two targets The address of the storage unit, get the response message, and send the response message to the controller.
  • the processing manner indicated by the first information includes a first processing manner
  • the first processing manner includes a processing manner of storing data in a storage unit
  • the instruction decoder of the storage medium is based on at least two target storage units , performing data processing according to the processing mode indicated by the first information, including: an instruction decoder of the storage medium storing the data sent by the controller in at least two target storage units according to the manner indicated by the first information.
  • the processing manner indicated by the first information includes a second processing manner
  • the second processing manner includes a manner of performing data processing based on a storage unit that has stored data
  • the instruction decoder of the storage medium is based on at least two
  • the target storage unit performs data processing according to the processing mode indicated by the first information, including: an instruction decoder of the storage medium processing the data stored in the at least two target storage units according to the second processing mode.
  • the method further includes: the instruction decoder of the storage medium performs data processing according to the at least two target storage units.
  • the address sequence of the target storage unit sends the data stored in at least two target storage units to the controller.
  • the first processing instruction further includes fourth information, where the fourth information is used to indicate a data grouping requirement, and the data grouping requirement includes grouping at least two target storage units in units of storage behaviors, or The storage column groups at least two target storage units in units.
  • the instruction decoder of the storage medium performs data processing based on the at least two target storage units according to the processing mode indicated by the first information, including: the instruction decoder of the storage medium performs data processing on the at least two target storage units according to the data grouping requirements indicated by the fourth information. Perform grouping to get at least one grouping.
  • the instruction decoder of the storage medium performs data processing according to the processing mode indicated by the first information based on the target storage unit in each group.
  • the instruction decoder of the storage medium performs data processing based on the target storage unit in each group according to the processing method indicated by the first information, including: the instruction decoder of the storage medium for any group, and The line enables the target storage unit in any group; the instruction decoder of the storage medium performs data processing on the target storage unit enabled in parallel in any group according to the processing method indicated by the first information, so that the parallel enabled target storage unit in any group is processed.
  • the difference between the processing times of the target storage units is less than the threshold.
  • At least two target storage units are located in the same logical unit number, and the target storage unit is the smallest unit for data processing.
  • the method further includes: the instruction decoder of the storage medium parses the first The instruction is processed to obtain the first information and the second information.
  • the sum of the lengths of the at least two target storage units is not less than the data length indicated by the second information.
  • a method for processing data is provided, the method is applied to a storage device, the storage device includes a controller and a storage medium, the storage medium includes an instruction decoder and a plurality of storage units, and the method includes:
  • the controller determines the first information and the second information, the first information is used to indicate the processing mode, the second information is used to indicate the data length of the data to be processed, and the data length is used to determine at least two of the multiple storage units of the storage medium.
  • target storage units at least two target storage units are used for data processing;
  • the controller encapsulates the first information and the second information to obtain the first processing instruction
  • the controller sends the first processing instruction to the instruction decoder of the storage medium.
  • the controller determining the first information and the second information includes: receiving a second processing instruction, where the second processing instruction includes the first reference information and the second reference information, and the first reference information is used to indicate Processing mode, the second reference information is used to indicate the data length of the data to be processed.
  • the first reference information is determined as the first information, and the second information is determined based on the second reference information.
  • the controller determining the first information and the second information includes: the number of the second processing instructions includes at least two, and determining the second information based on the second reference information includes: responding to the at least two The data length indicated by the second reference information of the second processing instruction is less than the lower limit of the reference range, the controller combines the second reference information of at least two second processing instructions to obtain the second information, and the data length indicated by the second information is within the reference range .
  • the controller determines the first information and the second information, including: in response to the data length indicated by the second reference information of the second processing instruction being greater than the upper limit of the reference range, the controller divides the second reference The information obtains at least two second pieces of information, and the data length indicated by any second piece of information is within the reference range.
  • the controller determining the first information and the second information includes: in response to the data length indicated by the second reference information of the second processing instruction being within the reference range, using the second reference information as the second information information.
  • the method before the controller sends the first processing instruction to the instruction decoder of the storage medium, the method further includes: the controller obtains third information, the third information is used to indicate an address, and the third information is encapsulated in a in the first processing instruction.
  • the method further includes: receiving a response message sent by the instruction decoder of the storage medium, where the response message includes the first processing instruction The instruction identifier and the addresses of at least two target memory locations.
  • the method further includes: sending data, and the data is stored in the instruction decoder of the storage medium in at least two target storage units .
  • the method further includes: receiving at least two messages sent by the instruction decoder of the storage medium in order of addresses of the at least two target storage units data stored in the target storage unit.
  • the method before the controller sends the first processing instruction to the instruction decoder of the storage medium, the method further includes: the controller determines fourth information, where the fourth information is used to indicate a data packet requirement, and the data packet requirement includes The at least two target storage units are grouped in units of storage rows, or the at least two target storage units are grouped in units of storage columns, and the fourth information is encapsulated in the first processing instruction.
  • At least two target storage units are located in the same logical unit number, and the target storage unit is the smallest unit for data processing.
  • the sum of the lengths of the at least two target storage units is not less than the data length indicated by the second information.
  • the controller sends the first processing instruction to the instruction decoder of the storage medium, including: the controller receives the storage medium identifier, and sends the storage medium identifier to the storage medium indicated by the storage medium identifier.
  • the instruction decoder sends the first processing instruction.
  • FIG. 1 is a schematic structural diagram of a storage device according to an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of a storage device according to an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for processing data provided by an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of a storage device according to an embodiment of the present application.
  • FIG. 5 is a schematic flowchart of data processing in a related art provided by an embodiment of the present application.
  • FIG. 6 is a schematic flowchart of data processing provided by an embodiment of the present application.
  • FIG. 7 is a schematic diagram of processing data according to an embodiment of the present application.
  • FIG. 8 is a schematic diagram of processing data according to an embodiment of the present application.
  • FIG. 9 is a schematic diagram of processing data according to an embodiment of the present application.
  • the storage device includes a controller and a storage medium
  • the storage medium includes a command decoder and a plurality of storage units
  • the controller and the command decoder of the storage medium connect. Therefore, the instruction decoder of the storage medium can receive the processing instruction sent by the controller, and perform data processing based on the received processing instruction.
  • a storage medium is a logical unit number (logical unit number, LUN), and the LUN is also called a Die.
  • LUN logical unit number
  • multiple storage cells form an array, which is also called a bank.
  • the array includes M rows and N columns, where M and N are integers not less than 1.
  • a storage unit is uniquely identified by a row and a column.
  • the storage medium further includes an input/output (input/output, IO) interface, and the IO interface is connected to the controller, so that the data processing result is returned to the controller as required.
  • IO input/output
  • the number of storage media included in the storage device is multiple.
  • Each of the multiple storage media respectively includes the above-mentioned instruction decoder and multiple storage units, which will not be repeated here.
  • the controller in the storage medium the controller is connected to the instruction controllers of the plurality of storage mediums, respectively.
  • any storage medium in addition to the above-mentioned controller and a plurality of storage units, it also includes a row address decoder (row address decoder) and a column address decoder (column address decoder), The row address decoder and the column address decoder also correspond to a multiplexer (MUX) respectively.
  • the instruction decoder sends an instruction to the row address decoder, and the row address decoder controls the MUX corresponding to the row address decoder to enable one or more rows in the array according to the instruction.
  • the instruction decoder also sends an instruction to the column address decoder, and the column address decoder controls one or more columns in the MUX enable array corresponding to the column address decoder according to the instruction. Since the memory cells are uniquely identified by rows and columns, enabling of one or more memory cells in the array can be achieved after the rows and columns in the array are respectively enabled. In this embodiment, the enabled storage unit may be used for data processing.
  • any storage medium further includes a data processing unit, and the data processing unit is connected to the instruction decoder, so as to cooperate with the instruction decoder to complete the data processing process according to the control of the instruction decoder.
  • the instruction decoder firstly enables the storage units in the array by controlling the row address decoder and the column address decoder, and then controls the data processing unit to perform data processing based on the enabled storage units.
  • the data processing unit reads and erases the enabled storage unit according to the control of the instruction decoder.
  • the data processing unit is further connected to the controller, so as to receive data sent by the controller, and write the received data into the enabled storage unit according to the control of the instruction decoder.
  • an embodiment of the present application provides a method for processing data, and the method is applied to an interaction process between a controller and an instruction decoder of a storage medium.
  • the method includes the following contents.
  • the controller sends a first processing instruction to an instruction decoder of a storage medium.
  • the first processing instruction includes first information and second information, the first information is used to indicate the processing mode, and the second information is used to indicate the data length of the data to be processed.
  • the processing methods indicated by the first information include, but are not limited to, reading, writing and erasing, and overwriting. Among them, reading refers to obtaining the data stored in the storage unit and returning it to the controller, writing refers to storing data in a storage unit that does not store data, erasing refers to deleting the data stored in the storage unit, and overwriting refers to The data is stored in the storage unit where the data has been stored.
  • reading refers to obtaining the data stored in the storage unit and returning it to the controller
  • writing refers to storing data in a storage unit that does not store data
  • erasing refers to deleting the data stored in the storage unit
  • overwriting refers to The data is stored in the storage unit where the data has been stored.
  • the above manners are all examples, and are not used to limit the processing manner of the first information
  • the data length of the data to be processed indicated by the second information is determined according to actual requirements.
  • the second information can indicate the data length in various ways.
  • the second information includes a length value, and the data length is equal to the length value.
  • the second information is the number of storage units, and the data length is equal to the product of the number of storage units and the length of the storage unit.
  • the second information includes a first address and a second address located after the first address, the data length is equal to the difference between the second address and the first address.
  • the controller first determines the first information and the second information, and then encapsulates the first information and the second information to obtain the above-mentioned first processing instruction, so as to send the first processing instruction to the instruction decoder of the storage medium instruction.
  • determining the first information and the second information by the controller includes: receiving a second processing instruction, where the second processing instruction includes first reference information and second reference information, the first reference information is used to indicate a processing method, and the second The reference information is used to indicate the data length of the data to be processed.
  • the first reference information is determined as the first information, and the second information is determined based on the second reference information.
  • the second processing instruction includes an instruction sent by the processor to the controller, the processor is an element other than the storage device, and the processor and the storage device may be integrated in the same computer equipment, or may be located in different computer equipment respectively.
  • the processing methods indicated by the first reference information include but are not limited to reading, writing, erasing, overwriting, etc.
  • the first reference information is used as the first information, so that the first processing instruction and the second processing instruction Indications are handled the same way.
  • the second information is determined based on the second reference information, including the following three cases A1-A3.
  • the number of the second processing instructions includes at least two
  • determining the second information based on the second reference information includes: in response to the data length indicated by the second reference information of the at least two second processing instructions being less than the lower limit of the reference range, The controller combines the second reference information of at least two second processing instructions to obtain the second information, and the data length indicated by the second information is within the reference range.
  • the reference range is the value range of the data length, and this embodiment does not limit the lower limit and the upper limit of the reference range.
  • the data length indicated by the second information being within the reference range means that the data length indicated by the second information is not less than the lower limit of the reference range and not greater than the upper limit of the reference range.
  • the lower limit and the upper limit of the reference range are determined based on the processing efficiency when the storage medium performs data processing. For example, the processing efficiency when the storage medium processes data of different data lengths is obtained, and the lower limit and the upper limit of the reference range are determined according to the data length corresponding to the processing efficiency higher than the efficiency threshold. Therefore, when the storage medium processes the data within the reference range, the storage medium can have higher processing efficiency.
  • the processing methods indicated by the first reference information are both writing, the data length indicated by one second reference information is 64B, and the data length indicated by the other second reference information is 96B, the data lengths indicated by the two second reference information are both smaller than the lower limit 128B of the reference range. Therefore, the controller combines the data lengths indicated by the two second reference information, that is, the sum 160B of 64B and 96B is used as the second information, and the data length 160B indicated by the second information is within the reference range 128B-1MB. For the controller, it only needs to send a first processing instruction to the instruction decoder of the storage medium, the processing method indicated by the first information of the first processing instruction is writing, and the second information of the first processing instruction indicates The data length is 160B.
  • the controller does not combine the second reference information of at least two second processing instructions, then for each second processing instruction, the controller needs to send a first processing instruction to the instruction decoder of the storage medium, and also That is to say, the controller needs to send at least two first processing instructions to the instruction decoder of the storage medium.
  • the controller since the controller combines the second reference information of at least two second processing instructions, the number of first processing instructions sent by the controller to the instruction decoder of the storage medium is reduced. Therefore, the processing resources that the controller needs to consume in the data processing process are reduced, and the data processing efficiency is improved.
  • the second reference information of the at least two second processing instructions is combined under the condition that the processing methods indicated by the first reference information of the at least two second processing instructions are the same. For example, if the processing modes indicated by the first reference information of the two second processing instructions are both writing, the second reference information of the two second processing instructions is combined. However, if the processing mode indicated by the first reference information of one second processing instruction is write, and the processing mode indicated by the first reference information of another second processing instruction is read, then the two second processing instructions will not be processed. merge.
  • the controller in response to the data length indicated by the second reference information of the second processing instruction being greater than the upper limit of the reference range, divides the second reference information to obtain at least two pieces of second information, and the data length indicated by any second information is equal to within the reference range.
  • the manner of determining the upper limit of the reference range may refer to the description in Case A1, which will not be repeated here.
  • the data lengths indicated by different second information may be the same or different, as long as the data lengths indicated by each second information are all within the reference range.
  • the controller receives a second processing instruction, the processing method indicated by the first reference information of the second processing instruction is reading, and the data length indicated by the second reference information of the second processing instruction is 4MB, which is greater than the upper limit of the reference range of 1MB. Therefore, the controller divides the second reference information into multiple pieces of second information, for example, divides the second reference information into four equally, so as to obtain four pieces of second information, and the data length indicated by each second information is 1MB, located in The reference range is 128B-1MB. For the controller, four first processing instructions are subsequently sent to the finger decoder of the storage medium. The processing method indicated by the first information of each first processing instruction is read, and the data length indicated by the second information is all 1MB. .
  • the controller When the controller does not divide the second reference information of the second processing instruction, the controller only sends one first processing instruction to the instruction decoder of the storage medium.
  • the storage medium needs to process relatively long data (for example, 4MB in the above example) in one data processing process, so the storage medium takes a long time to complete one data processing.
  • information needs to be returned to the controller. Since it takes a long time for the storage medium to complete one data processing, the controller needs to wait for a long time to receive the information returned by the storage medium. For example, in a data reading scenario, after the storage medium completes the data reading according to the first processing instruction, the read data needs to be returned to the controller. For the controller, it takes a long time to receive the data read from the storage medium.
  • the controller divides the second reference information of the second processing instruction, at least two first processing instructions are obtained. According to each first processing instruction, the length of data to be processed by the storage medium in one data processing process is reduced (for example, from 4MB to 1MB in the above example), thereby shortening the time required for the storage medium to complete one data processing. In a scenario where the storage medium needs to return information to the controller, the controller only needs to wait a short period of time to receive the information returned by the storage medium.
  • the second reference information in response to the data length indicated by the second reference information of the second processing instruction being within the reference range, the second reference information is used as the second information.
  • the second reference information may be directly used as the second information.
  • the second processing instruction sent by the processor to the controller is the first processing instruction sent by the controller to the instruction decoder of the storage medium, that is, the second processing instruction is the same as the first processing instruction.
  • the controller When the controller is connected to an instruction decoder of one storage medium, the controller only needs to send the first processing instruction to the instruction decoder of the storage medium.
  • the storage medium corresponds to a chip enable (CE) pin, and the controller enables the storage medium through the CE pin to obtain the enabled storage medium, thereby sending the first processing instruction to the enabler storage medium.
  • CE chip enable
  • the controller When the controller is connected to the instruction decoders of multiple storage media, the controller also needs to determine to which instruction decoder of the storage medium to send the first processing instruction.
  • the controller receives the storage medium identifier, and sends the first processing instruction to an instruction decoder of the storage medium indicated by the storage medium identifier.
  • the storage medium identifier is carried in the second processing instruction sent by the processor to the controller, and the storage medium identifier is, for example, a logical address.
  • the controller stores the mapping relationship between the logical address and the physical address, the controller can determine the physical address corresponding to the logical address according to the mapping relationship, and stores the storage medium indicated by the physical address corresponding to the logical address in multiple storage media.
  • the medium is determined to be a target storage medium, and an instruction decoder of the target storage medium is used to receive the first processing instruction. Therefore, the controller enables the target storage medium through the CE pin of the target storage medium, and sends the first processing instruction to the enabled target storage medium.
  • the instruction decoder of the storage medium receives the first processing instruction sent by the controller.
  • the instruction decoder of the storage medium Since the instruction decoder of the storage medium is connected to the controller, after the controller sends the first processing instruction, the instruction decoder of the storage medium correspondingly receives the first processing instruction.
  • the instruction decoder of the storage medium determines at least two target storage units from the plurality of storage units of the storage medium based on the data length indicated by the second information.
  • the first processing instruction includes the first information and the second information.
  • the method further includes: an instruction decoder of the storage medium parses the first processing instruction to obtain the first information and the second information. After obtaining the first information and the second information, the instruction decoder of the storage medium can determine the data length indicated by the second information, so that at least two target storage units can be determined from the plurality of storage units of the storage medium based on the data length .
  • one storage medium is one LUN
  • at least two target storage units determined from multiple storage units of the storage medium are also located in the same LUN.
  • the target storage unit is the smallest unit for data processing.
  • data processing is performed based on an integer number of target storage units.
  • the sum of the lengths of at least two target storage units is not less than the data length.
  • the data length can divide the length of the target storage unit
  • the sum of the lengths of at least two target storage units equals the data length.
  • the sum of the lengths of at least two target storage units is greater than the length of the data.
  • the instruction decoder of the storage medium determines at least two target storage units from a plurality of storage units of the storage medium based on the data length indicated by the second information, including 3031 and 3032 as follows.
  • the instruction decoder of the storage medium determines the starting address of the data to be processed.
  • the starting address of the data to be processed affects the number of target storage units.
  • the data length and the length of the storage unit indicated by the second information are the same.
  • the starting address of the data to be processed is different, so the number of target storage units may also be different.
  • the data length indicated by the second information as 32B and the length of the storage unit as 16B as an example, referring to FIG. 4 , in response to the starting address of the data to be processed is the first address of the storage unit 0 in the 0th row, then the target storage unit is memory cell 0 and memory cell 1 in row 0, and the number of target memory cells is 2.
  • the target storage unit In response to the starting address of the data to be processed is located between the first address and the last address of the storage unit 0 in the 0th row, the target storage unit is the storage unit 0, the storage unit 1 and the storage unit 3 in the 0th row, The number of target storage units is 3. It can be seen from this that the starting address of the data to be processed needs to be determined in this embodiment, so as to facilitate the subsequent determination of the number of target storage units. Exemplarily, the manner of determining the starting address of the data to be processed includes the following two cases.
  • the first processing instruction further includes third information
  • the third information is used to indicate an address
  • the instruction decoder of the storage medium determines the address indicated by the third information as the starting address of the data to be processed.
  • the first processing instruction is obtained by encapsulating the first information and the second information by the controller.
  • the method further includes: the controller obtains third information for indicating an address, and encapsulates the third information in the first processing instruction. in a processing instruction.
  • the second processing instruction sent by the processor to the controller includes information for indicating the address, and the controller parses the second processing instruction to obtain the information for indicating the address, so as to use the information for indicating the address as the information for indicating the address. third information.
  • the instruction decoder of the storage medium determines the starting address of the data to be processed based on the plurality of storage units of the storage medium.
  • the instruction decoder of the storage medium randomly selects a storage unit from a plurality of storage units in the storage medium, and uses the first address of the randomly selected storage unit as the starting address of the data to be processed. Further, in some embodiments, the instruction decoder of the storage medium obtains, according to the processing manner indicated by the first information of the first processing instruction, the storage unit corresponding to the processing manner indicated by the first information from a plurality of storage units of the storage medium , a storage unit is randomly determined from the storage units corresponding to the processing mode indicated by the first information, so that the first address of the randomly determined storage unit is used as the starting address of the data to be processed.
  • the storage unit corresponding to the processing mode indicated by the first information refers to a storage unit that does not store data
  • the instruction decoder of the storage medium randomly determines a storage unit from the storage units that do not store data, and uses the first address of the randomly determined storage unit as the starting address of the data to be processed.
  • the instruction decoder of the storage medium determines at least two targets from the multiple storage units of the storage medium based on the second information, the length of the multiple storage units, the length of at least one storage row, and the starting address of the data to be processed storage unit.
  • this embodiment determines the first target storage unit based on the starting address of the data to be processed, and determines the target storage unit based on the data length indicated by the second information, the length of the storage unit, and the starting address of the data to be processed.
  • the total number For ease of description, the total number of target storage units is denoted as the first number, and in this embodiment, the first number of storage units including the first target storage unit are used as at least two target storage units.
  • a first number of storage units including the first target storage unit are used as at least two target storage units, including: Taking the first target storage unit as a starting point, the first consecutive storage units are used as at least two target storage units. Thereby, the addresses of at least two target memory cells are made consecutive.
  • the first target storage unit is storage unit 0 in row 0, and the total number of target storage units is 4, then the target storage units are: storage unit 0, storage unit 1, storage unit in row 0 2 and storage unit 3.
  • the above-mentioned at least two target storage units may cover at least one storage row, and in this embodiment, the storage row covered by the at least two target storage units needs to be determined in combination with the length of the storage row.
  • the length of the storage row is equal to the sum of the lengths of the storage units included in the storage row. For example, if a storage row includes 16 storage cells with a length of 16B, the length of the storage row is 256B.
  • the first storage row can be determined based on the starting address of the data to be processed
  • the total number of storage rows can be determined based on the data length indicated by the second information, the length of the storage row and the starting address of the data to be processed, Record the total number of stored rows as the second number.
  • overwritten memory lines refer to: a second number of consecutive memory lines including the first memory line.
  • the first storage The row is the 0th row, and the total number of overwritten storage rows is 3, so it can be determined that the overwritten storage rows are the 0th row, the 1st row and the 2nd row in the storage medium.
  • a reference number of storage units including the first target storage unit are used as at least two target storage units, including: in the first target storage unit After that, the storage unit is randomly determined, and the first target storage unit and the randomly determined storage unit are regarded as at least two target storage units, and the addresses of the at least two target storage units are continuous or discontinuous.
  • the case where the addresses of at least two target storage units are consecutive may refer to the above examples, and the examples will not be repeated here.
  • the addresses of at least two target storage units are discontinuous, referring to FIG.
  • the target storage unit It can be: storage unit 0, storage unit 2, storage unit 3, and storage unit 4 in row 0, wherein the addresses of storage unit 0 and storage unit 2 are discontinuous.
  • at least two target storage units also cover at least one storage row, and the covered storage row can be determined according to the randomly determined address of the target storage unit.
  • the instruction decoder of the storage medium needs to return the address of the target storage unit to the controller, so that the controller can know the storage unit.
  • the instruction decoder of the medium is based on which target storage units perform data processing. Therefore, in an exemplary embodiment, after the instruction decoder of the storage medium determines the at least two target storage units, the method further includes: the instruction decoder of the storage medium encapsulates the instruction identifier of the first processing instruction and the at least two target storage units. address, obtain a response message, send a response message to the controller, and the controller can determine the addresses of at least two target storage units by receiving the response message.
  • the instruction identifier of the first processing instruction of the response message is used by the controller to distinguish different first processing instructions.
  • the controller can determine which first processing instruction the instruction decoder of the storage medium is based on according to the instruction identifier of the first processing instruction carried in the response message. A target memory location identified by a processing instruction.
  • the first processing instruction is parsed by the instruction decoder of the storage medium to obtain the first information and the second information (and possibly the third information), and the instruction decoder of the storage medium determines based on the second information at least Two target memory cells, at least two memory cells covering at least one memory row.
  • the instruction decoder of the storage medium can send the overwritten memory row to the row address decoder, and send the target memory cells in each memory row to the column address decoder, so that the row address decoder and the column address decoder can be enabled .
  • the instruction decoder of the storage medium in this embodiment may also only perform parsing of the first processing instruction, and send the obtained second information (and possibly the third information) to the row address decoder and the column address decoder respectively. Therefore, the row address decoder automatically determines the covered storage row according to the method in the above description according to the received information, and the column address decoder determines the memory row in each storage row by itself according to the method in the above description according to the received information.
  • Target memory cells for enabling row and column address decoders For the process of enabling the row address decoder and the column address decoder, please refer to the description in 304 below.
  • the instruction decoder of the storage medium performs data processing according to the processing mode indicated by the first information based on the at least two target storage units.
  • the instruction decoder can implement data processing based on at least two target storage units, and this data processing manner is also called burst processing.
  • the first processing instruction further includes fourth information, where the fourth information is used to indicate data grouping requirements, and the data grouping requirements include grouping at least two target storage units in units of storage behaviors, or, storing The column unit groups at least two target storage units.
  • the instruction decoder of the storage medium groups the at least two target storage units according to the data grouping requirement indicated by the fourth information to obtain at least one group. Based on the target storage unit in each group, data processing is performed according to the processing mode indicated by the first information.
  • the fourth information may be obtained from the second processing instruction by the controller, and the controller encapsulates the fourth information in the first processing instruction before sending the first processing instruction to the instruction decoder of the storage medium.
  • the fourth information is represented as a numerical value, and different values of the fourth information are used to indicate different data grouping requirements. For example, if the value of the fourth information is the first value, it indicates that the data grouping requirement is to group at least two target storage units in units of storage behaviors. The value of the fourth information is the second value, indicating that the data grouping requirement is to group at least two target storage units in units of storage columns, and the first value and the second value are different values.
  • the decoder in response to the data grouping request including grouping at least two target storage units in units of storage behaviors, the decoder is instructed to perform data processing in units of storage behaviors. That is, for a memory line that includes target memory cells, the instruction decoder first performs data processing based on each target memory cell in one memory line, and then switches to another memory line, based on each target memory cell in the other memory line. The storage unit performs data processing, and so on. After traversing each storage row including the target storage unit, the data processing process ends. For example, referring to FIG.
  • the instruction decoder is first based on the Storage unit 0-storage unit 15 perform data processing, then switch to the first row, and perform data processing based on storage unit 0-storage unit 15 in the first row, thereby completing the data processing process.
  • the decoder in response to the data grouping request including grouping the at least two target memory cells in memory column units, the decoder is instructed to perform data processing in memory column units.
  • the instruction decoder For a storage rank including target storage units, the instruction decoder first performs data processing based on each target storage unit in one of the storage ranks, and then switches to another storage rank to perform data processing based on each target storage unit in the other storage rank. Processing, and so on, ends the data processing process after traversing each storage column including the target storage unit. Still taking the target storage unit including storage unit 0-storage unit 15 in row 0 and storage unit 0-storage unit 15 in row 1 as an example, the instruction decoder is first based on the storage units in row 0 and row 1.
  • the embodiment of the present application does not limit the processing order of the target storage units in each group.
  • the data grouping requirement includes grouping at least two target storage units in storage row units, and the instruction decoder performs data processing based on the storage units in row 0 and row 1 respectively, then the instruction decoder first performs data processing based on row 0 Data processing, and then data processing based on row 1, or the instruction decoder first performs data processing based on row 1, and then performs data processing based on row 0.
  • the process that the instruction decoder performs data processing based on the storage unit includes: enabling the storage unit, and performing data processing based on the enabled storage unit. Therefore, when performing data processing based on the target storage unit in each group, the instruction decoder also needs to enable the target storage unit in each group, so that in the group, data processing is performed based on the enabled target storage unit .
  • the target storage units in any group are enabled in parallel, so as to shorten the time required for data processing and improve the data processing efficiency.
  • the instruction decoder of the storage medium performs data processing based on the target storage unit in each group according to the processing mode indicated by the first information, including: the instruction decoder of the storage medium enables any grouping in parallel. target storage unit in .
  • the data processing is performed on the parallel-enabled target storage units in any group according to the processing mode indicated by the first information, so that the difference between the processing times of the parallel-enabled target storage units in any group is less than the threshold.
  • the instruction decoder In response to grouping in storage behavior units, in a parallel enabling process, the instruction decoder sends a first instruction to the row address decoder, and the row address decoder controls the MUX corresponding to the row address decoder according to the first instruction, so that The MUX corresponding to the row address decoder enables a memory row containing the target memory cell.
  • the instruction decoder sends a second instruction corresponding to the first instruction to the column address decoder, and the column address decoder controls the MUX corresponding to the column address decoder according to the second instruction, so that the MUX corresponding to the column address decoder runs in parallel.
  • One or more storage columns can correspond to the storage row, thereby enabling the target storage cells included in the storage row in parallel. Afterwards, data processing is performed on the parallel enabled target storage cells in the storage row according to the processing mode indicated by the first information.
  • the difference between the processing times of the target memory cells that are enabled in parallel is less than a threshold. In other words, it can be considered that the data processing process of the target memory cells in the same memory row is performed synchronously.
  • a target duration is set in the storage medium, and the target duration is the time required for the process of enabling and data processing of a storage unit.
  • the instruction decoder sends an instruction to the row address decoder and the column address decoder and starts timing, and after the target time period elapses, it is considered that the enabling and data processing of one memory cell has been completed.
  • the timing starts from the instruction decoder sending the command, and after a target duration elapses, each target in the storage row is considered to be The enabling and data processing of the storage unit has been completed.
  • the instruction decoder can send new instructions to the row and column address decoders to instruct parallel enable and data processing of target memory cells in other memory rows.
  • the above-mentioned target duration is marked as T, and the moment when the instruction decoder sends the instruction for the first time is marked as 0, Then there are: at time 0, the instruction decoder sends the first instruction to the row address decoder, and sends the second instruction corresponding to the first instruction to the column address decoder, and the row address decoder controls the row address decoder according to the first instruction.
  • the corresponding MUX enables the 0th row, and the column address decoder controls the MUX corresponding to the column address decoder to enable the 0th to 15th columns according to the first instruction, thereby enabling the storage units 0-15 in the 0th row.
  • Data processing can be performed after completion. At time T, the data processing process based on memory cells 0-15 in row 0 is considered complete.
  • the instruction decoder sends a new first instruction to the row address decoder and a new second instruction to the column address decoder to enable memory cells 0-15 in row 1, and after the enable is complete Data processing is performed, and at time 2T, it is considered that the data processing process based on the memory cells 0-15 in the first row has been completed, thereby ending the data processing process.
  • the command decoder sends a first command to the column address decoder, and the column address decoder controls the corresponding column address decoder according to the first command.
  • MUX enables a memory rank containing the target memory cells.
  • the instruction decoder sends a second instruction corresponding to the first instruction to the row address decoder, and the row address decoder controls the MUX corresponding to the row address decoder according to the second instruction, so that the MUX corresponding to the row address decoder is enabled.
  • One or more storage rows corresponding to the storage column thereby enabling the target storage units included in the storage column in parallel.
  • data processing is performed on the parallel-enabled target storage units in the storage row according to the processing mode indicated by the first information, so that the difference between the processing times of the parallel-enabled target storage units in the storage row is less than the threshold.
  • FIG. 5 shows a process of data processing in the related art.
  • each time the storage medium receives a processing instruction sent by the controller it enables and performs data processing on one storage unit. After completing the enabling and data processing of one storage unit, wait for receiving the next processing instruction of the controller, and perform enabling and data processing on the next storage unit according to the next processing instruction.
  • the controller needs to send 4 processing instructions.
  • the time required for the storage medium to complete the enabling of a storage unit and data processing is denoted as P, and the time required for the storage medium to wait for an instruction is denoted as Q. It can be seen from FIG. 5 that the length of 64B is processed according to the related art The total time required for the data is 4P+3Q.
  • each time the storage medium receives a concurrent processing instruction sent by the controller data processing can be performed on at least two target storage units, which reduces the number of processing instructions that the controller needs to send, and stores The medium does not need to wait to receive other processing instructions.
  • the enabling process of each target storage unit is parallel, the data processing process of each target storage unit is performed synchronously.
  • the related art can only complete data processing for one storage unit, while in this embodiment, data processing for at least two target storage units can be completed, thereby shortening the time required for data processing. As shown in FIG.
  • the time required to complete the enabling and data processing of one storage unit is still denoted as P, then according to the method provided in this embodiment, data processing with a length of 64B is performed, and the controller only needs to send a processing instruction, And the total time required to process 64B-length data is P, which reduces the time by (3P+3Q) compared to the related art.
  • the method provided by this embodiment is not limited to the case of parallel execution.
  • the target storage unit in the group can also be serially enabled according to actual requirements.
  • the difference between serial enable and parallel enable is that parallel enable is to synchronously enable each target storage unit in the same group, while serial enable is to sequentially enable each target storage unit in the same group.
  • An example is given to illustrate the process of serial enabling: in the case of grouping according to storage rows and the target storage unit includes storage units 0-2 in row 0, the process of enabling and data processing of one storage unit is required.
  • the time is marked as T, and the moment when the instruction decoder starts to send instructions is marked as 0, then at time 0, the instruction decoder instructs the row address decoder to enable the 0th row and the column address decoder to enable the 0th column, so that the Cell 0 in row 0 is enabled.
  • the instruction decoder instructs the row address decoder to enable the 0th row, and instructs the column address decoder to enable the 1st column, so that the memory cell 1 in the 0th row is enabled.
  • the instruction decoder instructs the row address decoder to enable the 0th row and the column address decoder to enable the 2nd column, so that the memory cell 2 in the 0th row is enabled.
  • time 3T it is considered that the data processing process based on the memory cell 0-2 in the 0th row has been completed, thereby ending the data processing process.
  • the first information can be used to indicate various processing methods.
  • the process of completing the data processing by the instruction decoder of the storage medium according to the processing modes indicated by the first information is also different, see the following cases C1 and C2.
  • the processing mode indicated by the first information includes the first processing mode
  • the first processing mode includes the processing mode of storing data in the storage unit.
  • the first processing manner includes but is not limited to writing and overwriting.
  • the instruction decoder of the storage medium also needs to acquire data so as to perform data storage according to the first processing mode. Therefore, the method provided in this embodiment further includes: the controller sends data.
  • the data sent by the controller is data received by the controller from the processor.
  • the instruction decoder of the storage medium performs data processing according to the processing mode indicated by the first information based on the at least two target storage units, including: storing the data sent by the controller in the at least two target storage units according to the first processing mode. middle.
  • the controller after sending the first processing instruction to the instruction decoder of the storage medium, the controller continues to send data to the instruction decoder of the storage medium, so that the instruction decoder stores the data in the target storage unit.
  • the controller after sending the first processing instruction to the instruction decoder of the storage medium, the controller sends data to the data processing unit in the storage medium, and after the instruction decoder determines that the target storage unit is enabled, it controls the data processing unit to store the data in the data processing unit. in the target storage unit.
  • the processing mode indicated by the first information includes a second processing mode
  • the second processing mode includes a data processing mode based on a storage unit that has stored data.
  • the second processing manner includes, but is not limited to, reading and erasing.
  • the instruction decoder of the storage medium performs data processing according to the processing mode indicated by the first information based on the at least two target storage units, including: the instruction decoder of the storage medium, according to the second processing mode, performs data processing on the data stored in the at least two target storage units. data are processed.
  • the method further includes: the instruction decoder of the storage medium processes the data stored in the at least two target storage units according to the second processing mode.
  • the address sequence of the storage units sends the data stored in at least two target storage units to the controller.
  • the controller also receives the data stored in the at least two target storage units sent by the instruction decoder of the storage medium.
  • the instruction decoder of the storage medium realizes the sending of data through multiple sending processes, and the length of the data sent during each sending process is determined based on the bit width of the IO interface, that is, the length of the data sent during each sending process.
  • the instruction decoder of the storage medium first divides the data stored in the first target storage unit into multiple parts according to the bit width of the IO interface, and sends each part to the controller according to the address in the first-to-last order. After all the parts in the first target storage unit are sent, the data stored in the second target storage unit is divided and sent in the same way. And so on, until the data stored in each target storage unit has been sent.
  • the data stored in the first target storage unit is firstly divided into 16 parts with a length of 1B.
  • the 1st part, the 2nd part, ..., the 16th part in the first target storage unit are sent in the order after arrival, so that the data stored in the first target storage unit is sent to the 16th sending process.
  • controller After that, the data stored in the second target storage unit is also divided into 16 parts with a length of 1B, and the data stored in the second target storage unit is sent to the controller through 16 sending processes.
  • FIG. 7 shows the process of reading the data of 64B.
  • the instruction decoder of the storage medium controls the row address decoder and the corresponding MUX to enable the 0th row, and controls the column address decoder and the corresponding MUX to enable the 0th to 3rd columns, so that the storage unit 0 in the 0th row is enabled. -3 is enabled. After that, read the data stored in the memory cells 0-3 in the 0th row, and read 64B of data in total.
  • FIG. 8 shows the process of reading the data of 256B.
  • the instruction decoder of the storage medium controls the row address decoder and the corresponding MUX to enable the 0th row, and controls the column address decoder and the corresponding MUX to enable the 0th to 15th columns, so that the storage unit 0 in the 0th row is 0 -15 is enabled.
  • the data stored in the memory cells 0-15 in the 0th row and read 256B of data in total.
  • FIG. 9 shows a process of reading data of 4KB (ie, 4096B).
  • the instruction decoder of the storage medium controls the row address decoder and the corresponding MUX to enable the 0th row, and controls the column address decoder and the corresponding MUX to enable the 0th to 15th columns, thereby enabling the memory cells in the 0th row. 0-15, read 256B of data.
  • the instruction decoder of the storage medium controls the row address decoder and the corresponding MUX to enable row 1, and controls the column address decoder and the corresponding MUX to enable columns 0-15, thereby enabling the memory cells in row 1 0-15, continue to read 256B of data.
  • the instruction decoder of the storage medium controls the row address decoder and the corresponding MUX to enable the 15th row, and controls the column address decoder and the corresponding MUX to enable the 0-15th column, so that the 15th row Memory cells 0-15 are enabled to read 256B of data.
  • a total of 4KB of data in 16 rows is read.
  • the controller only needs to send one processing instruction, so that the instruction decoder of the storage medium can perform continuous data processing based on at least two storage units.
  • the data processing method provided in this embodiment can reduce the number of processing instructions that the controller needs to send. It not only reduces the processing resources that the controller needs to consume in the process of data processing, avoids the waste of resources, but also improves the efficiency of data processing.
  • processor may be a central processing unit (Central Processing Unit, CPU), or other general-purpose processors, digital signal processing (digital signal processing, DSP), application specific integrated circuit (application specific integrated circuit, ASIC), field-programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc.
  • a general purpose processor may be a microprocessor or any conventional processor or the like. It should be noted that the processor may be a processor supporting an advanced RISC machine (ARM) architecture.
  • ARM advanced RISC machine
  • the above-mentioned storage medium may include a read-only storage medium and a random access storage medium, and provide instructions and data to the processor.
  • Storage media may also include non-volatile random access storage media.
  • the storage medium may also store device type information.
  • the storage medium may be a volatile storage medium or a non-volatile storage medium, or may include both volatile and non-volatile storage media.
  • the non-volatile storage medium may be a phase change memory (phase change memory, PCM), a read-only storage medium (read-only memory, ROM), a programmable read-only storage medium (programmable ROM, PROM), an erasable storage medium Programmable read-only storage medium (erasable PROM, EPROM), electrically erasable programmable read-only storage medium (electrically EPROM, EEPROM), or flash memory.
  • the volatile storage medium may be random access memory (RAM), which acts as an external cache. By way of example and not limitation, many forms of RAM are available.
  • static random access storage media static random access storage media
  • dynamic random access storage media dynamic random access memory, DRAM
  • synchronous dynamic random access storage media synchronous DRAM, SDRAM
  • double data rate synchronous dynamic storage media Random access storage media double data date SDRAM, DDR SDRAM
  • enhanced synchronous dynamic random access storage media enhanced SDRAM, ESDRAM
  • synchronous link dynamic random access storage media direct memory bus random access Access storage media (direct rambus RAM, DR RAM).
  • the above-mentioned embodiments it may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • software it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions when loaded and executed on a computer, result in whole or in part of the processes or functions described herein.
  • the computer may be a general purpose computer, special purpose computer, computer network, or other programmable device.
  • the computer instructions may be stored in or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions may be downloaded from a website site, computer, server or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, optical fiber, digital subscriber line) or wireless (eg, infrared, wireless, microwave, etc.).
  • the computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that includes an integration of one or more available media.
  • the usable media may be magnetic media (eg, floppy disks, hard disks, magnetic tapes), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk), and the like.

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Abstract

一种存储装置和处理数据的方法，属于计算机技术领域。其中，存储装置包括控制器和存储介质，存储介质包括指令解码器和多个存储单元，控制器和存储介质的指令解码器连接。控制器，用于向存储介质的指令解码器发送第一处理指令，该第一处理指令包括第一信息和第二信息，第一信息用于指示处理方式，第二信息用于指示需要处理的数据的数据长度。相应地，存储介质的指令解码器，用于接收控制器发送的第一处理指令，基于第二信息指示的数据长度，从存储介质的多个存储单元中确定至少两个目标存储单元，从而基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理。该存储装置减少了控制器需要发送的处理指令的数量。

Description

存储装置和处理数据的方法
本申请要求于2021年04月07日提交的申请号为202110373612.5、发明名称为“一种存储器的操作方法及装置”的中国专利申请的优先权，以及于2021年04月30日提交的申请号为202110485385.5、发明名称为“存储装置和处理数据的方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本申请涉及计算机技术领域，特别涉及存储装置和处理数据的方法。
背景技术
计算机设备中包括多种元件，存储介质便是多种元件中的一种。在存储介质中，数据以多个存储单元的形式存储，存储单元是进行数据处理的最小操作单元。
相关技术中，通过计算机设备中的控制器向存储介质发送指令，每个指令针对存储介质中的一个存储单元。因此，在需要基于多个存储单元进行数据处理的情况下，控制器则需要向存储介质发送多个处理指令。该方式需要控制器消耗较多的处理资源，导致资源浪费，且处理数据的效率不高。
发明内容
本申请实施例提供了一种存储装置和处理数据的方法，以解决相关技术提供的问题，技术方案如下：
第一方面，提供了一种存储装置，该存储装置包括控制器和存储介质，存储介质包括指令解码器和多个存储单元，控制器和存储介质的指令解码器连接。其中，控制器，用于向存储介质的指令解码器发送第一处理指令该，第一处理指令包括第一信息和第二信息，第一信息用于指示处理方式，第二信息用于指示需要处理的数据的数据长度。相应地，存储介质的指令解码器，用于接收控制器发送的第一处理指令。基于该第一处理指令中第二信息指示的数据长度，从存储介质的多个存储单元中确定至少两个目标存储单元。之后，基于至少两个目标存储单元，按照该第一处理指令中第一信息指示的处理方式进行数据处理。
能够看出，控制器仅需发送一个处理指令，便能够使得存储介质的指令解码器基于至少两个存储单元进行连续的数据处理。相比于每个处理指令仅能指示指令解码器基于一个存储单元进行数据处理的情况，本实施例提供的存储装置能够减少控制器需要发送的处理指令的数量。因此，不仅降低了数据处理过程中控制器需要消耗的处理资源、避免了资源浪费，而且提高了数据处理的效率。
在一种可能的实现方式中，存储介质的多个存储单元位于至少一个存储行中，存储介质的指令解码器，用于确定需要处理的数据的起始地址，基于第二信息、多个存储单元的长度、至少一个存储行的长度和需要处理的数据的起始地址，从存储介质的多个存储单元中确定至少两个目标存储单元。提供了确定至少两个目标存储单元的一种示例性实现方式，从而使得存储介质的指令解码器能够基于确定出的至少两个目标存储单元实现数据处理。
在一种可能的实现方式中，第一处理指令还包括第三信息，第三信息用于指示地址，存储介质的指令解码器，用于将第三信息指示的地址确定为需要处理的数据的起始地址，至少两个目标存储单元的地址连续。其中，在第一处理指令携带第三信息的情况下，存储介质的指令解码器直接将第三信息指示的地址作为需要处理的数据的起始地址。由此，可以在后续过程中将需要处理的数据的起始地址所在的存储单元作为首个目标存储单元，将包括首个目标存储单元在内的、连续的存储单元确定为至少两个目标存储单元。
在一种可能的实现方式中，存储介质的指令解码器，用于基于存储介质的多个存储单元确定需要处理的数据的起始地址，至少两个目标存储单元的地址连续或者不连续。相应地，存储介质的指令解码器，还用于封装第一处理指令的指令标识和至少两个目标存储单元的地址，得到响应消息，向控制器发送响应消息；控制器，还用于接收响应消息。在该实现方式中，存储介质的指令解码器在多个存储单元中随机确定需要处理的数据的起始地址，随机确定至少两个目标存储单元，则至少两个目标存储单元可能连续，也可能不连续。由于至少两个目标存储单元是随机确定的，因而指令解码器还需要将至少两个目标存储单元的地址返回给控制器，以便于控制器确定指令解码器是基于哪几个目标存储单元实现的数据处理。
在一种可能的实现方式中，第一信息指示的处理方式包括第一处理方式，第一处理方式包括将数据存储于存储单元的处理方式，控制器，还用于发送数据。相应地，存储介质的指令解码器，用于按照第一处理方式，将控制器发送的数据存储于至少两个目标存储单元中。其中，第一处理方式例如为写入、覆盖。指令解码器进行的数据处理过程是指对数据的存储过程。
在一种可能的实现方式中，第一信息指示的处理方式包括第二处理方式，第二处理方式包括基于已存储数据的存储单元进行数据处理的方式，存储介质的指令解码器，用于按照第二处理方式，对至少两个目标存储单元中已存储的数据进行处理。其中，第二处理方式例如为读取、擦除。指令解码器进行的数据处理过程是指对已存储的数据的处理过程。
在一种可能的实现方式中，存储介质的指令解码器，还用于按照至少两个目标存储单元的地址顺序，向控制器发送至少两个目标存储单元中已存储的数据。控制器，还用于接收存储介质的指令解码器发送的至少两个目标存储单元中已存储的数据。例如在处理方式为读取时，存储介质的指令解码器需要将读取到的数据返回至控制器。其中，指令解码器通过多次发送过程完成数据的发送，每次发送过程中发送的数据长度取决于发送接口的位宽。
在一种可能的实现方式中，第一处理指令中还包括第四信息，第四信息用于指示数据分组要求，数据分组要求包括以存储行为单位对至少两个目标存储单元进行分组，或者以存储列为单位对至少两个目标存储单元进行分组，存储介质的指令解码器，用于按照第四信息指示的数据分组要求对至少两个目标存储单元进行分组，得到至少一个分组，基于各个分组中的目标存储单元，按照第一信息指示的处理方式进行数据处理。在该实现方式中，根据第四信息的指示，存储介质的指令解码器可以存储行为单位进行数据处理，也就是完成一个存储行中各个目标存储单元的数据处理之后，切换至其他存储行，对其他存储行的目标存储单元进行数据处理。或者，还可以存储列为单位进行数据处理，在完成一个存储列中各个目标存储单元的数据处理之后，切换至其他存储列。该第四信息使得指令解码器进行数据处理的过程较为灵活。
在一种可能的实现方式中，存储介质的指令解码器，用于对于任一分组，并行使能任一分组中的目标存储单元，按照第一信息指示的处理方式对任一分组中并行使能的目标存储单元进行数据处理，使得任一分组中并行使能的目标存储单元的处理时间之间的差值小于阈值。对同一分组内的目标存储单元进行并行使能及数据处理，减少了使能及数据处理所需的时间，因而缩短了数据处理所需的总时间。
在一种可能的实现方式中，至少两个目标存储单元位于同一逻辑单元号中，目标存储单元为进行数据处理的最小单元。在本实施例中，一个存储介质即为一个逻辑单元号，因而从存储介质的多个存储单元中确定出的至少两个目标存储单元是位于同一逻辑单元号中的。
在一种可能的实现方式中，存储介质的指令解码器，还用于解析第一处理指令，得到第一信息和第二信息。指令解码器通过对第一处理指令的解析获得第一信息和第二信息。
在一种可能的实现方式中，至少两个目标存储单元的长度之和不小于第二信息指示的数据长度。由于目标存储单元是进行数据处理的最小单元，因而至少两个目标存储单元的长度之和可能等于第二信息指示的数据长度，也可能大于第二信息指示的数据长度。例如，在数据长度不能整除存储单元的长度时，至少两个目标存储单元的长度之和大于第二信息指示的数据长度。
在一种可能的实现方式中，存储介质的数量为多个，控制器用于接收存储介质标识，向存储介质标识指示的存储介质的指令解码器发送第一处理指令。在存储介质的数量为多个时，控制器基于存储介质标识确定向哪一个存储介质的指令解码器发送该第一处理指令。例如，该存储介质标识为处理器发送的逻辑地址，则控制器将该逻辑地址对应的物理地址指示的指令解码器作为用于接收第一处理指令的指令解码器。
第二方面，提供了一种处理数据的方法，该方法应用于存储装置，存储装置包括控制器和存储介质，存储介质包括指令解码器和多个存储单元，方法包括：
存储介质的指令解码器接收控制器发送的第一处理指令，第一处理指令包括第一信息和第二信息，第一信息用于指示处理方式，第二信息用于指示需要处理的数据的数据长度；
存储介质的指令解码器基于第二信息指示的数据长度，从存储介质的多个存储单元中确定至少两个目标存储单元；
存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理。
在一种可能的实现方式中，存储介质的多个存储单元位于至少一个存储行中，存储介质的指令解码器基于第二信息指示的数据长度，从存储介质的多个存储单元中确定至少两个目标存储单元，包括：存储介质的指令解码器确定需要处理的数据的起始地址；存储介质的指令解码器基于第二信息、多个存储单元的长度、至少一个存储行的长度和需要处理的数据的起始地址，从存储介质的多个存储单元中确定至少两个目标存储单元。
在一种可能的实现方式中，第一处理指令还包括第三信息，第三信息用于指示地址，存储介质的指令解码器确定需要处理的数据的起始地址，包括：存储介质的指令解码器将第三信息指示的地址确定为需要处理的数据的起始地址，至少两个目标存储单元的地址连续。
在一种可能的实现方式中，存储介质的指令解码器确定需要处理的数据的起始地址，包括：基于存储介质的多个存储单元确定需要处理的数据的起始地址，至少两个目标存储单元的地址连续或者不连续。存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理之后，方法还包括：存储介质的指令解码器封装第一处理指令的指令标识和至少两个目标存储单元的地址，得到响应消息，向控制器发送响应消息。
在一种可能的实现方式中，第一信息指示的处理方式包括第一处理方式，第一处理方式包括将数据存储于存储单元的处理方式，存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理，包括：存储介质的指令解码器按照第一信息指示的方式，将控制器发送的数据存储于至少两个目标存储单元中。
在一种可能的实现方式中，第一信息指示的处理方式包括第二处理方式，第二处理方式包括基于已存储数据的存储单元进行数据处理的方式，存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理，包括：存储介质的指令解码器按照第二处理方式，对至少两个目标存储单元中已存储的数据进行处理。
在一种可能的实现方式中，存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理之后，方法还包括：存储介质的指令解码器按照至少两个目标存储单元的地址顺序，向控制器发送至少两个目标存储单元中已存储的数据。
在一种可能的实现方式中，第一处理指令中还包括第四信息，第四信息用于指示数据分组要求，数据分组要求包括以存储行为单位对至少两个目标存储单元进行分组，或者以存储列为单位对至少两个目标存储单元进行分组。存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理，包括：存储介质的指令解码器按照第四信息指示的数据分组要求对至少两个目标存储单元进行分组，得到至少一个分组。存储介质的指令解码器基于各个分组中的目标存储单元，按照第一信息指示的处理方式进行数据处理。
在一种可能的实现方式中，存储介质的指令解码器基于各个分组中的目标存储单元，按照第一信息指示的处理方式进行数据处理，包括：存储介质的指令解码器对于任一分组，并行使能任一分组中的目标存储单元；存储介质的指令解码器按照第一信息指示的处理方式对任一分组中并行使能的目标存储单元进行数据处理，使得任一分组中并行使能的目标存储单 元的处理时间之间的差值小于阈值。
在一种可能的实现方式中，至少两个目标存储单元位于同一逻辑单元号中，目标存储单元为进行数据处理的最小单元。
在一种可能的实现方式中，存储介质的指令解码器基于各个分组中的目标存储单元，按照第一信息指示的处理方式进行数据处理之前，方法还包括：存储介质的指令解码器解析第一处理指令，得到第一信息和第二信息。
在一种可能的实现方式中，至少两个目标存储单元的长度之和不小于第二信息指示的数据长度。
第三方面，提供了一种处理数据的方法，方法应用于存储装置，存储装置包括控制器和存储介质，存储介质包括指令解码器和多个存储单元，方法包括：
控制器确定第一信息和第二信息，第一信息用于指示处理方式，第二信息用于指示需要处理的数据的数据长度，数据长度用于从存储介质的多个存储单元中确定至少两个目标存储单元，至少两个目标存储单元用于数据处理；
控制器封装第一信息和第二信息，得到第一处理指令；
控制器向存储介质的指令解码器发送第一处理指令。
在一种可能的实现方式中，控制器确定第一信息和第二信息，包括：接收第二处理指令，第二处理指令包括第一参考信息和第二参考信息，第一参考信息用于指示处理方式，第二参考信息用于指示需要处理的数据的数据长度。将第一参考信息确定为第一信息，基于第二参考信息确定第二信息。
在一种可能的实现方式中，控制器确定第一信息和第二信息，包括：第二处理指令的数量包括至少两个，基于第二参考信息确定第二信息，包括：响应于至少两个第二处理指令的第二参考信息指示的数据长度小于参考范围的下限，控制器合并至少两个第二处理指令的第二参考信息得到第二信息，第二信息指示的数据长度位于参考范围内。
在一种可能的实现方式中，控制器确定第一信息和第二信息，包括：响应于第二处理指令的第二参考信息指示的数据长度大于参考范围的上限，控制器划分该第二参考信息得到至少两个第二信息，任一第二信息指示的数据长度均位于参考范围内。
在一种可能的实现方式中，控制器确定第一信息和第二信息，包括：响应于第二处理指令的第二参考信息指示的数据长度位于参考范围内，将第二参考信息作为第二信息。
在一种可能的实现方式中，控制器向存储介质的指令解码器发送第一处理指令之前，方法还包括：控制器获取第三信息，第三信息用于指示地址，将第三信息封装于第一处理指令中。
在一种可能的实现方式中，控制器向存储介质的指令解码器发送第一处理指令之后，方法还包括：接收存储介质的指令解码器发送的响应消息，该响应消息中包括第一处理指令的指令标识和至少两个目标存储单元的地址。
在一种可能的实现方式中，控制器向存储介质的指令解码器发送第一处理指令之后，方法还包括：发送数据，数据用于存储介质的指令解码器存储于至少两个目标存储单元中。
在一种可能的实现方式中，控制器向存储介质的指令解码器发送第一处理指令之后，方法还包括：接收存储介质的指令解码器按照至少两个目标存储单元的地址顺序发送的至少两个目标存储单元中存储的数据。
在一种可能的实现方式中，控制器向存储介质的指令解码器发送第一处理指令之前，方法还包括：控制器确定第四信息，第四信息用于指示数据分组要求，数据分组要求包括以存储行为单位对至少两个目标存储单元进行分组，或者以存储列为单位对至少两个目标存储单元进行分组，将第四信息封装于第一处理指令中。
在一种可能的实现方式中，至少两个目标存储单元位于同一逻辑单元号中，目标存储单元为进行数据处理的最小单元。
在一种可能的实现方式中，至少两个目标存储单元的长度之和不小于第二信息指示的数据长度。
在一种可能的实现方式中，存储装置的数量为多个，控制器向存储介质的指令解码器发送第一处理指令，包括：控制器接收存储介质标识，向存储介质标识指示的存储介质的指令解码器发送第一处理指令。
附图说明
图1为本申请实施例提供的一种存储装置的结构示意图；
图2为本申请实施例提供的一种存储装置的结构示意图；
图3为本申请实施例提供的一种处理数据的方法的流程图；
图4为本申请实施例提供的一种存储装置的结构示意图；
图5为本申请实施例提供的一种相关技术中的处理数据的流程示意图；
图6为本申请实施例提供的一种处理数据的流程示意图；
图7为本申请实施例提供的一种处理数据的示意图；
图8为本申请实施例提供的一种处理数据的示意图；
图9为本申请实施例提供的一种处理数据的示意图。
具体实施方式
本申请的实施方式部分使用的术语仅用于对本申请的具体实施例进行解释，而非旨在限定本申请。
本申请实施例提供了一种存储装置，参见图1，该存储装置包括控制器和存储介质，存储介质包括指令解码器(command decoder)和多个存储单元，控制器和存储介质的指令解码器连接。从而，该存储介质的指令解码器能够接收控制器发送的处理指令，基于接收到的处理指令进行数据处理。其中，一个存储介质即为一个逻辑单元号(logical unit number，LUN)，LUN也称为Die。在存储介质中，多个存储单元形成阵列，阵列也称为bank。在该阵列中包括M个行和N个列，M和N为不小于1的整数。一个存储单元由一个行和一个列进行唯一标识。另外，存储介质中还包括输入输出(input/output，IO)接口，该IO接口与控制器连接，从而根据需要将数据处理结果返回至控制器。
示例性地，参见图2，存储装置中包括的存储介质的数量为多个。多个存储介质中的各个存储介质分别包括上述指令解码器和多个存储单元，此处不再进行赘述。对于存储介质中的控制器而言，该控制器和多个存储介质的指令控制器分别连接。
示例性地，参见图1，对于任一存储介质而言，除了包括上述控制器和多个存储单元以外，还包括行地址解码器(row address decoder)和列地址解码器(column address decoder)，行地址解码器和列地址解码器还分别对应有多路复用器(multiplexer，MUX)。指令解码器向行地址解码器发送指令，行地址解码器根据该指令控制行地址解码器对应的MUX使能(enable)阵列中的一个或多个行。指令解码器还向列地址解码器发送指令，列地址解码器根据该指令控制列地址解码器对应的MUX使能阵列中的一个或多个列。由于存储单元通过行和列唯一标识，因而在分别使能阵列中的行和列之后，便能够实现阵列中的一个或多个存储单元的使能。在本实施例中，经过使能的存储单元可以用于进行数据处理。
参见图1，任一存储介质中还包括数据处理单元，数据处理单元与指令解码器连接，从而根据指令解码器的控制，与指令解码器配合完成数据处理过程。其中，指令解码器首先通过控制行地址解码器和列地址解码器使能阵列中的存储单元，之后控制数据处理单元基于使能的存储单元进行数据处理。例如，该数据处理单元根据指令解码器的控制对使能的存储单元进行读取、擦除等处理。又例如，该数据处理单元还与控制器连接，从而接收控制器发送的数据，根据指令解码器的控制将接收到的数据写入至使能的存储单元中。
基于上述图1和图2所示的存储装置，本申请实施例提供了一种处理数据的方法，该方法应用于控制器和存储介质的指令解码器的交互过程。参见图3，该方法包括如下的内容。
301，控制器向存储介质的指令解码器发送第一处理指令。
在第一处理指令中，包括第一信息和第二信息，第一信息用于指示处理方式，第二信息用于指示需要处理的数据的数据长度。第一信息指示的处理方式包括但不限于：读取、写入擦除、覆盖等方式。其中，读取是指获取存储单元中已存储的数据并返回至控制器，写入是指向未存储数据的存储单元中存储数据，擦除是指删除存储单元中已存储的数据，覆盖是指向已存储数据的存储单元中存储数据。当然，以上方式均为举例，不用于对第一信息指示的处理方式造成限定。第二信息指示的需要处理的数据的数据长度根据实际需求确定。在本实施例中，第二信息能够通过多种方式指示数据长度。例如，第二信息包括长度数值，数据长度等于该长度数值。又例如，第二信息为存储单元的个数，数据长度等于存储单元的个数与存储单元的长度之间的乘积。再例如，第二信息包括第一地址和位于第一地址之后的第二地址，则数据长度等于第二地址与第一地址之间的差值。
对于控制器而言，控制器首先确定第一信息和第二信息，之后，封装第一信息和第二信息即可得到上述第一处理指令，从而向存储介质的指令解码器发送该第一处理指令。示例性地，控制器确定第一信息和第二信息，包括：接收第二处理指令，第二处理指令包括第一参考信息和第二参考信息，第一参考信息用于指示处理方式，第二参考信息用于指示需要处理的数据的数据长度。将第一参考信息确定为第一信息，基于第二参考信息确定第二信息。
其中，该第二处理指令包括处理器向控制器发送的指令，处理器是位于存储装置以外的其他元件，处理器和存储装置可以集成于同一计算机设备中，也可以分别位于不同的计算机设备中。第一参考信息指示的处理方式包括但不限于读取、写入、擦除、覆盖等等，本实施例中将第一参考信息作为第一信息，从而使得第一处理指令和第二处理指令指示的处理方式相同。示例性地，基于第二参考信息确定第二信息，包括如下的三种情况A1-A3。
情况A1，第二处理指令的数量包括至少两个，基于第二参考信息确定第二信息，包括：响应于至少两个第二处理指令的第二参考信息指示的数据长度小于参考范围的下限，控制器合并至少两个第二处理指令的第二参考信息得到第二信息，第二信息指示的数据长度位于参考范围内。
其中，参考范围即为数据长度的取值范围，本实施例不对参考范围的下限和上限进行限定。第二信息指示的数据长度位于参考范围内是指：第二信息指示的数据长度不小于参考范围的下限，且不大于参考范围的上限。示例性地，参考范围的下限和上限基于存储介质进行数据处理时的处理效率确定。例如，获得存储介质对不同数据长度的数据进行处理时的处理效率，根据高于效率阈值的处理效率对应的数据长度确定参考范围的下限和上限。由此，使得存储介质对该参考范围内的数据进行处理时，存储介质能够具有较高的处理效率。
以参考范围的下限为128B、上限为1MB为例，对控制器合并第二参考信息的过程进行说明：
在控制器接收到的两个第二处理指令中，第一参考信息指示的处理方式均为写入，一个第二参考信息指示的数据长度为64B，另一个第二参考信息指示的数据长度为96B，则两个第二参考信息指示的数据长度均小于参考范围的下限128B。因此，控制器对两个第二参考信息指示的数据长度进行合并，也就是将64B与96B之和160B作为第二信息，该第二信息指示的数据长度160B位于参考范围128B-1MB内。对于控制器而言，后续仅需要向存储介质的指令解码器发送一个第一处理指令，该第一处理指令的第一信息指示的处理方式为写入，该第一处理指令的第二信息指示的数据长度为160B。
在控制器不对至少两个第二处理指令的第二参考信息进行合并的情况下，则针对每个第二处理指令，控制器均需要向存储介质的指令解码器发送一个第一处理指令，也就是说控制器需要向存储介质的指令解码器发送至少两个第一处理指令。在情况A1中，由于控制器对至少两个第二处理指令的第二参考信息进行了合并，因而减少了控制器向存储介质的指令解码器发送的第一处理指令的数量。由此，减小了数据处理过程中控制器需要消耗的处理资源，提高了数据处理效率。
示例性地，本实施例在至少两个第二处理指令的第一参考信息指示的处理方式相同的情况下，对至少两个第二处理指令的第二参考信息进行合并。例如，两个第二处理指令的第一 参考信息指示的处理方式均为写入，则对这两个第二处理指令的第二参考信息进行合并。但是，如果一个第二处理指令的第一参考信息指示的处理方式为写入，另一个第二处理指令的第一参考信息指示的处理方式为读取，则不对这两个第二处理指令进行合并。
情况A2，响应于第二处理指令的第二参考信息指示的数据长度大于参考范围的上限，控制器划分该第二参考信息得到至少两个第二信息，任一第二信息指示的数据长度均位于参考范围内。
其中，参考范围的上限的确定方式参见情况A1中的说明，此处不再进行赘述。在控制器划分第二参考信息得到第二信息的过程中，不同第二信息指示的数据长度可以相同，也可以不同，只要各个第二信息指示的数据长度均位于参考范围内即可。
以参考范围的下限为128B、参考范围的上限为1MB为例，对控制器划分第二参考信息的过程进行说明：
控制器接收第二处理指令，该第二处理指令的第一参考信息指示的处理方式为读取，该第二处理指令的第二参考信息指示的数据长度为4MB，大于参考范围的上限1MB。因此，控制器将第二参考信息划分为多个第二信息，例如将第二参考信息平均划分为四份，从而得到四个第二信息，各个第二信息指示的数据长度均为1MB，位于参考范围128B-1MB内。对于控制器而言，后续向存储介质的指解码器发送四个第一处理指令，各个第一处理指令的第一信息指示的处理方式均为读取，第二信息指示的数据长度均为1MB。
在控制器不对第二处理指令的第二参考信息进行划分的情况下，控制器仅向存储介质的指令解码器发送一个第一处理指令。根据该第一处理指令，存储介质需要在一次数据处理过程中对较长的数据进行处理(例如上例中的4MB)，因而存储介质完成一次数据处理所需的时间较长。在一些场景中，存储介质完成一次数据处理之后，需要向控制器返回信息。由于存储介质完成一次数据处理所需的时间较长，因而控制器需要等待较长时间才能接收到存储介质返回的信息。例如，在数据读取场景中，存储介质根据第一处理指令完成数据读取之后，需要向控制器返回读取到的数据。对于控制器而言，需要等待较长时间才能接收到存储介质读取的数据。
而在情况A2中，由于控制器对第二处理指令的第二参考信息进行了划分，得到了至少两个第一处理指令。根据各个第一处理指令，减少了存储介质在一次数据处理过程中需要处理的数据的长度(例如上例中由4MB减少至1MB)，从而缩短了存储介质完成一次数据处理所需的时间。在存储介质需要向控制器返回信息的场景下，控制器仅需等待较短的时间即可接收到存储介质返回的信息。
情况A3，响应于第二处理指令的第二参考信息指示的数据长度位于参考范围内，将第二参考信息作为第二信息。
在第二处理指令的第二参考信息指示的数据长度位于参考范围内的情况下，将第二参考信息直接作为第二信息即可。在情况A3中，处理器向控制器发送的第二处理指令即为控制器向存储介质的指令解码器发送的第一处理指令，也就是说，第二处理指令与第一处理指令相同。
以上，说明了控制器生成第一处理指令的方式。在控制器与一个存储介质的指令解码器连接的情况下，控制器向该存储介质的指令解码器发送第一处理指令即可。需要说明的是，存储介质对应有芯片使能(chip enable，CE)管脚，控制器通过CE管脚使能存储介质，得到使能的存储介质，从而将该第一处理指令发送至使能的存储介质。
在控制器与多个存储介质的指令解码器连接的情况下，控制器还需要确定向哪一个存储介质的指令解码器发送该第一处理指令。示例性地，控制器接收存储介质标识，向该存储介质标识指示的存储介质的指令解码器发送该第一处理指令。其中，该存储介质标识携带于处理器向控制器发送的第二处理指令中，该存储介质标识例如为逻辑地址。控制器中存储有逻辑地址与物理地址的映射关系，控制器根据该映射关系能够确定与该逻辑地址对应的物理地址，在多个存储介质中将与该逻辑地址对应的物理地址所指示的存储介质确定为目标存储介质，该目标存储介质的指令解码器用于接收第一处理指令。因此，控制器通过该目标存储介 质的CE管脚使能该目标存储介质，将第一处理指令发送至使能的目标存储介质。
302，存储介质的指令解码器接收控制器发送的第一处理指令。
由于存储介质的指令解码器与控制器连接，因而在控制器发送了第一处理指令之后，存储介质的指令解码器相应的对第一处理指令进行接收。
303，存储介质的指令解码器基于第二信息指示的数据长度，从存储介质的多个存储单元中确定至少两个目标存储单元。
根据301中的说明可知，第一处理指令中包括第一信息和第二信息。为得到第一处理指令中的第一信息和第二信息，示例性地，方法还包括：存储介质的指令解码器解析第一处理指令，得到第一信息和第二信息。在得到第一信息和第二信息之后，存储介质的指令解码器便能够确定第二信息指示的数据长度，从而能够基于该数据长度从存储介质的多个存储单元中确定至少两个目标存储单元。
需要说明的是，由于一个存储介质即为一个LUN，因而从存储介质的多个存储单元中确定出的至少两个目标存储单元也位于同一LUN中。并且，目标存储单元为进行数据处理的最小单元。换言之，在数据处理过程中，是基于整数个目标存储单元进行的数据处理。对于任一目标存储单元而言，均不会仅基于该目标存储单元中的一部分进行数据处理。因此，至少两个目标存储单元的长度之和不小于数据长度。例如，在数据长度能够整除目标存储单元的长度的情况下，至少两个目标存储单元的长度之和等数据长度。又例如，在数据长度不能够整除目标存储单元的长度的情况下，至少两个目标存储单元的长度之和则大于数据长度。
在示例性实施例中，存储介质的指令解码器基于第二信息指示的数据长度，从存储介质的多个存储单元中确定至少两个目标存储单元，包括如下的3031和3032。
3031，存储介质的指令解码器确定需要处理的数据的起始地址。
其中，需要处理的数据的起始地址影响着目标存储单元的数量。在第二信息指示的数据长度、存储单元的长度均相同的情况下。需要处理的数据的起始地址不同，则目标存储单元的数量也可能不同。以第二信息指示的数据长度为32B，存储单元的长度为16B为例，参见图4，响应于需要处理的数据的起始地址为第0行中存储单元0的地址首位，则目标存储单元为第0行中的存储单元0和存储单元1，目标存储单元的数量为2。响应于需要处理的数据的起始地址位于第0行中存储单元0的地址首位和地址末位之间，则目标存储单元为第0行中的存储单元0、存储单元1和存储单元3，目标存储单元的数量为3。由此可知，本实施例需要确定需要处理的数据的起始地址，以便于后续确定目标存储单元的数量。示例性地，需要处理的数据的起始地址的确定方式包括如下的两种情况。
情况B1，第一处理指令还包括第三信息，第三信息用于指示地址，存储介质的指令解码器将第三信息指示的地址确定为需要处理的数据的起始地址。根据上文说明可知，第一处理指令由控制器封装第一信息和第二信息得到。在第一处理指令还包括第三信息的情况下，控制器在发送封装得到的第一处理指令之前，方法还包括：控制器获取用于指示地址的第三信息，将第三信息封装于第一处理指令中。示例性地，处理器向控制器发送的第二处理指令中包括用于指示地址的信息，控制器解析该第二处理指令得到用于指示地址的信息，从而将该用于指示地址的信息作为第三信息。
情况B2，存储介质的指令解码器基于存储介质的多个存储单元确定需要处理的数据的起始地址。
示例性地，存储介质的指令解码器在存储介质的多个存储单元中随机选择存储单元，将随机选择的存储单元的地址首位作为需要处理的数据的起始地址。进一步地，在一些实施方式中，存储介质的指令解码器根据第一处理指令的第一信息指示的处理方式，从存储介质的多个存储单元中获得第一信息指示的处理方式对应的存储单元，从第一信息指示的处理方式对应的存储单元中随机确定存储单元，从而将随机确定的存储单元的地址首位作为需要处理的数据的起始地址。以第一信息指示的处理方式为写入为例，由于写入是指向未存储数据的存储单元中存储数据，因而第一信息指示的处理方式对应的存储单元是指：未存储数据的存储单元，则存储介质的指令解码器从未存储数据的存储单元中随机确定存储单元，将随机确 定的存储单元的地址首位作为需要处理的数据的起始地址。
3032，存储介质的指令解码器基于第二信息、多个存储单元的长度、至少一个存储行的长度和需要处理的数据的起始地址，从存储介质的多个存储单元中确定至少两个目标存储单元。
示例性地，本实施例基于需要处理的数据的起始地址确定首个目标存储单元，基于第二信息指示的数据长度、存储单元的长度和需要处理的数据的起始地址确定目标存储单元的总数量。为便于描述，将目标存储单元的总数量记为第一数量，则本实施例将包括首个目标存储单元在内的第一数量个存储单元作为至少两个目标存储单元。
在示例性实施例中，响应于按照上述情况B1确定需要处理的数据的起始地址，则将包括首个目标存储单元在内的第一数量个存储单元作为至少两个目标存储单元，包括：以首个目标存储单元为起点，将连续的第一数量个存储单元作为至少两个目标存储单元。由此，使得至少两个目标存储单元的地址连续。例如，参见图4，首个目标存储单元为第0行的存储单元0、目标存储单元的总数量为4个，则目标存储单元为：第0行的存储单元0、存储单元1、存储单元2和存储单元3。
能够理解的是，存储介质的多个存储单元位于至少一个存储行中，一个存储行中包括的存储单元数量是有限的。因此，上述至少两个目标存储单元可能覆盖至少一个存储行，本实施例需要结合存储行的长度确定至少两个目标存储单元覆盖的存储行。其中，存储行的长度等于存储行包括的各个存储单元的长度之和。例如，一个存储行中包括16个长度为16B的存储单元，则该存储行的长度为256B。
示例性地，基于需要处理的数据的起始地址能够确定首个存储行，基于第二信息指示的数据长度、存储行的长度和需要处理的数据的起始地址能够确定存储行的总数量，将存储行的总数量记为第二数量。因此，被覆盖的存储行是指：包括首个存储行在内的第二数量个连续的存储行。例如，参见图4，在第二信息指示的数据长度为512B、存储行的长度为256B、需要处理的数据的起始地址为第0行中存储单元8的地址首位的情况下，首个存储行即为第0行，被覆盖的存储行的总数量为3，从而能够确定被覆盖的存储行即为存储介质中的第0行、第1行和第2行。
或者，响应于按照上述情况B2确定需要处理的数据的起始地址，则将包括首个目标存储单元在内的参考数量个存储单元作为至少两个目标存储单元，包括：在首个目标存储单元之后随机确定存储单元，将首个目标存储单元与随机确定的存储单元作为至少两个目标存储单元，则至少两个目标存储单元的地址连续或者不连续。其中，至少两个目标存储单元的地址连续的情况可参见上文举例，此处不再进行重复举例。对于至少两个目标存储单元的地址不连续的情况，参见图4，仍以首个目标存储单元为第0行的存储单元0、目标存储单元的总数量为4个为例，则目标存储单元可以为：第0行的存储单元0、存储单元2、存储单元3和存储单元4，其中存储单元0和存储单元2的地址不连续。在此种情况中，至少两个目标存储单元也覆盖至少一个存储行，被覆盖的存储行可以根据随机确定出的目标存储单元的地址确定。
需要说明的是，由于在情况B2中目标存储单元是由存储介质的指令解码器随机确定的，因而存储介质的指令解码器需要向控制器返回目标存储单元的地址，以便于控制器得知存储介质的指令解码器是基于哪些目标存储单元进行的数据处理。因此，在示例性实施例中，存储介质的指令解码器确定至少两个目标存储单元之后，方法还包括：存储介质的指令解码器封装第一处理指令的指令标识和至少两个目标存储单元的地址，得到响应消息，向控制器发送响应消息，控制器通过接收该响应消息即可确定至少两个目标存储单元的地址。其中，该响应消息的第一处理指令的指令标识用于控制器区分不同的第一处理指令。在控制器向存储介质的指令解码器发送了多个第一处理指令的情况下，控制器根据响应消息中携带的第一处理指令的指令标识能够确定存储介质的指令解码器是基于哪一个第一处理指令确定出的目标存储单元。
在以上说明中，由存储介质的指令解码器解析第一处理指令，得到第一信息和第二信息 (还可能包括第三信息)，且由存储介质的指令解码器基于该第二信息确定至少两个目标存储单元，至少两个存储单元覆盖至少一个存储行。存储介质的指令解码器可以将被覆盖的存储行发送至行地址解码器，将各个存储行中的目标存储单元发送至列地址解码器，以便于行地址解码器和列地址解码器进行使能。示例性地，本实施例中存储介质的指令解码器还可以仅进行第一处理指令的解析，将得到的第二信息(还可能包括第三信息)分别发送给行地址解码器和列地址解码器，从而由行地址解码器根据接收到的信息自行按照上述说明中的方式确定被覆盖的存储行，由列地址解码器根据接收到的信息自行按照上述说明中的方式确定各个存储行中的目标存储单元，以便于行地址解码器和列地址解码器进行使能。其中，行地址解码器和列地址解码器进行使能的过程参见后文304中的说明。
304，存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理。
能够看出，指令解码器根据控制器发送的一个第一处理指令，能够基于至少两个目标存储单元实现数据处理，该数据处理方式也称为并发(burst)处理。
在示例性实施例中，第一处理指令中还包括第四信息，第四信息用于指示数据分组要求，数据分组要求包括以存储行为单位对至少两个目标存储单元进行分组，或者，以存储列为单位对至少两个目标存储单元进行分组。相应地，存储介质的指令解码器按照第四信息指示的数据分组要求对至少两个目标存储单元进行分组，得到至少一个分组。基于各个分组中的目标存储单元，按照第一信息指示的处理方式进行数据处理。示例性地，该第四信息可以由控制器从第二处理指令中获得，控制器在向存储介质的指令解码器发送第一处理指令之前，将该第四信息封装于第一处理指令中。
示例性地，第四信息表示为数值，第四信息的不同取值用于指示不同的数据分组要求。例如，第四信息的取值为第一数值，则指示数据分组要求为以存储行为单位对至少两个目标存储单元进行分组。第四信息的取值为第二数值，则指示数据分组要求为以存储列为单位对至少两个目标存储单元进行分组，第一数值和第二数值为不同的数值。
其中，响应于数据分组要求包括以存储行为单位对至少两个目标存储单元进行分组，则指令解码器以存储行为单位进行数据处理。也就是说，对于包括有目标存储单元的存储行，指令解码器先基于其中一个存储行中的各个目标存储单元进行数据处理，再切换至另一存储行，基于另一存储行中的各个目标存储单元进行数据处理，以此类推，在遍历各个包括目标存储单元的存储行之后结束数据处理过程。例如，参见图4，以目标存储单元包括第0行中的存储单元0-存储单元15、第1行中的存储单元0-存储单元15为例，则指令解码器先基于第0行中的存储单元0-存储单元15进行数据处理，再切换至第1行，基于第1行中的存储单元0-存储单元15进行数据处理，从而完成数据处理过程。
或者，响应于数据分组要求包括以存储列为单位对至少两个目标存储单元进行分组，则指令解码器以存储列为单位进行数据处理。对于包括有目标存储单元的存储列，指令解码器先基于其中一个存储列中的各个目标存储单元进行数据处理，再切换至另一存储列，基于另一存储列中的各个目标存储单元进行数据处理，以此类推，在遍历各个包括目标存储单元的存储列之后结束数据处理过程。仍以目标存储单元包括第0行中的存储单元0-存储单元15、第1行中的存储单元0-存储单元15为例，则指令解码器先基于第0行和第1行的存储单元0进行数据处理，再切换至存储单元1，基于第0行和第1行的存储单元1进行数据处理。以此类推，直至基于第0行和第1行的存储单元15进行数据处理，从而完成数据处理过程。
能够理解的是，本申请实施例不对各个分组中的目标存储单元的处理顺序进行限定。例如，数据分组要求包括以存储行为单位对至少两个目标存储单元进行分组，指令解码器分别基于第0行和第1行中的存储单元进行数据处理，则指令解码器先基于第0行进行数据处理、再基于第1行进行数据处理，或者，指令解码器先基于第1行进行数据处理、再基于第0行进行数据处理。
进一步地，对于任一存储单元而言，指令解码器基于存储单元进行数据处理的过程包括：对该存储单元进行使能，基于使能的存储单元进行数据处理。因此，在基于各个分组中的目 标存储单元进行数据处理时，指令解码器也需要对各个分组中的目标存储单元进行使能，以便于在该分组中，基于使能的目标存储单元进行数据处理。
示例性地，本实施例中对任一分组中的目标存储单元进行并行使能，以便于缩短数据处理所需消耗的时间，提高数据处理效率。示例性地，存储介质的指令解码器基于各个分组中的目标存储单元，按照第一信息指示的处理方式进行数据处理，包括：存储介质的指令解码器对于任一分组，并行使能任一分组中的目标存储单元。按照第一信息指示的处理方式对任一分组中并行使能的目标存储单元进行数据处理，使得任一分组中并行使能的目标存储单元的处理时间之间的差值小于阈值。
响应于以存储行为单位进行分组，则在一次并行使能过程中，指令解码器向行地址解码器发送第一指令，行地址解码器根据该第一指令控制行地址解码器对应的MUX，使得行地址解码器对应的MUX使能一个包括有目标存储单元的存储行。相应地，指令解码器向列地址解码器发送与第一指令对应的第二指令，列地址解码器根据该第二指令控制列地址解码器对应的MUX，使得列地址解码器对应的MUX并行使能与该存储行对应的一个或多个存储列，从而并行使能该存储行中包括的目标存储单元。之后，按照第一信息指示的处理方式对该存储行中并行使能的目标存储单元进行数据处理。通过对同一存储行中的目标存储单元的并行使能，使得并行使能的目标存储单元的处理时间之间的差值小于阈值。换言之，可以认为同一存储行中的目标存储单元的数据处理过程是同步进行的。
需要说明的是，在存储介质中设置有目标时长，该目标时长是对一个存储单元进行使能和数据处理的过程所需要的时间。换言之，从指令解码器向行地址解码器和列地址解码器发送指令开始计时，在经过目标时长之后，则认为已经完成了对一个存储单元的使能和数据处理。在本实施例中，由于同一存储行中的各个目标存储单元的数据处理过程是同步进行的，因而从指令解码器发送指令开始计时，经过一个目标时长后，则认为该存储行中的各个目标存储单元的使能和数据处理过程均已完成。因此，指令解码器可以向行地址解码器和列地址解码器发送新的指令，以指示对其他存储行中的目标存储单元进行并行使能以及数据处理。
以目标存储单元包括第0行中的存储单元0-15、第1行中的存储单元0-15为例，将上述目标时长记为T，将指令解码器首次发送指令的时刻记为0，则有：在0时刻，指令解码器向行地址解码器发送第一指令、向列地址解码器发送与第一指令对应的第二指令，行地址解码器根据该第一指令控制行地址解码器对应的MUX使能第0行，列地址解码器根据该第一指令控制列地址解码器对应的MUX使能第0-15列，从而使能第0行中的存储单元0-15，在使能完成后进行数据处理。在T时刻，认为基于第0行中的存储单元0-15的数据处理过程已完成。因此，指令解码器向行地址解码器发送新的第一指令、向列地址解码器发送新的第二指令，以对第1行中的存储单元0-15进行使能，在使能完成后进行数据处理，在2T时刻，认为基于第1行中的存储单元0-15的数据处理过程已完成，从而结束数据处理过程。
或者，响应于以存储列为单位进行分组，则在一次并行使能过程中，指令解码器向列地址解码器发送第一指令，列地址解码器根据该第一指令控制列地址解码器对应的MUX使能一个包括有目标存储单元的存储列。相应地，指令解码器向行地址解码器发送与第一指令对应的第二指令，行地址解码器根据该第二指令控制行地址解码器对应的MUX，使得行地址解码器对应的MUX使能该存储列对应的一个或多个存储行，从而并行使能该存储列中包括的目标存储单元。之后，按照第一信息指示的处理方式对该存储列中并行使能的目标存储单元进行数据处理，使得该存储列中并行使能的目标存储单元的处理时间之间的差值小于阈值。
在并行使能的情况中，本实施例中进行数据处理所需的时间小于相关技术中进行数据处理所需的时间。参见图5，图5示出了相关技术中进行数据处理的过程。在相关技术中，存储介质每接收到控制器发送的一个处理指令，则对一个存储单元进行使能及数据处理。在完成对一个存储单元的使能及数据处理之后，等待接收控制器的下一个处理指令，按照下一个处理指令对下一个存储单元进行使能及数据处理。以一个存储单元的长度为16B为例，如果按照相关技术对64B长度的数据进行处理，则控制器需要发送4个处理指令。在此基础上，将存储介质完成一个存储单元的使能及数据处理所需的时间记为P，将存储介质等待指令所 需的时间记为Q，由图5可知，按照相关技术处理64B长度的数据所需的总时间为4P+3Q。
而在本实施例中，参见图6，存储介质每接收控制器发送的一个并发处理指令，可以对至少两个目标存储单元进行数据处理，减少了控制器需要发送的处理指令的数量，且存储介质无需等待接收其他的处理指令。并且，由于对各个目标存储单元的使能过程是并行的，因而各个目标存储单元的数据处理过程是同步进行的。在同样的时长中，相关技术仅能完成对一个存储单元的数据处理，而本实施例中可以完成至少两个目标存储单元的数据处理，从而缩短了数据处理所需的时间。如图6所示，仍将完成一个存储单元的使能及数据处理所需的时间记为P，则按照本实施例提供的方法进行64B长度的数据处理，控制器仅需发送一个处理指令，且处理64B长度的数据所需的总时间为P，相比于相关技术减少了(3P+3Q)的时间。
当然，本实施例提供的方法不仅局限于并行使能的情况。示例性地，对于任一分组而言，本实施例也可以根据实际需求对该分组中的目标存储单元进行串行使能。串行使能与并行使能的区别在于，并行使能是对同一分组内的各个目标存储单元进行同步使能，而串行使能是对同一分组内的各个目标存储单元进行依次使能。举例对串行使能的过程进行说明：在按照存储行进行分组、目标存储单元包括第0行中的存储单元0-2的情况下，将一个存储单元进行使能和数据处理的过程所需要的时间记为T，将指令解码器开始发送指令的时刻记为0，则在0时刻指令解码器指示行地址解码器使能第0行、指示列地址解码器使能第0列，从而使得第0行中的存储单元0被使能。在T时刻，指令解码器指示行地址解码器使能第0行、指示列地址解码器使能第1列，从而使得第0行中的存储单元1被使能。在2T时刻，指令解码器指示行地址解码器使能第0行、指示列地址解码器使能第2列，从而使得第0行中的存储单元2被使能。在3T时刻，认为基于第0行中的存储单元0-2的数据处理过程已完成，从而结束数据处理过程。
另外，基于以上说明可知，第一信息能够用于指示多种处理方式。在第一信息指示的处理方式不同的情况下，存储介质的指令解码器按照第一信息指示的处理方式完成数据处理的过程也不同，参见如下的情况C1和情况C2。
情况C1，第一信息指示的处理方式包括第一处理方式，第一处理方式包括将数据存储于存储单元的处理方式。示例性地，第一处理方式包括但不限于写入和覆盖。存储介质的指令解码器还需要获取数据，以便于按照第一处理方式进行数据存储。因此，本实施例提供的方法还包括：控制器发送数据。示例性地，控制器发送的数据为控制器从处理器接收到的数据。相应地，存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理，包括：按照第一处理方式将控制器发送的数据存储于至少两个目标存储单元中。示例性地，控制器在向存储介质的指令解码器发送第一处理指令之后，继续向存储介质的指令解码器发送数据，从而由指令解码器将数据存储于目标存储单元中。或者，控制器在向存储介质的指令解码器发送第一处理指令之后，向存储介质中的数据处理单元发送数据，指令解码器在确定目标存储单元使能之后，控制数据处理单元将数据存储于目标存储单元中。
情况C2，第一信息指示的处理方式包括第二处理方式，第二处理方式包括基于已存储数据的存储单元进行数据处理的方式。示例性地，第二处理方式包括但不限于读取和擦除。存储介质的指令解码器基于至少两个目标存储单元，按照第一信息指示的处理方式进行数据处理，包括：存储介质的指令解码器按照第二处理方式，对至少两个目标存储单元中已存储的数据进行处理。
在示例性实施例中，在存储介质的指令解码器按照第二处理方式对至少两个目标存储单元中已存储的数据进行处理之后，方法还包括：存储介质的指令解码器按照至少两个目标存储单元的地址顺序，向控制器发送至少两个目标存储单元中已存储的数据。相应地，控制器还接收存储介质的指令解码器发送的至少两个目标存储单元中已存储的数据。示例性地，存储介质的指令解码器通过多次发送过程实现数据的发送，每次发送过程所发送的数据长度基于IO接口的位宽来确定，也就是说每次发送过程所发送的数据长度不大于IO接口的位宽。因此，存储介质的指令解码器首先按照IO接口的位宽将首个目标存储单元中已存储的数据划分为多个部分，按照地址由先到后的顺序向控制器分别发送各个部分。在首个目标存储单元 中的各个部分均发送完毕之后，按照相同的方式对第二个目标存储单元中已存储的数据进行划分及发送。以此类推，直至各个目标存储单元中已存储的数据均发送完毕为止。
例如，目标存储单元的数量为两个、长度为16B，IO接口的位宽为1B，则首先将首个目标存储单元中已存储的数据划分成长度为1B的16个部分，按照地址由先到后的顺序依次发送首个目标存储单元中的第1个部分、第2个部分、……、第16个部分，从而通过16次发送过程将首个目标存储单元中已存储的数据发送至控制器。之后，将第二个目标存储单元中已存储的数据也划分成长度为1B的16个部分，通过16次发送过程将第二个目标存储单元中已存储的数据发送至控制器。
以上，说明了本申请实施例提供的处理数据的方法。接下来，以存储单元的长度为16B、处理方式为读取为例，通过如下的三个示例对本申请实施例提供的数据处理方式的应用过程进行说明。
示例一，参见图7，图7示出了对64B的数据进行读取的过程。其中，存储介质的指令解码器控制行地址解码器和对应的MUX使能第0行，控制列地址解码器和对应的MUX使能第0-3列，从而使得第0行中的存储单元0-3被使能。之后，读取第0行中存储单元0-3中存储的数据，共读取64B的数据。
示例二，参见图8，图8示出了对256B的数据进行读取的过程。其中，存储介质的指令解码器控制行地址解码器和对应的MUX使能第0行，控制列地址解码器和对应的MUX使能第0-15列，从而使得第0行中的存储单元0-15被使能。之后，读取第0行中的存储单元0-15中存储的数据，共读取256B的数据。
示例三，参见图9，图9示出了对4KB(即4096B)的数据进行读取的过程。其中，存储介质的指令解码器控制行地址解码器和对应的MUX使能第0行，控制列地址解码器和对应的MUX使能第0-15列，从而使能第0行中的存储单元0-15，读取256B的数据。之后，存储介质的指令解码器控制行地址解码器和对应的MUX使能第1行，控制列地址解码器和对应的MUX使能第0-15列，从而使能第1行中的存储单元0-15，继续读取256B的数据。以此类推，直至存储介质的指令解码器控制行地址解码器和对应的MUX使能第15行，控制列地址解码器和对应的MUX使能第0-15列，从而使得第15行中的存储单元0-15被使能，读取256B的数据。由此，共读取16行中4KB的数据。
综上所述，控制器仅需发送一个处理指令，便能够使得存储介质的指令解码器基于至少两个存储单元进行连续的数据处理。相比于每个处理指令仅能指示指令解码器基于一个存储单元进行数据处理的情况，本实施例提供的数据处理方式能够减少控制器需要发送的处理指令的数量。不仅降低了数据处理过程中控制器需要消耗的处理资源、避免了资源浪费，而且提高了数据处理的效率。
应理解的是，上述处理器可以是中央处理器(Central Processing Unit，CPU)，还可以是其他通用处理器、数字信号处理器(digital signal processing，DSP)、专用集成电路(application specific integrated circuit，ASIC)、现场可编程门阵列(field－programmable gate array，FPGA)或者其他可编程逻辑器件、分立门或者晶体管逻辑器件、分立硬件组件等。通用处理器可以是微处理器或者是任何常规的处理器等。值得说明的是，处理器可以是支持进阶精简指令集机器(advanced RISC machines，ARM)架构的处理器。
进一步地，在一种可选的实施例中，上述存储介质可以包括只读存储介质和随机存取存储介质，并向处理器提供指令和数据。存储介质还可以包括非易失性随机存取存储介质。例如，存储介质还可以存储设备类型的信息。
该存储介质可以是易失性存储介质或非易失性存储介质，或可包括易失性和非易失性存储介质两者。其中，非易失性存储介质可以是相变存储器(phase change memory，PCM)、只读存储介质(read-only memory，ROM)、可编程只读存储介质(programmable ROM，PROM)、可擦除可编程只读存储介质(erasable PROM，EPROM)、电可擦除可编程只读存储介质(electrically EPROM，EEPROM)或闪存。易失性存储介质可以是随机存取存储介质(random  access memory，RAM)，其用作外部高速缓存。通过示例性但不是限制性说明，许多形式的RAM可用。例如，静态随机存取存储介质(static RAM，SRAM)、动态随机存取存储介质(dynamic random access memory，DRAM)、同步动态随机存取存储介质(synchronous DRAM，SDRAM)、双倍数据速率同步动态随机存取存储介质(double data date SDRAM，DDR SDRAM)、增强型同步动态随机存取存储介质(enhanced SDRAM，ESDRAM)、同步连接动态随机存取存储介质(synchlink DRAM，SLDRAM)和直接内存总线随机存取存储介质(direct rambus RAM，DR RAM)。
在上述实施例中，可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。所述计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行所述计算机程序指令时，全部或部分地产生按照本申请所述的流程或功能。所述计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。所述计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，所述计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线)或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。所述计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。所述可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk)等。
以上所述仅为本申请的实施例，并不用以限制本申请，凡在本申请的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本申请的保护范围之内。

Claims (19)

  1. 一种存储装置，其特征在于，所述存储装置包括控制器和存储介质，所述存储介质包括指令解码器和多个存储单元，所述控制器和所述存储介质的指令解码器连接；
    所述控制器，用于向所述存储介质的指令解码器发送第一处理指令，所述第一处理指令包括第一信息和第二信息，所述第一信息用于指示处理方式，所述第二信息用于指示需要处理的数据的数据长度；
    所述存储介质的指令解码器，用于接收所述控制器发送的第一处理指令，基于所述第二信息指示的数据长度，从所述存储介质的多个存储单元中确定至少两个目标存储单元，基于所述至少两个目标存储单元，按照所述第一信息指示的处理方式进行数据处理。
  2. 根据权利要求1所述的存储装置，其特征在于，所述存储介质的多个存储单元位于至少一个存储行中，所述存储介质的指令解码器，用于确定需要处理的数据的起始地址，基于所述第二信息、所述多个存储单元的长度、所述至少一个存储行的长度和所述需要处理的数据的起始地址，从所述存储介质的多个存储单元中确定所述至少两个目标存储单元。
  3. 根据权利要求2所述的存储装置，其特征在于，所述第一处理指令还包括第三信息，所述第三信息用于指示地址，所述存储介质的指令解码器，用于将所述第三信息指示的地址确定为所述需要处理的数据的起始地址，所述至少两个目标存储单元的地址连续。
  4. 根据权利要求2所述的存储装置，其特征在于，所述存储介质的指令解码器，用于基于所述存储介质的多个存储单元确定所述需要处理的数据的起始地址，所述至少两个目标存储单元的地址连续或者不连续；
    所述存储介质的指令解码器，还用于封装所述第一处理指令的指令标识和所述至少两个目标存储单元的地址，得到响应消息，向所述控制器发送所述响应消息；
    所述控制器，还用于接收所述响应消息。
  5. 根据权利要求1-4任一所述的存储装置，其特征在于，所述第一信息指示的处理方式包括第一处理方式，所述第一处理方式包括将数据存储于存储单元的处理方式，所述控制器，还用于发送数据；
    所述存储介质的指令解码器，用于按照所述第一处理方式，将所述控制器发送的数据存储于所述至少两个目标存储单元中。
  6. 根据权利要求1-4任一所述的存储装置，其特征在于，所述第一信息指示的处理方式包括第二处理方式，所述第二处理方式包括基于已存储数据的存储单元进行数据处理的方式，所述存储介质的指令解码器，用于按照所述第二处理方式，对所述至少两个目标存储单元中已存储的数据进行处理。
  7. 根据权利要求6所述的存储装置，其特征在于，所述存储介质的指令解码器，还用于按照所述至少两个目标存储单元的地址顺序，向所述控制器发送所述至少两个目标存储单元中已存储的数据；
    所述控制器，还用于接收所述存储介质的指令解码器发送的所述至少两个目标存储单元中已存储的数据。
  8. 根据权利要求1-4任一所述的存储装置，其特征在于，所述第一处理指令中还包括第四信息，所述第四信息用于指示数据分组要求，所述数据分组要求包括以存储行为单位对所 述至少两个目标存储单元进行分组，或者以存储列为单位对所述至少两个目标存储单元进行分组，所述存储介质的指令解码器，用于按照所述第四信息指示的数据分组要求对所述至少两个目标存储单元进行分组，得到至少一个分组，基于各个分组中的目标存储单元，按照所述第一信息指示的处理方式进行数据处理。
  9. 根据权利要求8所述的存储装置，其特征在于，所述存储介质的指令解码器，用于对于任一分组，并行使能所述任一分组中的目标存储单元，按照所述第一信息指示的处理方式对所述任一分组中并行使能的目标存储单元进行数据处理，使得所述任一分组中并行使能的目标存储单元的处理时间之间的差值小于阈值。
  10. 根据权利要求1-9任一所述的存储装置，其特征在于，所述至少两个目标存储单元位于同一逻辑单元号中，所述目标存储单元为进行数据处理的最小单元。
  11. 根据权利要求1-10任一所述的存储装置，其特征在于，所述存储介质的指令解码器，还用于解析所述第一处理指令，得到所述第一信息和所述第二信息。
  12. 根据权利要求1-11任一所述的存储装置，其特征在于，所述至少两个目标存储单元的长度之和不小于所述第二信息指示的数据长度。
  13. 根据权利要求1-12任一所述的存储装置，其特征在于，所述存储介质的数量为多个，所述控制器用于接收存储介质标识，向所述存储介质标识指示的存储介质的指令解码器发送所述第一处理指令。
  14. 一种处理数据的方法，其特征在于，所述方法应用于存储装置，所述存储装置包括控制器和存储介质，所述存储介质包括指令解码器和多个存储单元，所述方法包括：
    所述存储介质的指令解码器接收所述控制器发送的第一处理指令，所述第一处理指令包括第一信息和第二信息，所述第一信息用于指示处理方式，所述第二信息用于指示需要处理的数据的数据长度；
    所述存储介质的指令解码器基于所述第二信息指示的数据长度，从所述存储介质的多个存储单元中确定至少两个目标存储单元；
    所述存储介质的指令解码器基于所述至少两个目标存储单元，按照所述第一信息指示的处理方式进行数据处理。
  15. 根据权利要求14所述的方法，其特征在于，所述存储介质的多个存储单元位于至少一个存储行中，所述存储介质的指令解码器基于所述第二信息指示的数据长度，从所述存储介质的多个存储单元中确定至少两个目标存储单元，包括：
    所述存储介质的指令解码器确定需要处理的数据的起始地址；
    所述存储介质的指令解码器基于所述第二信息、所述多个存储单元的长度、所述至少一个存储行的长度和所述需要处理的数据的起始地址，从所述存储介质的多个存储单元中确定所述至少两个目标存储单元。
  16. 根据权利要求15所述的方法，其特征在于，所述第一处理指令还包括第三信息，所述第三信息用于指示地址，所述存储介质的指令解码器确定需要处理的数据的起始地址，包括：
    所述存储介质的指令解码器将所述第三信息指示的地址确定为所述需要处理的数据的起始地址，所述至少两个目标存储单元的地址连续。
  17. 根据权利要求14-16任一所述的方法，其特征在于，所述第一处理指令中还包括第四信息，所述第四信息用于指示数据分组要求，所述数据分组要求包括以存储行为单位对所述至少两个目标存储单元进行分组，或者以存储列为单位对所述至少两个目标存储单元进行分组，所述存储介质的指令解码器基于所述至少两个目标存储单元，按照所述第一信息指示的处理方式进行数据处理，包括：
    所述存储介质的指令解码器按照所述第四信息指示的数据分组要求对所述至少两个目标存储单元进行分组，得到至少一个分组；
    所述存储介质的指令解码器基于各个分组中的目标存储单元，按照所述第一信息指示的处理方式进行数据处理。
  18. 根据权利要求17所述的方法，其特征在于，所述存储介质的指令解码器基于各个分组中的目标存储单元，按照所述第一信息指示的处理方式进行数据处理，包括：
    所述存储介质的指令解码器对于任一分组，并行使能所述任一分组中的目标存储单元；
    所述存储介质的指令解码器按照所述第一信息指示的处理方式对所述任一分组中并行使能的目标存储单元进行数据处理，使得所述任一分组中并行使能的目标存储单元的处理时间之间的差值小于阈值。
  19. 一种处理数据的方法，其特征在于，所述方法应用于存储装置，所述存储装置包括控制器和存储介质，所述存储介质包括指令解码器和多个存储单元，所述方法包括：
    所述控制器确定第一信息和第二信息，所述第一信息用于指示处理方式，所述第二信息用于指示需要处理的数据的数据长度，所述数据长度用于从所述存储介质的多个存储单元中确定至少两个目标存储单元，所述至少两个目标存储单元用于数据处理；
    所述控制器封装所述第一信息和所述第二信息，得到第一处理指令；
    所述控制器向所述存储介质的指令解码器发送所述第一处理指令。
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080022163A1 (en) * 2006-06-28 2008-01-24 Hitachi, Ltd. Storage system and data protection method therefor
CN101930798A (zh) * 2009-06-25 2010-12-29 联发科技股份有限公司 闪存装置、存储器装置以及控制闪存装置的方法
CN105934793A (zh) * 2014-12-27 2016-09-07 华为技术有限公司 一种存储系统数据分发的方法、分发装置与存储系统
CN111341367A (zh) * 2018-12-18 2020-06-26 深圳市江波龙电子股份有限公司 一种存储设备的控制方法及存储设备、电子设备
CN111370047A (zh) * 2018-12-25 2020-07-03 东芝存储器株式会社 存储装置
CN112115078A (zh) * 2019-06-19 2020-12-22 铠侠股份有限公司 存储系统、存储控制器及半导体存储装置

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10073786B2 (en) * 2015-05-28 2018-09-11 Micron Technology, Inc. Apparatuses and methods for compute enabled cache

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080022163A1 (en) * 2006-06-28 2008-01-24 Hitachi, Ltd. Storage system and data protection method therefor
CN101930798A (zh) * 2009-06-25 2010-12-29 联发科技股份有限公司 闪存装置、存储器装置以及控制闪存装置的方法
CN105934793A (zh) * 2014-12-27 2016-09-07 华为技术有限公司 一种存储系统数据分发的方法、分发装置与存储系统
CN111341367A (zh) * 2018-12-18 2020-06-26 深圳市江波龙电子股份有限公司 一种存储设备的控制方法及存储设备、电子设备
CN111370047A (zh) * 2018-12-25 2020-07-03 东芝存储器株式会社 存储装置
CN112115078A (zh) * 2019-06-19 2020-12-22 铠侠股份有限公司 存储系统、存储控制器及半导体存储装置

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP4293672A4

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