WO2022210615A1 - Dispositif à semi-conducteur - Google Patents

Dispositif à semi-conducteur Download PDF

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Publication number
WO2022210615A1
WO2022210615A1 PCT/JP2022/015217 JP2022015217W WO2022210615A1 WO 2022210615 A1 WO2022210615 A1 WO 2022210615A1 JP 2022015217 W JP2022015217 W JP 2022015217W WO 2022210615 A1 WO2022210615 A1 WO 2022210615A1
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semiconductor layer
type semiconductor
semiconductor device
layer
present
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PCT/JP2022/015217
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Japanese (ja)
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慎平 松田
安史 樋口
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株式会社Flosfia
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/24—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only semiconductor materials not provided for in groups H01L29/16, H01L29/18, H01L29/20, H01L29/22
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Definitions

  • the present invention relates to a semiconductor device useful as a power device or the like.
  • Gallium oxide (Ga 2 O 3 ) is a transparent semiconductor that has a wide bandgap of 4.8-5.3 eV at room temperature and hardly absorbs visible and ultraviolet light. It is therefore a particularly promising material for use in opto - electronic devices and transparent electronics operating in the deep UV region.
  • LEDs Light-emitting diodes
  • transistors have been developed (see Non-Patent Document 1). According to Patent Document 4, the gallium oxide can control the bandgap by forming a mixed crystal of indium and aluminum, respectively or in combination, and constitutes an extremely attractive material system as an InAlGaO-based semiconductor. .
  • Gallium oxide (Ga 2 O 3 ) has five crystal structures ⁇ , ⁇ , ⁇ , ⁇ , and ⁇ , and generally the most stable structure is ⁇ -Ga 2 O 3 .
  • ⁇ -Ga 2 O 3 has a ⁇ -Gallic structure, it is not necessarily suitable for use in semiconductor devices, unlike crystal systems generally used in electronic materials and the like.
  • the growth of the ⁇ -Ga 2 O 3 thin film requires a high substrate temperature and a high degree of vacuum, there is also the problem of increased manufacturing costs.
  • ⁇ -Ga 2 O 3 even a high concentration (for example, 1 ⁇ 10 19 /cm 3 or more) of dopant (Si) is 800% after ion implantation. C. to 1100.degree. C., it could not be used as a donor without annealing.
  • ⁇ -Ga 2 O 3 has the same crystal structure as the sapphire substrate that has already been widely used, so it is suitable for use in optoelectronic devices, and has a wider band than ⁇ -Ga 2 O 3 . Since it has a gap, it is particularly useful for power devices. Therefore, semiconductor devices using ⁇ -Ga 2 O 3 as a semiconductor are eagerly awaited.
  • Patent Documents 1 and 2 ⁇ -Ga 2 O 3 is used as a semiconductor, and as an electrode capable of obtaining ohmic characteristics suitable for this, two layers consisting of a Ti layer and an Au layer, a Ti layer, an Al layer and an Au layer are disclosed. A semiconductor device using three layers, or four layers consisting of a Ti layer, an Al layer, a Ni layer and an Au layer is described. Further, Patent Document 3 discloses a semiconductor using ⁇ -Ga 2 O 3 as a semiconductor and using either Au, Pt, or a laminate of Ni and Au as an electrode capable of obtaining Schottky characteristics suitable for the semiconductor. A device is described.
  • An object of the present invention is to provide a semiconductor device with reduced device resistance.
  • the present inventors have found a semiconductor element comprising an oxide semiconductor layer including at least a source region and a source electrode disposed on the source region, wherein the source A semiconductor device in which a region includes at least an n + -type semiconductor layer and an n++ -type semiconductor layer disposed on the n + -type semiconductor layer and having a higher carrier density than the n + -type semiconductor layer does not include the n++ -type semiconductor layer.
  • the inventors have found that the element resistance is reduced, and have found that the semiconductor device thus obtained can solve the above-described conventional problems.
  • the inventors of the present invention completed the present invention through further studies.
  • a semiconductor device comprising an oxide semiconductor layer including at least a source region, and a source electrode arranged on the source region, wherein the source region comprises an n + -type semiconductor layer and on the n + -type semiconductor layer
  • a semiconductor device comprising at least an n++-type semiconductor layer disposed in the region of the n+-type semiconductor layer and having a carrier density higher than that of the n+-type semiconductor layer.
  • [3] The semiconductor device according to [1] or [2], wherein the n + -type semiconductor layer and the n++ -type semiconductor layer have the same main component.
  • [4] The semiconductor device according to any one of [1] to [3], wherein the n++ type semiconductor layer is an epitaxial layer.
  • [5] The semiconductor device according to [4], wherein the n++ type semiconductor layer is epitaxially doped.
  • [6] The semiconductor device according to any one of [1] to [5], wherein the n++ type semiconductor layer has a carrier density of 1.0 ⁇ 10 19 /cm 3 or more.
  • n + -type semiconductor layer has a carrier density in the range of 1.0 ⁇ 10 17 /cm 3 or more and less than 1.0 ⁇ 10 19 /cm 3 .
  • [8] The semiconductor device according to any one of [1] to [7], wherein the n++ type semiconductor layer has a thickness in the range of 1 nm to 1 ⁇ m.
  • [9] The semiconductor device according to any one of [1] to [8], wherein the thickness of the n + -type semiconductor layer is greater than the thickness of the n++ -type semiconductor layer.
  • a semiconductor device with reduced element resistance can be provided.
  • FIG. 1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention
  • FIG. 1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention
  • FIG. 1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention
  • FIG. 1 schematically illustrates a preferred manufacturing process for a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the present invention
  • FIG. FIG. 4 is a diagram showing results of IV measurement in Examples.
  • FIG. 10 is a diagram showing results of IV measurement in a comparative example
  • 1 is a configuration diagram of a mist CVD apparatus used in an embodiment of the present invention
  • FIG. 1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. 1 is a block configuration diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. 1 is a circuit diagram showing an example of a control system employing a semiconductor device according to an embodiment of the invention
  • FIG. FIG. 4 is a diagram showing simulation results in an embodiment of the present invention
  • 1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention
  • FIG. 1 schematically illustrates a metal oxide semiconductor field effect transistor (MOSFET) according to an embodiment of the invention
  • a semiconductor device of the present invention is a semiconductor element comprising an oxide semiconductor layer including at least a source region, and a source electrode disposed on the source region, wherein the source region comprises at least an n + -type semiconductor layer and the It is characterized by including an n++ type semiconductor layer disposed on the n+ type semiconductor layer and having a higher carrier density than the n+ type semiconductor layer.
  • the oxide semiconductor layer is not particularly limited as long as it does not hinder the object of the present invention.
  • the semiconductor layer preferably contains a crystalline oxide semiconductor as a main component.
  • the crystalline oxide semiconductor include metal oxides containing one or more metals selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. can give.
  • the crystalline oxide semiconductor preferably contains at least one metal selected from aluminum, indium and gallium, more preferably at least gallium, and ⁇ -Ga 2 O 3 or mixed crystals thereof are most preferred.
  • the crystal structure of the oxide semiconductor layer is also not particularly limited as long as it does not hinder the object of the present invention.
  • the crystal structure of the oxide semiconductor layer includes, for example, a corundum structure, a ⁇ -gallia structure, a hexagonal structure (eg, ⁇ -type structure, etc.), a cubic crystal structure (eg, ⁇ -type structure, etc.), a cubic crystal structure, or a tetragonal structure. crystal structure and the like.
  • the crystalline oxide semiconductor preferably has a corundum structure, a ⁇ -gallia structure or a hexagonal crystal structure (eg, ⁇ -type structure, etc.), and more preferably has a corundum structure.
  • the “main component” means that the crystalline oxide semiconductor accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 90%, in atomic ratio, of all components of the oxide semiconductor layer. % or more, and may be 100%.
  • the thickness of the oxide semiconductor layer is not particularly limited, and may be 1 ⁇ m or less or 1 ⁇ m or more, but in the embodiment of the present invention, it is preferably 10 ⁇ m or more. .
  • the surface area of the semiconductor film is not particularly limited .
  • the semiconductor layer is usually single crystal, but may be polycrystal.
  • the oxide semiconductor layer usually includes two or more semiconductor layers.
  • the oxide semiconductor layer includes, for example, an n + type semiconductor layer, an n ⁇ type semiconductor layer (drift layer), a p type semiconductor layer (current blocking layer), an n ⁇ type semiconductor layer (channel layer), and an n + type semiconductor layer as a source region. type semiconductor layer as well as an n++ type semiconductor layer. Further, the carrier density of the oxide semiconductor layer can be appropriately set by adjusting the doping amount.
  • the oxide semiconductor layer preferably contains a dopant.
  • the dopant is not particularly limited and may be a known one.
  • suitable examples of the dopant include tin, germanium, silicon, titanium, zirconium and vanadium.
  • an n-type dopant such as niobium, or a p-type dopant such as magnesium, calcium, zinc, or the like can be used.
  • the n-type dopant is preferably at least one selected from Sn, Ge and Si.
  • the content of the dopant is preferably 0.00001 atomic % or more, more preferably 0.00001 atomic % to 20 atomic %, and more preferably 0.00001 atomic % to 10 atomic % in the composition of the semiconductor layer. is most preferred. More specifically, the dopant concentration may typically be about 1 ⁇ 10 16 /cm 3 to 1 ⁇ 10 22 /cm 3 , and the dopant concentration may be, for example, about 1 ⁇ 10 17 /cm 3 . A low concentration of 3 or less may be used. Further, according to the present invention, the dopant may be contained at a high concentration of about 1 ⁇ 10 20 /cm 3 or higher. In the embodiment of the present invention, it is preferable to contain the carrier concentration of 1 ⁇ 10 17 /cm 3 or more.
  • the source region is not particularly limited as long as it includes at least an n + -type semiconductor layer and an n++ -type semiconductor layer disposed on the n + -type semiconductor layer and having a higher carrier density than the n + -type semiconductor layer.
  • the carrier density can be determined using a known method. Examples of methods for determining the carrier density include SIMS (secondary ion mass spectrometry), SCM (scanning capacitance microscopy), SMM (scanning microwave microscopy), and SRA (spreading resistance measurement). etc.
  • SIMS secondary ion mass spectrometry
  • SCM scanning capacitance microscopy
  • SMM scanning microwave microscopy
  • SRA scanning resistance measurement
  • the main component of the n + -type semiconductor layer and the main component of the n++ -type semiconductor layer are the same. Further, in the embodiment of the present invention, it is preferable that the n + type semiconductor layer and the n ++ type semiconductor layer have the same crystal structure, and the n + type semiconductor layer and the n ++ type semiconductor layer have a corundum structure. It is more preferable to have
  • the “main component” means, for example, when the main component of the n + type semiconductor layer is gallium oxide, the atomic ratio of gallium in all metal elements in the n + type semiconductor layer is 50% or more.
  • the atomic ratio of gallium in all metal elements in the n + -type semiconductor layer is preferably 70% or more, more preferably 90% or more, and may be 100%.
  • the n++ type semiconductor layer is preferably an epitaxial layer, and more preferably the n++ type semiconductor layer is epitaxially doped.
  • epitaxial doping means doping by epitaxial growth, not doping by ion implantation or the like.
  • the n-type dopant contained in the n + -type semiconductor layer and/or the n++-type semiconductor layer include at least one n-type dopant selected from tin, germanium, silicon, titanium, zirconium, vanadium and niobium. mentioned.
  • the n-type dopant is preferably at least one selected from Sn, Ge and Si.
  • the carrier density of the n++ type semiconductor layer is not particularly limited as long as it is higher than the carrier density of the n+ type semiconductor layer.
  • the n++ type semiconductor layer preferably has a carrier density of 1.0 ⁇ 10 19 /cm 3 or more, more preferably 6.0 ⁇ 10 19 /cm 3 or more. .
  • the carrier density of the n++ type semiconductor layer is not particularly limited. In an embodiment of the present invention, it is preferable that the carrier density of the n+ type semiconductor layer is in the range of 1.0 ⁇ 10 17 /cm 3 or more and less than 1.0 ⁇ 10 19 /cm 3 . By setting the carrier density of the n + -type semiconductor layer within the preferred range as described above, the source resistance can be reduced more satisfactorily.
  • the method of doping the n+ type semiconductor layer is not particularly limited, and may be diffusion, ion implantation, or epitaxial growth.
  • the mobility of the n+ type semiconductor layer is higher than the mobility of the n++ type semiconductor layer.
  • the thickness of the n++ type semiconductor layer is not particularly limited as long as the object of the present invention is not hindered.
  • the n++ type semiconductor layer preferably has a thickness in the range of 1 nm to 1 ⁇ m, more preferably in the range of 10 nm to 100 nm. In an embodiment of the present invention, the thickness of the n+ type semiconductor layer is preferably larger than the thickness of the n++ type semiconductor layer.
  • the source contact resistance and the source resistance in the semiconductor device can be satisfactorily reduced by using the above-described preferable combination of the n + -type semiconductor layer and the n++ -type semiconductor layer, the element resistance is further reduced.
  • a semiconductor device can be realized.
  • the oxide semiconductor layer may be formed using known means.
  • means for forming the semiconductor layer include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulse growth, and ALD.
  • the means for forming the semiconductor layer is preferably MOCVD, mist CVD, mist epitaxy or HVPE, preferably mist CVD or mist epitaxy.
  • the mist CVD method or mist epitaxy method for example, the mist CVD apparatus shown in FIG.
  • a semiconductor film containing a crystalline oxide semiconductor as a main component is formed on a substrate by transporting droplets onto a substrate with a carrier gas (transporting step) and then thermally reacting the atomized droplets in the vicinity of the substrate. (film formation step) to form the semiconductor layer.
  • the atomization step atomizes the raw material solution.
  • the means for atomizing the raw material solution is not particularly limited as long as it can atomize the raw material solution, and may be any known means.
  • atomizing means using ultrasonic waves is preferable.
  • Atomized droplets obtained using ultrasonic waves have an initial velocity of zero and are preferable because they float in the air. Since it is a possible mist, there is no damage due to collision energy, so it is very suitable.
  • the droplet size is not particularly limited, and may be droplets of several millimeters, preferably 50 ⁇ m or less, more preferably 100 nm to 10 ⁇ m.
  • the raw material solution is not particularly limited as long as it contains a raw material capable of being atomized or dropletized and capable of forming a semiconductor film, and may be an inorganic material or an organic material.
  • the raw material is preferably a metal or a metal compound, and one or two selected from aluminum, gallium, indium, iron, chromium, vanadium, titanium, rhodium, nickel, cobalt and iridium. More preferably, it contains more than one species of metal.
  • a solution in which the metal is dissolved or dispersed in an organic solvent or water in the form of a complex or salt can be preferably used.
  • forms of the complex include acetylacetonate complexes, carbonyl complexes, ammine complexes, hydride complexes, and the like.
  • the salt form include organic metal salts (e.g., metal acetates, metal oxalates, metal citrates, etc.), metal sulfide salts, metal nitrate salts, metal phosphate salts, metal halide salts (e.g., metal chlorides, salts, metal bromides, metal iodides, etc.).
  • hydrohalic acid examples include hydrobromic acid, hydrochloric acid, and hydroiodic acid. Among them, hydrobromic acid or Hydroiodic acid is preferred.
  • oxidizing agent examples include hydrogen peroxide (H 2 O 2 ), sodium peroxide (Na 2 O 2 ), barium peroxide (BaO 2 ), benzoyl peroxide (C 6 H 5 CO) 2 O 2 and the like. , hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, and organic peroxides such as peracetic acid and nitrobenzene.
  • the raw material solution may contain a dopant.
  • the dopant By including the dopant in the raw material solution, the doping can be performed well.
  • the dopant is not particularly limited as long as it does not interfere with the object of the present invention.
  • the dopant include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or Mg, H, Li, Na, K, Rb, Cs, Fr, Be, Ca, Sr, Ba , Ra, Mn, Fe, Co, Ni, Pd, Cu, Ag, Au, Zn, Cd, Hg, Ti, Pb, N or P, and the like.
  • the content of the dopant is appropriately set by using a calibration curve showing the relationship between the concentration of the dopant in the raw material and the desired carrier density.
  • the solvent of the raw material solution is not particularly limited, and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent.
  • the solvent preferably contains water, more preferably water or a mixed solvent of water and alcohol.
  • the atomized liquid droplets are transported into the film forming chamber using a carrier gas.
  • the carrier gas is not particularly limited as long as it does not interfere with the object of the present invention. Suitable examples include oxygen, ozone, inert gases such as nitrogen and argon, and reducing gases such as hydrogen gas and forming gas. mentioned.
  • one type of carrier gas may be used, two or more types may be used, and a diluted gas with a reduced flow rate (for example, a 10-fold diluted gas, etc.) may be further used as a second carrier gas. good too.
  • the carrier gas may be supplied at two or more locations instead of at one location.
  • the flow rate of the carrier gas is not particularly limited, it is preferably 0.01 to 20 L/min, more preferably 1 to 10 L/min.
  • the flow rate of diluent gas is preferably 0.001 to 2 L/min, more preferably 0.1 to 1 L/min.
  • the semiconductor film is formed on the substrate by thermally reacting the atomized droplets in the vicinity of the substrate.
  • the thermal reaction is not particularly limited as long as the atomized droplets react with heat, and the reaction conditions and the like are not particularly limited as long as they do not interfere with the object of the present invention.
  • the thermal reaction is usually carried out at a temperature equal to or higher than the evaporation temperature of the solvent, preferably at a temperature that is not too high (for example, 1000° C.), more preferably 650° C. or less, most preferably from 300° C. to 650° C. preferable.
  • the thermal reaction is carried out under vacuum, under a non-oxygen atmosphere (for example, under an inert gas atmosphere, etc.), under a reducing gas atmosphere, or under an oxygen atmosphere, as long as the object of the present invention is not hindered.
  • a non-oxygen atmosphere for example, under an inert gas atmosphere, etc.
  • a reducing gas atmosphere for example, under an inert gas atmosphere, etc.
  • an oxygen atmosphere for example, under an inert gas atmosphere, etc.
  • the reaction may be carried out under atmospheric pressure, increased pressure or reduced pressure, but is preferably carried out under atmospheric pressure in the embodiment of the present invention.
  • the film thickness can be set by adjusting the film formation time.
  • the substrate is not particularly limited as long as it can support the semiconductor film.
  • the material of the substrate is also not particularly limited as long as it does not interfere with the object of the present invention, and may be a known substrate, an organic compound, or an inorganic compound.
  • the shape of the substrate may be any shape, and is effective for all shapes. Cylindrical, helical, spherical, ring-shaped, etc. are mentioned, but in the embodiment of the present invention, the substrate is preferable.
  • the thickness of the substrate is not particularly limited in embodiments of the present invention.
  • the substrate is not particularly limited as long as it has a plate shape and serves as a support for the semiconductor film.
  • the substrate may be an insulator substrate, a semiconductor substrate, a metal substrate, or a conductive substrate.
  • a substrate with a membrane is also preferred.
  • the substrate for example, a base substrate containing a substrate material having a corundum structure as a main component, or a base substrate containing a substrate material having a ⁇ -gallia structure as a main component, a substrate material having a hexagonal crystal structure as a main component.
  • a base substrate etc. are mentioned.
  • the “main component” means that the substrate material having the specific crystal structure accounts for preferably 50% or more, more preferably 70% or more, and even more preferably 90%, in atomic ratio, of all components of the substrate material. % or more, and may be 100%.
  • the substrate material is not particularly limited as long as it does not interfere with the object of the present invention, and may be any known material.
  • the substrate material having the corundum structure for example, ⁇ -Al 2 O 3 (sapphire substrate) or ⁇ -Ga 2 O 3 are preferably mentioned, a-plane sapphire substrate, m-plane sapphire substrate, r-plane sapphire substrate , a c-plane sapphire substrate, an ⁇ -type gallium oxide substrate (a-plane, m-plane, or r-plane) and the like are more preferable examples.
  • the base substrate mainly composed of a substrate material having a ⁇ -Gallia structure is, for example, a ⁇ -Ga 2 O 3 substrate, or a substrate containing Ga 2 O 3 and Al 2 O 3 with more than 0 wt % of Al 2 O 3 and A mixed crystal substrate having a content of 60 wt % or less may be used.
  • Examples of base substrates mainly composed of a substrate material having a hexagonal crystal structure include SiC substrates, ZnO substrates, and GaN substrates.
  • annealing may be performed after the film formation process.
  • Annealing treatment temperature is not particularly limited as long as the object of the present invention is not impaired, and is usually 300°C to 650°C, preferably 350°C to 550°C.
  • the annealing treatment time is usually 1 minute to 48 hours, preferably 10 minutes to 24 hours, more preferably 30 minutes to 12 hours.
  • the annealing treatment may be performed under any atmosphere as long as the object of the present invention is not hindered.
  • a non-oxygen atmosphere or an oxygen atmosphere may be used.
  • the non-oxygen atmosphere includes, for example, an inert gas atmosphere (e.g., nitrogen atmosphere), a reducing gas atmosphere, etc. In the embodiment of the present invention, an inert gas atmosphere is preferable, and a nitrogen atmosphere Lower is more preferred.
  • the semiconductor film may be directly provided on the substrate, or other layers such as a stress relaxation layer (for example, a buffer layer, an ELO layer, etc.), a peeling sacrificial layer, etc. may be formed on the substrate.
  • the semiconductor film may be provided via the semiconductor film.
  • the means for forming each layer is not particularly limited, and known means may be used. In the embodiment of the present invention, the mist CVD method is preferred.
  • the semiconductor film may be used as the semiconductor layer in the semiconductor device after using known means such as peeling from the substrate or the like, or may be used as the semiconductor layer in the semiconductor device as it is. may be used.
  • the source electrode is not particularly limited as long as it has conductivity, as long as it does not hinder the object of the present invention.
  • the constituent material of the source electrode may be a conductive inorganic material or a conductive organic material.
  • the material of the source electrode is preferably metal.
  • Suitable examples of the metal include at least one metal selected from Groups 4 to 10 of the periodic table. Examples of metals belonging to Group 4 of the periodic table include titanium (Ti), zirconium (Zr), hafnium (Hf), and the like. Examples of metals belonging to Group 5 of the periodic table include vanadium (V), niobium (Nb), and tantalum (Ta).
  • Examples of Group 6 metals of the periodic table include chromium (Cr), molybdenum (Mo), and tungsten (W).
  • Examples of metals of Group 7 of the periodic table include manganese (Mn), technetium (Tc), and rhenium (Re).
  • Examples of metals belonging to Group 8 of the periodic table include iron (Fe), ruthenium (Ru), and osmium (Os).
  • Examples of metals belonging to Group 9 of the periodic table include cobalt (Co), rhodium (Rh), and iridium (Ir).
  • Examples of metals of Group 10 of the periodic table include nickel (Ni), palladium (Pd), and platinum (Pt).
  • the source electrode preferably contains at least one metal selected from titanium (Ti), tantalum (Ta) and tungsten (W).
  • the source electrode may contain a conductive metal oxide.
  • the conductive metal oxide contained in the source electrode include metal oxide conductive films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO).
  • the source electrode may be composed of a single layer, or may include a plurality of metal layers. If the source electrode comprises a plurality of metal layers, for example using Group 4 metals for the first and third layers, a metal layer located between the first and third layers.
  • a method for forming the source electrode is not particularly limited. Specific examples of the method for forming the source electrode include a dry method and a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD. Wet methods include, for example, screen printing and die coating.
  • the oxide semiconductor layer further includes a channel layer, and a gate electrode is arranged on the channel layer with the gate insulating film interposed therebetween.
  • the constituent material of the channel layer may be the same as the constituent material of the oxide semiconductor layer described above.
  • the conductivity type of the channel layer is not particularly limited, and may be n-type or p-type. When the conductivity type of the channel layer is the n-type, preferable examples of the constituent material of the channel layer include ⁇ -Ga 2 O 3 and mixed crystals thereof.
  • the constituent material of the channel layer is preferably, for example, ⁇ -Ga 2 O 3 containing a p-type dopant or a mixed crystal thereof.
  • Metal oxides containing at least one metal selected from Group 9 eg, ⁇ -Ir 2 O 3 , ⁇ -Cr 2 O 3 , ⁇ -Rh 2 O 3 ), and the like.
  • the metal oxide containing at least one metal selected from Group 9 of the periodic table may be a mixed crystal with other metal oxide such as Ga 2 O 3 .
  • a constituent material of the gate insulating film is not particularly limited, and may be a known material.
  • materials for the gate insulating film include SiO 2 film, polysilicon film, phosphorus-added SiO 2 film (PSG film), boron-added SiO 2 film, phosphorus-boron-added SiO 2 film (BPSG film), and the like.
  • methods for forming the gate insulating film include CVD, atmospheric pressure CVD, plasma CVD, mist CVD, and the like. In an embodiment of the present invention, the method for forming the gate insulating film is preferably mist CVD or atmospheric pressure CVD.
  • the constituent material of the gate electrode is not particularly limited, and may be a known electrode material.
  • Examples of the constituent material of the gate electrode include the constituent materials of the source electrode described above.
  • a method for forming the gate electrode is not particularly limited. Specific examples of the method for forming the gate electrode include a dry method and a wet method. Dry methods include, for example, sputtering, vacuum deposition, and CVD. Wet methods include, for example, screen printing and die coating. In the embodiment of the present invention, it is preferable that the lower end of the n++ layer is positioned higher than the lower end of the gate insulating film, since the device resistance of the semiconductor device can be reduced more satisfactorily. .
  • the distance from the outer edge of the gate insulating film to the inner edge of the n + -type semiconductor layer is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less. With such a preferable configuration, the source resistance can be further reduced.
  • the semiconductor device of the present invention is useful for various semiconductor elements, especially for power devices.
  • the semiconductor element includes a horizontal element (horizontal device) in which an electrode is formed on one side of a semiconductor layer and current flows in a direction perpendicular to the film thickness direction of the semiconductor layer (horizontal device), and electrodes are formed on both front and back sides of the semiconductor layer.
  • a horizontal element horizontal device
  • vertical device vertical device
  • the semiconductor device is suitable for both horizontal and vertical devices.
  • it is preferably used for a vertical device.
  • the semiconductor device examples include metal semiconductor field effect transistors (MESFET), high electron mobility transistors (HEMT), metal oxide semiconductor field effect transistors (MOSFET), static induction transistors (SIT), junction field effect transistors ( JFET) or an insulated gate bipolar transistor (IGBT).
  • the semiconductor device is preferably MOSFET, SIT, JFET or IGBT, more preferably MOSFET or IGBT.
  • FIG. 1 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET) which is one of the preferred embodiments of the present invention.
  • the MOSFET of FIG. 1 includes a drain electrode 5c, an n+ type semiconductor layer 3, an n ⁇ type semiconductor layer 7 as a drift layer, a p type semiconductor layer 2 as a current blocking layer, a channel layer 6, and an n+ type semiconductor layer as a source region. and an n++ type semiconductor layer 1b, a gate insulating film 4, a gate electrode 5a and a source electrode 5b.
  • the n++ type semiconductor layer 1b is an epitaxial layer, and is formed by epitaxial growth on the n+ type semiconductor layer 1a.
  • the n+ type semiconductor layer 3, the n ⁇ type semiconductor layer 7, the channel layer 6, the p type semiconductor layer 2, the n+ type semiconductor layer 1a and the n++ type semiconductor layer 1b constitute an oxide semiconductor layer 8.
  • the carrier density of the n+ type semiconductor layer 1a is in the range of 1.0 ⁇ 10 18 /cm 3 or more and less than 1.0 ⁇ 10 19 /cm 3 .
  • the carrier density of the n++ type semiconductor layer 1b is 1.0 ⁇ 10 19 /cm 3 or more, preferably in the range of 1.0 ⁇ 10 19 /cm 3 to 1.0 ⁇ 10 20 /cm 3 . is within.
  • the p-type semiconductor layer 2 may be a high resistance layer (for example, a resistivity of 1.0 ⁇ 10 10 ⁇ cm or more).
  • a high resistance layer for example, a resistivity of 1.0 ⁇ 10 10 ⁇ cm or more.
  • an epitaxial layer obtained by epitaxially doping the n++ type semiconductor layer 1b is used as the source region 1, so that a high concentration (for example, 1.0 ⁇ 10 19 /cm 3 or more) n++ type A semiconductor layer 1b can be realized. Therefore, the source contact resistance can be reduced even when a material such as gallium oxide (especially ⁇ -Ga 2 O 3 ) that is difficult to increase the carrier density by ion implantation is used.
  • the source region 1 an n+ type semiconductor layer and an n++ type semiconductor layer 1b epitaxially grown on the n+ type semiconductor layer are used. With such a configuration, the source resistance of the entire source region can be reduced. In addition, in the embodiment of the present invention, it is preferable that the mobility of the n + -type semiconductor layer is higher than the mobility of the n++ -type semiconductor layer. With such a preferable configuration, the source resistance of the source region can be reduced more satisfactorily. In the embodiment of the present invention, the distance a from the outer edge of the gate insulating film 4 to the inner edge of the n + -type semiconductor layer 1a is preferably 10 ⁇ m or less, more preferably 5 ⁇ m or less.
  • the n+ type semiconductor layer 1a and/or the n++ type semiconductor layer 1b may be at least partially embedded in the channel layer 6.
  • FIG. FIG. 13 shows an example in which the n+ type semiconductor layer 1a and the n++ type semiconductor layer 1b are embedded in the channel layer 6.
  • FIG. 14 shows an example in which the n + -type semiconductor layer 1a is embedded in the channel layer 6.
  • FIG. 2 shows the main part of a metal oxide semiconductor field effect transistor (MOSFET) which is one of the preferred embodiments of the present invention.
  • MOSFET metal oxide semiconductor field effect transistor
  • the MOSFET shown in FIG. 2 differs from the MOSFET shown in FIG. 1 in that the channel layer 6 has a trench and at least part of the gate electrode 5a is embedded in the trench.
  • the n++ type semiconductor layer 1b is an epitaxial layer epitaxially doped. A semiconductor layer 1b can be realized. Therefore, the source contact resistance can be reduced even when a material such as gallium oxide (especially ⁇ -Ga 2 O 3 ), which is difficult to increase in concentration by ion implantation, is used.
  • the source region 1 an n+ type semiconductor layer and an n++ type semiconductor layer 1b epitaxially grown on the n+ type semiconductor layer are used. With such a configuration, the source resistance of the entire source region can be further reduced. In addition, in the embodiment of the present invention, it is preferable that the mobility of the n + -type semiconductor layer is higher than the mobility of the n++ -type semiconductor layer. With such a preferable configuration, the source resistance of the source region can be reduced more satisfactorily.
  • each layer in Figs. 1 and 2 is not particularly limited as long as it does not hinder the object of the present invention, and may be known means. For example, after forming a film by a vacuum vapor deposition method, a CVD method, a sputtering method, or various coating techniques, a means for patterning by a photolithographic method, or a means for directly patterning using a printing technique or the like can be used.
  • FIG. 3(a) shows a laminated structure in which an n+ type semiconductor layer 3, an n ⁇ type semiconductor layer 7 and a p type semiconductor layer 2 are laminated on a substrate 9 in this order.
  • the p-type semiconductor layer 2 may be a high resistance layer.
  • the p-type semiconductor layer 2 is patterned using a known patterning technique. By forming a channel layer 6, an n + -type semiconductor layer 1a as a source region, and an n++ -type semiconductor layer 1b on the layered structure of FIG. 3A, the layered structure of FIG. 3B is obtained.
  • the n+ type semiconductor layer 1a and the n++ type semiconductor layer 1b are patterned by forming a film using an epitaxial growth method such as a mist CVD method and then etching using a known etching technique.
  • a gate insulating film 4 and a gate electrode 5a are formed on the laminate shown in FIG. 3(b) to obtain the laminate shown in FIG. 3(c).
  • the gate insulating film 4 and the gate electrode 5a can be processed into the shape shown in FIG. 3(c) by etching using a known etching technique after forming films using a known film forming method. can.
  • a source electrode 5b is formed on the laminate shown in FIG. 3(c) using a known film formation method to obtain the laminate shown in FIG. 4(d).
  • a method for forming the source electrode 5b the above-described dry method, wet method, or the like can be used.
  • the semiconductor device of FIG. 4(d) can be obtained by forming the drain electrode 5c using a known film formation method. In the semiconductor device of FIG.
  • the source region 1 includes the n + -type semiconductor layer 1a and the n++ -type semiconductor layer 1b arranged on the n + -type semiconductor layer 1a, and the n++ -type semiconductor layer is an epitaxial layer. Therefore, the element resistance (particularly source contact resistance) is further reduced.
  • the effect of the semiconductor device according to the embodiment of the present invention was verified using device simulation.
  • the simulated semiconductor device is the semiconductor device shown in FIG.
  • the carrier densities of the n+ type semiconductor layer and the n++ type semiconductor layer are 1.0 ⁇ 10 18 /cm 3 and 2.0 ⁇ 10 19 /cm 3 respectively, and the mobility of the n+ type semiconductor layer and the n++ type semiconductor layer is 20 cm 2 respectively.
  • /Vs and 0.0001 cm 2 /Vs, and the thicknesses of the n+ type semiconductor layer and the n++ type semiconductor layer were calculated under the conditions of 150 nm and 50 nm, respectively.
  • FIG. 12(a) shows the current density distribution when the gate voltage is 20 V and the drain voltage is 1 V
  • FIG. 12(b) shows the current flow line when the gate voltage is 20 V and the drain voltage is 1 V.
  • FIGS. 12A and 12B when the carrier density of the n++ type semiconductor layer is higher than the carrier density of the n+ type semiconductor layer, and the mobility of the n+ type semiconductor layer is n++ type semiconductor It can be seen that the contact resistance can be reduced better if it is greater than the mobility of the layer.
  • Example 1 in order to confirm the effect of the n++ layer, a prototype semiconductor device having a structure similar to that of the semiconductor device shown in FIG. 1 was fabricated according to the above procedure.
  • the configuration of Example 1 is as follows. An n ⁇ type semiconductor layer made of tin-doped ⁇ -Ga 2 O 3 as the n ⁇ type semiconductor layer 3, an n+ type semiconductor layer made of tin doped ⁇ -Ga 2 O 3 as the n+ type semiconductor layer 1a, and an n++ type semiconductor layer 1b as the n+ type semiconductor layer 1a , an n++ type semiconductor layer (having a carrier density of 1.0 ⁇ 10 18 /cm 3 or more) made of tin-doped ⁇ -Ga 2 O 3 epitaxially grown on the n+ type semiconductor layer.
  • Example 1 An Al layer and a Ti layer were used in this order.
  • Comparative Example 1 a semiconductor device was prototyped in the same manner as in Example 1, except that the n++ type semiconductor layer was not provided. 5 and 6 show the results of IV measurement of the semiconductor devices manufactured in Example 1 and Comparative Example 1. As is clear from FIGS. , the device resistance (especially the source contact resistance) is reduced.As a reference, compared to the case where the n++ layer is formed by ion implantation, the n++ type semiconductor layer in Example 1 has a lower contact resistance. This is a new finding that was first obtained after trial production of a semiconductor device using gallium oxide (particularly ⁇ - Ga 2 O 3 ). Since it is difficult to perform a high-temperature activation process after ion implantation, it was found that doping by epitaxial growth can reduce source contact resistance and source resistance better than ion implantation.
  • the semiconductor device according to the embodiment of the present invention described above can be applied to power converters such as inverters and converters in order to exhibit the functions described above. More specifically, it can be applied as diodes built into inverters and converters, switching elements such as thyristors, power transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors), and the like. can.
  • FIG. 8 is a block configuration diagram showing an example of a control system using a semiconductor device according to an embodiment of the present invention
  • FIG. 9 is a circuit diagram of the same control system, which is particularly suitable for mounting on an electric vehicle. control system.
  • the control system 500 has a battery (power source) 501, a boost converter 502, a step-down converter 503, an inverter 504, a motor (to be driven) 505, and a drive control section 506, which are mounted on an electric vehicle.
  • the battery 501 is composed of a storage battery such as a nickel-metal hydride battery or a lithium-ion battery, and stores electric power by charging at a power supply station or regenerative energy during deceleration, and is necessary for the operation of the running system and electrical system of the electric vehicle. DC voltage can be output.
  • the boost converter 502 is, for example, a voltage conversion device equipped with a chopper circuit, and boosts the DC voltage of, for example, 200 V supplied from the battery 501 to, for example, 650 V by the switching operation of the chopper circuit, and outputs it to a running system such as a motor. be able to.
  • the step-down converter 503 is also a voltage converter equipped with a chopper circuit. It can be output to the electrical system including
  • the inverter 504 converts the DC voltage supplied from the boost converter 502 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to the motor 505 .
  • a motor 505 is a three-phase AC motor that constitutes the driving system of the electric vehicle, and is rotationally driven by the three-phase AC voltage output from the inverter 504. The rotational driving force is transmitted to the wheels of the electric vehicle via a transmission or the like (not shown). to
  • various sensors are used to measure actual values such as the number of revolutions and torque of the wheels and the amount of depression of the accelerator pedal (acceleration amount) from the running electric vehicle. is entered.
  • the output voltage value of inverter 504 is also input to drive control section 506 .
  • the drive control unit 506 has the function of a controller equipped with a calculation unit such as a CPU (Central Processing Unit) and a data storage unit such as a memory. By outputting it as a feedback signal, the switching operation of the switching element is controlled.
  • the AC voltage applied to the motor 505 by the inverter 504 is corrected instantaneously, so that the operation control of the electric vehicle can be accurately executed, and safe and comfortable operation of the electric vehicle is realized. It is also possible to control the output voltage to the inverter 504 by giving the feedback signal from the drive control unit 506 to the boost converter 502 .
  • FIG. 9 is a circuit configuration excluding the step-down converter 503 in FIG. 8, that is, only a configuration for driving the motor 505.
  • the semiconductor device of the present invention is employed as a Schottky barrier diode in a boost converter 502 and an inverter 504 for switching control.
  • Boost converter 502 is incorporated in a chopper circuit to perform chopper control
  • inverter 504 is incorporated in a switching circuit including IGBTs to perform switching control.
  • An inductor (such as a coil) is interposed in the output of the battery 501 to stabilize the current. It is stabilizing the voltage.
  • the driving control unit 506 is provided with an operation unit 507 made up of a CPU (Central Processing Unit) and a storage unit 508 made up of a non-volatile memory.
  • a signal input to the drive control unit 506 is supplied to the calculation unit 507, and a feedback signal for each semiconductor element is generated by performing necessary calculations.
  • the storage unit 508 temporarily holds the calculation result by the calculation unit 507, accumulates physical constants and functions required for drive control in the form of a table, and outputs them to the calculation unit 507 as appropriate.
  • the calculation unit 507 and the storage unit 508 can employ known configurations, and their processing capabilities can be arbitrarily selected.
  • the switching operations of the boost converter 502, the step-down converter 503, and the inverter 504 use diodes and switching elements such as thyristors, power transistors, IGBTs, MOSFETs, and the like. .
  • gallium oxide (Ga 2 O 3 ), especially corundum-type gallium oxide ( ⁇ -Ga 2 O 3 ), as the material for these semiconductor elements the switching characteristics are greatly improved. Furthermore, by applying the semiconductor device or the like according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 500 can be realized.
  • each of the boost converter 502, the step-down converter 503, and the inverter 504 can expect the effects of the present invention.
  • the effect of the present invention can be expected in any of the above.
  • the control system 500 described above can apply the semiconductor device of the present invention not only to the control system of an electric vehicle, but also to a control system for various purposes such as stepping up or stepping down power from a DC power supply or converting power from DC to AC. can be applied to It is also possible to use a power source such as a solar cell as the battery.
  • FIG. 10 is a block configuration diagram showing another example of a control system employing a semiconductor device according to an embodiment of the present invention
  • FIG. 11 is a circuit diagram of the same control system, showing infrastructure equipment that operates on power from an AC power supply. This control system is suitable for installation in home appliances, etc.
  • a control system 600 receives power supplied from an external, for example, a three-phase AC power supply (power supply) 601, and includes an AC/DC converter 602, an inverter 604, a motor (to be driven) 605, It has a drive control unit 606, which can be mounted on various devices (described later).
  • the three-phase AC power supply 601 is, for example, a power generation facility of an electric power company (a thermal power plant, a hydroelectric power plant, a geothermal power plant, a nuclear power plant, etc.), and its output is stepped down via a substation and supplied as an AC voltage. be.
  • the AC/DC converter 602 is a voltage conversion device that converts AC voltage into DC voltage, and converts AC voltage of 100V or 200V supplied from the three-phase AC power supply 601 into a predetermined DC voltage. Specifically, the voltage is converted into a generally used desired DC voltage such as 3.3V, 5V, or 12V. When the object to be driven is a motor, conversion to 12V is performed.
  • a single-phase AC power supply may be used instead of the three-phase AC power supply. In that case, the same system configuration can be achieved by using a single-phase input AC/DC converter.
  • the inverter 604 converts the DC voltage supplied from the AC/DC converter 602 into a three-phase AC voltage by switching operation, and outputs the three-phase AC voltage to the motor 605 .
  • the form of the motor 604 differs depending on the object to be controlled. When the object to be controlled is a train, the motor 604 drives the wheels. It is a three-phase AC motor, and is rotationally driven by a three-phase AC voltage output from an inverter 604, and transmits its rotational driving force to a drive target (not shown).
  • the control system 600 does not require the inverter 604, and as shown in FIG. 10, a DC voltage is supplied from the AC/DC converter 602 to the driven object.
  • a personal computer is supplied with a DC voltage of 3.3V
  • an LED lighting device is supplied with a DC voltage of 5V.
  • various sensors are used to measure actual values such as the rotation speed and torque of the driven object, or the temperature and flow rate of the surrounding environment of the driven object, and these measurement signals are input to the drive control unit 606.
  • the output voltage value of inverter 604 is also input to drive control section 606 .
  • drive control section 606 gives a feedback signal to inverter 604 to control the switching operation of the switching element.
  • the AC voltage applied to the motor 605 by the inverter 604 is corrected instantaneously, so that the operation control of the object to be driven can be accurately executed, and the object to be driven can be operated stably.
  • FIG. 11 shows the circuit configuration of FIG.
  • the semiconductor device of the present invention is employed as a Schottky barrier diode in an AC/DC converter 602 and an inverter 604 for switching control.
  • the AC/DC converter 602 uses, for example, a Schottky barrier diode circuit configured in a bridge shape, and performs DC conversion by converting and rectifying the negative voltage component of the input voltage into a positive voltage.
  • the inverter 604 is incorporated in the switching circuit in the IGBT to perform switching control.
  • a capacitor (such as an electrolytic capacitor) is interposed between the AC/DC converter 602 and the inverter 604 to stabilize the voltage.
  • the drive control unit 606 is provided with an operation unit 607 made up of a CPU and a storage unit 608 made up of a non-volatile memory.
  • a signal input to the drive control unit 606 is supplied to the calculation unit 607, and a feedback signal for each semiconductor element is generated by performing necessary calculations.
  • the storage unit 608 also temporarily stores the results of calculations by the calculation unit 607, accumulates physical constants and functions necessary for drive control in the form of a table, and outputs them to the calculation unit 607 as appropriate.
  • the calculation unit 607 and the storage unit 608 can employ known configurations, and their processing capabilities can be arbitrarily selected.
  • the rectifying operation and switching operation of the AC/DC converter 602 and the inverter 604 are performed by diodes, switching elements such as thyristors and power transistors. , IGBT, MOSFET, etc. are used. Switching characteristics are improved by using gallium oxide (Ga 2 O 3 ), particularly corundum type gallium oxide ( ⁇ -Ga 2 O 3 ), as the material for these semiconductor elements. Furthermore, by applying the semiconductor film and the semiconductor device according to the present invention, extremely good switching characteristics can be expected, and further miniaturization and cost reduction of the control system 600 can be realized. That is, the AC/DC converter 602 and the inverter 604 can each be expected to have the effect of the present invention. can be expected.
  • FIGS. 10 and 11 exemplify the motor 605 as an object to be driven
  • the object to be driven is not necessarily limited to those that operate mechanically, and can be applied to many devices that require AC voltage.
  • the control system 600 as long as the drive object is driven by inputting power from an AC power supply, it can be applied to infrastructure equipment (for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water and sewage treatment Equipment, system equipment, labor-saving equipment, trains, etc.) and home appliances (e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.). can.
  • infrastructure equipment for example, power equipment such as buildings and factories, communication equipment, traffic control equipment, water and sewage treatment Equipment, system equipment, labor-saving equipment, trains, etc.
  • home appliances e.g., refrigerators, washing machines, personal computers, LED lighting equipment, video equipment, audio equipment, etc.
  • the semiconductor device of the present invention can be used in various fields such as semiconductors (for example, compound semiconductor electronic devices), electronic parts/electrical equipment parts, optical/electrophotographic equipment, industrial materials, etc., but it is particularly useful for power devices. be.
  • Substrate 21 Film forming apparatus (mist CVD apparatus) 22a Carrier gas source 22b Carrier gas (dilution) source 23a Flow control valve 23b Flow control valve 24 Mist generation source 24a Raw material solution 24b Raw fine particles 25 Container 25a Water 26 Ultrasonic vibrator 27 Film forming chamber 28 Hot plate 29 Supply pipe 30

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Abstract

La présente invention concerne un dispositif à semi-conducteur qui est particulièrement utile en tant que dispositif d'alimentation et présente une résistance à l'élément réduite. L'invention concerne un dispositif à semi-conducteur qui comprend : une couche semi-conductrice à oxyde qui comprend au moins une région de source ; et une électrode de source qui est disposée sur la région de source. La région de source comprend au moins : une couche semi-conductrice n + ; et une couche semi-conductrice n + + qui est disposée sur la couche semi-conductrice n + et présente une densité de porteurs supérieure à celle de la couche semi-conductrice n +. La couche semi-conductrice n + + est une couche épitaxiale.
PCT/JP2022/015217 2021-03-31 2022-03-28 Dispositif à semi-conducteur WO2022210615A1 (fr)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013236040A (ja) * 2012-05-11 2013-11-21 Hitachi Ltd 炭化珪素半導体装置およびその製造方法
JP2019068011A (ja) * 2017-10-05 2019-04-25 株式会社東芝 半導体装置
WO2020013259A1 (fr) * 2018-07-12 2020-01-16 株式会社Flosfia Dispositif à semi-conducteur et système à semi-conducteur comprenant un dispositif à semi-conducteur
JP2020107899A (ja) * 2014-07-22 2020-07-09 株式会社Flosfia 半導体装置

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013236040A (ja) * 2012-05-11 2013-11-21 Hitachi Ltd 炭化珪素半導体装置およびその製造方法
JP2020107899A (ja) * 2014-07-22 2020-07-09 株式会社Flosfia 半導体装置
JP2019068011A (ja) * 2017-10-05 2019-04-25 株式会社東芝 半導体装置
WO2020013259A1 (fr) * 2018-07-12 2020-01-16 株式会社Flosfia Dispositif à semi-conducteur et système à semi-conducteur comprenant un dispositif à semi-conducteur

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