WO2022208949A1 - 撮像素子 - Google Patents

撮像素子 Download PDF

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Publication number
WO2022208949A1
WO2022208949A1 PCT/JP2021/037153 JP2021037153W WO2022208949A1 WO 2022208949 A1 WO2022208949 A1 WO 2022208949A1 JP 2021037153 W JP2021037153 W JP 2021037153W WO 2022208949 A1 WO2022208949 A1 WO 2022208949A1
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Prior art keywords
voltage
pixel
pixels
transistor
imaging device
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PCT/JP2021/037153
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English (en)
French (fr)
Japanese (ja)
Inventor
健市 奥村
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Sony Semiconductor Solutions Corp
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Sony Semiconductor Solutions Corp
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Priority to JP2023510196A priority Critical patent/JPWO2022208949A1/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/70—SSIS architectures; Circuits associated therewith
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/12—Image sensors

Definitions

  • the present disclosure relates to imaging devices.
  • This expansion of the dynamic range is a field that can also be applied when receiving infrared light.
  • Sensors using InGaAs indium gallium arsenide
  • PD photodiode
  • the readout electrodes are arranged in a grid pattern, all the pixels have the same size, and the pixels cannot be set to different sizes.
  • the present disclosure provides an imaging element that controls sensitivity for each pixel in an imaging sensor having a common well region.
  • an imaging device includes well regions, electrodes, and pixel circuits.
  • the well region is shared across pixels.
  • the electrodes are arranged in a two-dimensional array to read out the charge in each pixel from the well region.
  • the pixel circuit is connected to the electrode and applies a controlled bias voltage for each pixel.
  • the pixel circuit includes an amplifier having an inverting input terminal connected to the electrode, a first capacitor connected between an output terminal of the amplifier and the inverting input terminal, and in parallel with the first capacitor. and a reset switch connected to a controlled reference voltage may be applied to the non-inverting input terminal of the amplifier for each pixel.
  • the bias voltage may be determined based on the reference voltage.
  • a switch may be further provided for switching the reference voltage input to the non-inverting input terminal of the amplifier.
  • the pixel circuit includes a floating diffusion connected to the electrode, a first transistor having a gate connected to the floating diffusion and outputting a drain current based on a power supply voltage, and a selection signal input to the gate. , a second transistor having one end connected in series with the first transistor and outputting a signal related to the pixel value of the pixel from the other end; and a second capacitor connected between the floating diffusion and a ground point. and a third transistor having a gate to which a reset signal is input, one end of which is connected to the floating diffusion, and the other end of which the bias voltage is applied.
  • the voltage applied to the gate and the other end of the third transistor may be controlled in conjunction with each other.
  • the voltage applied to the gate of the third transistor is higher when the voltage applied to the other terminal is higher than when the voltage applied to the other terminal is lower. may be set higher.
  • the pixel circuit may further include a second switch, one end of which is connected to the floating diffusion, and a third capacitor, which is connected between the other end of the second switch and a ground point. , the second switch is turned on when there is a difference in the bias voltage between pixels and the bias voltage is high, and is turned off when the bias voltage is low. good too. .
  • the pixel circuit includes a floating diffusion that receives a pixel signal, a first transistor that has a gate connected to the floating diffusion and outputs a drain current based on a power supply voltage, a selection signal that is input to the gate, and one end of which is a second transistor connected in series with the first transistor and outputting a signal related to the pixel value of the pixel from the other end; a second capacitor connected between the floating diffusion and a ground point; a third transistor to which a voltage is input, one end of which is connected to the floating diffusion, and the other end of which the bias voltage is applied, a memory region connected to the electrode, the floating diffusion, and the memory region; , and a gate to which a voltage for controlling transfer timing of carriers from the memory region to the floating diffusion is applied.
  • the pixel circuit further has an offset control voltage input to a gate, one end connected to the memory area, and an offset bias voltage applied to the other end, and the offset control voltage controls the offset voltage of the memory area.
  • a fifth transistor may be provided.
  • the bias voltage may be controlled to a first voltage and a second voltage that collects carriers from a range narrower than the first voltage to the electrode in the well region.
  • the first voltage and the second voltage may be controlled so as to be alternately arranged in the array of pixels.
  • the pixels that are not read out are arranged in a checkered pattern, and the pixels that are not read out are alternately applied with the first voltage and the second voltage is applied between the pixels that are not read out.
  • the pixels to be energized and may be arranged.
  • the voltages applied to the pixels to which the first voltage is applied and the pixels to which the second voltage is applied may be controlled for each frame in which pixel values are obtained.
  • FIG. 1 is a block diagram schematically showing an imaging element according to one embodiment
  • FIG. FIG. 2 is a conceptual diagram showing part of a pixel array according to one embodiment
  • FIG. 2 is a conceptual diagram showing part of a pixel array according to one embodiment
  • FIG. 4 is a diagram schematically showing a cross section of a pixel and a pixel circuit according to one embodiment
  • FIG. 2 is a diagram showing a pixel circuit according to one embodiment
  • 4 is a chart showing reset timing according to one embodiment
  • FIG. 2 is a diagram showing a pixel circuit according to one embodiment
  • FIG. 2 is a diagram showing a pixel circuit according to one embodiment
  • FIG. 2 is a diagram showing a pixel circuit according to one embodiment
  • FIG. 2 is a diagram showing a pixel circuit according to one embodiment
  • FIG. 2 is a diagram showing a pixel circuit according to one embodiment
  • FIG. 2 is a diagram showing a pixel circuit according to one embodiment
  • FIG. 3 is a diagram showing an arrangement example of pixels according to one embodiment
  • FIG. 3 is a diagram showing an arrangement example of pixels according to one embodiment
  • FIG. 3 is a diagram showing an arrangement example of pixels according to one embodiment
  • FIG. 3 is a diagram showing an arrangement example of pixels according to one embodiment
  • FIG. 3 is a diagram showing an arrangement example of pixels according to one embodiment
  • FIG. 1 is a diagram partially showing pixels belonging to a pixel array in an imaging element (solid-state imaging device) according to one embodiment.
  • the imaging device 1 is, for example, an infrared image sensor that includes photodiodes having InGaAs well regions as pixels, and has sensitivity to light with a wavelength of 800 nm or longer, for example.
  • the imaging device 1 includes a pixel array 10 and an extra-pixel area 200.
  • the extra-pixel area includes a row scanning section 201, a control section 202, a horizontal selection section 203, a column scanning section 204, and an output terminal Vout.
  • Peripheral circuits for driving the pixel array 10 and acquiring signals are provided in the extra-pixel region.
  • FIG. 2 is a diagram showing an example of the pixel array 10.
  • the pixel array 10 includes a plurality of pixels 100 arranged in a two-dimensional array.
  • the pixel array 10 includes, for example, a plurality of pixels 100 arranged in a rectangular shape.
  • a plurality of pixels 100 have, for example, a common InGaAs well region. Boundaries of pixels 100 are indicated by dotted lines. Each pixel 100 comprises a first electrode 102 .
  • the first electrode 102 is one of electrodes forming the pixel 100 .
  • the imaging device 1 By acquiring carriers generated by the reception of light by the first electrode 102, the imaging device 1 outputs the received signal as an image signal.
  • the row scanning unit 201 is connected to a control line that connects the pixels 100 belonging to the same row in the pixel array 10 .
  • the control lines include, for example, a row selection line that selects a row of pixels 100, and a reset line that resets charges stored in pixels 100 belonging to the same row.
  • the row scanning unit 201 includes a shift register, an address decoder, etc., and drives each pixel 100 of the pixel array 10, for example, in units of rows.
  • a signal output from each pixel 100 in a pixel row selected and scanned by the row scanning unit 201 is supplied to the horizontal selection unit 203 via a vertical signal line.
  • the horizontal selection unit 203 is composed of an amplifier, a horizontal selection switch, and the like provided for each vertical signal line.
  • the column scanning unit 204 is configured with a shift register, an address decoder, etc., and sequentially drives the horizontal selection switches of the horizontal selection unit 203 while scanning them. By selective scanning of columns by the column scanning unit 204, the signals of the respective pixels 100 transmitted via the respective vertical signal lines are sequentially output to the signal lines and output from Vout via the signal lines. Vout is connected to, for example, a signal processing circuit or the like.
  • the control unit 202 receives a clock given from the outside and information instructing an operation mode, and outputs data such as internal information of the imaging device 1 .
  • the control unit 202 further includes a timing generator that generates various timing signals. Based on the various timing signals generated by this timing generator, any one of the row scanning unit 201, horizontal selection unit 203, and column scanning unit 204 is selected. Execute drive control to drive one of them at the appropriate timing.
  • FIG. 3 shows an example of controlling the size of the pixel 100 according to this embodiment.
  • Pixel 100 receives carriers from virtually different sized regions. For example, as shown in FIG. 3, as virtual pixels 100, a pixel that reads carriers from a larger circular region and a smaller circular region provided between the larger circular regions reads carriers. A pixel to be read out is virtually defined. This magnitude difference can be implemented by controlling the performance (sensitivity) of carrier readout by the first electrode 102 . Details of this control will be described later.
  • FIG. 4 is a diagram schematically showing a cross section of the pixel 100 and a pixel circuit associated with the pixel 100 according to one embodiment.
  • the imaging device 1 may have a layered structure of, for example, a semiconductor substrate having the photoelectric conversion unit 101 and a circuit substrate 30 .
  • the photoelectric conversion unit 101 photoelectrically converts incident light, such as light with a wavelength in the infrared region, for each pixel 100, for example. It has a first electrode 102, a first semiconductor layer 103, a photoelectric conversion film 105, a second semiconductor layer 106, and a second electrode 107 in order from the position closer to the circuit board 30. As shown in FIG.
  • a pixel circuit 300 provided on the circuit board 30 is a readout circuit for signal charges generated in the photoelectric conversion unit 101 .
  • the pixel circuit 300 is connected to the first electrode 102 of the photoelectric conversion unit 101 for each pixel 100.
  • the first electrode 102 and the pixel circuit 300 are connected via a bump electrode 110 and a contact electrode 111, for example.
  • the first electrode 102 is arranged in the passivation film 108
  • the bump electrode 110 and the contact electrode 111 are arranged in the interlayer insulating film 109 .
  • the interlayer insulating film 109 is provided in contact with the circuit board 30, for example.
  • a bump electrode 110 and a contact electrode 111 are provided in this interlayer insulating film 109 for each pixel 100 .
  • the contact electrodes 111 and the bump electrodes 110 are arranged in this order from the position closer to the circuit board 30 .
  • the first electrode 102 and the bump electrode 110 are in contact, and the bump electrode 110 and the contact electrode 111 are in contact.
  • the photoelectric conversion section 101 and the circuit board 30 are bump-bonded.
  • the photoelectric conversion section 101 and the circuit board 30 may be Cu-Cu bonded.
  • the interlayer insulating film 109 is made of, for example, an inorganic insulating material.
  • inorganic insulating materials include SiN (silicon nitride), Al 2 O 3 (aluminum oxide), SiO 2 (silicon oxide), HfO 2 (hafnium oxide), and the like.
  • the passivation film 108 is provided between the interlayer insulating film 109 and the first semiconductor layer 103, for example.
  • a first electrode 102 is provided in this passivation film 108 for each pixel 100 .
  • Part of the first electrode 102 may be provided in the interlayer insulating film 109 .
  • the passivation film 108 is made of, for example, an inorganic insulating material. Examples of the inorganic insulating material include SiN, Al2O3 , SiO2 , HfO2 , and the like.
  • Passivation film 108 may be made of the same inorganic insulating material as interlayer insulating film 109 .
  • the first electrode 102 is electrically connected to the photoelectric conversion film 105 via the first semiconductor layer 103 .
  • the first electrode 102 is an electrode supplied with a voltage for reading signal charges (holes or electrons) generated in the photoelectric conversion film 105 and is provided separately in the pixel 100 . In the following description, signal charges are assumed to be holes as a non-limiting example.
  • One end of the first electrode 102 is in contact with the first semiconductor layer 103 , and the first electrode 102 is electrically connected to the photoelectric conversion film 105 via the first semiconductor layer 103 .
  • the other end of first electrode 102 is in contact with bump electrode 110 .
  • Adjacent first electrodes 102 are electrically separated by a passivation film 108 .
  • the first electrode 102 includes, for example, Ti (titanium), W (tungsten), TiN (titanium nitride), Pt (platinum), Au (gold), Pd (palladium), Zn (zinc), Ni (nickel), Al (aluminum), or an alloy containing at least one of them.
  • the first electrode 102 may be a single film of such constituent materials, or may be a laminated film in which two or more kinds are combined.
  • the first electrode 102 may be composed of a laminated film of Ti and W, for example.
  • the first semiconductor layer 103 provided between the passivation film 108 and the photoelectric conversion film 105 is provided in common for all the pixels 100, for example.
  • the first semiconductor layer 103 is for electrically separating the adjacent pixels 100, and the first semiconductor layer 103 is provided with, for example, a plurality of diffusion regions 104. As shown in FIG.
  • a compound semiconductor material having a bandgap larger than that of the compound semiconductor material forming the photoelectric conversion film 105 for the first semiconductor layer 103 dark current can be suppressed.
  • n-type InP indium phosphide
  • the diffusion regions 104 provided in the first semiconductor layer 103 are arranged apart from each other for each pixel 100 .
  • the diffusion regions 104 are arranged for each pixel 100 and the first electrode 102 is connected to each diffusion region 104 .
  • the diffusion region 104 is for reading signal charges generated in the photoelectric conversion film 105 for each pixel 100 .
  • This diffusion region 104 contains, for example, p-type impurities. Examples of p-type impurities include zinc and the like.
  • a PN junction interface is formed between the diffusion region 104 and the first semiconductor layer 103 other than the diffusion region 104, and the adjacent pixels 100 are electrically isolated from each other.
  • the diffusion region 104 is provided, for example, in the thickness direction of the first semiconductor layer 103, and is also provided in part of the photoelectric conversion film 105 in the thickness direction.
  • the photoelectric conversion film 105 provided between the first semiconductor layer 103 and the second semiconductor layer 106 is provided over all the pixels 100, for example. In other words, all the pixels 100 are provided with the photoelectric conversion film 105 in common.
  • the photoelectric conversion film 105 absorbs light of a predetermined wavelength to generate signal charges, and is made of a compound semiconductor material such as a III-V group semiconductor. Examples of compound semiconductor materials forming the photoelectric conversion film 105 include InGaAs, InAsSb (indium arsenide antimony), GaAsSb (gallium arsenide antimony), InAs (indium arsenide), InSb (indium antimonide), HgCdTe (mercury cadmium tellurium), and the like. is mentioned.
  • a photoelectric conversion film 105 containing Ge (germanium) may be formed.
  • the photoelectric conversion film 105 may be made of a material having a Type II structure.
  • photoelectric conversion of light with wavelengths from the visible region to the short infrared region is performed.
  • the second semiconductor layer 106 is provided in common for all pixels 100, for example.
  • the second semiconductor layer 106 is provided between the photoelectric conversion film 105 and the second electrode 107 and is in contact with them.
  • the second semiconductor layer 106 is a region where charges discharged from the second electrode 107 move, and is made of, for example, a compound semiconductor containing n-type impurities.
  • n-type InP can be used for the second semiconductor layer 106 .
  • the received light is converted into carriers in the second semiconductor layer 106 and the photoelectric conversion film 105.
  • the imaging device 1 By reading this carrier in the first electrode 102, the imaging device 1 generates image information from the received light. That is, the arrangement of the first electrodes 102 is the arrangement of pixels, and the pixel value is determined by the amount of carriers read by each first electrode 102 .
  • each pixel 100 performance can be controlled.
  • each pixel 100 is controlled by controlling the bias voltage applied to each first electrode 102 of the pixel 100 .
  • the bias voltage applied to each first electrode 102 of the pixel 100 By this control, as shown in FIG. 3, pixels 100 having light-receiving regions of virtually different sizes are generated. By acquiring pixel values from the pixels 100 having different sizes of the generated light receiving regions, various functions can be exhibited.
  • the pixel circuit 300 will be described in detail below.
  • the pixel circuit 300 may be implemented by CTIA (Capacitive Transimpedance Amplifier), for example.
  • the pixel circuit 300 is provided for each pixel 100 and includes an amplifier Amp, a capacitor Cfb, and switches SWrst and SWout.
  • the amplifier Amp is composed of a differential amplifier circuit.
  • a switch SWout is connected to the output end of this amplifier Amp, and the output from the pixel is appropriately transmitted to the output terminal Vout based on the control from the horizontal selection section 203 of the extra-pixel circuit in FIG.
  • a capacitor Cfb (first capacitor) is connected between the output terminal and the inverting input terminal of the amplifier Amp.
  • the capacitance of the capacitor Cfb is, for example, a capacitance smaller than the parasitic capacitance in the photoelectric conversion unit.
  • the amplifier Amp constitutes a negative feedback amplifier circuit. In such a configuration, most of the charge generated by the exposure of the photodiode is stored in the capacitor Cfb, making it possible to increase the amplitude of the output voltage with respect to the amount of charge generated in the photodiode.
  • a switch SWrst is a switch for resetting the capacitor Cfb.
  • the switch SWrst may be configured as a reset transistor with a p-type MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor).
  • MOSFET Metal-Oxide-Semiconductor Field-Effect-Transistor
  • a reference voltage is applied to the non-inverting input terminal of the amplifier Amp.
  • This reference voltage defines a reference voltage for output amplitude.
  • the bias voltage can be controlled for each pixel 100 by controlling this reference voltage.
  • switches SW1, SW2, SW3, and SW4 may be provided for determining the voltage to be applied as the reference voltage.
  • the reference voltage of the amplifier Amp can be controlled for each pixel 100.
  • FIG. Controlling the reference voltage allows the pixel 100 to which a higher reference voltage is applied to collect charge from a wider range. Therefore, a pixel 100 having a wide light receiving area can be formed by increasing the reference voltage, and a pixel 100 having a narrow light receiving area can be formed by decreasing the reference voltage.
  • a pixel that collects charges from a wide range is referred to as a large pixel
  • a pixel that collects charges from a narrow range is referred to as a small pixel. That is, a large pixel and a small pixel are defined when there is a difference in reference voltage.
  • VrefA and VrefB VrefA > VrefB.
  • VrefA VrefA > VrefB.
  • the same bias voltage is applied to the pixel circuits 300 of the two pixels 100 in FIG.
  • two pixels 100 can be controlled as pixels 100 having the same light receiving area if the same voltage is applied to surrounding pixels 100 as well.
  • the same reference voltage is applied in this manner.
  • the switches SW1 and SW4 When the switches SW1 and SW4 are turned on and the switches SW2 and SW3 are turned off, a higher bias voltage is applied to the pixel 100 on the left side than the pixel 100 on the right side.
  • the pixel 100 on the left side can acquire carriers from a wider area than the pixel 100 on the right side, and the size of the pixel 100 on the left side can be apparently increased.
  • the opposite case it is possible to make the pixel 100 on the right side appear larger than the pixel 100 on the left side.
  • This bias voltage control can be performed for each row or column, or for each arbitrary pixel 100.
  • the voltages applied as the reference voltages are not limited to two types, and three or more types of voltages may be used.
  • the first electrode 102 is controlled in three types: large pixels, small pixels, or off-state pixels. can do. By performing such control, it is possible to control the forms of the pixels 100 in various pixel arrays 10 as described later.
  • the imaging device by using the CTIA circuit as the pixel circuit, it is possible to control the performance of each pixel by changing the reference voltage. For example, it is possible to obtain pixel values in a wide area by increasing the bias voltage, narrow the pixel area and increase sensitivity by decreasing the bias voltage, or change the resolution of the sensor.
  • This control may be, for example, two types of fixed voltages as described above.
  • the reference voltage can be a variable voltage. By making the reference voltage variable, it is possible to continuously control the light receiving area, sensitivity, resolution, etc. of the pixels. By using pixels of two different sizes, it is also possible to compare pixels of arbitrary sensitivity and expand the dynamic range.
  • the apparent size of periodic pixels may be controlled to change.
  • the reference voltage may be replaced for each frame of image acquisition. Dynamic range expansion can be achieved by comparing pixel values obtained from pixels with different sensitivities as described above, but by replacing the reference voltage for each frame, information can be obtained with different sensitivities for pixels at the same position. Therefore, it is possible to adjust the dynamic range with higher accuracy in a situation where there is no positional deviation.
  • the reference voltage may be controlled at the timing when the capacitor Cfb is reset. By controlling in this way, an appropriate bias voltage is applied at the timing when electric charge is accumulated from the first electrode 102 to the capacitor Cfb.
  • the pixel circuit 300 is a CTIA circuit in the first embodiment described above, it is not limited to this.
  • the pixel circuit 300 may be an FD (Floating Diffusion) accumulation type circuit as another non-limiting example.
  • FD Floating Diffusion
  • FIG. 5 is a diagram showing a pixel circuit 300 according to this embodiment.
  • the pixel circuit 300 includes transistors Mrst, Mamp, Msel, and a capacitor Cfd.
  • the transistor Mrst (third transistor) is a reset transistor.
  • transistor Mrst releases the charge stored in capacitor Cfd according to RSTA applied to its gate.
  • the potential of FD becomes VrstA in the left pixel circuit 300 and VrstB in the right pixel circuit 300 .
  • the light receiving region can be controlled for each pixel 100 in the same manner as in the above-described embodiment. can be done. For example, by setting VrstA ⁇ VrstB, the light receiving area of the pixel 100 on the left can be expanded compared to the pixel 100 on the right.
  • the large pixel and the small pixel were defined by the reference voltage applied to the non-inverting input terminal of the differential amplifier.
  • Mrst is an n-type MOSFET, defined by the bias voltage applied to the source of Mrst. For example, if VrstA>VrstB, then the pixels to which the bias of VrstA is applied are defined as large pixels and the pixels to which VrstB is applied are defined as small pixels.
  • Capacitor Cfd (second capacitor) is a capacitor for accumulating charge in FD.
  • the transistor Mamp (first transistor) is a transistor that outputs a drain current amplified according to the charge accumulated in the FD.
  • the transistor Msel (second transistor) is a transistor that outputs a drain current based on the drain current of the transistor Mamp to Vout via the horizontal selection section 203 based on the selection signal.
  • switches corresponding to the switches SW1 to SW4 in the above-described embodiment are switches for controlling the voltage applied to the source of the transistor Mrst.
  • switches By arranging the switches in this manner and appropriately controlling the potential of the source of the transistor Mrst, it is possible to appropriately set the potential that serves as the reference for the FD. Control of the bias voltage is the same as in the above-described embodiments.
  • the overflow voltage may be adjusted by switching between VrstA and VrstB and controlling the gate voltage of the transistor Mrst.
  • the transistor Mrst is an n-type MOSFET.
  • FIG. 6 is a timing chart showing the potentials of the transistor Mrst and FD. From the top, the selection signal applied to the gate of the transistor Msel, the reference voltage RSTA, the RSTA applied to the gate of the transistor Mrst when RSTB is used as the bias voltage, the RSTB, the small pixel, the large pixel dark, and the bright FD potential at time.
  • VrstA and VrstB in the figure are voltages applied to the source of the transistor Mrst, respectively, and are indicated by dotted lines.
  • VofA and VofB are allowable voltages that can drop due to carriers flowing into the floating diffusion of the pixel circuit 250 for large pixels and small pixels, respectively.
  • VrstA>VrstB is satisfied in the same manner as above, that is, the pixel 100 to which VrstA is applied as the bias voltage has a wider light-receiving area than the pixel 100 to which VrstB is applied as the bias voltage.
  • a pixel to which VrstA is a bias voltage is referred to as a large pixel
  • a pixel to which VrstB is given as a bias voltage is referred to as a small pixel.
  • the reset signals RSTA and RSTB become High, a High potential is applied to the gate of the transistor Mrst and the FD is reset (reset period).
  • the reset signal RSTB is set to the original potential (Low) after the FD is reset.
  • the reset signal RSTA does not return to the original potential (Low) after the FD is reset, and is set to a potential higher than Low by the offset potential.
  • the large pixel and the small pixel are defined by the potential difference between the FD and the first electrode 102. If the saturation voltage of the FD is the same, then the small pixel becomes saturated after the large pixel is saturated. Depending on the potential difference, the pixel circuit 300 of the small pixel begins to read charges over a wide range. It is desirable to avoid such situations.
  • the FD accumulation period ends at the timing when the selection signal becomes High, and the signal of the selected pixel 100 is output for a predetermined time (signal readout period) from this timing.
  • the reset signal becomes High, and the FDA of each pixel circuit 300 is reset.
  • control is performed so that RSTA > RSTB (Low). Otherwise, both RSTA and RSTB are controlled to Low level signals.
  • FIG. 7 is an implementation example of a pixel circuit 300 according to one embodiment.
  • the pixel circuit 300 may further include a capacitor Cfd2 and a switch SW5 in addition to the configuration of FIG.
  • the switch SW5 is a switch controlled together with RST and Vrst.
  • the switch SW5 is, for example, a switch that is turned on when the pixel 100 is set as a large pixel and turned off when it is set as a small pixel.
  • the FD of the pixel circuit 300 is connected to the capacitor Cfd2 (third capacitor) via the switch SW5 (second switch). In this manner, the charge amount that can be accumulated in the FD may be changed depending on whether the pixel is large or small. As described above, when the overflow potential on the large pixel side is lowered, if the large pixel overflows, the amount of charge read out from the large pixel is limited. Therefore, there is a high possibility that the magnitude of the signal charge amount Qs in the large pixel will decrease.
  • FIG. 8 is an implementation example of a pixel circuit 300 according to one embodiment.
  • the pixel circuit 300 may comprise a transistor Mtx.
  • the transistor Mtx (fourth transistor) is a transfer transistor.
  • the charge output from the pixel 100 may be stored once in the memory area and transmitted to the FD by the transfer transistor at appropriate timing.
  • the reference potential of the memory area of the pixel circuit 300 connected to the first electrode 102 is determined by the reference voltage Vrst.
  • the potential of the memory area is also set to Vrst via the transistor Mtx.
  • FIG. 9 is an implementation example of a pixel circuit 300 according to one embodiment.
  • This pixel circuit 300 is a circuit obtained by adding an overflow gate to the implementation of FIG.
  • the pixel circuit 300 includes a transistor Mofg that allows an overflow current to flow when the memory area is saturated with charges.
  • the reference voltage in the memory area is set to the reference voltage Vrst through the transistor Mtx. Further, when the charge is saturated in the memory area, the charge is discharged through the transistor Mofg. A voltage is applied to the gate of the transistor Mofg as well, so that the drain current flows appropriately.
  • this transistor Mofg (fifth transistor) is an n-type MOSFET, and the voltage applied to the gate (offset control voltage) and the voltage applied to the source (offset bias voltage) cause an offset in the memory area. Control voltage.
  • FIG. 10 is an implementation example of a pixel circuit 300 according to one embodiment. It can also be applied to such a VD (Voltage Domain) type pixel circuit 300 . Since this drive is basically the same as in the second embodiment, the details will be omitted.
  • VD Voltage Domain
  • Fig. 11 shows an arrangement in which large pixels and small pixels are arranged alternately. With such an arrangement, as indicated by the solid line, a readout range equivalent to that of the regular octagonal large pixels and the square small pixels filling the space between them can be obtained.
  • pixels that are not read out are arranged at the four-connected positions of the pixels that are read over a wide range, and the diagonal positions of the pixels that are read over a wide range (out of the eight-connected positions, the four-connected positions are excluded).
  • (position) are arranged with pixels to be read out in a narrow range. That is, in the pixel array 10, pixels that are not read out may be arranged in a checkerboard pattern, and wide range readout pixels and narrow range readout pixels may be alternately arranged therebetween. As shown in this figure, a circular area of pixels can be formed. Furthermore, it is possible to control the size ratio by using the voltage to be set, the number of pixels for which the voltage is set, and pixel addition.
  • pixels to be read out in a narrow range are arranged above and below pixels to be read out in a wide range, and pixels not to be read out are arranged to the left and right. and By arranging them in this way, it is possible to form a pixel in a light receiving area that is nearly rectangular.
  • the small pixel signal may not be used, or may be added to the large pixel signal as a rectangular area.
  • signals obtained from small pixels can be used for other applications such as an illuminance meter. This arrangement can be used, for example, for linear sensors such as spectroscopic sensors.
  • Fig. 14 shows the position of the center of gravity shifted.
  • FIG. 15 is an example in which large pixels and small pixels are exchanged for each frame in the configuration of FIG. By switching in this way, it is possible to generate an image with a wide dynamic range without lowering the resolution.
  • Such permutation for each frame is not limited to the example of FIG. 11, and can be applied to other examples.
  • an InGaAs infrared region image sensor has been described as an example, but the aspect of the present disclosure is not limited to this.
  • it can be applied in the visible region as long as it shares the well region.
  • the well region is not limited to InGaAs.
  • the imaging element according to each embodiment described above may be provided in a solid-state imaging device, for example. It may also be provided with other suitable sensors.
  • the pixel circuit is an amplifier having an inverting input terminal connected to the electrode; a first capacitor connected between the output terminal of the amplifier and the inverting input terminal; a reset switch connected in parallel with the first capacitor; with a controlled reference voltage is applied to a non-inverting input terminal of the amplifier for each pixel; (1) The imaging device according to (1).
  • the pixel circuit is a floating diffusion connected to the electrode; a first transistor having a gate connected to the floating diffusion and outputting a drain current based on a power supply voltage; a second transistor having a gate to which a selection signal is input, one end of which is connected in series with the first transistor, and which outputs a signal related to the pixel value of the pixel from the other end; a second capacitor connected between the floating diffusion and a ground point; a third transistor having a gate to which a reset signal is input, one end connected to the floating diffusion, and the other end to which the bias voltage is applied;
  • the imaging device according to (1) comprising:
  • the voltage applied to the gate of the third transistor is higher when the voltage applied to the other terminal is higher than when the voltage applied to the other terminal is lower. set high, The imaging device according to (6).
  • the pixel circuit further comprises: a second switch, one end of which is connected to the floating diffusion; a third capacitor connected between the other end of the second switch and a ground point; with The second switch is turned on when there is a difference in the bias voltage between pixels and when the bias voltage is a high voltage, and turned off when the bias voltage is a low voltage.
  • the pixel circuit is a floating diffusion that receives the pixel signal; a first transistor having a gate connected to the floating diffusion and outputting a drain current based on a power supply voltage; a second transistor having a gate to which a selection signal is input, one end of which is connected in series with the first transistor, and which outputs a signal related to the pixel value of the pixel from the other end; a second capacitor connected between the floating diffusion and a ground point; a third transistor having a gate to which a reset voltage is input, one end connected to the floating diffusion, and the other end to which the bias voltage is applied; a memory region connected to the electrode; a fourth transistor connected between the floating diffusion and the memory region and having a gate to which a voltage for controlling transfer timing of carriers from the memory region to the floating diffusion is applied;
  • the imaging device comprising:
  • the pixel circuit further comprises: a fifth transistor having a gate to which an offset control voltage is input, one end connected to the memory region, an offset bias voltage applied to the other end, and the offset control voltage controlling the offset voltage of the memory region;
  • a fifth transistor having a gate to which an offset control voltage is input, one end connected to the memory region, an offset bias voltage applied to the other end, and the offset control voltage controlling the offset voltage of the memory region;
  • the bias voltage is a first voltage; a second voltage for collecting carriers from a range narrower than the first voltage to an electrode in the well region; controlled by (1) The imaging device according to (1).
  • the pixels that are not read out are arranged in a checkered pattern, The pixels to which the first voltage is applied and the pixels to which the second voltage is applied are alternately arranged between the pixels that are not read out.

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025192503A1 (ja) * 2024-03-11 2025-09-18 ソニーセミコンダクタソリューションズ株式会社 撮像素子および電子機器

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JP2016086407A (ja) * 2014-10-23 2016-05-19 パナソニックＩｐマネジメント株式会社 撮像装置および画像取得装置
WO2017150167A1 (ja) * 2016-02-29 2017-09-08 ソニー株式会社 固体撮像素子
WO2019155841A1 (ja) * 2018-02-07 2019-08-15 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子および撮像装置

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JP2016086407A (ja) * 2014-10-23 2016-05-19 パナソニックＩｐマネジメント株式会社 撮像装置および画像取得装置
WO2017150167A1 (ja) * 2016-02-29 2017-09-08 ソニー株式会社 固体撮像素子
WO2019155841A1 (ja) * 2018-02-07 2019-08-15 ソニーセミコンダクタソリューションズ株式会社 固体撮像素子および撮像装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2025192503A1 (ja) * 2024-03-11 2025-09-18 ソニーセミコンダクタソリューションズ株式会社 撮像素子および電子機器

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