WO2022206029A1 - 一种集成电容的环路控制系统 - Google Patents

一种集成电容的环路控制系统 Download PDF

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WO2022206029A1
WO2022206029A1 PCT/CN2021/138246 CN2021138246W WO2022206029A1 WO 2022206029 A1 WO2022206029 A1 WO 2022206029A1 CN 2021138246 W CN2021138246 W CN 2021138246W WO 2022206029 A1 WO2022206029 A1 WO 2022206029A1
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module
signal
loop control
digital
counter module
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PCT/CN2021/138246
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English (en)
French (fr)
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李国成
尤勇
刘军
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华润微集成电路(无锡)有限公司
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Publication of WO2022206029A1 publication Critical patent/WO2022206029A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters

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  • the invention belongs to the field of integrated circuit design and manufacture, in particular to a loop control system of integrated capacitors.
  • capacitors are often used to realize various functions such as compensation, delay, voltage regulation, and integration. Large area, so the usual method is to use the chip external capacitor to achieve.
  • a functional circuit realized by using an external capacitor is shown in Figure 1, and its working mode is illustrated as follows: the loop control system detects the working state of the system and outputs a control signal Ctrl to the capacitor control module according to the circuit requirements. After detecting the control signal, the capacitor control circuit performs various operations such as charging and discharging the capacitor, thereby changing the electrical characteristics of the capacitor and outputting the signal COMP to the loop control module. The loop control module detects the change in capacitance and adjusts the loop operating mode or state until the system reaches a steady state. The process of outputting, adjusting, receiving feedback, and continuing to adjust the signal runs through the whole system.
  • the loop control module detects that the COMP voltage needs to be charged for the capacitor after analysis, it will control the Ctrl signal to a high level, so that the capacitor control module is a capacitor When charging, the potential of the COMP point rises.
  • the loop control module thinks that it is necessary to discharge the capacitor, the output Ctrl signal is low level, so that the capacitor control module discharges the capacitor, and the potential of the COMP point decreases.
  • the loop control module detects the COMP potential, controls the working state of the loop, and continuously adjusts the Ctrl signal, so that the system loop can be stabilized.
  • the required capacitance value is very large. If it is integrated inside the chip, it will occupy a considerable area. Therefore, the usual method is to use an external capacitor on the chip. And this method will inevitably lead to an increase in system costs.
  • the purpose of the present invention is to provide a loop control system integrating capacitors, which is used to solve the problem that the capacitors need to occupy a large amount of chip area in the prior art.
  • the present invention provides a loop control system integrating capacitors, the loop control system includes: a loop control module, a capacitor control module, an oscillator module, a counter module and a digital-to-analog conversion module ; the loop control module is used to output a first control signal to the capacitance control module by detecting the state of the COMP signal; the capacitance control module is used to receive the first control signal and send a second control signal to the
  • the oscillator module controls the working state of the oscillator module, and the capacitance control module also outputs a carry-in or step-down control signal to the counter module; the oscillator module is used for generating a pulse signal according to the second control signal to The counter module; the counter module is used to start counting according to the pulse signal, and enter the carry count mode or the abort count mode according to the carry or abort control signal, and finally output several bits of digital logic signals to the digital-analog A conversion module; the digital-to-analog conversion
  • the number of bits of the digital logic signal is configured according to system precision and system speed.
  • the decision to enter the carry count mode or the drop count mode according to the carry or drop control signal further includes: after the counter module receives the carry control signal, it enters the carry count mode, and every time there is a pulse signal input, the The digital logic signal output by the counter module advances by one bit, and after receiving the retreat control signal, the counter module enters the retreat counting mode, and the logic signal output by the counter module retreats one bit each time a pulse signal is input.
  • the digital logic signal output by the counter module is 3-16 bits.
  • the digital logic signal output by the counter module is 3 bits, and each time the counter module receives the pulse signal when the counter module receives the carry control signal, the counter module follows 000, 001, 010, 011, The sequence of 100, 101, 110, and 111 outputs digital logic signals sequentially increasing from the lowest bit 000 or any intermediate state; when the counter module receives the abdication control signal, each time it receives a pulse signal, the counter module follows 111, The sequence of 110, 101, 100, 011, 010, 001, and 000 outputs the digital logic signals that decrease sequentially from the highest bit 111 or any intermediate state.
  • the counter module switches from the current counting mode to the opposite counting mode.
  • the precision of the digital-to-analog conversion module is related to the number of bits of the digital logic signal output by the counter module, and the precision of the digital-to-analog conversion module is improved so that the COMP signal is equal to or tends to be equal to the analog potential. .
  • the COMP signal output by the digital-to-analog conversion module fluctuates in a staircase shape with the change of the counting mode of the counter module, and the number of bits of the digital logic signal output by the counter module is increased to make all
  • the COMP signal change curve is a smooth curve.
  • the loop control module, the capacitance control module, the oscillator module, the counter module and the digital-to-analog conversion module are all integrated in the same chip.
  • controlling the working state of the oscillator module includes: controlling the frequency, duty cycle or/and on-time parameters of the oscillator module.
  • the loop control system of the integrated capacitor of the present invention has the following beneficial effects:
  • the invention provides a loop control system integrating capacitors.
  • the counter module is used to receive a pulse signal from the oscillator module to start Count, and decide to increase or decrease the count according to the carry or abort control signal, and finally output a number of digital logic signals to the digital-to-analog conversion module, and increase the number of bits of the digital logic signal output by the counter module to improve the digital-to-analog conversion.
  • the accuracy of COMP can make the COMP signal close to the analog potential, so as to realize the output, adjustment, receiving feedback and continuous adjustment of the signal of the loop control system, and finally make the loop control system achieve a stable effect.
  • FIG. 1 is a schematic structural diagram of a functional circuit realized by using an external capacitor.
  • FIG. 2 is a schematic diagram showing the working sequence principle of the functional circuit shown in FIG. 1 using an external capacitor.
  • FIG. 3 is a schematic structural diagram of a loop control system integrating capacitors according to an embodiment of the present invention.
  • FIG. 4 is a schematic diagram showing a working sequence principle of the loop control system integrating capacitors according to an embodiment of the present invention.
  • this embodiment provides a loop control system with integrated capacitors.
  • the loop control system includes: a loop control module 101 , a capacitance control module 102 , an oscillator module 103 , a counter module 104 and a digital-analog module Conversion module 105 .
  • the loop control module 101 , the capacitance control module 102 , the oscillator module 103 , the counter module 104 and the digital-to-analog conversion module 105 are all integrated on-chip.
  • the external capacitor is integrated into the same chip, and the external capacitor is saved on the premise of only increasing a small amount of chip area, which greatly reduces the overall cost of the circuit system.
  • the loop control module 101 is configured to output a first control signal to the capacitance control module 102 according to system requirements by detecting the state of the COMP signal.
  • the capacitance control module 102 is connected to the loop control module 101 , the oscillator module 103 and the counter module 104 for receiving the first control signal of the loop control module 101 , and sends a second control signal to the oscillator module 103 to control the working state of the oscillator module 103 , and the capacitance control module 102 also outputs a carry-in or drop-out control signal to the counter module 104 according to system requirements.
  • controlling the working state of the oscillator module 103 includes: controlling the frequency, duty cycle or/and on-time parameters of the oscillator module 103 .
  • the oscillator module 103 is connected to the counter module 104 for generating a required pulse signal OSC to the counter module 104 according to the second control signal sent by the capacitance control module 102 .
  • the oscillator module 103 can convert direct current power into alternating current power with a certain frequency, thereby generating a pulse signal whose magnitude and direction vary with the period.
  • the counter module 104 is connected to the digital-to-analog conversion module 105, and is used to start counting according to the pulse signal received from the oscillator module 103, and enter the carry count according to the carry or drop control signal. In the mode or the abdication counting mode, a digital logic signal of several bits is finally output to the digital-to-analog conversion module 105 .
  • the number of bits of the digital logic signal output by the counter module 104 is configured according to system precision and system speed.
  • the digital logic signal output by the counter module 104 is 3-16 bits.
  • the digital logic signal output by the counter module 104 may also have a higher number of bits, which is not limited to the examples listed here.
  • the decision to enter the carry counting mode or the aborting counting mode according to the carry or abort control signal further includes: after receiving the carry control signal, the counter module 104 enters the carry count mode, and every time a pulse signal is input, the The digital logic signal output by the counter module 104 advances by one bit. After the counter module 104 receives the abdication control signal, it enters the abdication counting mode. Every time a pulse signal is input, the digital logic signal output by the counter module 104 retreats by one bit. .
  • the digital logic signal output by the counter module 104 is 3 bits.
  • the counter module 104 receives the carry control signal, each time it receives a pulse signal, the counter module follows 000, 001, The sequence of 010, 011, 100, 101, 110, and 111 outputs digital logic signals sequentially increasing from the lowest bit 000 or any intermediate state;
  • the counter module 104 receives the abdication control signal, each time it receives the pulse signal, the The counter module outputs a digital logic signal that decreases sequentially from the highest bit 111 or any intermediate state in the order of 111, 110, 101, 100, 011, 010, 001, and 000.
  • the digital-to-analog conversion module 105 is connected to the loop control module 101 for decoding the received digital logic signals of several bits to generate a corresponding COMP signal, the COMP signal Return to the loop control module 101 .
  • the capacitor control module 102 when the loop control module 101 detects the COMP signal voltage and determines that the voltage is insufficient after analysis, the capacitor control module 102 The output control signal is a high level, the oscillator module 103 starts to work, and the required pulse signal is generated according to the system requirements, and the pulse signal is transmitted to the counter module 104 as a clock signal, and the counter module 104 according to the The number of pulses of the pulse signal is processed to carry out or abort, and at the same time, the capacitance control module 102 generates a control signal for the count of carry or abort and transmits it to the counter module 104 .
  • the counter module 104 detects the oscillator pulse signal OSC and the carry or abort control signal, and the output is a digital logic signal of several digits, the digits of which can be chosen according to different requirements such as system accuracy and speed. After the counter module 104 receives the carry control signal, the output digital logic signal advances one bit each time a pulse signal is input, and when the counter module 104 receives the abdication control signal, it outputs a pulse signal each time a pulse signal is input. The digital logic signal is back one bit. Taking the three-bit counter module 104 as an example, when the carry or abort control signal is in the carry state, the digital logic signal it outputs after receiving the pulse signal OSC can be sequentially incremented from the lowest bit 000 or any intermediate state.
  • the digital logic signal The sequence is 000, 001, 010, 011, 100, 101, 110, 111; when the carry or the abdication control signal is in the abdication state, the digital logic signal output after receiving the pulse signal OSC can start from the highest bit 111 or any The intermediate states decrease in sequence, and the sequence of the digital logic signal is 111, 110, 101, 100, 011, 010, 001, 000.
  • the digital logic signal it outputs after receiving the pulse signal OSC can be sequentially incremented from the lowest bit 0000 or any intermediate state
  • the sequence of the digital logic signals is 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111; when the carry-in or back-off control signal is in the back-off state
  • the output digital logic signal can be sequentially decreased from the highest bit 1111 or any intermediate state.
  • the sequence of the digital logic signal is 0111, 0110, 0101, 0100, 0011, 0010, 0001, 0000.
  • the counter module 104 switches from the current counting mode to the opposite counting mode, and the counting mode includes carry counting.
  • Mode and Backoff Counting Mode, Carry Counting Mode and Backoff Counting Mode are mutually opposite counting modes.
  • the digital-to-analog conversion module 105 receives the digital logic signal sequence output by the counter module 104, decodes the digital logic signal sequence, generates an analog output level COMP signal and feeds it back to the loop control module 101, the
  • the precision of the digital-to-analog conversion module 105 is related to the number of digits of the digital logic signal output by the counter module 104, and increasing the number of digits of the digital logic signal sequence output by the counter module 104 can improve the precision of the digital-to-analog conversion module 105, Make the COMP signal equal to or tend to be equal to the analog potential, and the specific number of digits can be selected according to the accuracy requirements of the loop control system and many other requirements.
  • the analog potential COMP signal fluctuates in steps with the change of the counting mode of the counter module 104, and the number of bits of the digital logic signal output by the counter module 104 is increased to make the analog potential COMP signal change
  • the curve is a smooth curve, and the effect is similar to the charging and discharging of the external capacitor.
  • the three-digit counter module 104 is used for explanation and explanation. In actual situations, there may be various options and optimized designs. For example, the frequency of the oscillator module 103 and other information can be changed with the system requirements, more or less pulses are generated in the same time, and the COMP signal voltage value can be increased or decreased more quickly or slowly; The signal is not limited to two states of high and low level, and there can be various combination settings and so on.
  • the present invention provides a loop control system integrating capacitors.
  • the counter module is used to receive the oscillator module.
  • the pulse signal starts to count, and decides to increase or decrease the count according to the carry or abort control signal, and finally outputs a number of digital logic signals to the digital-to-analog conversion module.
  • the invention can integrate the traditional external capacitor into the inside of the chip, save the external capacitor on the premise of only increasing a small amount of chip area, and greatly reduce the overall cost of the circuit system.
  • the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

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Abstract

本发明提供一种集成电容的环路控制系统，配置有环路控制模块、电容控制模块、振荡器模块、计数器模块及数模转换模块，其中，计数器模块用于收到振荡器模块的脉冲信号开始计数，并根据进位或退位控制信号决定计数增加或减少，最终输出若干位的数字逻辑信号至所述数模转换模块，通过增加所述计数器模块输出的数字逻辑信号的位数以提高数模转换的精度，可以使得COMP信号接近模拟电位，从而实现环路控制系统的信号的输出、调整、接收反馈、继续调整，最终使得环路控制系统达到稳定的效果。本发明可以将传统的外置电容集成到芯片的内部，在只增加少量芯片面积的前提下节省掉外置电容，使得电路系统整体成本大幅减小。

Description

一种集成电容的环路控制系统
相关申请的交叉引用
本申请要求于2021年3月30日提交中国专利局、申请号为202110340345.1、发明名称为“一种集成电容的环路控制系统”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于集成电路设计及制造领域，特别是涉及一种集成电容的环路控制系统。
背景技术
在许多电路系统中，为了使电路正常工作，经常会使用到电容来实现补偿、延时、稳压、积分等各种功能，有时需要的电容容值很大，如果集成在芯片内部会占据相当大的面积，因此通常的方法都是使用芯片外接电容的方式实现。
一种采用外接电容实现的功能电路如图1所示，其工作方式举例说明如下：环路控制系统通过检测系统工作状态，根据电路需求输出控制信号Ctrl给电容控制模块。电容控制电路检测到控制信号后对电容进行充电、放电等各种操作，从而改变电容的电特性并输出信号COMP给到环路控制模块。环路控制模块检测到电容的变化会对环路工作模式或状态进行调节，直到系统达到稳定状态。这种信号的输出、调整、接收反馈、继续调整的过程贯穿系统工作的始终。
对于上述电路，其最为常见的工作方式如图2所示，当环路控制模块检测到COMP电压经分析认为需要为电容充电时，会控制Ctrl信号为高电平，从而使电容控制模块为电容充电，COMP点电位升高。当环路控制模块认为需要为电容放电时输出Ctrl信号为低电平，使得电容控制模块为电容放电，COMP点电位降低。环路控制模块检测COMP电位，对环路工作状态进行控制，不断调整Ctrl信号，最终使得系统环路达到稳定等目的。
通常情况下为了保证系统环路的安全稳定，需要的电容容值很大，如果集成在芯片内部会占据相当大的面积，因此通常的方法都是使用芯片外接电容的方式实现。而这种方式必然导致系统成本的增加。
发明内容
鉴于以上所述现有技术的缺点，本发明的目的在于提供一种集成电容的环路控制系统，用于解决现有技术中电容需要占用大量芯片面积的问题。
为实现上述目的及其他相关目的，本发明提供一种集成电容的环路控制系统，所述环路控制系统包括：环路控制模块、电容控制模块、振荡器模块、计数器模块及数模转换模块；所述环路控制模块用于通过检测COMP信号状态，输出第一控制信号至所述电容控制模块；所述电容控制模块用于接收所述第一控制信号并发出第二控制信号至所述振荡器模块，控制所述振荡器模块的工作状态，所述电容控制模块还输出进位或退位控制信号至所述计数器模块；所述振荡器模块用于根据所述第二控制信号产生脉冲信号至所述计数器模块；所述计数器模块用于根据所述脉冲信号开始计数，并根据所述进位或退位控制信号进入进位计数模式或退位计数模式，最终输出若干位的数字逻辑信号至所述数模转换模块；所述数模转换模块用于对接收到的若干位的所述数字逻辑信号进行解码产生COMP信号，所述COMP信号返回至所述环路控制模块。
可选地，所述数字逻辑信号的位数根据系统精度及系统速度进行配置。
可选地，所述根据所述进位或退位控制信号决定进入进位计数模式或退位计数模式，还包括：所述计数器模块接收到进位控制信号后，进入进位计数模式，每次有脉冲信号输入则所述计数器模块输出的数字逻辑信号前进一位，所述计数器模块接收到退位控制信号后，进入退位计数模式，每次有脉冲信号输入则所述计数器模块输出的逻辑信号后退一位。
可选地，所述计数器模块输出的数字逻辑信号为3～16位。
可选地，所述计数器模块输出的数字逻辑信号为3位，所述计数器模块接收到进位控制信号时每次接收到所述脉冲信号后，所述计数器模块按照000、001、010、011、100、101、110、111的顺序输出从最低位000或任意中间态依次递增的数字逻辑信号；所述计数器模块接收到退位控制信号时每次接收到脉冲信号后，所述计数器模块按照111、110、101、100、011、010、001、000的顺序输出从最高位111或任意中间态依次递减的数字逻辑信号。
可选地，所述环路控制模块控制所述进位或退位控制信号翻转后，再次接收到所述脉冲信号后，所述计数器模块从当前的计数模式切换至相反的计数模式。
可选地，所述数模转换模块的精度与所述计数器模块输出的数字逻辑信号的位数相关，提高所述数模转换模块的精度以使得所述COMP信号与模拟电位相等或趋于相等。
可选地，所述数模转换模块输出的所述COMP信号随所述计数器模块的计数模式的变化呈阶梯状起伏变化，增加所述计数器模块输出的所述数字逻辑信号的位数以使所述COMP信号变化曲线呈平滑曲线。
可选地，所述环路控制模块、电容控制模块、振荡器模块、计数器模块及数模转换模块均集成在同一个芯片内部。
可选地，所述控制所述振荡器模块的工作状态包括：控制所述振荡器模块的频率、占空比或/及导通时间参数。
如上所述，本发明的集成电容的环路控制系统，具有以下有益效果：
本发明提供了一种集成电容的环路控制系统，通过配置环路控制模块、电容控制模块、振荡器模块、计数器模块及数模转换模块，计数器模块用于收到振荡器模块的脉冲信号开始计数，并根据进位或退位控制信号决定计数增加或减少，最终输出若干位的数字逻辑信号给所述数模转换模块，通过增加所述计数器模块输出的数字逻辑信号的位数以提高数模转换的精度，可以使得COMP信号接近模拟电位，从而实现环路控制系统的信号的输出、调整、接收反馈、继续调整，最终使得环路控制系统达到稳定的效果。
附图说明
图1显示为一种采用外接电容实现的功能电路的结构示意图。
图2显示为图1所示的采用外接电容实现的功能电路的工作时序原理示意图。
图3显示为本发明实施例的集成电容的环路控制系统的结构示意图。
图4显示为本发明实施例的集成电容的环路控制系统的工作时序原理示意图。
元件标号说明
101                    环路控制模块
102                    电容控制模块
103                    振荡器模块
104                    计数器模块
105                    数模转换模块
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
如图3所示，本实施例提供一种集成电容的环路控制系统，所述环路控制系统包括： 环路控制模块101、电容控制模块102、振荡器模块103、计数器模块104及数模转换模块105。在本公开其它实施方式中，所述环路控制模块101、电容控制模块102、振荡器模块103、计数器模块104及数模转换模块105均为片内集成，本实施例的环路控制系统将外置电容集成到同一个芯片的内部，在只增加少量芯片面积的前提下节省掉外置电容，使得电路系统整体成本大幅减小。
如图3所示，所述环路控制模块101用于通过检测COMP信号状态，根据系统要求输出第一控制信号至电容控制模块102。
如图3所示，所述电容控制模块102连接于所述环路控制模块101、所述振荡器模块103及所述计数器模块104，用于接收环路控制模块101的所述第一控制信号，并发出第二控制信号至所述振荡器模块103，控制振荡器模块103的工作状态，所述电容控制模块102还根据系统要求输出进位或退位控制信号至所述计数器模块104。在本公开其它实施方式中，控制振荡器模块103的工作状态包括：控制振荡器模块103的频率、占空比或/及导通时间参数。
如图3所示，所述振荡器模块103连接于所述计数器模块104，用于根据所述电容控制模块102发出的所述第二控制信号产生所需的脉冲信号OSC至所述计数器模块104。例如，所述振荡器模块103为可以将直流电能转换为具有一定频率的交流电能，从而产生大小和方向均随着周期发生变化的脉冲信号。
如图3所示，所述计数器模块104连接于所述数模转换模块105，用于根据接收到所述振荡器模块103的脉冲信号开始计数，并根据所述进位或退位控制信号进入进位计数模式或退位计数模式，最终输出若干位的数字逻辑信号至所述数模转换模块105。
在本公开其它实施方式中，所述计数器模块104输出数字逻辑信号的位数根据系统精度及系统速度进行配置。例如，所述计数器模块104输出的数字逻辑信号为3～16位。在其他实施例中，所述计数器模块104输出的数字逻辑信号也可以为更高的位数，并不限于此处所列举的示例。
在本公开其它实施方式中，根据进位或退位控制信号决定进入进位计数模式或退位计数模式，还包括：计数器模块104接收到进位控制信号后，进入进位计数模式，每次有脉冲信号输入则所述计数器模块104输出的数字逻辑信号前进一位，所述计数器模块104接收到退位控制信号后，进入退位计数模式，每次有脉冲信号输入则所述计数器模块104输出的数字逻辑信号后退一位。
在本公开其它实施方式中，所述计数器模块104输出的数字逻辑信号为3位，所述计数器模块104接收到进位控制信号时每次接收到脉冲信号后，所述计数器模块按照000、 001、010、011、100、101、110、111的顺序输出从最低位000或任意中间态依次递增的数字逻辑信号；当所述计数器模块104接收到退位控制信号时每次接收到脉冲信号后，所述计数器模块按照111、110、101、100、011、010、001、000的顺序输出从最高位111或任意中间态依次递减的数字逻辑信号。
如图3所示，所述数模转换模块105连接于所述环路控制模块101，用于对接收到的若干位所述数字逻辑信号进行解码，产生相对应的COMP信号，所述COMP信号返回到所述环路控制模块101。
在本公开其它实施方式中，对于本实施例的所述集成电容的环路控制系统，当所述环路控制模块101检测到COMP信号电压，经分析认为其电压不足时，所述电容控制模块102输出控制信号为高电平，所述振荡器模块103开始工作，根据系统需求产生所需的脉冲信号，所述脉冲信号传输至计数器模块104，作为时钟信号，所述计数器模块104根据所述脉冲信号的脉冲个数进行进位或退位处理，同时所述电容控制模块102产生进位或退位计数的控制信号并传输至所述计数器模块104。
所述计数器模块104检测振荡器脉冲信号OSC以及进位或退位控制信号，其输出为若干位数字逻辑信号，其位数可根据系统精度、速度等不同需求自行取舍。当所述计数器模块104接收到进位控制信号以后，每次有脉冲信号输入则其输出的数字逻辑信号前进一位，当计数器模块104接收到退位控制信号以后，每次有脉冲信号输入则其输出的数字逻辑信号后退一位。以三位计数器模块104为例，当进位或退位控制信号处于进位状态时每次接收到脉冲信号OSC后其输出的数字逻辑信号可从最低位000或任意中间态依次递增，所述数字逻辑信号的顺序为000、001、010、011、100、101、110、111；当进位或退位控制信号处于退位状态时每次接收到脉冲信号OSC后其输出的数字逻辑信号可从最高位111或任意中间态依次递减，所述数字逻辑信号的顺序为111、110、101、100、011、010、001、000。又如，当所述计数器模块104为4位时，当进位或退位控制信号处于进位状态时每次接收到脉冲信号OSC后其输出的数字逻辑信号可从最低位0000或任意中间态依次递增，所述数字逻辑信号的顺序为0000、0001、0010、0011、0100、0101、0110、0111、1000、1001、1010、1011、1100、1101、1110、1111；当进位或退位控制信号处于退位状态时每次接收到脉冲信号OSC后其输出的数字逻辑信号可从最高位1111或任意中间态依次递减，所述数字逻辑信号的顺序为1111、1110、1101、1100、1011、1010、1001、1000、0111、0110、0101、0100、0011、0010、0001、0000。所述环路控制模块101控制所述进位或退位控制信号翻转后，再次接收到所述脉冲信号后，所述计数器模块104从当前的计数模式切换至相反的计数模式，该计数模式包括进位计数模式和退位计数模式，进位计数模式与 退位计数模式为互为相反的计数模式。
所述数模转换模块105接收所述计数器模块104输出的数字逻辑信号数列，并对该数字逻辑信号数列进行解码，生成模拟输出电平COMP信号并反馈到所述环路控制模块101，所述数模转换模块105的精度与所述计数器模块104输出的数字逻辑信号的位数相关，增加所述计数器模块104输出的数字逻辑信号数列的位数可以提高所述数模转换模块105的精度，使得COMP信号与模拟电位相等或趋于相等，具体位数可根据环路控制系统的精度要求等诸多需求进行选择。
上述采用3位计数器模块104的环路控制系统的工作时序原理图如图4所示，由图4的Ctrl曲线、OSC曲线、进退位曲线、D0曲线、D1曲线及D2曲线可以看出的，当所述计数器模块104接收到进位控制信号Ctrl以后，每次有脉冲信号输入则其输出的数字逻辑信号前进一位，当计数器模块104接收到退位控制信号Ctrl以后，每次有脉冲信号输入则其输出的数字逻辑信号后退一位。由COMP曲线可以看出，模拟电位COMP信号随所述计数器模块104的计数模式的变化呈阶梯状起伏，增加所述计数器模块104输出的数字逻辑信号的位数以使所述模拟电位COMP信号变化曲线呈平滑曲线，得到与外接电容进行充放电相似的效果。
上述为便于理解仅以三位的计数器模块104进行说明讲解，在实际情况中可以有多种选择及优化设计。例如振荡器模块103的频率等信息可以随系统需求而变化，相同时间内产生更多或更少的脉冲个数，可以更迅速或缓慢地增大或减小COMP信号电压值；进位或退位控制信号也不局限于高低电平两种状态，可以有多种组合设置等。
如上所述，本发明提供了一种集成电容的环路控制系统，通过配置环路控制模块、电容控制模块、振荡器模块、计数器模块及数模转换模块，计数器模块用于收到振荡器模块的脉冲信号开始计数，并根据进位或退位控制信号决定计数增加或减少，最终输出若干位的数字逻辑信号至所述数模转换模块，通过增加所述计数器模块输出的数字逻辑信号的位数以提高数模转换的精度，可以使得COMP信号接近模拟电位，从而实现环路控制系统的信号的输出、调整、接收反馈、继续调整，最终使得环路控制系统达到稳定的效果。本发明可以将传统的外置电容集成到芯片的内部，在只增加少量芯片面积的前提下节省掉外置电容，使得电路系统整体成本大幅减小。
所以，本发明有效克服了现有技术中的种种缺点而具高度产业利用价值。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，举凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成 的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (13)

  1. 一种集成电容的环路控制系统，其特征在于，所述环路控制系统包括：环路控制模块、电容控制模块、振荡器模块、计数器模块及数模转换模块；
    所述环路控制模块用于通过检测COMP信号状态，输出第一控制信号至所述电容控制模块；
    所述电容控制模块用于接收所述第一控制信号并发出第二控制信号至所述振荡器模块，控制所述振荡器模块的工作状态，所述电容控制模块还输出进位或退位控制信号至所述计数器模块；
    所述振荡器模块用于根据所述第二控制信号产生脉冲信号至所述计数器模块；
    所述计数器模块用于根据所述脉冲信号开始计数，并根据所述进位或退位控制信号进入进位计数模式或退位计数模式，最终输出若干位的数字逻辑信号至所述数模转换模块；
    所述数模转换模块用于对接收到的若干位的所述数字逻辑信号进行解码产生COMP信号，所述COMP信号返回至所述环路控制模块。
  2. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述数字逻辑信号的位数根据系统精度及系统速度进行配置。
  3. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述根据所述进位或退位控制信号决定控制进入进位计数模式或退位计数模式，还包括：所述计数器模块接收到进位控制信号后，进入进位计数模式，每次有脉冲信号输入则所述数字逻辑信号前进一位；所述计数器模块接收到退位控制信号后，进入退位计数模式，每次有脉冲信号输入则所述数字逻辑信号后退一位。
  4. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述计数器模块输出的数字逻辑信号为3～16位。
  5. 根据权利要求4所述的集成电容的环路控制系统，其特征在于：所述计数器模块输出的数字逻辑信号为3位，所述计数器模块接收到进位控制信号时每次接收到脉冲信号后，所述计数器模块按照000、001、010、011、100、101、110、111的顺序输出从最低位000或任意中间态依次递增的数字逻辑信号；所述计数器模块接收到退位控制信号时每次接收到脉冲信号后，所述计数器模块按照111、110、101、100、011、010、001、000的顺序输出从最高位111或任意中间态依次递减的数字逻辑信号。
  6. 根据权利要求4所述的集成电容的环路控制系统，其特征在于：所述计数器模块输出的数字逻辑信号为4位，所述计数器模块接收到进位控制信号时每次接收到脉冲信号后，所述计数器模块按照0000、0001、0010、0011、0100、0101、0110、0111、1000、1001、1010、1011、1100、1101、1110、1111的顺序输出从最低位0000或任意中间态依次递增的数字逻辑信号；所述计数器模块接收到退位控制信号时每次接收到脉冲信号后，所述计数器模块按照1111、1110、1101、1100、1011、1010、1001、1000、0111、0110、0101、0100、0011、0010、0001、0000的顺序输出从最高位1111或任意中间态依次递减的数字逻辑信号。
  7. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述环路控制模块控制所述进位或退位控制信号翻转后，再次接收到所述脉冲信号后，所述计数器模块从当前的计数模式切换至相反的计数模式。
  8. 根据权利要求7所述的集成电容的环路控制系统，其特征在于：所述进位计数模式与所述退位计数模式互为相反的计数模式。
  9. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述数模转换模块的精度与所述计数器模块输出的数字逻辑信号的位数相关，提高所述数模转换模块的精度以使得所述COMP信号与模拟电位相等或趋于相等。
  10. 根据权利要求9所述的集成电容的环路控制系统，其特征在于：增加所述计数器模块输出的数字逻辑信号的位数提高所述数模转换模块的精度。
  11. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述数模转换模块输出的所述COMP信号随所述计数器模块的计数模式的变化呈阶梯状起伏变化，增加所述计数器模块输出的所述数字逻辑信号的位数以使所述COMP信号变化曲线呈平滑曲线。
  12. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述环路控制模块、电容控制模块、振荡器模块、计数器模块及数模转换模块均集成在同一个芯片内部。
  13. 根据权利要求1所述的集成电容的环路控制系统，其特征在于：所述控制所述振荡器模块的工作状态包括：控制所述振荡器模块的频率、占空比或/及导通时间参数。
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CN107426881A (zh) * 2017-09-07 2017-12-01 上海晶丰明源半导体股份有限公司 积分器、led电流纹波消除电路和方法、led驱动器及led设备
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