WO2022205220A1 - 均衡器参数的调整方法、训练序列的发送方法及装置 - Google Patents

均衡器参数的调整方法、训练序列的发送方法及装置 Download PDF

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Publication number
WO2022205220A1
WO2022205220A1 PCT/CN2021/084742 CN2021084742W WO2022205220A1 WO 2022205220 A1 WO2022205220 A1 WO 2022205220A1 CN 2021084742 W CN2021084742 W CN 2021084742W WO 2022205220 A1 WO2022205220 A1 WO 2022205220A1
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equalizer
data
training sequence
fixed pattern
pattern data
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PCT/CN2021/084742
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English (en)
French (fr)
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孙达
曹炜
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华为技术有限公司
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Priority to PCT/CN2021/084742 priority Critical patent/WO2022205220A1/zh
Priority to CN202180094538.1A priority patent/CN116888932A/zh
Publication of WO2022205220A1 publication Critical patent/WO2022205220A1/zh

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/01—Equalisers

Definitions

  • the present application relates to the field of communication technologies, and in particular, to a method for adjusting parameters of an equalizer, a method and an apparatus for sending a training sequence.
  • the equalizer is a filter with adjustable parameters set in the communication system.
  • the typical function of an equalizer is to reduce intersymbol interference.
  • Adaptive equalization is a technique that automatically adjusts the parameters of an equalizer based on channel characteristics. By adjusting the parameters of the equalizer based on the adaptive equalization, it helps the equalizer to adapt to the dynamic change of the channel characteristics, so that the equalizer has better performance.
  • a typical method for adjusting equalizer parameters based on adaptive equalization technology is: the transmitter sends a training sequence to the receiver, and the training sequence is a string of random data. After the receiving end obtains the training sequence through equalizer processing, the receiving end measures the magnitude of the interference of each data signal corresponding to the training sequence to each subsequent data signal. The receiving end adjusts the parameters of the equalizer according to the magnitude of the interference.
  • Embodiments of the present application provide a method for adjusting parameters of an equalizer, a method and a device for sending a training sequence, which can improve the accuracy of adjusting parameters of the equalizer.
  • the technical solution is as follows.
  • a method for adjusting parameters of an equalizer is provided.
  • the method is, for example, applied to a receiving end of a training sequence.
  • the method specifically includes: acquiring a training sequence processed by a first equalizer; the first position in the sequence; determine the inter-symbol interference generated by the fixed pattern data at the second position; and adjust the parameters of the first equalizer according to the inter-symbol interference.
  • the training sequence includes fixed pattern data
  • the second position is a position after the first position in the training sequence
  • the above method increases the fixed pattern data in the training sequence, because the fixed pattern data realizes the effect of amplifying and superimposing the inter-symbol interference at the trailing, thereby reducing the technical difficulty of measuring the inter-symbol interference at the trailing, so determined.
  • the accuracy of the inter-symbol interference at the trailing position is higher, so adjusting the equalizer parameters according to the inter-symbol interference can effectively improve the accuracy of parameter adjustment.
  • the principle of amplifying and superimposing the intersymbol interference at the tail by the fixed pattern data is that, according to the principle of a linear system, the signal received by the receiving end is the convolution of the signal sent by the transmitting end and the channel impulse response. . After the flat part (ie, the low frequency part) of the channel impulse response is convolved with the transmitted signal, the high frequency part of the transmitted signal will be filtered, and the low frequency part of the transmitted signal will be preserved.
  • the signal strengths (probabilities) of various frequency points in the transmitted signal of the classical training sequence are basically the same. If the proportion of the low frequency signal is increased in the training sequence, the low frequency response of the channel will be enhanced in the received signal, so the error caused by the tailing of the channel impulse response will be amplified.
  • Fixed pattern data refers to data in which the pattern remains unchanged for multiple unit time periods.
  • the waveform of a signal carrying a fixed pattern of data is similar to that of direct current, approximating a straight line.
  • the unit time period is, for example, a unit time interval (unit interval, UI), and a UI is a time length corresponding to one bit.
  • the fixed pattern data is a series of consecutive 1s; or the fixed pattern data is a series of consecutive 0s.
  • the above-mentioned second position is not a position inside the fixed pattern data.
  • the above-mentioned second position is a position in random data.
  • the first position is the position of the last bit of the fixed pattern data, random data starts after the last bit of the fixed pattern data, and the second position is one bit in the random data.
  • the fixed pattern data includes consecutive identical data of at least 4 UIs.
  • the fixed pattern data is at least 4 bits of consecutive 0s, and for another example, the fixed pattern data is at least 4 bits of consecutive 1s.
  • the training sequence sequentially includes a first data segment in the fixed pattern data, random data, a second data segment in the fixed pattern data, and random data.
  • the training sequence includes at least 4 bits of consecutive 1-random data-at least 4 bits of consecutive 0-random data.
  • the method for determining the position (first position) of the fixed pattern data in the training sequence includes: searching for one or more times in the training sequence, thereby determining the position with the greatest probability of containing the fixed pattern data as the first position.
  • the first position is determined by template matching. Specifically, each continuous symbol in the training sequence is compared with the pre-stored fixed pattern data to obtain the probability that each continuous symbol contains the fixed pattern data, and the symbol bit with the highest probability is used as the first position .
  • the first position is determined in a manner similar to a binary search.
  • the training sequence into multiple subsequences, count the number of consecutive 1s (or 0s) in each subsequence in the training sequence, and determine whether the number of consecutive 1s (or 0s) in each subsequence in the training sequence exceeds the set number A fixed number; if the number of consecutive 1s (or 0s) in a certain subsequence in the training sequence exceeds the set number, it is determined that the fixed pattern data belongs to this subsequence, and then the subsequence is further divided, and continuous 1s are counted. (or 0). And so on, continue to narrow the scope of statistics, and finally locate the first position.
  • the parameter of the first equalizer is, for example, a degeneration resistor (Rs) or a degeneration capacitor (Cs).
  • the method for determining the inter-symbol interference generated by the fixed code pattern data at the second position includes: according to the voltage of the data at the second position and the reference voltage. correlation to determine intersymbol interference.
  • the above method can convert the voltage of the data from an analog signal to a judgment result in a digital form, which is convenient for counting by a counter, etc., so the difficulty of counting inter-symbol interference is greatly reduced, and the implementation complexity is reduced.
  • the reference voltage includes a first reference voltage and a second reference voltage, the voltage values of the first reference voltage and the second reference voltage are not equal, and the trailing error caused by the fixed pattern data is determined in the following manner:
  • the reference voltage is the judgment threshold, and the data at the second position is compared to obtain the first judgment result;
  • the second reference voltage is used as the judgment threshold, and the data at the second position is compared to obtain the second judgment result;
  • the first judgment result The total number with the same value as the second judgment result is taken as the first total number; the total number with different values in the first and second judgment results is taken as the second total number; according to the first total number and the second total number to determine the inter-symbol interference, wherein the inter-symbol interference is positively correlated with the first total number, and the inter-symbol interference is negatively correlated with the second total number.
  • the above method can accurately determine the inter-symbol interference at the tail, and effectively solve the problem that the noise intensity of the inter-symbol interference cannot be effectively measured.
  • the adjustment method of the parameters of the first equalizer includes: if the inter-symbol interference is less than the set interference threshold, reducing the parameters of the first equalizer; if the inter-symbol interference is greater than the set interference threshold, increasing the first equalizer.
  • the above method is helpful to solve the problem of insufficient equalization or excessive equalization of the equalizer, and to improve the channel equalization performance of the equalizer.
  • the training sequence is obtained by processing the first equalizer and the second equalizer, the training sequence also includes random data, and the receiving end also adjusts the second equalizer according to the error corresponding to one or more symbol bits in the random data. parameter.
  • the random data is, for example, a pseudo-random sequence.
  • random data is a 56-bit random 0 or 1.
  • the error brought by the random data is specially used to adjust the parameters of the second equalizer
  • the error brought by the fixed pattern data is specially used to adjust the parameters of the first equalizer, so that the first equalizer and the second equalizer can be adjusted.
  • the parameter adjustment process will not interfere with each other, and the system in which the first equalizer and the second equalizer coexist is supported, which facilitates parameter adjustment of the two equalizers at the same time.
  • one or more sign bits in the random data include a first sign bit
  • a method for adjusting the parameters of the second equalizer includes: adjusting the second equalizer according to the correlation between the error corresponding to the first sign bit and the sign value.
  • the parameter of the equalizer, the sign value is the value on the sign bit before the first sign bit in the random data, and the parameter of the second equalizer is negatively correlated with the correlation amount.
  • the above method can decouple the functions of the first equalizer and the second equalizer to avoid mutual interference between the first equalizer and the second equalizer, so that the parameters of the first equalizer and the second equalizer can be adjusted more accurately.
  • the adjustment method of the parameters of the second equalizer includes: according to the correlation between the error corresponding to the i-th symbol bit and the symbol value on the (i-m) symbol bits, adjusting the m-th tap of the second equalizer.
  • Parameters, i and m are both positive integers.
  • the distance between the second position and the first position is greater than N symbols, where N is the number of taps of the second equalizer.
  • the second equalizer is responsible for eliminating the inter-symbol interference caused by the fixed pattern data to the subsequent N symbol bits, while the first equalizer is responsible for eliminating the code generated by the fixed pattern data for the subsequent symbol bits starting from N+1 symbols. Interference between the first equalizer and the second equalizer is decoupled. Since the influence of channel equalization of the second equalizer is hardly introduced during parameter adjustment, the parameters of the first equalizer are adjusted more accurately.
  • the second position is the N+1th sign bit after the first position.
  • the above method can ensure the accuracy of parameter adjustment, and at the same time avoid the huge computational overhead caused by the detection of inter-symbol interference in a large number of positions.
  • the length ratio between the fixed pattern data and the random data in the training sequence is 1:7.
  • a typical training frame of length 128 bits it contains 8 bits of 11111111 (fixed pattern data), followed by 56 bits of random 0 or 1 (random data), followed by 8 bits of 00000000 (fixed pattern data), and finally a 56-bit random 0 or 1 (random data).
  • the above method ensures the rationality of the ratio of fixed pattern data to random data, avoids that the proportion of fixed pattern data is too small to increase the training time, and at the same time avoids that the proportion of fixed pattern data is too large to weaken the randomness of the training sequence.
  • the length of the fixed pattern data is between 4 bits and 16 bits.
  • the fixed pattern data includes a first data segment and a second data segment
  • the second data segment is data obtained by inverting each bit in the first data segment.
  • the first data segment is, for example, a data segment composed of at least 4 consecutive 1s
  • the second data segment is, for example, a data segment composed of at least 4 consecutive 0s.
  • the content of the first data segment includes one 0, and the rest of the first data segment is 1; the content of the second data segment includes one 1, and the rest of the second data segment is 0.
  • the content of the first data segment includes two 1s, and the rest of the first data segment is 0; the content of the second data segment includes two 0s, and the rest of the second data segment is 1.
  • the above method balances the number of 0s and the number of 1s, that is, the number of 0s and 1s in the fixed pattern data is almost the same, thereby eliminating the direct current (DC) offset (DC offset) of the signal.
  • the above-mentioned second equalizer is a decision feedback equalizer DFE.
  • the above-mentioned first equalizer is a continuous time linear equalizer CTLE.
  • serializer/deserializer serializer/deserializer
  • a method for sending a training sequence is provided.
  • a training sequence is generated, the training sequence includes fixed pattern data, the fixed pattern data is in a first position in the training sequence, and the fixed pattern data is in the first position.
  • the intersymbol interference generated by the two positions is used to adjust the parameters of the first equalizer, the second position is the position after the first position in the training sequence, and the first equalizer is the equalizer set in the receiving end of the training sequence; send the training sequence .
  • the above method increases the fixed pattern data in the training sequence, because the fixed pattern data realizes the effect of amplifying and superimposing the inter-symbol interference at the trailing, thereby reducing the technical difficulty of measuring the inter-symbol interference at the trailing, so determined.
  • the accuracy of the inter-symbol interference at the trailing position is higher, so adjusting the equalizer parameters according to the inter-symbol interference can effectively improve the accuracy of parameter adjustment.
  • the first position is the position of the last bit of the fixed pattern data
  • the second position is the position of random data in the training sequence.
  • the training sequence further includes random data, and errors corresponding to one or more symbol bits in the random data are used to adjust parameters of the second equalizer, which is an equalizer set at the receiving end of the training sequence.
  • the error brought by the random data is specially used to adjust the parameters of the second equalizer
  • the error brought by the fixed pattern data is specially used to adjust the parameters of the first equalizer, so that the first equalizer and the second equalizer can be adjusted.
  • the parameter adjustment process will not interfere with each other, and the system in which the first equalizer and the second equalizer coexist is supported, which facilitates parameter adjustment of the two equalizers at the same time.
  • the length ratio between the fixed pattern data and the random data in the training sequence is 1:7.
  • the above length ratio can better take into account the training time and data randomness, and has wider applicability.
  • the length of the fixed pattern data is between 4 bits and 16 bits.
  • the fixed pattern data includes a first data segment and a second data segment
  • the second data segment is data obtained by inverting each bit in the first data segment.
  • the above method balances the number of 0s and the number of 1s, that is, the number of 0s and 1s in the fixed pattern data is almost the same, thereby eliminating the direct current (DC) offset (DC offset) of the signal.
  • an apparatus for adjusting parameters of an equalizer in a third aspect, is provided, and the apparatus for adjusting parameters of an equalizer has the function of implementing the first aspect or any optional manner of the first aspect.
  • the apparatus for adjusting parameters of the equalizer includes at least one unit, and the at least one unit is configured to implement the method provided in the first aspect or any optional manner of the first aspect.
  • an apparatus for sending a training sequence in a fourth aspect, is provided, and the apparatus for sending a training sequence has a function of implementing the second aspect or any optional manner of the second aspect.
  • the apparatus for sending a training sequence includes at least one unit, and the at least one unit is configured to implement the method provided in the second aspect or any optional manner of the second aspect.
  • the units in the apparatus for sending training sequences are implemented by software, and the units in the apparatus for sending training sequences are program modules. In other embodiments, the units in the apparatus for transmitting the training sequence are implemented by hardware or firmware.
  • a fifth aspect provides an electronic device, the electronic device includes a processor and a first equalizer, the processor is configured to execute an instruction, so that the electronic device executes the first aspect or any optional manner of the first aspect.
  • the method provided is that the first equalizer is used to process the obtained training sequence.
  • the electronic device further includes a second equalizer.
  • the second equalizer is used to cooperate with the first equalizer, so as to process and obtain the training sequence.
  • an electronic device in a sixth aspect, includes a processor and a communication interface, the processor is configured to execute an instruction, so that the electronic device executes the second aspect or any optional manner of the second aspect.
  • the communication interface is used to send the training sequence.
  • a seventh aspect provides a computer-readable storage medium, where at least one instruction is stored in the storage medium, and when the instruction is executed on a computer, causes the computer to execute the above-mentioned first aspect or any optional manner of the first aspect. provided method.
  • a computer-readable storage medium in which at least one instruction is stored, and when the instruction is run on a computer, the computer executes the second aspect or any of the optional methods of the second aspect. provided method.
  • a computer program product includes one or more computer program instructions, when the computer program instructions are loaded and run by a computer, the computer can execute the first aspect or any one of the first aspects.
  • the method provided by the selection method is provided.
  • a tenth aspect provides a computer program product, the computer program product includes one or more computer program instructions, when the computer program instructions are loaded and run by a computer, the computer program can execute the second aspect or any one of the second aspects.
  • the method provided by the selection method is not limited to:
  • a chip including a memory and a processor, where the memory is used to store computer instructions, and the processor is used to call and run the computer instructions from the memory, so as to execute the above-mentioned first aspect and any possibility of the first aspect. method in the implementation.
  • a twelfth aspect provides a chip, including a memory and a processor, the memory is used to store computer instructions, and the processor is used to call and run the computer instructions from the memory to execute the above second aspect or any one of the second aspects Methods provided by optional methods.
  • a communication system includes the equalizer parameter adjustment apparatus of the third aspect and the training sequence transmission apparatus of the fourth aspect.
  • a fourteenth aspect provides a communication system including the electronic device of the fifth aspect and the electronic device of the sixth aspect.
  • an apparatus for adjusting parameters of an equalizer is provided, and the apparatus can be provided as a receiving end of a training sequence, for example, a receiving end of a SERDES.
  • the device for adjusting parameters of the equalizer includes: a first equalizer, a fixed code pattern data positioning circuit, an error detection circuit, and an equalizing parameter adjusting circuit, and each hardware in the device for adjusting parameters of the equalizer is used to implement the above-mentioned first aspect or the first aspect any of the methods provided by the alternative.
  • the apparatus for adjusting parameters of the equalizer further includes a second equalizer and a least mean square (least mean square, LMS) adjusting circuit.
  • LMS least mean square
  • a sixteenth aspect provides an apparatus for sending a training sequence, and the apparatus can be provided as a sending end of a training sequence, for example, a sending end of a SERDES.
  • the apparatus for sending training sequences includes: a training sequence generator and a transmitting circuit. Each piece of hardware in the apparatus is used to implement the method provided in the first aspect or any optional manner of the first aspect.
  • a communication system comprising the apparatus of the fifteenth aspect and the apparatus of the sixteenth aspect, the communication system may be provided as a SERDES.
  • FIG. 1 is a schematic diagram of an intersymbol interference phenomenon provided by an embodiment of the present application.
  • FIG. 2 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • FIG. 3 is a flowchart of a method for adjusting an equalizer parameter provided by an embodiment of the present application
  • FIG. 4 is a schematic diagram of a format of a training sequence provided by an embodiment of the present application.
  • FIG. 5 is an architecture diagram of a SERDES system provided by an embodiment of the present application.
  • FIG. 6 is a schematic diagram of a data positioning waveform provided by an embodiment of the present application.
  • FIG. 7 is a schematic structural diagram of an apparatus for sending a training sequence provided by an embodiment of the present application.
  • FIG. 8 is a schematic structural diagram of an apparatus for adjusting parameters of an equalizer provided by an embodiment of the present application.
  • the training sequence is a data sequence used to adjust the parameters of the receiver equalizer.
  • the training sequence is carried in the data frame sent by the sender.
  • the frame header (frame head) carries the training sequence, and the training sequence is followed by service data.
  • the training sequence occupies one or more consecutive symbols in the data frame.
  • the role of the training sequence includes, but is not limited to, training at the receiving end (that is, adjusting the parameters of the equalizer), channel estimation, and the like.
  • a pattern refers to the waveform of a signal representing data.
  • the signal includes, but is not limited to, a radio frequency signal in the field of wireless communication, an electrical signal or an optical signal in the field of wired communication, and the like.
  • a high level represents data "1”
  • a low level represents data "0”
  • waveforms such as high and low levels are patterns.
  • Fixed pattern data refers to data in which the pattern remains unchanged for multiple unit time periods.
  • the unit time period is, for example, a unit time interval (unit interval, UI), and a UI is a time length corresponding to one bit.
  • the fixed pattern data is binary data.
  • the values of multiple consecutive bits in the fixed pattern data remain unchanged.
  • the values of N consecutive bits in the fixed pattern data are all 1, or the values of N consecutive bits in the fixed pattern data are all 0, and N is a positive integer greater than or equal to 2.
  • the value of each bit in the fixed pattern data is the same.
  • the fixed pattern data is a series of consecutive 1s; or the fixed pattern data is a series of consecutive 0s.
  • the fixed pattern data is 11111111.
  • most of the bits in the fixed pattern data have the same value, and a small number of bits with different values from other bits are allowed.
  • the fixed pattern data is 11111101.
  • the waveform of the signal carrying fixed pattern data is similar to the waveform of direct current, and the waveform of the signal carrying fixed pattern data approximates a straight line in multiple unit time periods.
  • the waveform of the signal carrying fixed pattern data is high level in multiple unit time periods; for another example, the waveform of the signal carrying fixed pattern data is low level in multiple unit time periods.
  • the fixed pattern data includes consecutive identical data of at least 4 UIs.
  • the fixed pattern data is at least 4 bits of consecutive 0s, and for another example, the fixed pattern data is at least 4 bits of consecutive 1s.
  • ISI Inter-symbol interference
  • Inter-symbol interference means that due to unsatisfactory channel characteristics, the waveform of the symbol is distorted and broadened, and the waveform of the previous symbol has a long tail, which spreads to the sampling time of the current symbol. Judgment interferes. For example, as shown in Figure 1, when the sender sends a high-level signal (digital signal 1), it will continue to pull up the level of the following signal after passing through the channel; otherwise, the sender sends a low-level signal (digital signal 1). 0), after passing through the channel, the level of the following signal will be pulled down.
  • An equalizer is a filter whose parameters can be adjusted.
  • the equalizer is usually set at the receiving end of the communication system, and the equalizer usually works in the baseband signal processing unit or the intermediate frequency signal processing unit in the receiving end.
  • the typical role of an equalizer is to reduce or even eliminate intersymbol interference.
  • the basic principle of the equalizer to reduce the intersymbol interference is that the equalizer will generate a characteristic approximately opposite to the channel characteristic, thereby compensating for the channel characteristic and correcting the distorted waveform. Among them, the characteristics of the equalizer are reflected by the parameters of the equalizer.
  • Decision is a process of comparing the voltage of the data with the decision threshold.
  • a typical implementation of the decision is to compare the voltage of the data with the decision threshold; if the voltage of the data is greater than the decision threshold, the decision result is determined to be 1; if the voltage of the data is less than or equal to the decision threshold, the decision result is determined to be 0.
  • the decision threshold refers to the reference voltage used in the decision.
  • the decision threshold is also called the decision threshold.
  • CTLE is an analog equalizer.
  • CTLE can be realized by active circuit or passive circuit.
  • CTLE acts as a combination of high pass filter and amplifier.
  • the basic principle of CTLE is that when a signal transmitted on a channel is received, CTLE first amplifies the entire signal proportionally, and then CTLE filters the amplified signal through a high-pass filter. When the signal passes through the CTLE, the low-frequency components are attenuated more, and the high-frequency components are attenuated less, thereby compensating for the loss of high-frequency components.
  • DFE is a digital equalizer.
  • DFE includes finite-length unit impulse response (finite impulse response, FIR) filter, adder and decider.
  • FIR finite impulse response
  • the role of DFE is usually to enhance high-frequency components and increase the energy ratio of high-frequency components to low-frequency components.
  • Serializer and deserializer (serializer/deserializer, SERDES)
  • SERDES is a serial high-speed interface in a chip.
  • SERDES are used in serial wired communication systems.
  • SERDES includes two components: sender and receiver.
  • the transmitter and receiver of SERDES are usually located in two physical devices.
  • the transmitter of SERDES includes a feed-forward equalizer (FFE).
  • FFE feed-forward equalizer
  • the receiving end of SERDES includes CTLE and DFE. Usually, when the receiving end of the SERDES receives a signal, it first processes the signal through the CTLE, then processes the signal output by the CTLE through the DFE, and then samples the signal output by the DFE to obtain the data carried by the signal.
  • FIG. 1 is a signal waveform diagram. Among the two waveforms in FIG. 1 , one waveform represents the digital pulse signal sent by the transmitting end, and the other waveform represents the signal received by the receiving end.
  • This channel-widened signal will interfere with adjacent signals, and the noise generated by the interference between the transmitted data is called inter-symbol interference.
  • the technical means of eliminating inter-symbol interference is called channel equalization, which can adjust the strength of high-frequency signals and low-frequency signals to be consistent.
  • the modules commonly used for channel equalization include FFE, DFE and CTLE.
  • FFE and DFE are equalization filters of digital circuit properties
  • CTLE is an equalization filter of analog circuit properties.
  • CTLE is an equalizer implemented by a pure analog circuit, compared to digital equalizers such as FFE and DFE, CTLE currently does not have an effective adjustment algorithm and adjustment strategy that automatically adapts to channel characteristics. This problem has long been a problem for SERDES systems. a difficulty and pain point.
  • this embodiment proposes a new method for effectively adjusting CTLE equalization parameters in a SERDES system.
  • the method is applied to scenarios where parameters of other equalizers other than CTLE are adjusted.
  • the method is applied to other wired or wireless communication systems than the SERDES system.
  • FIG. 2 is a schematic diagram of an application scenario provided by an embodiment of the present application.
  • the application scenario shown in FIG. 2 includes a first device 200 and a second device 210 .
  • the application scenario is, for example, a wireless network communication scenario or a wired network communication scenario.
  • the typical product forms, internal components and connection relationships of the first device 200 and the second device 210 are illustrated below with examples.
  • the first device 200 is any device having a wireless communication function or a wired communication function.
  • the product form of the first device 200 includes many situations.
  • the first device 200 is user equipment.
  • the first device 200 is a tablet computer, a desktop computer, a laptop computer, a notebook computer, an Ultra-mobile Personal Computer (UMPC), a handheld computer, a netbook, a Personal Digital Assistant (PDA), Internet-connected user devices such as mobile phones.
  • the first device 200 is an IoT node in the Internet of Things, or an in-vehicle communication device in the Internet of Vehicles.
  • the first device 200 is a communication entity such as a communication server, a router, a switch, and a network bridge, or the first device 200 may include various forms of macro base stations, micro base stations, relay stations, and the like.
  • the first device 200 can optionally be a complete device, or a chip or a processing system installed in the complete device, and the device installed with these chips or processing systems can implement this function under the control of these chips or processing systems. The methods and functions of the application embodiments.
  • the first device 200 includes at least one processor 201 , a memory 202 and a communication interface 203 .
  • the processor 201 is, for example, a general-purpose central processing unit (central processing unit, CPU), a network processor (network processor, NP), a graphics processing unit (graphics processing unit, GPU), a neural-network processing unit (neural-network processing units, NPU) ), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the solution of the present application.
  • the processor 201 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.
  • the memory 202 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or a device that can store information and instructions.
  • ROM read-only memory
  • RAM random access memory
  • Other types of dynamic storage devices such as electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, optical disks storage (including compact discs, laser discs, compact discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer without limitation.
  • the memory 202 exists independently and is connected to the processor 201 through an internal connection 204 .
  • the memory 202 and the processor 201 are optionally integrated.
  • the memory 202 stores program codes 206 involved in implementing the method for sending the training sequence provided by the embodiment of the present application.
  • the memory 202 is used to store fixed pattern data.
  • the Communication interface 203 uses any transceiver-like device for communicating with other devices or a communication network.
  • the communication interface 203 includes, for example, at least one of a wired communication interface or a wireless communication interface.
  • the wired communication interface is, for example, an Ethernet interface.
  • the Ethernet interface is, for example, an optical interface, an electrical interface or a combination thereof.
  • the wireless communication interface is, for example, a wireless local area network (wireless local area network, WLAN) interface, a cellular communication interface, or a combination thereof.
  • the second device 210 is any device having a wired communication function or a wireless communication function.
  • the product form of the second device 210 includes many situations.
  • the second device 210 is user equipment.
  • the second device 210 is a tablet computer, a desktop computer, a laptop computer, a notebook computer, an Ultra-mobile Personal Computer (UMPC), a handheld computer, a netbook, a Personal Digital Assistant (PDA), Internet-connected user devices such as mobile phones.
  • the second device 210 is an IoT node in the Internet of Things, or an in-vehicle communication device in the Internet of Vehicles.
  • the second device 210 is a communication entity such as a communication server, a router, a switch, and a network bridge, or the second device 210 may include various forms of macro base stations, micro base stations, relay stations, and the like.
  • the second device 210 can optionally be a device of a whole machine, or a chip or a processing system installed in the whole device, and the device with these chips or processing systems installed can realize this function under the control of these chips or processing systems.
  • the second device 210 includes at least one processor 211 , a memory 212 and a communication interface 213 .
  • the processor 211 is, for example, a general-purpose central processing unit (central processing unit, CPU), a network processor (network processor, NP), a graphics processing unit (graphics processing unit, GPU), a neural-network processing unit (neural-network processing units, NPU) ), a data processing unit (DPU), a microprocessor or one or more integrated circuits for implementing the solution of the present application.
  • the processor 211 includes an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof.
  • the PLD is, for example, a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.
  • the memory 212 is, for example, a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, or a random access memory (RAM) or a device that can store information and instructions.
  • ROM read-only memory
  • RAM random access memory
  • Other types of dynamic storage devices such as electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disk storage, optical disks storage (including compact discs, laser discs, compact discs, digital versatile discs, Blu-ray discs, etc.), magnetic disk storage media, or other magnetic storage devices, or capable of carrying or storing desired program code in the form of instructions or data structures and capable of Any other medium accessed by a computer without limitation.
  • the memory 212 exists independently and is connected to the processor 211 through an internal connection 214 .
  • the memory 212 and the processor 211 are optionally integrated together.
  • the memory 212 stores program codes 216 involved in implementing the method for adjusting the equalizer parameters provided by the embodiments of the present application.
  • the communication interface 213 includes a first equalizer 2131 .
  • the communication interface 213 further includes a second equalizer 2132 .
  • Both the first equalizer 2131 and the second equalizer 2132 are used for channel equalization to eliminate or reduce the influence of inter-symbol interference.
  • the first equalizer 2131 is an equalizer realized by an analog circuit.
  • the second equalizer 2132 is an equalizer realized by a digital circuit.
  • the first equalizer 2131 or the second equalizer 2132 includes, without limitation, a time domain equalizer or a frequency domain equalizer.
  • the first equalizer 2131 or the second equalizer 2132 includes, without limitation, a linear equalizer or a nonlinear equalizer.
  • the first equalizer 2131 or the second equalizer 2132 includes, without limitation, a linear transversal equalizer, a linear lattice equalizer, a decision feedback equalizer, or a fractionally spaced equalizer.
  • the Communication interface 213 uses any transceiver-like device for communicating with other devices or a communication network.
  • the communication interface 213 includes, for example, at least one of a wired communication interface or a wireless communication interface.
  • the wired communication interface is, for example, an Ethernet interface.
  • the Ethernet interface is, for example, an optical interface, an electrical interface or a combination thereof.
  • the wireless communication interface is, for example, a wireless local area network (wireless local area network, WLAN) interface, a cellular communication interface, or a combination thereof.
  • the first device and the second device are connected through a channel.
  • the access is achieved through a wired network and/or a wireless network.
  • the wired network is, for example, a network based on electrical signal communication or a network based on optical signal communication.
  • a wireless network is, for example, a network based on radio frequency signal communication.
  • the application scenario shown in FIG. 2 is specifically a SERDES system.
  • the first device plays the role of a transmitter in the SERDES system, and the first device is also called a serializer in the SERDES system.
  • the second device plays the role of a receiver in the SERDES system, and the second device is also called a deserializer in the SERDES system.
  • the first device includes an FFE or other equalizer.
  • the first equalizer 2131 in the second device is CTLE.
  • the second equalizer in the second device is a DFE.
  • FIG. 3 is a flowchart of a method for adjusting parameters of an equalizer provided by an embodiment of the present application. The method shown in FIG. 3 includes the following steps S301 to S307.
  • the method shown in FIG. 3 involves interaction between multiple devices.
  • first device and “second device” are used to distinguish and describe multiple different devices.
  • the method shown in FIG. 3 mainly concerns how the second device adjusts the parameters of the equalizer by using the training sequence sent by the first device.
  • the embodiment shown in FIG. 3 does not limit the order of each step (S303 to S306) performed by the receiving end.
  • S303 to S306 are not necessarily performed sequentially, and the execution order of S303 to S306 can also be interchanged.
  • the scenario on which the method shown in FIG. 3 is based is optionally shown in FIG. 2 .
  • the first device in the method shown in FIG. 3 is the first device 200 in FIG. 2
  • the second device in the method shown in FIG. 3 is the second device in FIG. 2 device 210.
  • the first equalizer in the method shown in FIG. 3 is the first equalizer 2131 in FIG. 2
  • the second equalizer in the method shown in FIG. 3 is the second equalizer 2132 in FIG. 2 .
  • the method shown in FIG. 3 may be implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • the processor 211 in the second device implements steps S303 to S307 in the method shown in FIG. 3 by reading the program code 216 stored in the memory 212, or the processor 211 reads the program code stored in the internal storage. Steps S303 to S307 in the method shown in FIG. 3 are implemented.
  • the physical structure of the processor 211 is designed by means of algorithm hardware, so that the processor 211 is a hardware accelerator dedicated to adjusting the parameters of the equalizer.
  • the processor 211 independently completes the following steps S303 to S307, or the processor 211 cooperates with the CPU to complete the following steps S303 to S307.
  • the processor 211 is configured to execute steps S303 to S305 according to the instruction of the CPU, and send the determined ISI to the CPU.
  • the CPU is responsible for executing step S306.
  • Step S301 the first device generates a training sequence, where the training sequence includes fixed pattern data.
  • How the first device obtains the fixed code pattern data includes multiple implementation manners, and the following is an example of implementation manner a and implementation manner b.
  • the fixed pattern data is preset.
  • the administrator configures the fixed pattern data for the first device through a command line, a user interface or other means, and the first device generates a training sequence according to the preconfigured fixed pattern data.
  • the first device sends a plurality of candidate fixed pattern data to the second device in advance.
  • the second device selects one fixed pattern data from a plurality of candidate fixed pattern data, and sends the selected fixed pattern data to the first device.
  • the first device generates the training sequence according to the fixed pattern data selected by the second device.
  • the second device needs to train the equalizer, the second device actively sends the fixed pattern data to the first device, and the first device generates the above-mentioned training sequence according to the fixed pattern data sent by the second device.
  • the fixed pattern data includes a first data segment and a second data segment.
  • the second data segment is data obtained by inverting each bit in the first data segment.
  • the first data segment and the second data segment have an inverse relationship with each other. Specifically, if the value of the i-th bit in the first data segment is 0, the value of the i-th bit in the second data segment is 1; if the value of the i-th bit in the first data segment is 1 , the value of the i-th bit in the second data segment is 0.
  • the number of 0s and the number of 1s are balanced, that is, the number of 0s and 1s in the fixed pattern data is almost the same, thereby eliminating the direct current (DC) deviation of the signal ( DC offset).
  • the content of each bit in the first data segment is 1, and the content of each bit in the second data segment is 0.
  • P_DC_SEG positive direct current segment, positive DC data segment
  • N_DC_PATTERN negative direct current segment, negative DC segment
  • RANDOM_SEG in FIG. 4 is a specific example of random data.
  • P_DC_SEG is 8 11111111
  • N_DC_SEG is 8 00000000
  • 00000000 is the data obtained by inverting each bit in 11111111.
  • the fixed pattern data is located at the head of the training frame.
  • the first data segment in the fixed pattern data is located from the 1st bit to the nth bit in the training frame, where n is the length of the first data segment.
  • the header of a training frame includes 8 11111111 (the first data segment in the fixed pattern data). In this way, after receiving the training frame, the receiving end can find the fixed pattern data more quickly starting from the first bit of the training frame.
  • the fixed pattern data is located at the end of the training frame.
  • the fixed pattern data is located at the center of the training frame.
  • the fixed pattern data is located in a set position of the training frame, for example, the set position is the position sent by the receiver to the transmitter, or the position preconfigured by the administrator at the receiver and the transmitter.
  • the receiving end announces the identification of position i to the transmitting end, and after receiving the identification of position i, the transmitting end sets bits starting from the i-th bit in the training frame as fixed pattern data.
  • the content of the first data segment is mostly ones, with a small number of zeros allowed.
  • the content of the second data segment is mainly 0, and a small amount of 1 is allowed.
  • the content of the first data segment includes one 0, and the rest of the first data segment is 1; the content of the second data segment includes one 1, and the rest of the second data segment is 0.
  • the first data segment is 11111101 and the second data segment is 00000010.
  • the first data segment is 11111011, and the second data segment is 00000100.
  • the content of the first data segment includes two 1s, and the rest of the first data segment is 0; the content of the second data segment includes two 0s, and the rest of the second data segment is 1 .
  • the first data segment is 11110101 and the second data segment is 00001010.
  • a small number of 0s appear in the first data segment, and a small number of 1s appear in the second data segment, which helps the training sequence to match the situation where there are reflection points on the channel, and helps the solution support more scenarios.
  • the training sequence also includes random data.
  • the random data is a pseudo-random sequence.
  • the random data is binary data.
  • RANDOM_SEG in FIG. 4 is a specific example of random data, and RANDOM_SEG is 56-bit random 0 or 1. Since the intensity of each frequency point in the frequency spectrum of the random data signal is the same, the random data signal is closer to the data signal of the actual service.
  • the data transmission scene in the actual service can be effectively simulated to ensure balanced
  • the adjustment of the parameters of the controller better matches the actual business scenario, which helps to improve the adjustment effect of the parameters.
  • How the first device generates random data includes multiple ways, and two ways are used as examples below.
  • the first device includes a pseudo-random code training sequence generator, and the first device generates random data through the pseudo-random code training sequence generator.
  • Implementation Mode 2 The first device scatters the service data to obtain random data. Wherein, breaking up is, for example, changing the arrangement order of different values in the business data.
  • the second device restores the random data to obtain the service data before being scattered.
  • random data and fixed pattern data appear alternately in the training sequence.
  • random data is located between the first data segment and the second data segment in the training sequence.
  • the training sequence includes such data structures: P_DC_SEG (the first data segment in the fixed pattern data) - RANDOM_SEG (random data) - N_DC_SEG (the second data segment in the fixed pattern data) ) - RANDOM_SEG (random data).
  • the length of the fixed pattern data is between 4 bits and 16 bits.
  • the length of the fixed pattern data is 4 bits, 8 bits or 16 bits.
  • the length of the fixed pattern data is 4 bits, 8 bits or 16 bits.
  • it contains 8 bits of 11111111 (fixed pattern data), followed by 56 bits of random 0 or 1 (random data), followed by 8 bits of 00000000 (fixed pattern data), and finally a 56-bit random 0 or 1 (random data).
  • How to determine the length of the above-mentioned fixed pattern data includes various implementation manners.
  • an administrator configures the length of the above-mentioned fixed pattern data in the first device.
  • the first device (sending end) and the second device (receiving end) determine the length of the above-mentioned fixed code pattern data through negotiation.
  • the length ratio between the fixed pattern data and the random data in the training sequence is 1:7.
  • the length of the fixed pattern data is 8 bits
  • the length of the random data is 56 bits.
  • the above length ratio can better take into account the training time and data randomness, and has wider applicability.
  • the random data and the fixed pattern data are sent cyclically according to a training frame (training frame, TF) as a unit.
  • the training sequence includes one or more consecutive TFs, and each TF includes random data and fixed pattern data.
  • the fixed pattern data in each TF in the same training sequence is the same.
  • the training sequence includes N training frames, which are training frame 1, training frame 2...training frame N respectively. Training frame 1, training frame 2... each training frame in training frame N contains the same P_DC_SEG, and each training frame in training frame 1, training frame 2... training frame N contains the same N_DC_SEG.
  • the administrator configures the length of the TF in the first device.
  • the first device (sending end) and the second device (receiving end) determine the length of a TF through negotiation.
  • the length of one TF is 128 bits.
  • Step S302 the first device sends a training sequence.
  • Step S303 the second device acquires the training sequence obtained by processing the first equalizer.
  • Step S304 the second device determines the first position where the fixed pattern data is located in the training sequence.
  • first position refers to the position where the fixed pattern data is located in the training sequence.
  • second position refers to the position where the fixed pattern data is located in the training sequence. How to determine the above-mentioned first position includes various ways. Specifically, since the fixed pattern data belongs to the low frequency pattern, the attenuation of the channel is very small, and a stable period occurs, so the position of the fixed pattern data can be locked through periodic cyclic detection. The specific implementation manner of determining the first position is illustrated below by way of implementation manner A and implementation manner B.
  • the second device stores the fixed pattern data in advance, and the fixed pattern data stored in advance by the second device can be understood as a template. After the second device acquires the training sequence, the second device compares each segment of consecutive symbols in the training sequence with the pre-stored fixed pattern data. Through the comparison, the second device obtains the probability that each segment of consecutive symbols in the training sequence is fixed pattern data. The second device determines the position with the highest probability from the training sequence, and uses the position with the highest probability as the position of the fixed pattern data (the first position).
  • the second device divides the training sequence into a plurality of subsequences.
  • the second device counts the number of consecutive 1s in each subsequence in the training sequence, and the second device determines whether the number of consecutive 1s in each subsequence in the training sequence exceeds the set number; if a certain subsequence in the training sequence contains consecutive 1s If the number exceeds the set number, it is determined that the fixed pattern data belongs to the subsequence. After that, the subsequence is further divided, and the number of consecutive 1s continues to be counted.
  • the scope of statistics is continuously narrowed, and finally fixed pattern data is located.
  • the counted objects are replaced from 1s to 0s, such as counting the number of consecutive 0s in each subsequence in the training sequence.
  • the position of the fixed code pattern data is locked, and the position of the fixed code pattern data can play the role of a reference position, which is convenient for locating the position (second position) of the subsequent data statistics, thereby facilitating the determination of inter-symbol interference. .
  • Step S305 the second device determines the intersymbol interference generated by the fixed code pattern data at the second position.
  • the second position is the position after the fixed pattern data in the training sequence, that is, the position after the above-mentioned first position.
  • the second position is the position where the receiver (the second device) performs error detection.
  • the distance between the second position and the first position is greater than N symbols.
  • the training sequence includes M symbols in total
  • the fixed pattern data is located between the a-th symbol to the b-th symbol
  • the second position is between the (b+N)-th symbol bit and the M-th symbol bit in the training sequence.
  • Location. N is a positive integer.
  • N is a positive integer greater than or equal to 2.
  • N is the tap number (tap number) of the second equalizer.
  • the scheme supports a system in which the first equalizer and the second equalizer coexist, and the first equalizer and the second equalizer can be improved.
  • the overall parameter adjustment effect of the equalizer is that, since the first equalizer and the second equalizer equalize the signal at the same time, the parameter adjustment process of the two equalizers often interferes with each other, resulting in the two equalizers. There are technical difficulties in adjusting the parameters of each equalizer at the same time.
  • the second equalizer in the process of receiving the training sequence at the receiving end, is responsible for eliminating the inter-symbol interference caused by the fixed pattern data to the subsequent N symbol bits, and the first An equalizer is responsible for eliminating the intersymbol interference caused by the fixed pattern data starting from N+1 symbols to subsequent symbol bits, so that the functions of the first equalizer and the second equalizer are decoupled. Therefore, in the parameter adjustment process, the influence of the two equalizers, the first equalizer and the second equalizer, can be distinguished.
  • the first equalizer can be adjusted more accurately. Equalizer parameters.
  • the second position is the N+1th sign bit after the first position.
  • the fixed pattern data is located in the a-th symbol to the b-th symbol, and the second position is the (b+N+1)-th symbol bit in the training sequence.
  • the technical principle to achieve this effect is that the inter-symbol interference of the fixed pattern data to the subsequent symbol bits gradually decreases. In each symbol bit starting from the N+1th symbol bit, the N+1th symbol The inter-symbol interference on the bit is the largest and can best represent the influence of the overall noise at the tail. Therefore, adjusting the parameters of the first equalizer according to the inter-symbol interference on the N+1 symbol bit can ensure the accuracy of parameter adjustment and avoid Huge computational overhead for detecting intersymbol interference over a large number of locations.
  • the second position includes not only the N+1 th sign bit after the first position, but also the sign bit after the N+1 th sign bit.
  • the second device determines the inter-symbol interference of the N+1 th symbol bit and the N+2 th symbol bit after the first position, and the second device performs an average operation on the two inter-symbol interferences or A summation operation is performed, and the parameters of the first equalizer are adjusted according to the operation result.
  • the second device determines intersymbol interference at the second location based on a correlation between the voltage of the data at the second location and the reference voltage.
  • the voltage value of the reference voltage is optionally preset.
  • the reference voltage is pre-stored in the second device.
  • the reference voltage acts as a decision threshold.
  • the correlation between the voltage of the data and the reference voltage is specifically the numerical value relationship between the voltage of the data and the reference voltage.
  • the reference voltage includes a first reference voltage and a second reference voltage.
  • the voltage values of the first reference voltage and the second reference voltage are not equal.
  • the first reference voltage and the second reference voltage optionally have preset voltage values.
  • the roles of the first reference voltage and the second reference voltage are different.
  • the first reference voltage is used to determine the value of the data at the second location.
  • the first reference voltage is also sometimes referred to as the center level or "0" level.
  • the function of the first reference voltage is similar to the zero point of the coordinate system, and other voltage values inside the receiving end are relative voltage values with respect to the first reference voltage.
  • the second reference voltage is used to determine whether the data at the second position is positive or negative.
  • the second reference voltage is also sometimes referred to as a desired level or a target level.
  • Using the first reference voltage and the second reference voltage to determine the inter-symbol interference includes: taking the first reference voltage as the decision threshold, comparing the data at the second position to obtain the first decision result; taking the second reference voltage as the decision threshold , compare the data at the second position to obtain the second judgment result; take the total number of the same value in the first judgment result and the second judgment result as the first total number; use the first judgment result and the second judgment result
  • the total number with different median values is taken as the second total number; the inter-symbol interference is determined according to the first total number and the second total number.
  • the inter-symbol interference is positively correlated with the first total number, and the inter-symbol interference is negatively correlated with the second total number.
  • the first decision result indicates a numerical relationship between the voltage of the data at the second position and the first reference voltage.
  • the second decision result indicates the numerical relationship between the data at the second position and the second reference voltage.
  • the following describes the process of determining the inter-symbol interference by using a formula as an example.
  • the following formula 1 is a specific example of determining the ISI by using the first reference voltage and the second reference voltage.
  • tail_err ⁇ M(p_tail_i)*C(p_tail_i)- ⁇ M(n_tail_i)*C(n_tail_i); formula 1;
  • tail_err is the intersymbol interference generated by the fixed pattern data at the second position
  • the physical meaning of tail_err is the error caused by the tailing of the channel impulse response
  • tail_err is used to evaluate the amount of ISI tailing noise.
  • the literal translation of tail is the tail, which is the second position mentioned above.
  • the meaning of err is error (error), that is, the above-mentioned inter-symbol interference.
  • p in p_tail represents P_DC_SEG (the first data segment in the fixed pattern data).
  • p_tail indicates the position where the trailing phenomenon occurs in the P_DC_SEG, and p_tail is specifically the N+1 th symbol bit after the first data segment.
  • n_tail_i represents the p_tail in the ith training frame in a training sequence.
  • n in n_tail represents N_DC_SEG (the second data segment in the fixed pattern data).
  • n_tail indicates the position where the trailing phenomenon occurs in N_DC_SEG, and n_tail is specifically the N+1 th symbol bit after the second data segment.
  • n_tail_i represents the n_tail in the ith training frame in a training sequence.
  • N_DC_SEG will make the data voltage on n_tail lower than expected.
  • C represents the decision result at the center level, that is, the above-mentioned first decision result.
  • M represents the decision result at the desired level, that is, the above-mentioned second decision result.
  • * means multiply.
  • the physical meaning of multiplying C and M is to calculate the same total number of M and C minus the total number of different M and C.
  • ⁇ is the summation symbol, and the range of the summation can be optionally set according to requirements, for example, the range of the summation is an integer multiple of the training frame.
  • Step S306 the second device adjusts the parameters of the first equalizer according to the intersymbol interference generated by the fixed pattern data at the second position.
  • the above-mentioned inter-symbol interference is specifically used in a scenario in which two equalizer parameters, a degeneration resistor (Rs) and a degeneration capacitor (Cs), are adjusted.
  • Rs degeneration resistor
  • Cs degeneration capacitor
  • the adjustment of equalizer parameters is achieved by setting a threshold for intersymbol interference.
  • the second device compares the intersymbol interference generated at the second location with a set interference threshold. If the inter-symbol interference is less than the set interference threshold, the second device reduces the parameters of the first equalizer; if the inter-symbol interference is greater than the set interference threshold, the second device increases the parameters of the first equalizer; if the inter-symbol interference is greater than the set interference threshold, the second device increases the parameters of the first equalizer; equal to the set interference threshold, the second device keeps the parameters of the first equalizer unchanged.
  • the aforementioned disturbance thresholds are sometimes referred to as error target values, error expectations, or error expectations.
  • the interference threshold is, for example, a small positive number.
  • the interference threshold is optionally set according to specific circuit characteristics of the first equalizer and the second device.
  • Adjusting the parameters of the first equalizer in the above manner helps to improve the channel equalization performance of the first equalizer.
  • the principle of achieving this technical effect is that when the first equalizer is insufficiently equalized, the intersymbol interference obtained by statistics at the second position will be very positive, so increase the equalization parameter of the first equalizer, that is, increase the high frequency part. gain or increase the attenuation of the low-frequency part to solve the lack of equalization.
  • the equalization of the first equalizer is too large, the intersymbol interference obtained by statistics at the second position will be a random number near 0 with a small absolute value.
  • by reducing the equalization parameter of the first equalizer that is, reducing The gain of the high frequency part or the attenuation of the low frequency part is reduced, so as to solve the situation of excessive equalization.
  • this embodiment also relates to a parameter adjustment process of the second equalizer.
  • the above training sequence is obtained by processing the first equalizer and the second equalizer.
  • the second device not only uses the fixed pattern data in the training sequence processed by the first equalizer and the second equalizer to perform the above-mentioned parameter adjustment process of the first equalizer, but also uses the first equalizer and the second equalizer
  • the random data in the obtained training sequence is processed to adjust the parameters of the second equalizer.
  • Step S307 the second device adjusts the parameters of the second equalizer according to the errors corresponding to one or more symbol bits in the random data.
  • the second device determines the parameters of the second equalizer by counting the correlation between the received error of each symbol bit and the value of each preceding symbol. For example, the second device adjusts the parameters of the second equalizer according to the correlation between the error corresponding to the first sign bit in the random data and the sign value.
  • the first sign bit is a sign bit in the random data.
  • the sign value is the value on one or more sign bits preceding the first sign bit in the random data.
  • the parameters of the second equalizer are inversely related to the correlation amount.
  • the parameter determination process of the second equalizer specifically includes: the second device adjusts the second equalizer according to the correlation between the error corresponding to the ith symbol bit and the symbol values on the (im) symbol bits Parameters for the mth tap.
  • i and m are both positive integers.
  • the principle of this approach is that the product S(in)*E(i) is inversely proportional to the coefficient of the nth tap of the second equalizer.
  • E(i) is the error of the symbol at the i-th position measured by the receiving end, and S(in) represents the symbol value S(in) at the in-th position. Therefore, the coefficient adaptive adjustment of the n-th tap of the second equalizer can be accomplished through the statistical value ⁇ i S(in)E(i) of the random data.
  • the parameter adjustment process of the second equalizer is implemented by a least mean square (least mean square, LMS) algorithm.
  • LMS least mean square
  • the LMS algorithm is an adaptive equalization algorithm based on the minimum average error.
  • the second device after determining the intersymbol interference generated by the fixed code pattern data at the second position, the second device also uses the intersymbol interference at the second position as the noise margin of the system, and outputs the noise margin of the system.
  • S306 and S307 are performed sequentially. For example, S306 is performed first, and then S307 is performed; for another example, S307 is performed first, and then S306 is performed. In other embodiments, S306 and S307 are executed in parallel, that is, the second device executes S306 and S307 at the same time.
  • the fixed pattern data can realize the effect of amplifying and superimposing the intersymbol interference at the trailing, thereby reducing the technical difficulty of measuring the intersymbol interference at the trailing , so the accuracy of the determined inter-symbol interference at the tail is higher, so adjusting the equalizer parameters according to the inter-symbol interference can effectively improve the accuracy of parameter adjustment.
  • the noise intensity of the inter-symbol interference at each position cannot be effectively measured due to the influence of the accuracy of the receiver decider. This is because the intersymbol interference effect at the trailing point is manifested as the superposition of many small noises, that is, the intersymbol interference value of each tap is very small, but the accumulation is very large. In a large range, the effect of the equalizer will make the statistical intersymbol interference at the tail be a random number close to 0, so it is difficult to obtain accurate equalizer parameters.
  • the signal received by the receiver is the convolution of the signal sent by the transmitter and the channel impulse response.
  • the flat part (ie, the low frequency part) of the channel impulse response is convolved with the transmitted signal, the high frequency part of the transmitted signal will be filtered, and the low frequency part of the transmitted signal will be preserved.
  • the signal strengths (probabilities) of various frequency points in the transmitted signal of the classical training sequence are basically the same. If the proportion of the low frequency signal is increased in the training sequence, the low frequency response of the channel will be enhanced in the received signal, so the error caused by the tailing of the channel impulse response will be amplified.
  • the inter-symbol interference at the smear can basically be greater than the detection accuracy of the decider, and the inter-symbol interference at the smear can be determined more accurately. Therefore, using a more accurate Intersymbol interference obviously enables more precise adjustment of equalizer parameters.
  • FIG. 5 is an architecture diagram of a SERDES system
  • FIG. 5 is a specific example of FIG. 2 .
  • FIG. 5 includes a transmitter 500 of the SERDES system and a receiver 510 of the SERDES system.
  • the transmitting end 500 of the SERDES system is a specific example of the first device.
  • the receiving end 510 of the SERDES system is a specific example of the second device.
  • the transmitter 500 includes a training sequence generator 501 .
  • the training sequence generator 501 is a specific example of the processor 201 in FIG. 2 .
  • step S301 is implemented by, for example, the training sequence generator 501 .
  • the training sequence generator 501 is used to generate training sequences.
  • the training sequence generator 501 specifically includes a random data generator 5011 , a fixed pattern data memory 5021 and a fixed pattern data memory 5022 .
  • the random code generator 5011 is used to generate random data.
  • the fixed code data memory 5021 is used to store the configured fixed code data P_DC_CODE (positive DC data segment, ie, the first data segment).
  • the fixed pattern data storage 5021 is, for example, a configurable register, or other storage such as a memory, a cache, and a flash memory.
  • the fixed code data memory 5022 is used to store the configured fixed code data N_DC_CODE (negative DC data segment, that is, the second data segment).
  • the fixed pattern data memory 5022 and the fixed pattern data memory 5021 are different or the same memory.
  • the fixed pattern data storage 5022 is, for example, a configurable register, or other storage such as a memory, a cache, and a flash memory.
  • the receiving end 510 includes a receiving circuit 5110, a CTLE 5131, a DFE 5132, an LMS adaption circuit 5113, a fixed pattern data positioning circuit 5111, an error detection circuit 5112, and an equalization parameter adjustment circuit 5114.
  • the receiving circuit 5110 is used to provide the received data signal to the CTLE 5131 and the DFE 5132.
  • Both CTLE 5131 and DFE 5132 are used for channel equalization. Specifically, after the data signal provided by the receiving circuit 5110 is processed by the CTLE 5131 and the DFE 5132, the training sequence is obtained by performing judgment and sampling.
  • the fixed pattern data positioning circuit 5111 is used to locate the fixed pattern data in the training sequence, that is, to determine the first position of the fixed pattern data in the training sequence. For example, referring to Fig. 4, the fixed code pattern data location circuit 5111 realizes the detection and location of P_DC_CODE and N_DC_CODE in the training code stream. In the method shown in FIG. 3 , step S304 is implemented, for example, by the fixed code pattern data positioning circuit 5111 .
  • the error detection circuit 5112 is used to determine the inter-symbol interference caused by the fixed pattern data at the second position, that is, to determine the error at the tail caused by the fixed pattern data. For example, referring to FIG. 4 , the error detection circuit 5112 is used to detect the error caused by the interference of P_DC_CODE or N_DC_CODE to adjacent random codes. The error detection circuit 5112 is also used to provide the detected error to the equalization parameter adjustment circuit. In the method shown in FIG. 3 , step S305 is implemented by, for example, the error detection circuit 5112 .
  • the equalization parameter adjustment circuit 5114 is configured to adjust the parameters of the first equalizer according to the intersymbol interference. For example, the equalization parameter adjustment circuit 5114 is used to adjust the CTLE coefficients.
  • the LMS adjustment circuit 5113 is configured to adjust the parameters of the second equalizer according to the error corresponding to one or more sign bits in the random data. For example, the LMS adjustment circuit 5113 completes the DFE coefficient adjustment by using the classical LMS algorithm. In the method shown in FIG. 3 , step S307 is implemented by, for example, the LMS adjustment circuit 5113 .
  • the method for adjusting the parameters of the equalizer in the above-mentioned SERDES system is described below.
  • the method includes the following steps (1) to (4).
  • Step (1) When the SERDES system is initialized for equalization parameter training, the transmitter sends a training sequence.
  • the training sequence includes consecutive TFs.
  • Each TF includes three parts: P_DC_SEG, N_DC_SEG and RANDOM_SEG.
  • the P_DC_SEGs of the TFs in a training sequence are all the same, and the N_DC_SEGs are all the same.
  • the code (code) value of the P_DC_SEG is preset in advance, or is the code value that needs to be sent as fed back by the receiving end.
  • N_DC_SEG is the sequence obtained by inverting each bit of P_DC_CODE.
  • RANDOM_SEG is a pseudo-random sequence.
  • RANDOM_SEG is optionally a pseudorandom sequence generated by a pseudorandom code generator.
  • RANDOM_SEG is a pseudo-random data sequence generated after some valid data sent to the receiver is broken up.
  • the data in the RANDOM_SEG of TF in a training data sequence are all pseudo-randomly generated or randomly scattered data.
  • Step (2) The receiver locks the P_DC_SEG position and the N_DC_SEG position.
  • the receiver checks the received data periodically according to the length of TF.
  • the receiving end performs the following steps S302 to S304 on the received equalized data to complete the adjustment of the equalization parameters of the CTLE.
  • the equalized data is obtained, for example, by performing data decision sampling after the received signal passes through CTLE and then DFE.
  • the receiving end uses template matching to compare each segment of consecutive symbols with P_DC_SEG/N_DC_SEG to find the position with the highest probability of P_DC_SEG/N_DC_SEG.
  • the receiving end obtains a waveform as shown in FIG. 6 , according to which the position of each received bit in the current TF can be located.
  • FIG. 6 shows a digital control signal waveform, the unit of the horizontal coordinate is UI or time, the vertical coordinate is 0 and 1, the low voltage is 0, and the high voltage is 1.
  • the receiving end is convenient to determine the position of p_tail and the position of n_tail in step S304, so as to count tail_err according to the position of p_tail and the position of n_tail.
  • P_DC_SEG/N_DC_SEG can also be avoided when the DFE coefficient is adjusted.
  • P_DC_SEG/N_DC_SEG is non-random data, although theoretically it has no effect on the adaptive adjustment of DFE coefficients, but because it is different from the actual application data, the data of RANDOM_SEG is closer to the actual data, so the more appropriate method is to use only RANDOM_SEG for The adjustment of the DFE coefficient avoids the data influence of P_DC_SEG/N_DC_SEG.
  • Step (3) The receiving end adaptively adjusts the parameters of the DFE.
  • the data in the RANDOM_SEG is a long random sequence, and the receiving end adopts the LMS algorithm to complete the adaptive adjustment of the parameters of the DFE by counting the data in the RANDOM_SEG.
  • the LMS algorithm estimates the coefficient of the DFE by counting the correlation between the received error of each symbol and the value of each preceding symbol.
  • the principle is that the product S(in)*E(i) of the symbol error (E(i)) at the i-th position measured by the receiving end and the symbol value S(in) at the previous in-th position and
  • the coefficient of the nth tap of the DFE is inversely proportional, so the adaptive adjustment of the coefficient of the nth tap of the DFE can be accomplished through the statistical value ⁇ i S(in)E(i) of the random sequence.
  • Step (4) The receiving end adjusts the parameters of the CTLE adaptively.
  • the DFE can cancel the interference (ISI) caused by the preceding N symbols of each symbol in the training code stream received by the receiving end to this symbol.
  • DFE has eliminated the ISI generated by P_DC_SEG and N_DC_SEG for the following N symbols, so the goal of CTLE is to eliminate the ISI effect of P_DC_SEG and N_DC_SEG on the following symbol positions starting from N+1. Because this influence shows a gradually decreasing trend with the trend, it is important to detect the error at the N+1 position.
  • the N+1th position after P_DC_SEG and N_DC_SEG is called p_tail and n_tail. According to the above formula 1, the tail data is counted, and tail_err is obtained.
  • the method provided in the above example is applied in a SERDES system with DFE off or without DFE.
  • the method provided by the above example provides a new SERDES training sequence, and the random sequence includes fixed pattern data and random data.
  • the fixed pattern data can achieve the effect of amplifying and superimposing the ISI at the trailing position, that is, amplifying the noise at the trailing ISI. Therefore, technical problems such as difficulty in self-adapting adjustment of CTLE parameters and poor adjustment accuracy can be solved.
  • This method can not only reduce the training time of CTLE, but also find the optimal parameters of CTLE more accurately, thus effectively improving the effect of CTLE self-adaptation and enhancing the equalization performance of SERDES system.
  • FIG. 7 is a schematic structural diagram of an apparatus for sending a training sequence provided by an embodiment of the present application.
  • the apparatus 700 shown in FIG. 7 is the first device 200 in FIG. 2 .
  • the apparatus 700 shown in FIG. 7 is used to implement the function of the first device in the method shown in FIG. 3 .
  • the apparatus 700 implements the functions of the sending end 500 in FIG. 5 .
  • the apparatus 700 includes a generating unit 701 and a sending unit 702 .
  • the generating unit 701 is configured to support the apparatus 700 to execute S301.
  • the sending unit 702 is configured to support the apparatus 700 to execute S302.
  • Each unit in the apparatus 700 is implemented in whole or in part by software, hardware, firmware or any combination thereof.
  • the apparatus embodiment described in FIG. 7 is only illustrative.
  • the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or may be Integration into another system, or some features can be ignored, or not implemented.
  • Each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned units in FIG. 7 can be implemented either in the form of hardware or in the form of software functional units.
  • the generating unit 701 is implemented by the random code generator 5011 , the configurable register 5021 and the configurable register 5021 in FIG. 5 .
  • the above-mentioned generating unit 701 may be generated by at least one processor 201 of the first device 200 in FIG. 2 after reading the program code stored in the memory 202.
  • the above units in FIG. 7 may also be implemented by different hardware in FIG. 2, for example, the generating unit 701 is composed of a part of the processing resources (for example, in a multi-core processor) of at least one processor 201 of the first device 200 in FIG. 2. one core or two cores), or by the rest of the processing resources (such as other cores in a multi-core processor) in at least one processor 201 of the first device 200 in FIG.
  • the sending unit 702 is implemented by the communication interface 203 of the first device 200 in FIG. 2 .
  • the above functional units can also be implemented by a combination of software and hardware.
  • the sending unit 702 is implemented by a hardware programmable device, and the generating unit 701 is a software functional unit generated after the CPU reads the program code stored in the memory.
  • FIG. 8 is a schematic structural diagram of an apparatus for adjusting parameters of an equalizer provided by an embodiment of the present application.
  • the apparatus 800 shown in FIG. 7 is the second device 210 in FIG. 2 .
  • the apparatus 800 shown in FIG. 7 is used to implement the function of the second device in the method shown in FIG. 3 .
  • the apparatus 800 implements the function of the receiving end 510 in FIG. 5 .
  • the apparatus 800 includes an acquisition unit 801 , a determination unit 802 , and an adjustment unit 803 .
  • the obtaining unit 801 is configured to support the apparatus 800 to execute S303.
  • the determining unit 802 is configured to support the apparatus 800 to perform S304 to S305.
  • the adjustment unit 803 is used to support the apparatus 800 to execute S306.
  • the adjustment unit 803 is further configured to support the apparatus 800 to perform S307.
  • Each unit in the apparatus 800 is implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • the apparatus embodiment described in FIG. 8 is only illustrative.
  • the division of the above-mentioned units is only a logical function division. In actual implementation, there may be other division methods.
  • multiple units or components may be combined or may be Integration into another system, or some features can be ignored, or not implemented.
  • Each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically alone, or two or more units may be integrated into one unit.
  • the above-mentioned units in FIG. 8 can be implemented either in the form of hardware or in the form of software functional units.
  • the acquisition unit 801 is implemented by CTLE 5131 and DFE 5132 in FIG. 5
  • the determination unit 802 is implemented by the P_DC_CODE or N_DC_CODE detection module 5111 in FIG.
  • the trailing error detection module 5112 and the LMS adjustment module 5113 are implemented.
  • the above-mentioned acquiring unit 801 , determining unit 802 , and adjusting unit 803 may be read from the memory 212 by at least one processor 211 of the second device 210 in FIG. 2 .
  • the generated software functional unit is realized.
  • the above units in FIG. 8 can also be implemented by different hardware in the second device 210 in FIG. 2, for example, the determining unit 802 is implemented by a part of the processing resources (for example, a multi-core processor) in the at least one processor 211 in FIG.
  • the adjustment unit 803 is implemented by the rest of the processing resources (such as other cores in the multi-core processor) in at least one processor 211 in FIG. field-programmable gate array, FPGA), or programmable devices such as coprocessors.
  • the obtaining unit 801 is optionally implemented by the first equalizer and the second equalizer in the communication interface 213 in FIG. 2 .
  • the above functional units can also be implemented by a combination of software and hardware.
  • the determination unit 802 is implemented by a hardware programmable device
  • the adjustment unit 803 is a software functional unit generated after the CPU reads the program code stored in the memory.
  • A refers to B, which means that A is the same as B or A is a simple deformation of B.
  • first and second in the description and claims of the embodiments of the present application are used to distinguish different objects, rather than used to describe the specific order of the objects, nor should they be construed as indicating or implying relative importance sex.
  • first equalizer and the second equalizer are used to distinguish different equalizers, but are not used to describe a specific order of the equalizers, nor can it be understood that the first equalizer is more important than the second equalizer.
  • the meaning of "at least one” means one or more, and the meaning of "plurality” means two or more.
  • a plurality of sign bits refers to two or more sign bits.
  • the above-described embodiments may be implemented in whole or in part by software, hardware, firmware, or any combination thereof.
  • software When implemented in software, it can be implemented in whole or in part in the form of a computer program product.
  • the computer program product includes one or more computer instructions.
  • the computer program instructions When the computer program instructions are loaded and executed on a computer, the processes or functions described in accordance with the embodiments of the present application are generated in whole or in part.
  • the computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable device.
  • Computer instructions may be stored in or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server, or data center over a wire (e.g.
  • a computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, or the like that contains one or more of the available mediums integrated.
  • Useful media may be magnetic media (eg, floppy disk, hard disk, magnetic tape), optical media (eg, DVD), or semiconductor media (eg, Solid State Disk (SSD)), among others.

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Abstract

本申请提供了一种均衡器参数的调整方法、训练序列的发送方法及装置，属于通信技术领域。本申请在训练序列中增加固定码型数据，由于固定码型数据实现对拖尾处的码间干扰进行放大叠加的作用，从而降低度量拖尾处码间干扰的技术难度，因此确定出的拖尾处码间干扰的精确度更高，因此根据码间干扰调整均衡器参数，能够有效提高参数调整的精度。

Description

均衡器参数的调整方法、训练序列的发送方法及装置 技术领域
本申请涉及通信技术领域，特别涉及一种均衡器参数的调整方法、训练序列的发送方法及装置。
背景技术
均衡器是通信系统中设置的一种参数可调的滤波器。均衡器的典型功能是减少码间干扰。自适应均衡是一种基于信道特性自动调整均衡器的参数的技术。通过基于自适应均衡调整均衡器的参数，有助于均衡器适应信道特性的动态变化，从而让均衡器具有更好的性能。
基于自适应均衡技术调整均衡器参数的典型方法是：发送端向接收端发送训练序列，训练序列是一串随机数据。接收端通过均衡器处理得到训练序列之后，接收端测量训练序列对应的每一个数据信号对后续每个数据信号的干扰的大小。接收端根据干扰的大小调整均衡器的参数。
采用上述方法时，均衡器参数调整的精度较差。
发明内容
本申请实施例提供了一种均衡器参数的调整方法、训练序列的发送方法及装置，能够提升均衡器参数调整的精度。该技术方案如下。
第一方面，提供了一种均衡器参数的调整方法，该方法例如应用在训练序列的接收端，该方法具体包括：获取通过第一均衡器处理得到的训练序列；确定固定码型数据在训练序列中所处的第一位置；确定固定码型数据在第二位置产生的码间干扰；根据该码间干扰调整该第一均衡器的参数。其中，训练序列包括固定码型数据，该第二位置为训练序列中第一位置之后的位置
上述方法通过在训练序列中增加固定码型数据，由于固定码型数据实现对拖尾处的码间干扰进行放大叠加的作用，从而降低度量拖尾处码间干扰的技术难度，因此确定出的拖尾处码间干扰的精确度更高，因此根据码间干扰调整均衡器参数，能够有效提高参数调整的精度。
其中，固定码型数据实现对拖尾处的码间干扰进行放大叠加的作用的原理在于，根据线性系统的原理，接收端接收到的信号是发送端发出的信号与信道冲激响应的卷积。信道冲激响应的平坦部分(即低频部分)与发送信号卷积后，发送信号的高频部分会被过滤，发送信号的低频部分会被保留。经典的训练序列的发送信号中各种频点的信号强度(概率)基本相同。如果在训练序列中增加低频信号的比例，则在接收到的信号中信道的低频响应则会被增强，因此信道冲击响应拖尾造成的误差会得到放大。
固定码型数据是指码型在多个单位时间段内保持不变的数据。携带固定码型数据的信号的波形类似于直流电的波形，近似于一条直线。其中，该单位时间段例如为单位时间间隔(unit interval，UI)，一个UI为一个比特对应的时间长度。例如，固定码型数据是一串连续的1；或者固定码型数据是一串连续的0。
可选地，上述第二位置不是固定码型数据内部的位置。例如，上述第二位置是随机数据中的位置。例如，第一位置是固定码型数据的最后一个比特的位置，固定码型数据的最后一个比特之后开始是随机数据，第二位置为随机数据中一个比特位。
可选地，固定码型数据包括至少4个UI的连续相同数据。例如，固定码型数据为至少4比特的连续0，又如，固定码型数据为至少4比特的连续1。
可选地，训练序列中固定码型数据与随机数据交替出现。在一种可能的实现中，训练序列依次包含固定码型数据中的第一数据段、随机数据、固定码型数据中的第二数据段以及随机数据。例如，训练序列包括至少4比特的连续1-随机数据-至少4比特的连续0-随机数据。
可选地，固定码型数据在训练序列中的位置(第一位置)的确定方式包括：在训练序列中一次或多次寻找，从而确定包含固定码型数据概率最大的位置，作为第一位置。在一种可能的实现中，采用模板匹配的方式确定第一位置。具体地，对训练序列中每一段连续的符号与预先保存的固定码型数据进行比对，从而得到每一段连续的符号包含固定码型数据的概率，将概率最大的一段符号位作为第一位置。在另一种可能的实现中，采用类似于二分搜索的方式确定第一位置。具体地，将训练序列划分为多个子序列，统计训练序列中每一个子序列中连续1(或0)的数量，判断训练序列中每一子序列中连续1(或0)的数量是否超过设定数量；如果训练序列中某一个子序列中连续1(或0)的数量超过设定数量，则确定固定码型数据属于该子序列，之后，对该子序列进一步划分，并继续统计连续1(或0)的数量。以此类推，不断缩小统计的范围，最终定位到第一位置。
第一均衡器的参数例如为退化电阻(degeneration resistor，Rs)或退化电容(degeneration capacitor，Cs)。
可选地，固定码型数据在第二位置产生的码间干扰的确定方式，也即是固定码型数据带来的拖尾误差的确定方式包括：根据第二位置上数据的电压与参考电压的相关性，确定码间干扰。
上述方式能够将数据的电压从模拟信号转换为数字形式的判决结果，便于通过计数器等进行统计，因此统计码间干扰的难度得以大大减小，减少了实现复杂度。
可选地，参考电压包括第一参考电压和第二参考电压，第一参考电压和第二参考电压的电压值不相等，固定码型数据带来的拖尾误差采用以下方式确定：以第一参考电压为判决阈值，对第二位置上数据进行比较，得到第一判决结果；以第二参考电压为判决阈值，对第二位置上数据进行比较，得到第二判决结果；将第一判决结果和第二判决结果中值相同的总个数作为第一总个数；将第一判决结果和第二判决结果中值不相同的总个数作为第二总个数；根据第一总个数和第二总个数确定码间干扰，其中码间干扰与第一总个数正相关，码间干扰与第二总个数负相关。
上述方式能够精确地确定拖尾处的码间干扰，有效地解决无法有效度量码间干扰的噪声强度的问题。
可选地，第一均衡器的参数的调整方式包括：若码间干扰小于设定的干扰阈值，减小第一均衡器的参数；若码间干扰大于设定的干扰阈值，增大第一均衡器的参数；若码间干扰等于设定的干扰阈值，保持第一均衡器的参数不变。
上述方式中有助于解决均衡器均衡不足或均衡过大的问题，提升均衡器的信道均衡性能。
可选地，训练序列是通过第一均衡器以及第二均衡器处理得到的，训练序列还包括随机 数据，接收端还根据随机数据中一个或多个符号位对应的误差，调整第二均衡器的参数。
随机数据例如是伪随机序列。例如，随机数据是56比特随机的0或1。
上述方式中，随机数据带来的误差专门用来调整第二均衡器的参数，固定码型数据带来的误差专门用来调整第一均衡器的参数，使得第一均衡器和第二均衡器的参数调整过程不会互相干扰，支持第一均衡器和第二均衡器并存的系统，便于对两个均衡器同时进行参数调整。
可选地，随机数据中一个或多个符号位包括第一符号位，第二均衡器的参数的调整方式包括：根据第一符号位对应的误差与符号值之间的相关量，调整第二均衡器的参数，符号值为随机数据中第一符号位之前的符号位上的值，第二均衡器的参数与相关量负相关。
上述方式能将第一均衡器和第二均衡器的作用解耦开来，避免第一均衡器和第二均衡器互相干扰，因此更精确地调整第一均衡器和第二均衡器的参数。
可选地，第二均衡器的参数的调整方式包括：根据第i个符号位对应的误差与(i-m)个符号位上符号值之间的相关量，调整第二均衡器第m个抽头的参数，i、m均为正整数。
可选地，第二位置与第一位置之间的距离大于N个符号，N为第二均衡器的抽头数。
上述方式中第二均衡器负责消除固定码型数据对后续N个符号位产生的码间干扰，而第一均衡器负责消除从N+1个符号开始固定码型数据对后续符号位产生的码间干扰，使得第一均衡器和第二均衡器的作用解耦开来，由于参数调整时几乎没有引入第二均衡器信道均衡带来的影响，因此更精确地调整第一均衡器的参数。
可选地，第二位置为第一位置之后的第N+1个符号位。
上述方式能够保证参数调整精度，同时避免检测大量位置上的码间干扰带来的巨大运算开销。
可选地，训练序列中固定码型数据与随机数据之间的长度比例为1:7。
例如，在一个典型的长度为128个比特的训练帧中，包含8个比特的11111111(固定码型数据)，之后是56比特的随机0或1(随机数据)，之后是8个比特的00000000(固定码型数据)，最后是56比特的随机0或1(随机数据)。
上述方式保证固定码型数据与随机数据比例的合理性，避免固定码型数据比例过小导致增加训练时间，同时避免固定码型数据比例过大造成训练序列的随机性减弱。
可选地，固定码型数据的长度位于4比特至16比特之间。
固定码型数据通过采用以上长度，有助于避免固定码型数据长度过短导致减弱固定码型数据的作用，同时避免固定码型数据过长导致影响数据的随机性以及影响时钟恢复电路(clock data recovery，CDR)的收敛。
可选地，固定码型数据包括第一数据段和第二数据段，第二数据段为第一数据段中每一个比特取反后得到的数据。
第一数据段例如是至少4个连续1组成的数据段，第二数据段例如是至少4个连续0组成的数据段。可选地，第一数据段的内容包括1个0，第一数据段其余内容均为1；第二数据段的内容包括1个1，第二数据段其余内容均为0。或者，第一数据段的内容包括2个1，第一数据段其余内容均为0；第二数据段的内容包括2个0，第二数据段其余内容均为1。
上述方式平衡0的数量和1的数量，也就是让固定码型数据中0与1差不多数量相同，从而消除信号的直流电(direct current，DC)偏差(DC offset)。
可选地，上述第二均衡器为判决反馈均衡器DFE。
可选地，上述第一均衡器为连续时间线性均衡器CTLE。
上述方式能支持串行器和解串器(serializer/deserializer，SERDES)的应用场景。
第二方面，提供了一种训练序列的发送方法，在该方法中，生成训练序列，训练序列包括固定码型数据，固定码型数据在训练序列中处于第一位置，固定码型数据在第二位置产生的码间干扰用于调整第一均衡器的参数，第二位置为训练序列中第一位置之后的位置，第一均衡器为训练序列的接收端中设置的均衡器；发送训练序列。
上述方法通过在训练序列中增加固定码型数据，由于固定码型数据实现对拖尾处的码间干扰进行放大叠加的作用，从而降低度量拖尾处码间干扰的技术难度，因此确定出的拖尾处码间干扰的精确度更高，因此根据码间干扰调整均衡器参数，能够有效提高参数调整的精度。
可选地，上述第一位置是固定码型数据的最后一个比特的位置，第二位置为训练序列中随机数据所在的位置。
可选地，训练序列还包括随机数据，随机数据中一个或多个符号位对应的误差用于调整第二均衡器的参数，第二均衡器为训练序列的接收端中设置的均衡器。
上述方式中，随机数据带来的误差专门用来调整第二均衡器的参数，固定码型数据带来的误差专门用来调整第一均衡器的参数，使得第一均衡器和第二均衡器的参数调整过程不会互相干扰，支持第一均衡器和第二均衡器并存的系统，便于对两个均衡器同时进行参数调整。
可选地，训练序列中固定码型数据与随机数据之间的长度比例为1:7。
上述长度比例能更好的兼顾训练时间和数据随机性，适用性更广。
可选地，固定码型数据的长度位于4比特至16比特之间。
固定码型数据通过采用以上长度，有助于避免固定码型数据长度过短导致减弱固定码型数据的作用，同时避免固定码型数据过长导致影响数据的随机性以及影响时钟恢复电路(clock data recovery，CDR)的收敛。
可选地，固定码型数据包括第一数据段和第二数据段，第二数据段为第一数据段中每一个比特取反后得到的数据。
上述方式平衡0的数量和1的数量，也就是让固定码型数据中0与1差不多数量相同，从而消除信号的直流电(direct current，DC)偏差(DC offset)。
第三方面，提供了一种均衡器参数的调整装置，该均衡器参数的调整装置具有实现上述第一方面或第一方面任一种可选方式的功能。该均衡器参数的调整装置包括至少一个单元，至少一个单元用于实现上述第一方面或第一方面任一种可选方式所提供的方法。
第四方面，提供了一种训练序列的发送装置，该训练序列的发送装置具有实现上述第二方面或第二方面任一种可选方式的功能。该训练序列的发送装置包括至少一个单元，至少一个单元用于实现上述第二方面或第二方面任一种可选方式所提供的方法。
在一些实施例中，训练序列的发送装置中的单元通过软件实现，训练序列的发送装置中的单元是程序模块。在另一些实施例中，训练序列的发送装置中的单元通过硬件或固件实现。第四方面提供的训练序列的发送装置的具体细节可参见上述第二方面或第二方面任一种可选方式，此处不再赘述。
第五方面，提供了一种电子设备，该电子设备包括处理器和第一均衡器，该处理器用于执行指令，使得该电子设备执行上述第一方面或第一方面任一种可选方式所提供的方法第一均衡器用于处理得到训练序列。
可选地，该电子设备还包括第二均衡器。第二均衡器用于和第一均衡器相互配合，从而处理得到训练序列。
第五方面提供的电子设备的具体细节可参见上述第一方面或第一方面任一种可选方式，此处不再赘述。
第六方面，提供了一种电子设备，该电子设备包括处理器和通信接口，该处理器用于执行指令，使得该电子设备执行上述第二方面或第二方面任一种可选方式所提供的方法，通信接口用于发送训练序列。第六方面提供的电子设备的具体细节可参见上述第二方面或第二方面任一种可选方式，此处不再赘述。
第七方面，提供了一种计算机可读存储介质，该存储介质中存储有至少一条指令，该指令在计算机上运行时，使得计算机执行上述第一方面或第一方面任一种可选方式所提供的方法。
第八方面，提供了一种计算机可读存储介质，该存储介质中存储有至少一条指令，该指令在计算机上运行时，使得计算机执行上述第二方面或第二方面任一种可选方式所提供的方法。
第九方面，提供了一种计算机程序产品，计算机程序产品包括一个或多个计算机程序指令，当计算机程序指令被计算机加载并运行时，使得计算机执行上述第一方面或第一方面任一种可选方式所提供的方法。
第十方面，提供了一种计算机程序产品，计算机程序产品包括一个或多个计算机程序指令，当计算机程序指令被计算机加载并运行时，使得计算机执行上述第二方面或第二方面任一种可选方式所提供的方法。
第十一方面，提供了一种芯片，包括存储器和处理器，存储器用于存储计算机指令，处理器用于从存储器中调用并运行该计算机指令，以执行上述第一方面及其第一方面任意可能的实现方式中的方法。
第十二方面，提供了一种芯片，包括存储器和处理器，存储器用于存储计算机指令，处理器用于从存储器中调用并运行该计算机指令，以执行上述第二方面或第二方面任一种可选方式所提供的方法。
第十三方面，提供了一种通信系统，该通信系统包括第三方面的均衡器参数的调整装置以及第四方面的训练序列的发送装置。
第十四方面，提供了一种通信系统，该通信系统包括第五方面的电子设备以及第六方面的电子设备。
第十五方面，提供了一种均衡器参数的调整装置，该装置可提供为训练序列的接收端，例如SERDES的接收端。均衡器参数的调整装置包括：第一均衡器、固定码型数据定位电路、误差检测电路以及均衡参数调整电路，该均衡器参数的调整装置中各个硬件用于实现上述第一方面或第一方面任一种可选方式所提供的方法。可选地，该均衡器参数的调整装置还包括第二均衡器以及最小均方算法(least mean square，LMS)调整电路。
第十六方面，提供了一种训练序列的发送装置，该装置可提供为训练序列的发送端，例 如SERDES的发送端。训练序列的发送装置包括：训练序列产生器以及发射电路。该装置中各个硬件用于实现上述第一方面或第一方面任一种可选方式所提供的方法。
第十七方面，提供了一种通信系统，该通信系统包括第十五方面的装置以及第十六方面的装置，该通信系统可提供为SERDES。
附图说明
图1是本申请实施例提供的一种码间干扰现象的示意图；
图2是本申请实施例提供的一种应用场景的示意图；
图3是本申请实施例提供的一种均衡器参数的调整方法的流程图；
图4是本申请实施例提供的一种训练序列的格式示意图；
图5是本申请实施例提供的一种SERDES系统的架构图；
图6是本申请实施例提供的一种数据定位波形的示意图；
图7是本申请实施例提供的一种训练序列的发送装置的结构示意图；
图8是本申请实施例提供的一种均衡器参数的调整装置的结构示意图。
具体实施方式
为使本申请的目的、技术方案和优点更加清楚，下面将结合附图对本申请实施方式作进一步地详细描述。
下面对本申请实施例涉及的一些术语概念做解释说明。
(1)训练序列
训练序列是一种用于调整接收端均衡器参数的数据序列。训练序列携带在发送端发送的数据帧中。例如，发送端发送的一个数据帧中，帧头(frame head)携带训练序列，训练序列之后为业务数据。训练序列在数据帧中占用一个或多个连续的符号。训练序列的作用包括而不限于接收端进行训练(即调整均衡器的参数)、信道估计等。
(2)码型(code pattern)
码型是指表示数据的信号的波形。其中，该信号包括而不限于无线通信领域的射频信号、有线通信领域中的电信号或光信号等。例如，高电平表示数据“1”，低电平表示数据“0”，高电平和低电平这样的波形即为码型。
(3)固定码型数据
固定码型数据是指码型在多个单位时间段内保持不变的数据。其中，该单位时间段例如为单位时间间隔(unit interval，UI)，一个UI为一个比特对应的时间长度。可选地，固定码型数据是二进制数据。
从数据内容的角度来看，固定码型数据中多个连续的比特位上取值保持不变。例如，固定码型数据中N个连续的比特位上取值均为1，或者固定码型数据中N个连续的比特位上取值均为0，N为大于或等于2的正整数。
可选地，固定码型数据中每个比特位上取值均相同。例如，固定码型数据是一串连续的1；或者固定码型数据是一串连续的0。作为具体示例，固定码型数据为11111111。可替代地，固定码型数据中大部分比特位取值相同，并允许出现少量与其他比特取值不同的比特。例如，固定码型数据中存在1或2个与其他比特取值不同的比特，而固定码型数据中剩余比特位上取值均相同。作为具体示例，固定码型数据为11111101。
从信号波形的角度来看，携带固定码型数据的信号的波形类似于直流电的波形，携带固 定码型数据的信号的波形在多个单位时间段内近似于一条直线。例如，携带固定码型数据的信号的波形在多个单位时间段内均为高电平；又如，携带固定码型数据的信号的波形在多个单位时间段内均为低电平。
可选地，固定码型数据包括至少4个UI的连续相同数据。例如，固定码型数据为至少4比特的连续0，又如，固定码型数据为至少4比特的连续1。
(4)码间干扰(inter symbol interference，ISI)
码间干扰是指由于信道特性不理想，导致码元的波形畸变、展宽，并使先前码元的波形出现很长的拖尾，蔓延到当前码元的抽样时刻上，从而对当前码元的判决造成干扰。例如，如图1所示，当发送端发送一个高电平信号(数字信号1)，经过信道后会持续将后面的信号电平拉高一些；反之发送端发送一个低电平信号(数字信号0)，则经过信道后会将后面的信号电平拉低一些。
(5)均衡器
均衡器是一种参数能调整的滤波器。均衡器通常设置在通信系统的接收端，均衡器通常工作在接收端中基带信号处理单元或中频信号处理单元等。均衡器的典型作用在于减少甚至消除码间干扰。均衡器实现减少码间干扰作用的基本原理在于，均衡器会产生与信道特性近似相反的特性，从而补偿信道特性，矫正已畸变的波形。其中，均衡器的特性通过均衡器的参数体现。
(6)判决以及判决阈值
判决是一种对数据的电压与判决阈值进行比较的过程。判决的一种典型实现方式是，对数据的电压与判决阈值比较；如果数据的电压大于判决阈值，则确定判决结果为1；如果数据的电压小于或等于判决阈值，则确定判决结果为0。其中，判决阈值是指判决时使用的参考电压。判决阈值也称判决门限。
(7)连续时间线性均衡器(continuous-time linear equalizer，CTLE)
CTLE是一种模拟均衡器。CTLE可通过有源电路或无源电路实现。CTLE的作用等效于高通滤波器和放大器的组合。CTLE的基本原理是，当接收到信道上传输的信号时，CTLE先将整个信号等比放大，然后CTLE通过高通滤波器对放大后的信号滤波。当信号通过CTLE后，低频分量衰减的多，高频分量衰减的少，从而补偿高频分量的损耗。
(8)判决反馈均衡器(decision feedback equalizer，DFE)
DFE是一种数字均衡器。DFE包括有限长单位冲激响应(finite impulse response，FIR)滤波器、加法器和判决器。DFE的作用通常是增强高频分量，加大了高频分量与低频分量的能量比。
(9)串行器和解串器(serializer/deserializer，SERDES)
SERDES是一种芯片中的串行高速接口。SERDES应用在串行有线通信系统中。SERDES包括发送端和接收端两种组件。SERDES的发送端和接收端通常分设在两个物理设备中。SERDES的发送端包括前向反馈均衡器(feed‐forward equalizer，FFE)。SERDES的接收端包括CTLE和DFE。通常情况下，当SERDES的接收端接收到信号时，先通过CTLE对信号进行处理，再通过DFE对CTLE输出的信号进行处理，再对DFE输出的信号进行采样判决，得到信号携带的数据。
在SERDES系统传输数据信号的过程中，通常数据信号在信道传输过程中会有衰减。在频域分析上，衰减的规律是高频信号衰减的多，低频信号衰减的少。在时域分析上，衰减的规律表现为发送端发送的一个标准数字脉冲信号，在经过信道后接收端接收的是一个展宽的信号。例如，如附图1所示，附图1是一种信号波形图。附图1中的两个波形中，一个波形表示发送端发送的数字脉冲信号，另一个波形表示接收端接收到的信号。这种被信道展宽后的信号会干扰前后相邻的信号，这种发送数据之间干扰产生的噪声被称为码间干扰。消除码间干扰的技术手段被称为信道均衡，信道均衡能够将高频信号和低频信号的强度调整为一致。
在一个SERDES系统中，常用进行信道均衡的模块包括FFE、DFE和CTLE。其中FFE和DFE为数字电路属性的均衡滤波器，CTLE是模拟电路属性的均衡滤波器。随着SERDES传输数据的速率的不断提升，信道的衰减也越来越大，码间干扰也越来越大，因此这三种均衡手段都会出现在主流的SERDES系统中。在三种均衡手段中，CTLE由于实现简单，功耗低均衡的能力强等因素通常在SERDES系统中承担关键均衡的作用。但是，由于CTLE是一个纯模拟电路实现的均衡器，相对于FFE和DFE这样的数字均衡器，CTLE当前还没有一个有效的自动适应信道特性的调节算法和调节策略，这个问题长期以来是SERDES系统的一个难点和痛点。
有鉴于此，本实施例提出了一种新的有效调整SERDES系统中CTLE均衡参数的方法。可替代地，该方法应用于对CTLE之外的其他均衡器进行参数调整的场景。可替代地，该方法应用于除SERDES系统之外的其他有线通信系统或者无线通信系统。
下面对本申请实施例的应用场景举例说明。
附图2是本申请实施例提供的一种应用场景的示意图。附图2示出的应用场景包括第一设备200和第二设备210。该应用场景例如为无线网络通信场景或者有线网络通信场景。下面对第一设备200和第二设备210的典型产品形态、内部元器件以及连接关系做举例说明。
(1)第一设备200
第一设备200为具有无线通信功能或者有线通信功能的任意装置。第一设备200的产品形态包括很多种情况。可选地，第一设备200为用户设备。例如，第一设备200为平板电脑、桌面型、膝上型、笔记本电脑、超级移动个人计算机(Ultra-mobile Personal Computer，UMPC)、手持计算机、上网本、个人数字助理(Personal Digital Assistant，PDA)、手机等可以联网的用户设备。或者，第一设备200为物联网中的物联网节点，或车联网中的车载通信装置。可选地，第一设备200为通信服务器、路由器、交换机、网桥等通信实体，或，第一设备200可以包括各种形式的宏基站，微基站，中继站等。第一设备200可选地为一个整机的设备，或者是安装在整机设备中的芯片或处理系统等，安装这些芯片或处理系统的设备可以在这些芯片或处理系统的控制下，实现本申请实施例的方法和功能。
第一设备200包括至少一个处理器201、存储器202以及通信接口203。
处理器201例如是通用中央处理器(central processing unit，CPU)、网络处理器(network processer，NP)、图形处理器(graphics processing unit，GPU)、神经网络处理器(neural-network processing units，NPU)、数据处理单元(data processing unit，DPU)、微处理器或者一个或多个用于实现本申请方案的集成电路。例如，处理器201包括专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。 PLD例如是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。
存储器202例如是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，又如是随机存取存储器(random access memory，RAM)或者可存储信息和指令的其它类型的动态存储设备，又如是电可擦可编程只读存储器(electrically erasable programmable read-only Memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。可选地，存储器202独立存在，并通过内部连接204与处理器201相连接。或者，可选地存储器202和处理器201集成在一起。
可选地，存储器202中保存实现本申请实施例提供的训练序列的发送方法所涉及的程序代码206。可选地，存储器202用于存放固定码型数据。
通信接口203使用任何收发器一类的装置，用于与其它设备或通信网络通信。通信接口203例如包括有线通信接口或者无线通信接口中的至少一项。其中，有线通信接口例如为以太网接口。以太网接口例如是光接口，电接口或其组合。无线通信接口例如为无线局域网(wireless local area networks，WLAN)接口，蜂窝通信接口或其组合等。
(2)第二设备
第二设备210为具有有线通信功能或者无线通信功能的任意装置。第二设备210的产品形态包括很多种情况。可选地，第二设备210为用户设备。例如，第二设备210为平板电脑、桌面型、膝上型、笔记本电脑、超级移动个人计算机(Ultra-mobile Personal Computer，UMPC)、手持计算机、上网本、个人数字助理(Personal Digital Assistant，PDA)、手机等可以联网的用户设备。或者，第二设备210为物联网中的物联网节点，或车联网中的车载通信装置。可选地，第二设备210为通信服务器、路由器、交换机、网桥等通信实体，或，第二设备210可以包括各种形式的宏基站，微基站，中继站等。第二设备210可选地为一个整机的设备，或者是安装在整机设备中的芯片或处理系统等，安装这些芯片或处理系统的设备可以在这些芯片或处理系统的控制下，实现本申请实施例的方法和功能。
第二设备210包括至少一个处理器211、存储器212以及通信接口213。
处理器211例如是通用中央处理器(central processing unit，CPU)、网络处理器(network processer，NP)、图形处理器(graphics processing unit，GPU)、神经网络处理器(neural-network processing units，NPU)、数据处理单元(data processing unit，DPU)、微处理器或者一个或多个用于实现本申请方案的集成电路。例如，处理器211包括专用集成电路(application-specific integrated circuit，ASIC)，可编程逻辑器件(programmable logic device，PLD)或其组合。PLD例如是复杂可编程逻辑器件(complex programmable logic device，CPLD)、现场可编程逻辑门阵列(field-programmable gate array，FPGA)、通用阵列逻辑(generic array logic，GAL)或其任意组合。
存储器212例如是只读存储器(read-only memory，ROM)或可存储静态信息和指令的其它类型的静态存储设备，又如是随机存取存储器(random access memory，RAM)或者可 存储信息和指令的其它类型的动态存储设备，又如是电可擦可编程只读存储器(electrically erasable programmable read-only Memory，EEPROM)、只读光盘(compact disc read-only memory，CD-ROM)或其它光盘存储、光碟存储(包括压缩光碟、激光碟、光碟、数字通用光碟、蓝光光碟等)、磁盘存储介质或者其它磁存储设备，或者是能够用于携带或存储具有指令或数据结构形式的期望的程序代码并能够由计算机存取的任何其它介质，但不限于此。可选地，存储器212独立存在，并通过内部连接214与处理器211相连接。或者，可选地存储器212和处理器211集成在一起。
可选地，存储器212中保存实现本申请实施例提供的均衡器参数的调整方法所涉及的程序代码216。
通信接口213包括第一均衡器2131。可选地，通信接口213还包括第二均衡器2132。第一均衡器2131以及第二均衡器2132均用于进行信道均衡，消除或减低码间干扰的影响。可选地，第一均衡器2131为通过模拟电路实现的均衡器。可选地，第二均衡器2132为通过数字电路实现的均衡器。第一均衡器2131或者第二均衡器2132包括而不限于时域均衡器或者频域均衡器。第一均衡器2131或者第二均衡器2132包括而不限于线性均衡器或者非线性均衡器。第一均衡器2131或者第二均衡器2132包括而不限于线性横向均衡器、线性格型均衡器、判决反馈均衡器或者分数间隔均衡器。
通信接口213使用任何收发器一类的装置，用于与其它设备或通信网络通信。通信接口213例如包括有线通信接口或者无线通信接口中的至少一项。其中，有线通信接口例如为以太网接口。以太网接口例如是光接口，电接口或其组合。无线通信接口例如为无线局域网(wireless local area networks，WLAN)接口，蜂窝通信接口或其组合等。
(3)第一设备与第二设备的连接关系
第一设备与第二设备之间通过通路相连。该通路通过有线网络和/或无线网络实现。有线网络例如是基于电信号通信的网络或者基于光信号通信的网络。无线网络例如是基于射频信号通信的网络。
可选地，附图2所示的应用场景具体为SERDES系统。第一设备扮演着SERDES系统中发送端的角色，第一设备也称为SERDES系统中的串行器(serializer)。第二设备扮演着SERDES系统中接收端的角色，第二设备也称为SERDES系统中的解串器(deserializer)。第一设备包括FFE或者其他均衡器。第二设备中的第一均衡器2131为CTLE。第二设备中的第二均衡器为DFE。
下面对本申请实施例的方法流程举例说明。
附图3是本申请实施例提供的一种均衡器参数的调整方法的流程图。附图3所示方法包括以下步骤S301至步骤S307。
附图3所示方法涉及多个设备之间的交互。为了区分不同的设备，用“第一设备”、“第二设备”区分描述多个不同的设备。附图3所示方法主要关于第二设备如何利用第一设备发送的训练序列调整均衡器的参数。
附图3所示实施例对接收端执行的各个步骤(S303至S306)的顺序不做限定，换句话说，S303至S306不一定是顺序执行的，S303至S306的执行顺序也可以互换。
附图3所示方法所基于的场景可选地如附图2所示。例如，结合附图2来看，附图3所 示方法中的第一设备为附图2中的第一设备200，附图3所示方法中的第二设备为附图2中的第二设备210。附图3所示方法中的第一均衡器为附图2中的第一均衡器2131，附图3所示方法中的第二均衡器为附图2中的第二均衡器2132。
附图3所示方法可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。在一种可能的实现中，第二设备中处理器211通过读取存储器212中保存的程序代码216实现附图3所示方法中步骤S303至S307，或者，处理器211通过内部存储的程序代码实现附图3所示方法中步骤S303至S307。在另一种可能的实现中，采用算法硬件化的手段设计处理器211的物理结构，使得处理器211为专用于调整均衡器参数的硬件加速器。处理器211独立完成下述步骤S303至S307，或者处理器211与CPU共同配合完成下述步骤S303至S307。例如，处理器211用于根据CPU的指示，执行步骤S303至步骤S305，并将确定出的码间干扰发送给CPU。CPU负责执行步骤S306。
步骤S301、第一设备生成训练序列，训练序列包括固定码型数据。
第一设备如何获得固定码型数据包括多种实现方式，下面通过实现方式a和实现方式b举例说明。
实现方式a.固定码型数据是预先设定的。
例如，管理人员通过命令行、用户界面或其他方式，针对第一设备配置固定码型数据，第一设备根据预先配置的固定码型数据生成训练序列。
实现方式b.固定码型数据是通过协商的方式确定的。
例如，第一设备预先向第二设备发送多个候选固定码型数据。第二设备从多个候选固定码型数据中选择一个固定码型数据，将选择出的固定码型数据发送给第一设备。第一设备根据第二设备选择出的固定码型数据生成上述训练序列。又如，当第二设备需要训练均衡器时，第二设备向第一设备主动发送固定码型数据，第一设备根据第二设备发送的固定码型数据生成上述训练序列。
以上介绍了固定码型数据的获得方式，下面对固定码型数据的具体数据结构举例说明。
在一些实施例中，固定码型数据包括第一数据段和第二数据段。第二数据段为第一数据段中每一个比特取反后得到的数据。换句话说，第一数据段和第二数据段具有互为取反的关系。具体来说，如果第一数据段中第i个比特位的值为0，第二数据段中第i个比特位的值为1；若第一数据段中第i个比特位的值为1，第二数据段中第i个比特位的值为0。通过设置第一数据段和第二数据段，从而平衡0的数量和1的数量，也就是让固定码型数据中0与1差不多数量相同，从而消除信号的直流电(direct current，DC)偏差(DC offset)。
可选地，第一数据段中每个比特的内容均为1，第二数据段中每个比特的内容均为0。示例性地，请参考附图4，附图4中的P_DC_SEG(positive direct current segment，正直流数据段)是第一数据段的具体示例，附图4中的N_DC_PATTERN(negative direct current segment，负直流数据段)是第二数据段的具体示例，附图4中的RANDOM_SEG是随机数据的具体示例。P_DC_SEG为8个11111111，N_DC_SEG为8个00000000，00000000为11111111中每一个比特取反后得到的数据。
可选地，固定码型数据位于训练帧的头部。在一种可能的实现中，固定码型数据中第一数据段位于训练帧中第1个比特至第n个比特，n为第一数据段的长度。例如，请参考附图4，一个训练帧的头部包含8个11111111(固定码型数据中第一数据段)。通过采用这种方式， 接收端收到训练帧之后，能够从训练帧的第1个比特开始更快速地找到固定码型数据。可替代地，固定码型数据位于训练帧的尾部。可替代地，固定码型数据位于训练帧的中心位置。可替代地，固定码型数据位于训练帧的设定位置，该设定位置例如是接收端向发送端发送的位置，又如是管理人员在接收端和发送端预先配置的位置。例如，接收端向发送端通告位置i的标识，发送端接收到位置i的标识之后，将训练帧中第i个比特开始的比特设置为固定码型数据。
可替代地，第一数据段的内容主要是1，且允许出现少量的0。第二数据段的内容主要是0，且允许出现少量的1。在一种可能的实现中，第一数据段的内容包括1个0，第一数据段其余内容均为1；第二数据段的内容包括1个1，第二数据段其余内容均为0。例如，第一数据段是11111101，第二数据段是00000010。又如，第一数据段是11111011，第二数据段是00000100。
在另一种可能的实现中，第一数据段的内容包括2个1，第一数据段其余内容均为0；第二数据段的内容包括2个0，第二数据段其余内容均为1。例如，第一数据段是11110101，第二数据段是00001010。第一数据段通过出现少量的0，第二数据段通过出现少量的1，有助于训练序列匹配信道上有反射点的情况，帮助方案支持更多的场景。
可选地，训练序列还包括随机数据。在一些实施例中，随机数据是伪随机序列。在一些实施例中，随机数据是二进制数据。示例性地，请参考附图4，附图4中的RANDOM_SEG是随机数据的具体示例，RANDOM_SEG是56比特随机的0或1。由于随机数据的信号的频谱中各个频点强度相同，随机数据的信号更接近于实际业务的数据信号，通过在训练序列中设置随机数据，能够有效地模拟实际业务中数据传输的场景，保证均衡器参数的调整与实际业务场景更匹配，从而有助于提升参数的调整效果。
第一设备如何生成随机数据包括多种方式，下面通过两种方式举例说明。
实现方式一、第一设备中包含伪随机码训练序列产生器，第一设备通过伪随机码训练序列产生器生成随机数据。
实现方式二、第一设备对业务数据进行打散，得到随机数据。其中，打散例如是改变业务数据中不同数值的排列顺序。
可选地，第二设备接收到第一设备发送的随机数据之后，第二设备对随机数据进行恢复，以得到打散前的业务数据。
可选地，训练序列中随机数据与固定码型数据交替出现。在一种可能的实现中，随机数据在训练序列中位于第一数据段与第二数据段之间。例如，请参考附图6，训练序列包括这样的数据结构：P_DC_SEG(固定码型数据中的第一数据段)——RANDOM_SEG(随机数据)——N_DC_SEG(固定码型数据中的第二数据段)——RANDOM_SEG(随机数据)。
可选地，固定码型数据的长度位于4比特至16比特之间。可选地，固定码型数据的长度为4比特、8比特或16比特。例如，在一个典型的长度为128个比特的训练帧中，包含8个比特的11111111(固定码型数据)，之后是56比特的随机0或1(随机数据)，之后是8个比特的00000000(固定码型数据)，最后是56比特的随机0或1(随机数据)。固定码型数据通过采用以上长度，有助于避免固定码型数据长度过短导致减弱固定码型数据的作用，同时避免固定码型数据过长导致影响数据的随机性以及影响时钟恢复电路(clock data recovery，CDR)的收敛。
如何确定上述固定码型数据的长度包括多种实现方式。在一种可能的实现方式中，由管理人员在第一设备中配置上述固定码型数据的长度。在另一种可能的实现方式中，第一设备(发送端)和第二设备(接收端)通过协商的方式确定上述固定码型数据的长度。
可选地，训练序列中固定码型数据与随机数据之间的长度比例为1:7。例如，固定码型数据的长度为8个比特，而随机数据的长度为56个比特。上述长度比例能更好的兼顾训练时间和数据随机性，适用性更广。
可选地，随机数据和固定码型数据是按照训练帧(training frame，TF)为单位循环发送的。具体地，训练序列包括一个或多个连续的TF，每一个TF包括随机数据和固定码型数据。可选地，同一个训练序列中各个TF中的固定码型数据相同。例如，请参考附图4，训练序列包括N个训练帧，分别是训练帧1、训练帧2……训练帧N。训练帧1、训练帧2……训练帧N中每个训练帧包含的P_DC_SEG都相同，训练帧1、训练帧2……训练帧N中每个训练帧包含的N_DC_SEG都相同。
如何确定TF的长度包括多种方式。在一种可能的实现方式中，管理人员在第一设备中配置TF的长度。或者，第一设备(发送端)和第二设备(接收端)通过协商的方式确定一个TF的长度。可选地，一个TF的长度为128个比特。通过为TF采用上述长度，保证TF长度的合理性，避免TF长度过长时，降低固定码型数据的出现频率从而造成增加训练时间，同时避免TF过短造成训练数据的随机性减弱。
步骤S302、第一设备发送训练序列。
步骤S303、第二设备获取通过第一均衡器处理得到的训练序列。
步骤S304、第二设备确定固定码型数据在训练序列中所处的第一位置。
本实施例涉及训练序列中的多个位置。为了区分描述，用“第一位置”“第二位置”区分描述训练序列中的不同位置。第一位置是指固定码型数据在训练序列中所处的位置。如何确定上述第一位置包括多种方式。具体地，由于固定码型数据属于低频的码型，因此信道的衰减很小，并且稳定的周期出现，因此通过周期的循环检测，能够实现锁定固定码型数据的位置。下面通过实现方式A和实现方式B，对确定第一位置的具体实现方式举例说明。
实现方式A.模板匹配的方式。
具体来说，第二设备会预先保存固定码型数据，第二设备预先保存的固定码型数据可理解为模板。第二设备获取训练序列之后，第二设备对训练序列中每一段连续的符号与预先保存的固定码型数据进行比对。第二设备通过比对，得到训练序列中每一段连续的符号是固定码型数据的概率。第二设备从训练序列中，确定概率最大的位置，将概率最大的位置作为固定码型数据的位置(第一位置)。
实现方式B.类似于二分搜索的方式。
具体来说，第二设备将训练序列划分为多个子序列。第二设备统计训练序列中每一个子序列中连续1的数量，第二设备判断训练序列中每一子序列中连续1的数量是否超过设定数量；如果训练序列中某一个子序列中连续1的数量超过设定数量，则确定固定码型数据属于该子序列。之后，对该子序列进一步划分，并继续统计连续1的数量。以此类推，不断缩小统计的范围，最终定位到固定码型数据。可替换地，统计的对象从1替换为0，例如统计训练序列中每一个子序列中连续0的数量。
通过执行上述步骤S304，从而锁定了固定码型数据的位置，而固定码型数据的位置能够 起到参考位置的作用，方便定位后续数据统计的位置(第二位置)，进而方便确定码间干扰。
步骤S305、第二设备确定固定码型数据在第二位置产生的码间干扰。
第二位置为训练序列中固定码型数据之后的位置，即上述第一位置之后的位置。第二位置为接收端(第二设备)进行误差检测的位置。
可选地，第二位置与第一位置之间的距离大于N个符号。例如，训练序列总共包括M个符号，固定码型数据位于第a个符号至第b个符号，第二位置为训练序列中第(b+N)个符号位至第M个符号位之间的位置。N为正整数。可选地，N为大于或等于2的正整数。可选地，N为第二均衡器的抽头数(tap数)。
固定码型数据的位置(第一位置)与误差统计的位置(第二位置)由于具有上述关系，让方案支持第一均衡器和第二均衡器并存的系统，能够提升第一均衡器和第二均衡器整体的参数调整效果。达到这一效果的技术原理在于，由于第一均衡器和第二均衡器这两个均衡器是同时对信号进行均衡的，经常出现两个均衡器的参数调整过程相互干扰的情况，导致对两个均衡器同时进行参数调整存在技术难点。而本实施例中，如果第二均衡器的抽头数为N，接收端接收训练序列的过程中，第二均衡器负责消除固定码型数据对后续N个符号位产生的码间干扰，而第一均衡器负责消除从N+1个符号开始固定码型数据对后续符号位产生的码间干扰，使得第一均衡器和第二均衡器的作用解耦开来。因此，在参数调整过程中，能够区分第一均衡器和第二均衡器这两个均衡器的影响。通过根据N+1个符号开始的后续符号位上的码间干扰调整第一均衡器的参数，由于参数调整时几乎没有引入第二均衡器信道均衡带来的影响，因此更精确地调整第一均衡器的参数。
可选地，第二位置为第一位置之后的第N+1个符号位。例如，固定码型数据位于第a个符号至第b个符号，第二位置为训练序列中第(b+N+1)个符号位。通过采用这一方式，在几乎不降低参数调整精度的同时，降低方案的计算复杂度。达到这一效果的技术原理在于，固定码型数据对后续符号位的码间干扰呈逐步递减的趋势，在从第N+1个符号位开始的每个符号位中，第N+1个符号位上的码间干扰最大，最能代表拖尾处整体噪声的影响，因此根据第N+1个符号位上的码间干扰来调整第一均衡器的参数，能够保证参数调整精度，同时避免检测大量位置上的码间干扰带来的巨大运算开销。
可替代地，第二位置不仅包括第一位置之后的第N+1个符号位，还包括第N+1个符号位之后的符号位。例如，第二设备确定第一位置之后的第N+1个符号位以及第N+2个符号位这两个符号位的码间干扰，第二设备对两个码间干扰进行平均值运算或者求和运算，根据运算结果调整第一均衡器的参数。
在一些实施例中，第二设备根据第二位置上数据的电压与参考电压的相关性，确定第二位置上的码间干扰。
参考电压的电压值可选地是预先设定的。参考电压预先保存在第二设备中。可选地，在确定第二位置上的码间干扰时，参考电压起到判决阈值的作用。换句话说，上述数据的电压与参考电压的相关性具体为数据的电压与参考电压之间的数值大小关系。通过采用上述方式，降低统计码间干扰的难度，减少了实现复杂度。具体来说，第二位置上数据的电压是模拟信号，而模拟信号难以进行数据统计和计算。而通过使用参考电压为判决阈值，能够将数据的电压从模拟信号转换为数字形式的判决结果，而数字形式的判决结果容易通过计数器等进行统计，因此实现复杂度得以大大减小。
在一些实施例中，参考电压包括第一参考电压和第二参考电压。第一参考电压和第二参考电压的电压值不相等。第一参考电压和第二参考电压可选地具有预先设定的电压值。可选地，第一参考电压和第二参考电压的作用有所区别。第一参考电压用于判决第二位置上数据的值。第一参考电压有时也称为中心电平或者“0”电平。第一参考电压的功能类似于坐标系的零点，接收端内部的其他电压值是相对于第一参考电压的相对电压值。第二参考电压用于判决第二位置上数据的正负。第二参考电压有时也称为期望电平或者目标电平。
利用上述第一参考电压和第二参考电压确定码间干扰例如包括：以第一参考电压为判决阈值，对第二位置上数据进行比较，得到第一判决结果；以第二参考电压为判决阈值，对第二位置上数据进行比较，得到第二判决结果；将第一判决结果和第二判决结果中值相同的总个数作为第一总个数；将第一判决结果和第二判决结果中值不相同的总个数作为第二总个数；根据第一总个数和第二总个数确定码间干扰。其中码间干扰与第一总个数正相关，码间干扰与第二总个数负相关。第一判决结果指示第二位置上数据的电压与第一参考电压之间的数值关系。第二判决结果指示第二位置上数据与第二参考电压之间的数值关系。
下面结合一个公式对确定码间干扰的过程举例说明。下述公式一是利用第一参考电压和第二参考电压确定码间干扰的具体示例。
tail_err＝∑M(p_tail_i)*C(p_tail_i)-∑M(n_tail_i)*C(n_tail_i)；公式一；
上述公式一中，tail_err即固定码型数据在第二位置上产生的码间干扰，tail_err的物理含义是信道冲激响应拖尾造成的误差，tail_err是用来评估ISI拖尾噪声的量。tail的直译为尾部，即上述第二位置。err的含义是误差(error)，即上述码间干扰。p_tail中p表示P_DC_SEG(固定码型数据中第一数据段)。p_tail表示P_DC_SEG产生拖尾现象的位置，p_tail具体为第一数据段之后第N+1个符号位。受信道的ISI的影响，P_DC_SEG会使得p_tail上的数据的电压比预期偏高。p_tail_i表示一个训练序列中第i个训练帧中的p_tail。n_tail中n表示N_DC_SEG(固定码型数据中第二数据段)。n_tail表示N_DC_SEG产生拖尾现象的位置，n_tail具体为第二数据段之后第N+1个符号位。n_tail_i表示一个训练序列中第i个训练帧中的n_tail。受信道的ISI的影响，N_DC_SEG会让n_tail上的数据电压比预期偏低。C表示中心电平处的判决结果，即上述第一判决结果。在一种可能的实现中，C的确定过程为：判断均衡后的信号电压值是否大于0，如果均衡后的信号电压值大于0则C＝1。如果均衡后的信号电压值小于或等于0则C＝-1。M表示期望电平处的判决结果，即上述第二判决结果。在一种可能的实现中，M是C＝1或C＝-1时，均衡后信号电压的期望值。具体地，通常情况下被判决为C＝1或C＝-1的信号电压为一个高斯分布，如果期望这个分布的均值电压为v，那么如果均衡后的信号电压大于v则M＝1，如果均衡后的信号电压小于或等于v则M＝-1。*表示相乘。C与M相乘的物理含义是计算M和C相同的总个数减去M和C不同的总个数。具体地，M的参考电压是C＝1(或C＝-1)时信号电压分布的期望均值处，所以上述公式的目标是当C＝1(或C＝-1)时，M＝1和M＝-1的个数相同。∑是求和符号，求和的范围可选地根据需求设定，例如求和的范围是训练帧的整数倍。
步骤S306、第二设备根据固定码型数据在第二位置产生的码间干扰，调整第一均衡器的参数。
可选地，上述码间干扰具体用于调整退化电阻(degeneration resistor，Rs)，退化电容(degeneration capacitor，Cs)这两种均衡器参数的场景。
在一些实施例中，通过为码间干扰设定阈值实现均衡器参数的调整。具体来说，第二设备对第二位置产生的码间干扰与设定的干扰阈值进行比较。若码间干扰小于设定的干扰阈值，第二设备减小第一均衡器的参数；若码间干扰大于设定的干扰阈值，第二设备增大第一均衡器的参数；若码间干扰等于设定的干扰阈值，第二设备保持第一均衡器的参数不变。
上述干扰阈值有时称为误差目标值、误差期望值或者误差预期值。干扰阈值例如是一个较小的正数。干扰阈值可选地根据具体的第一均衡器和第二设备的电路特点设定。
通过采用上述方式调整第一均衡器的参数，有助于提升第一均衡器的信道均衡性能。达到这一技术效果的原理在于，当第一均衡器均衡不足的时候，在第二位置统计得到的码间干扰会非常大正数，因此增大第一均衡器的均衡参数，即增加高频部分的增益或增大低频部分的衰减，从而解决均衡不足的情况。当第一均衡器均衡过大时，在第二位置统计得到的码间干扰会是一个绝对值很小的0附近的随机数，此时通过减小第一均衡器的均衡参数，即减小高频部分的增益或减小低频部分的衰减，从而解决均衡过大的情况。
可选地，本实施例还涉及第二均衡器的参数调整过程。具体地，上述训练序列是通过第一均衡器以及第二均衡器处理得到的。例如，第二设备不仅利用第一均衡器以及第二均衡器处理得到的训练序列中的固定码型数据，执行上述第一均衡器的参数调整过程，还利用第一均衡器以及第二均衡器处理得到的训练序列中的随机数据来调整第二均衡器的参数，具体的实现方式请参考下述步骤S307。
步骤S307、第二设备根据随机数据中一个或多个符号位对应的误差，调整第二均衡器的参数。
在一些实施例中，第二设备通过统计接收到的每一个符号位的误差与其前面每一个符号值的相关量，确定第二均衡器的参数。例如，第二设备根据随机数据中第一符号位对应的误差与符号值之间的相关量，调整第二均衡器的参数。其中，第一符号位是随机数据中的一个符号位。符号值为随机数据中第一符号位之前的一个或多个符号位上的值。第二均衡器的参数与相关量负相关。
在一些实施例中，第二均衡器的参数确定过程具体包括：第二设备根据第i个符号位对应的误差与(i-m)个符号位上符号值之间的相关量，调整第二均衡器第m个抽头的参数。其中，i、m均为正整数。这一方式的原理为，乘积S(i-n)*E(i)与第二均衡器的第n个抽头的系数成反比。其中，E(i)为接收端测量的第i个位置上的符号的误差，S(i-n)表示第i-n个位置上的符号值S(i-n)。因此，通过随机数据的统计值∑ iS(i-n)E(i)可以完成对第二均衡器的第n个抽头的系数自适应调节。
在一些实施例中，第二均衡器的参数调整过程通过最小均方算法(least mean square，LMS)算法实现。LMS算法是一种以最小均分误差为准则的自适应均衡算法。
可选地，第二设备确定固定码型数据在第二位置产生的码间干扰之后，还将第二位置的码间干扰作为系统的噪声余量，输出系统的噪声余量。
附图3所示实施例对S306与S307的时序不做限定。在一些实施例中，S306与S307顺序执行。例如，先执行S306，再执行S307；又如，先执行S307，再执行S306。在另一些实施例中，S306与S307并行执行，即，第二设备同时执行S306以及S307。
本实施例提供的方法，通过在训练序列中增加固定码型数据，固定码型数据能够实现对拖尾处的码间干扰进行放大叠加的作用，从而降低度量拖尾处码间干扰的技术难度，因此确 定出的拖尾处码间干扰的精确度更高，因此根据码间干扰调整均衡器参数，能够有效提高参数调整的精度。
下面，对训练序列中增加固定码型数据时，如何提高均衡器参数调整的精确度的技术原理进行具体介绍。
在训练序列由随机序列组成，而不包含固定码型数据的情况下，由于接收端判决器的精度影响，无法有效的度量每个位置的码间干扰的噪声强度。这是由于，拖尾处的码间干扰影响表现为很多的很小的噪声叠加，即每个抽头的码间干扰值都很小，但累加到一起却非常大。很大一个范围内，均衡器的作用会使得拖尾处统计的码间干扰是接近0的随机数，因此很难获得准确的均衡器参数。
而通过在训练序列中增加固定码型数据，实现对拖尾处的码间干扰进行放大叠加的作用。具体来说，根据线性系统的原理，接收端接收到的信号是发送端发出的信号与信道冲激响应的卷积。信道冲激响应的平坦部分(即低频部分)与发送信号卷积后，发送信号的高频部分会被过滤，发送信号的低频部分会被保留。经典的训练序列的发送信号中各种频点的信号强度(概率)基本相同。如果在训练序列中增加低频信号的比例，则在接收到的信号中信道的低频响应则会被增强，因此信道冲击响应拖尾造成的误差会得到放大。
那么，由于拖尾处的码间干扰得到了放大，拖尾处的码间干扰基本上能大于判决器检测的精度，能够更精确地确定出拖尾处的码间干扰，因此使用更加精确的码间干扰显然能够更加精确地调整均衡器参数。
下面结合一个实例，对附图2所示应用场景以及附图3所示方法举例说明。
请参考附图5，附图5是一种SERDES系统的架构图，附图5是附图2的具体示例。
附图5包括SERDES系统的发送端500以及SERDES系统的接收端510。SERDES系统的发送端500是第一设备的具体示例。SERDES系统的接收端510是第二设备的具体示例。
发送端500包括训练序列产生器501。训练序列产生器501是附图2中处理器201的具体示例。附图3所示方法中步骤S301例如通过训练序列产生器501实现。
训练序列产生器501用于生成训练序列。训练序列产生器501具体包括随机码产生器(random data generator)5011、固定码型数据存储器5021以及固定码型数据存储器5022。
随机码产生器5011用于生成随机数据。
固定码型数据存储器5021用于存放配置的固定码型数据P_DC_CODE(正直流数据段，即第一数据段)。固定码型数据存储器5021例如是可配置寄存器，或者是内存、缓存、闪存等其他存储器。
固定码型数据存储器5022用于存放配置的固定码型数据N_DC_CODE(负直流数据段，即第二数据段)。固定码型数据存储器5022和固定码型数据存储器5021为不同或者相同的存储器。固定码型数据存储器5022例如是可配置寄存器，或者是内存、缓存、闪存等其他存储器。
接收端510包括接收电路5110、CTLE 5131、DFE 5132、LMS调整(LMS adapt)电路5113、固定码型数据定位电路5111、误差检测电路5112以及均衡参数调整电路5114。
接收电路5110用于将接收到的数据信号提供给CTLE 5131以及DFE 5132。
CTLE 5131和DFE 5132均用于进行信道均衡。具体地，接收电路5110提供的数据信号经过CTLE 5131和DFE 5132处理之后，进行判决和采样得到训练序列。
固定码型数据定位电路5111用于在训练序列中对固定码型数据进行定位，也即是确定固定码型数据在训练序列中所处的第一位置。例如，结合附图4来看，固定码型数据定位电路5111实现对P_DC_CODE和N_DC_CODE在训练码流中的检测和定位。附图3所示方法中步骤S304例如通过固定码型数据定位电路5111实现。
误差检测电路5112用于确定固定码型数据在第二位置产生的码间干扰，也即是，确定固定码型数据带来的拖尾处的误差。例如，结合附图4来看，误差检测电路5112用于检测P_DC_CODE或者N_DC_CODE对相邻随机码的干扰产生的误差。误差检测电路5112还用于将检测到的误差提供给均衡参数调整电路。附图3所示方法中步骤S305例如通过误差检测电路5112实现。
均衡参数调整电路5114，用于根据码间干扰调整第一均衡器的参数。例如，均衡参数调整电路5114用于对对CTLE系数进行调整。
LMS调整电路5113用于根据随机数据中一个或多个符号位对应的误差，调整第二均衡器的参数。例如，LMS调整电路5113通过采用经典LMS算法完成DFE系数调节。附图3所示方法中步骤S307例如通过LMS调整电路5113实现。
下面介绍上述SERDES系统中均衡器参数的调整方法。该方法包括以下步骤(1)至步骤(4)。
步骤(1)在SERDES系统初始化进行均衡参数训练时，发送端发送训练序列。
训练序列包括连续的TF。每个TF包括P_DC_SEG，N_DC_SEG和RANDOM_SEG三个部分。在一个训练序列中的TF的P_DC_SEG都是相同的，N_DC_SEG也都是相同的。
P_DC_SEG的码(code)值是提前预设的，或者是接收端反馈的需要发送的code值。
N_DC_SEG为P_DC_CODE每一个比特取反得到的序列。
RANDOM_SEG是伪随机序列。RANDOM_SEG可选地是伪随机码生成器生成的伪随机序列。或者，RANDOM_SEG是发送给接收端的一些有效数据打散后生成的伪随机数据序列。在一个训练数据序列中的TF的RANDOM_SEG中的数据都是伪随机生成或随机打散后的数据。
步骤(2)接收端锁定P_DC_SEG位置以及N_DC_SEG位置。
因为发送端发送的数据是按TF循环发送的，因此接收端将接收到的数据按TF的长度进行周期的检测。接收端对接收到均衡后的数据进行以下步骤S302至步骤S304，完成对CTLE的均衡参数的调节。其中，均衡后的数据例如是接收信号先经过CTLE再经过DFE后进行数据判决采样得到的。
具体地，因为P_DC_SEG和N_DC_SEG都属于低频的码型，因此信道的衰减很小，并且稳定的周期出现，只需要周期的循环检测就能够比较容易的实现对P_DC_SEG/N_DC_SEG锁定。例如，接收端使用模板匹配的方式，将每一段连续的符号都和P_DC_SEG/N_DC_SEG做比对，找到P_DC_SEG/N_DC_SEG概率最大位置。或者，接收端通过统计1和0的个数，包含P_DC_SEG的序列中1的个数会多，包含N_DC_SEG的序列0的个数会多，然后通过缩小统计序列的长度，缩小范围最终确定P_DC_SEG和N_DC_SEG的位置。当完成锁定后， 接收端得到如附图6所示的波形，根据这个波形可以定位接收的每一个比特在当前TF中的位置。附图6示出了一个数字控制信号波形，水平坐标的单位是UI或时间，纵坐标为0和1，低电压为0，高电压为1。
接收端通过确定P_DC_SEG的位置以及N_DC_SEG的位置，便于确定步骤S304中的p_tail的位置以及n_tail的位置，以便根据p_tail的位置以及n_tail的位置统计tail_err。同时在DFE系数调节时也可以避开P_DC_SEG/N_DC_SEG。这是考虑到，P_DC_SEG/N_DC_SEG是非随机数据，虽然理论上对DFE系数自适应调节没有影响，但是由于和实际应用数据不同，RANDOM_SEG的数据更接近实际数据，因此更合适的方法是只用RANDOM_SEG进行DFE系数的调节，避开P_DC_SEG/N_DC_SEG的数据影响。
步骤(3)接收端对DFE的参数进行自适应调整。
RANDOM_SEG中的数据是较长的随机序列，接收端采用LMS算法通过统计RANDOM_SEG中的数据完成对DFE的参数进行自适应调整。LMS算法通过统计接收到的每一个符号的误差与它前面每一个符号值的相关量，估计DFE的系数。其原理为，接收端测量到的第i个位置上的符号的误差(E(i))与前面第i-n个位置上的符号值S(i-n)的乘积S(i-n)*E(i)与DFE的第n个抽头的系数成反比，因此通过随机序列的统计值∑ iS(i-n)E(i)可以完成对DFE的第n个抽头的系数自适应调节。
步骤(4)接收端对CTLE的参数进行自适应调整。
如果DFE的抽头数为N，则DFE可以消除接收端接收到的训练码流中每个符号的前面N个符号对这个符号产生的干扰(ISI)。DFE已经消除了P_DC_SEG和N_DC_SEG对后续的N个符号产生的ISI，所以CTLE的目标是消除从N+1开始P_DC_SEG和N_DC_SEG对后面符号位置上的ISI影响。因为这个影响随趋势呈现逐步递减的趋势，因此重点检测N+1位置上的误差。称P_DC_SEG和N_DC_SEG后第N+1位置为p_tail和n_tail。通过上述公式一进行拖尾数据的统计，得出tail_err。
当得到tail_err之后，考虑到受信道的ISI的影响，P_DC_SEG会使得p_tail上的数据的电压比预期偏高，而N_DC_SEG会让n_tail上的数据电压偏低。当CTLE均衡不足的时候，统计得到的tail_err会非常大正数，需要增大CTLE的均衡参数，即增加高频部分的增益或增大低频部分的衰减；当CTLE均衡过大时，则tail_err会是一个绝对值很小的0附近的随机数，此时则需要减小高频部分的增益或减小低频部分的衰减；当tail_err为一个稳定的负数时，则表明CTLE的均衡严重过大。根据具体的CTLE和接收端的电路特点和统计的TF个数，设定一个较小的正数做为tail_err的目标值进行CTLE均衡参数的自适应调节。
可替代地，上述实例提供的方法应用在DFE处于关闭状态或者没有DFE的SERDES系统中。
上述实例提供的方法提供了一种新的SERDES训练序列，该随机序列中包含固定码型数据和随机数据。固定码型数据能够实现对拖尾处ISI进行放大叠加的作用，也就是放大了ISI拖尾处的噪声。因此，能够解决CTLE参数自适应调节困难，调节精度差等技术问题。该方法不仅能减少CTLE训练的时间，并且能更准确的找到CTLE的最佳参数，因此有效地提高CTLE自适应的效果，增强了SERDES系统的均衡性能。
附图7是本申请实施例提供的一种训练序列的发送装置的结构示意图。
可选地，结合附图2来看，附图7所示的装置700为附图2中第一设备200。可选地，结合附图3来看，附图7所示的装置700用于实现附图3所示方法中第一设备的功能。可选地，结合附图5来看，装置700实现附图5中发送端500的功能。
请参考附图7，装置700包括生成单元701和发送单元702。生成单元701用于支持装置700执行S301。发送单元702用于支持装置700执行S302。
装置700中的各个单元全部或部分地通过软件、硬件、固件或者其任意组合来实现。附图7所描述的装置实施例仅仅是示意性的，例如，上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。附图7中上述各个单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
可选地，结合附图5来看，生成单元701通过附图5中随机码产生器5011、可配置寄存器5021以及可配置寄存器5021实现。
可选地，结合附图2来看，采用软件实现时，上述生成单元701可以是由附图2中第一设备200的至少一个处理器201读取存储器202中存储的程序代码后，生成的软件功能单元来实现。附图7中上述各个单元也可以由附图2中的不同硬件分别实现，例如生成单元701由附图2中第一设备200的至少一个处理器201中的一部分处理资源(例如多核处理器中的一个核或两个核)实现，或者由附图2中第一设备200至少一个处理器201中的其余部分处理资源(例如多核处理器中的其他核)，或者采用现场可编程门阵列(field－programmable gate array，FPGA)、或协处理器等可编程器件来完成。发送单元702由附图2中第一设备200的通信接口203实现。显然上述功能单元也可以采用软件硬件相结合的方式来实现，例如发送单元702由硬件可编程器件实现，而生成单元701是由CPU读取存储器中存储的程序代码后，生成的软件功能单元。
附图8是本申请实施例提供的一种均衡器参数的调整装置的结构示意图。
可选地，结合附图2来看，附图7所示的装置800为附图2中第二设备210。可选地，结合附图3来看，附图7所示的装置800用于实现附图3所示方法中第二设备的功能。可选地，结合附图5来看，装置800实现附图5中接收端510的功能。
请参考附图8，装置800包括获取单元801、确定单元802、调整单元803。获取单元801用于支持装置800执行S303。确定单元802用于支持装置800执行S304至S305。调整单元803用于支持装置800执行S306。可选地，调整单元803还用于支持装置800执行S307。
装置800中的各个单元全部或部分地通过软件、硬件、固件或者其任意组合来实现。附图8所描述的装置实施例仅仅是示意性的，例如，上述单元的划分，仅仅为一种逻辑功能划分，实际实现时可以有另外的划分方式，例如多个单元或组件可以结合或者可以集成到另一个系统，或一些特征可以忽略，或不执行。在本申请各个实施例中的各功能单元可以集成在一个处理单元中，也可以是各个单元单独物理存在，也可以两个或两个以上单元集成在一个单元中。附图8中上述各个单元既可以采用硬件的形式实现，也可以采用软件功能单元的形式实现。
可选地，结合附图5来看，获取单元801通过附图5中CTLE 5131和DFE 5132实现，确定单元802通过附图5中P_DC_CODE或N_DC_CODE检测模块5111实现，调整单元803通过附图5中拖尾处误差检测模块5112以及LMS调整模块5113实现。
可选地，结合附图2来看，在采用软件实现时，上述获取单元801、确定单元802、调整单元803可以是由附图2中第二设备210的至少一个处理器211读取存储器212中存储的程序代码后，生成的软件功能单元来实现。附图8中上述各个单元也可以由附图2中第二设备210中的不同硬件分别实现，例如确定单元802由附图2中的至少一个处理器211中的一部分处理资源(例如多核处理器中的一个核或两个核)实现，而调整单元803由附图2中至少一个处理器211中的其余部分处理资源(例如多核处理器中的其他核)，或者采用现场可编程门阵列(field－programmable gate array，FPGA)、或协处理器等可编程器件来完成。获取单元801可选地由附图2中的通信接口213中第一均衡器和第二均衡器实现。显然上述功能单元也可以采用软件硬件相结合的方式来实现，例如确定单元802由硬件可编程器件实现，而调整单元803是由CPU读取存储器中存储的程序代码后，生成的软件功能单元。
本说明书中的各个实施例均采用递进的方式描述，各个实施例之间相同相似的部分可互相参考，每个实施例重点说明的都是与其他实施例的不同之处。其中，A参考B，指的是A与B相同或者A为B的简单变形。
本申请实施例的说明书和权利要求书中的术语“第一”和“第二”等是用于区别不同的对象，而不是用于描述对象的特定顺序，也不能理解为指示或暗示相对重要性。例如，第一均衡器和第二均衡器用于区别不同的均衡器，而不是用于描述均衡器的特定顺序，也不能理解为第一均衡器比第二均衡器更重要。
本申请实施例，除非另有说明，“至少一个”的含义是指一个或多个，“多个”的含义是指两个或两个以上。例如，多个符号位是指两个或两个以上的符号位。
上述实施例可以全部或部分地通过软件、硬件、固件或者其任意组合来实现。当使用软件实现时，可以全部或部分地以计算机程序产品的形式实现。计算机程序产品包括一个或多个计算机指令。在计算机上加载和执行计算机程序指令时，全部或部分地产生按照本申请实施例描述的流程或功能。计算机可以是通用计算机、专用计算机、计算机网络、或者其他可编程装置。计算机指令可以存储在计算机可读存储介质中，或者从一个计算机可读存储介质向另一个计算机可读存储介质传输，例如，计算机指令可以从一个网站站点、计算机、服务器或数据中心通过有线(例如同轴电缆、光纤、数字用户线(DSL))或无线(例如红外、无线、微波等)方式向另一个网站站点、计算机、服务器或数据中心进行传输。计算机可读存储介质可以是计算机能够存取的任何可用介质或者是包含一个或多个可用介质集成的服务器、数据中心等数据存储设备。可用介质可以是磁性介质，(例如，软盘、硬盘、磁带)、光介质(例如，DVD)、或者半导体介质(例如固态硬盘Solid State Disk(SSD))等。
以上实施例仅用以说明本申请的技术方案，而非对其限制；尽管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的范围。

Claims (43)

  1. 一种均衡器参数的调整方法，其特征在于，所述方法包括：
    获取通过第一均衡器处理得到的训练序列，所述训练序列包括固定码型数据；
    确定所述固定码型数据在所述训练序列中所处的第一位置；
    确定所述固定码型数据在第二位置产生的码间干扰，所述第二位置为所述训练序列中所述第一位置之后的位置；
    根据所述码间干扰调整所述第一均衡器的参数。
  2. 根据权利要求1所述的方法，其特征在于，所述确定所述固定码型数据在第二位置产生的码间干扰，包括：
    根据所述第二位置上数据的电压与参考电压的相关性，确定所述码间干扰。
  3. 根据权利要求2所述的方法，其特征在于，所述参考电压包括第一参考电压和第二参考电压，所述第一参考电压和所述第二参考电压的电压值不相等，所述根据所述第二位置上数据的电压与参考电压的相关性，确定所述码间干扰包括：
    以所述第一参考电压为判决阈值，对所述第二位置上数据进行比较，得到第一判决结果；
    以所述第二参考电压为判决阈值，对所述第二位置上数据进行比较，得到第二判决结果；
    将所述第一判决结果和所述第二判决结果中值相同的总个数作为第一总个数；
    将所述第一判决结果和所述第二判决结果中值不相同的总个数作为第二总个数；
    根据所述第一总个数和所述第二总个数确定所述码间干扰，其中所述码间干扰与第一总个数正相关，所述码间干扰与第二总个数负相关。
  4. 根据权利要求1所述的方法，其特征在于，所述根据所述码间干扰调整所述第一均衡器的参数，包括：
    若所述码间干扰小于设定的干扰阈值，减小所述第一均衡器的参数；
    若所述码间干扰大于设定的干扰阈值，增大所述第一均衡器的参数；
    若所述码间干扰等于设定的干扰阈值，保持所述第一均衡器的参数不变。
  5. 根据权利要求1所述的方法，其特征在于，所述训练序列还包括随机数据，所述方法还包括：
    根据所述随机数据中一个或多个符号位对应的误差，调整第二均衡器的参数，所述训练序列是通过所述第一均衡器以及所述第二均衡器处理得到的。
  6. 根据权利要求5所述的方法，其特征在于，所述随机数据中一个或多个符号位包括第一符号位，所述根据所述随机数据中一个或多个符号位对应的误差，调整第二均衡器的参数，包括：
    根据所述第一符号位对应的误差与符号值之间的相关量，调整所述第二均衡器的参数， 所述符号值为所述随机数据中所述第一符号位之前的符号位上的值，所述第二均衡器的参数与所述相关量负相关。
  7. 根据权利要求6所述的方法，其特征在于，所述根据所述第一符号位对应的误差与符号值之间的相关量，调整所述第二均衡器的参数，包括：
    根据第i个符号位对应的误差与(i-m)个符号位上符号值之间的相关量，调整所述第二均衡器第m个抽头的参数，所述i、所述m均为正整数。
  8. 根据权利要求5至7中任一项所述的方法，其特征在于，所述第二位置与所述第一位置之间的距离大于N个符号，所述N为所述第二均衡器的抽头数。
  9. 根据权利要求8所述的方法，其特征在于，所述第二位置为所述第一位置之后的第N+1个符号位。
  10. 根据权利要求5至9中任一项所述的方法，其特征在于，所述训练序列中所述固定码型数据与所述随机数据之间的长度比例为1:7。
  11. 根据权利要求1至9中任一项所述的方法，其特征在于，所述固定码型数据的长度位于4比特至16比特之间。
  12. 根据权利要求1至11中任一项所述的方法，其特征在于，所述固定码型数据包括第一数据段和第二数据段，所述第二数据段为所述第一数据段中每一个比特取反后得到的数据。
  13. 根据权利要求5至10中任一项所述的方法，其特征在于，所述第二均衡器为判决反馈均衡器DFE。
  14. 根据权利要求1至13中任一项所述的方法，其特征在于，所述第一均衡器为连续时间线性均衡器CTLE。
  15. 一种训练序列的发送方法，其特征在于，所述方法包括：
    生成训练序列，所述训练序列包括固定码型数据，所述固定码型数据在所述训练序列中处于第一位置，所述固定码型数据在第二位置产生的码间干扰用于调整第一均衡器的参数，所述第二位置为所述训练序列中所述第一位置之后的位置，所述第一均衡器为所述训练序列的接收端中设置的均衡器；
    发送所述训练序列。
  16. 根据权利要求15所述的方法，其特征在于，所述训练序列还包括随机数据，所述随机数据中一个或多个符号位对应的误差用于调整第二均衡器的参数，所述第二均衡器为所述训练序列的接收端中设置的均衡器。
  17. 根据权利要求15或16所述的方法，其特征在于，所述训练序列中所述固定码型数据与所述随机数据之间的长度比例为1:7。
  18. 根据权利要求15至17中任一项所述的方法，其特征在于，所述固定码型数据的长度位于4比特至16比特之间。
  19. 根据权利要求15至18中任一项所述的方法，其特征在于，所述固定码型数据包括第一数据段和第二数据段，所述第二数据段为所述第一数据段中每一个比特取反后得到的数据。
  20. 根据权利要求15所述的方法，其特征在于，所述生成训练序列，包括：
    根据预先设定的所述固定码型数据生成所述训练序列；或者，
    根据接收端发送的所述固定码型数据生成所述训练序列。
  21. 一种均衡器参数的调整装置，其特征在于，所述装置包括：
    第一均衡器，用于处理得到训练序列，所述训练序列包括固定码型数据；
    固定码型数据定位电路，用于确定所述固定码型数据在所述训练序列中所处的第一位置；
    误差检测电路，用于确定所述固定码型数据在第二位置产生的码间干扰，所述第二位置为所述训练序列中所述第一位置之后的位置；
    均衡参数调整电路，用于根据所述码间干扰调整所述第一均衡器的参数。
  22. 根据权利要求21所述的装置，其特征在于，所述误差检测电路，用于根据所述第二位置上数据的电压与参考电压的相关性，确定所述码间干扰。
  23. 根据权利要求22所述的装置，其特征在于，所述参考电压包括第一参考电压和第二参考电压，所述第一参考电压和所述第二参考电压的电压值不相等，所述根据所述第二位置上数据的电压与参考电压的相关性，所述误差检测电路，用于以所述第一参考电压为判决阈值，对所述第二位置上数据进行比较，得到第一判决结果；以所述第二参考电压为判决阈值，对所述第二位置上数据进行比较，得到第二判决结果；将所述第一判决结果和所述第二判决结果中值相同的总个数作为第一总个数；将所述第一判决结果和所述第二判决结果中值不相同的总个数作为第二总个数；根据所述第一总个数和所述第二总个数确定所述码间干扰，其中所述码间干扰与第一总个数正相关，所述码间干扰与第二总个数负相关。
  24. 根据权利要求21所述的装置，其特征在于，所述均衡参数调整电路，用于若所述码间干扰小于设定的干扰阈值，减小所述第一均衡器的参数；若所述码间干扰大于设定的干扰阈值，增大所述第一均衡器的参数；若所述码间干扰等于设定的干扰阈值，保持所述第一均衡器的参数不变。
  25. 根据权利要求21所述的装置，其特征在于，所述训练序列还包括随机数据，所述装 置还包括：最小均方算法LMS调整电路，用于根据所述随机数据中一个或多个符号位对应的误差，调整第二均衡器的参数，所述训练序列是通过所述第一均衡器以及所述第二均衡器处理得到的。
  26. 根据权利要求25所述的装置，其特征在于，所述随机数据中一个或多个符号位包括第一符号位，所述均衡参数调整电路，用于根据所述第一符号位对应的误差与符号值之间的相关量，调整所述第二均衡器的参数，所述符号值为所述随机数据中所述第一符号位之前的符号位上的值，所述第二均衡器的参数与所述相关量负相关。
  27. 根据权利要求26所述的装置，其特征在于，所述均衡参数调整电路，用于根据第i个符号位对应的误差与(i-m)个符号位上符号值之间的相关量，调整所述第二均衡器第m个抽头的参数，所述i、所述m均为正整数。
  28. 根据权利要求25至27中任一项所述的装置，其特征在于，所述第二位置与所述第一位置之间的距离大于N个符号，所述N为所述第二均衡器的抽头数。
  29. 根据权利要求28所述的装置，其特征在于，所述第二位置为所述第一位置之后的第N+20个符号位。
  30. 根据权利要求25至29中任一项所述的装置，其特征在于，所述训练序列中所述固定码型数据与所述随机数据之间的长度比例为1:7。
  31. 根据权利要求21至29中任一项所述的装置，其特征在于，所述固定码型数据的长度位于4比特至16比特之间。
  32. 根据权利要求21至31中任一项所述的装置，其特征在于，所述固定码型数据包括第一数据段和第二数据段，所述第二数据段为所述第一数据段中每一个比特取反后得到的数据。
  33. 根据权利要求26至31中任一项所述的装置，其特征在于，所述第二均衡器为判决反馈均衡器DFE。
  34. 根据权利要求21至33中任一项所述的装置，其特征在于，所述第一均衡器为连续时间线性均衡器CTLE。
  35. 一种训练序列的发送装置，其特征在于，所述装置包括：
    训练序列产生器，用于生成训练序列，所述训练序列包括固定码型数据，所述固定码型数据在所述训练序列中处于第一位置，所述固定码型数据在第二位置产生的码间干扰用于调整第一均衡器的参数，所述第二位置为所述训练序列中所述第一位置之后的位置，所述第一均衡器为所述训练序列的接收端中设置的均衡器；
    发射电路，用于发送所述训练序列。
  36. 根据权利要求35所述的装置，其特征在于，所述训练序列产生器包括随机码产生器，所述随机码产生器用于产生所述训练序列还包括的随机数据，所述随机数据中一个或多个符号位对应的误差用于调整第二均衡器的参数，所述第二均衡器为所述训练序列的接收端中设置的均衡器。
  37. 根据权利要求35或36所述的装置，其特征在于，所述训练序列中所述固定码型数据与所述随机数据之间的长度比例为1:7。
  38. 根据权利要求35至37中任一项所述的装置，其特征在于，所述固定码型数据的长度位于4比特至16比特之间。
  39. 根据权利要求35至38中任一项所述的装置，其特征在于，所述固定码型数据包括第一数据段和第二数据段，所述第二数据段为所述第一数据段中每一个比特取反后得到的数据。
  40. 根据权利要求35所述的装置，其特征在于，所述训练序列产生器，用于根据预先设定的所述固定码型数据生成所述训练序列；或者，根据接收端发送的所述固定码型数据生成所述训练序列。
  41. 一种电子设备，其特征在于，所述电子设备包括处理器和第一均衡器，所述处理器用于执行指令，使得所述电子设备执行如权利要求1至权利要求14中任一项所述的方法，所述第一均衡器用于处理得到训练序列。
  42. 一种电子设备，其特征在于，所述电子设备包括处理器和通信接口，所述处理器用于执行指令，使得所述电子设备执行如权利要求15至权利要求20中任一项所述的方法，所述通信接口用于发送训练序列。
  43. 一种通信系统，其特征在于，所述系统包括如权利要求41所述的电子设备以及如权利要求42所述的电子设备；或者，所述系统包括如权利要求21至34中任一项所述的装置以及如权利要求35至39中任一项所述的装置。
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CN106301229A (zh) * 2016-08-17 2017-01-04 灿芯半导体(上海)有限公司 数据接收电路
CN107807867A (zh) * 2017-09-29 2018-03-16 曙光信息产业(北京)有限公司 测试通信链路稳定性的方法及装置
US10721106B1 (en) * 2019-04-08 2020-07-21 Kandou Labs, S.A. Adaptive continuous time linear equalization and channel bandwidth control

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Publication number Priority date Publication date Assignee Title
CN106301229A (zh) * 2016-08-17 2017-01-04 灿芯半导体(上海)有限公司 数据接收电路
CN107807867A (zh) * 2017-09-29 2018-03-16 曙光信息产业(北京)有限公司 测试通信链路稳定性的方法及装置
US10721106B1 (en) * 2019-04-08 2020-07-21 Kandou Labs, S.A. Adaptive continuous time linear equalization and channel bandwidth control

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